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panfrost/midgard: Extract emit_varying_read
[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value debug_options[] = {
54 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
56 DEBUG_NAMED_VALUE_END
57 };
58
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
60
61 int midgard_debug = 0;
62
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67
68 static bool
69 midgard_is_branch_unit(unsigned unit)
70 {
71 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
72 }
73
74 static void
75 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
76 {
77 block->successors[block->nr_successors++] = successor;
78 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
79 }
80
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
83
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
91 .ssa_args = { \
92 .rname = ssa, \
93 .uname = -1, \
94 .src1 = -1 \
95 }, \
96 .load_store = { \
97 .op = midgard_op_##name, \
98 .mask = 0xF, \
99 .swizzle = SWIZZLE_XYZW, \
100 .address = address \
101 } \
102 }; \
103 \
104 return i; \
105 }
106
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
109
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
112
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src *src, bool is_int)
115 {
116 if (!src) return blank_alu_src;
117
118 midgard_vector_alu_src alu_src = {
119 .rep_low = 0,
120 .rep_high = 0,
121 .half = 0, /* TODO */
122 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
123 };
124
125 if (is_int) {
126 /* TODO: sign-extend/zero-extend */
127 alu_src.mod = midgard_int_normal;
128
129 /* These should have been lowered away */
130 assert(!(src->abs || src->negate));
131 } else {
132 alu_src.mod = (src->abs << 0) | (src->negate << 1);
133 }
134
135 return alu_src;
136 }
137
138 /* load/store instructions have both 32-bit and 16-bit variants, depending on
139 * whether we are using vectors composed of highp or mediump. At the moment, we
140 * don't support half-floats -- this requires changes in other parts of the
141 * compiler -- therefore the 16-bit versions are commented out. */
142
143 //M_LOAD(ld_attr_16);
144 M_LOAD(ld_attr_32);
145 //M_LOAD(ld_vary_16);
146 M_LOAD(ld_vary_32);
147 //M_LOAD(ld_uniform_16);
148 M_LOAD(ld_uniform_32);
149 M_LOAD(ld_color_buffer_8);
150 //M_STORE(st_vary_16);
151 M_STORE(st_vary_32);
152 M_STORE(st_cubemap_coords);
153
154 static midgard_instruction
155 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
156 {
157 midgard_branch_cond branch = {
158 .op = op,
159 .dest_tag = tag,
160 .offset = offset,
161 .cond = cond
162 };
163
164 uint16_t compact;
165 memcpy(&compact, &branch, sizeof(branch));
166
167 midgard_instruction ins = {
168 .type = TAG_ALU_4,
169 .unit = ALU_ENAB_BR_COMPACT,
170 .prepacked_branch = true,
171 .compact_branch = true,
172 .br_compact = compact
173 };
174
175 if (op == midgard_jmp_writeout_op_writeout)
176 ins.writeout = true;
177
178 return ins;
179 }
180
181 static midgard_instruction
182 v_branch(bool conditional, bool invert)
183 {
184 midgard_instruction ins = {
185 .type = TAG_ALU_4,
186 .unit = ALU_ENAB_BRANCH,
187 .compact_branch = true,
188 .branch = {
189 .conditional = conditional,
190 .invert_conditional = invert
191 }
192 };
193
194 return ins;
195 }
196
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond,
199 midgard_jmp_writeout_op op,
200 unsigned dest_tag,
201 signed quadword_offset)
202 {
203 /* For unclear reasons, the condition code is repeated 8 times */
204 uint16_t duplicated_cond =
205 (cond << 14) |
206 (cond << 12) |
207 (cond << 10) |
208 (cond << 8) |
209 (cond << 6) |
210 (cond << 4) |
211 (cond << 2) |
212 (cond << 0);
213
214 midgard_branch_extended branch = {
215 .op = op,
216 .dest_tag = dest_tag,
217 .offset = quadword_offset,
218 .cond = duplicated_cond
219 };
220
221 return branch;
222 }
223
224 static void
225 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
226 {
227 ins->has_constants = true;
228 memcpy(&ins->constants, constants, 16);
229 }
230
231 static int
232 glsl_type_size(const struct glsl_type *type, bool bindless)
233 {
234 return glsl_count_attribute_slots(type, false);
235 }
236
237 /* Lower fdot2 to a vector multiplication followed by channel addition */
238 static void
239 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
240 {
241 if (alu->op != nir_op_fdot2)
242 return;
243
244 b->cursor = nir_before_instr(&alu->instr);
245
246 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
247 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
248
249 nir_ssa_def *product = nir_fmul(b, src0, src1);
250
251 nir_ssa_def *sum = nir_fadd(b,
252 nir_channel(b, product, 0),
253 nir_channel(b, product, 1));
254
255 /* Replace the fdot2 with this sum */
256 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
257 }
258
259 static int
260 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
261 {
262 switch (instr->intrinsic) {
263 case nir_intrinsic_load_viewport_scale:
264 return PAN_SYSVAL_VIEWPORT_SCALE;
265 case nir_intrinsic_load_viewport_offset:
266 return PAN_SYSVAL_VIEWPORT_OFFSET;
267 default:
268 return -1;
269 }
270 }
271
272 static void
273 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
274 {
275 int sysval = -1;
276
277 if (instr->type == nir_instr_type_intrinsic) {
278 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
279 sysval = midgard_nir_sysval_for_intrinsic(intr);
280 }
281
282 if (sysval < 0)
283 return;
284
285 /* We have a sysval load; check if it's already been assigned */
286
287 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
288 return;
289
290 /* It hasn't -- so assign it now! */
291
292 unsigned id = ctx->sysval_count++;
293 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
294 ctx->sysvals[id] = sysval;
295 }
296
297 static void
298 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
299 {
300 ctx->sysval_count = 0;
301
302 nir_foreach_function(function, shader) {
303 if (!function->impl) continue;
304
305 nir_foreach_block(block, function->impl) {
306 nir_foreach_instr_safe(instr, block) {
307 midgard_nir_assign_sysval_body(ctx, instr);
308 }
309 }
310 }
311 }
312
313 static bool
314 midgard_nir_lower_fdot2(nir_shader *shader)
315 {
316 bool progress = false;
317
318 nir_foreach_function(function, shader) {
319 if (!function->impl) continue;
320
321 nir_builder _b;
322 nir_builder *b = &_b;
323 nir_builder_init(b, function->impl);
324
325 nir_foreach_block(block, function->impl) {
326 nir_foreach_instr_safe(instr, block) {
327 if (instr->type != nir_instr_type_alu) continue;
328
329 nir_alu_instr *alu = nir_instr_as_alu(instr);
330 midgard_nir_lower_fdot2_body(b, alu);
331
332 progress |= true;
333 }
334 }
335
336 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
337
338 }
339
340 return progress;
341 }
342
343 static void
344 optimise_nir(nir_shader *nir)
345 {
346 bool progress;
347 unsigned lower_flrp =
348 (nir->options->lower_flrp16 ? 16 : 0) |
349 (nir->options->lower_flrp32 ? 32 : 0) |
350 (nir->options->lower_flrp64 ? 64 : 0);
351
352 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
353 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
354 NIR_PASS(progress, nir, nir_lower_idiv);
355
356 nir_lower_tex_options lower_tex_options = {
357 .lower_rect = true
358 };
359
360 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
361
362 do {
363 progress = false;
364
365 NIR_PASS(progress, nir, nir_lower_var_copies);
366 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
367
368 NIR_PASS(progress, nir, nir_copy_prop);
369 NIR_PASS(progress, nir, nir_opt_dce);
370 NIR_PASS(progress, nir, nir_opt_dead_cf);
371 NIR_PASS(progress, nir, nir_opt_cse);
372 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
373 NIR_PASS(progress, nir, nir_opt_algebraic);
374 NIR_PASS(progress, nir, nir_opt_constant_folding);
375
376 if (lower_flrp != 0) {
377 bool lower_flrp_progress = false;
378 NIR_PASS(lower_flrp_progress,
379 nir,
380 nir_lower_flrp,
381 lower_flrp,
382 false /* always_precise */,
383 nir->options->lower_ffma);
384 if (lower_flrp_progress) {
385 NIR_PASS(progress, nir,
386 nir_opt_constant_folding);
387 progress = true;
388 }
389
390 /* Nothing should rematerialize any flrps, so we only
391 * need to do this lowering once.
392 */
393 lower_flrp = 0;
394 }
395
396 NIR_PASS(progress, nir, nir_opt_undef);
397 NIR_PASS(progress, nir, nir_opt_loop_unroll,
398 nir_var_shader_in |
399 nir_var_shader_out |
400 nir_var_function_temp);
401
402 /* TODO: Enable vectorize when merged upstream */
403 // NIR_PASS(progress, nir, nir_opt_vectorize);
404 } while (progress);
405
406 /* Must be run at the end to prevent creation of fsin/fcos ops */
407 NIR_PASS(progress, nir, midgard_nir_scale_trig);
408
409 do {
410 progress = false;
411
412 NIR_PASS(progress, nir, nir_opt_dce);
413 NIR_PASS(progress, nir, nir_opt_algebraic);
414 NIR_PASS(progress, nir, nir_opt_constant_folding);
415 NIR_PASS(progress, nir, nir_copy_prop);
416 } while (progress);
417
418 NIR_PASS(progress, nir, nir_opt_algebraic_late);
419
420 /* We implement booleans as 32-bit 0/~0 */
421 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
422
423 /* Now that booleans are lowered, we can run out late opts */
424 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
425
426 /* Lower mods for float ops only. Integer ops don't support modifiers
427 * (saturate doesn't make sense on integers, neg/abs require dedicated
428 * instructions) */
429
430 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
431 NIR_PASS(progress, nir, nir_copy_prop);
432 NIR_PASS(progress, nir, nir_opt_dce);
433
434 /* Take us out of SSA */
435 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
436 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
437
438 /* We are a vector architecture; write combine where possible */
439 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
440 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
441
442 NIR_PASS(progress, nir, nir_opt_dce);
443 }
444
445 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
446 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
447 * r0. See the comments in compiler_context */
448
449 static void
450 alias_ssa(compiler_context *ctx, int dest, int src)
451 {
452 _mesa_hash_table_u64_insert(ctx->ssa_to_alias, dest + 1, (void *) ((uintptr_t) src + 1));
453 _mesa_set_add(ctx->leftover_ssa_to_alias, (void *) (uintptr_t) (dest + 1));
454 }
455
456 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
457
458 static void
459 unalias_ssa(compiler_context *ctx, int dest)
460 {
461 _mesa_hash_table_u64_remove(ctx->ssa_to_alias, dest + 1);
462 /* TODO: Remove from leftover or no? */
463 }
464
465 /* Do not actually emit a load; instead, cache the constant for inlining */
466
467 static void
468 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
469 {
470 nir_ssa_def def = instr->def;
471
472 float *v = rzalloc_array(NULL, float, 4);
473 nir_const_load_to_arr(v, instr, f32);
474 _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
475 }
476
477 static unsigned
478 nir_src_index(compiler_context *ctx, nir_src *src)
479 {
480 if (src->is_ssa)
481 return src->ssa->index;
482 else {
483 assert(!src->reg.indirect);
484 return ctx->func->impl->ssa_alloc + src->reg.reg->index;
485 }
486 }
487
488 static unsigned
489 nir_dest_index(compiler_context *ctx, nir_dest *dst)
490 {
491 if (dst->is_ssa)
492 return dst->ssa.index;
493 else {
494 assert(!dst->reg.indirect);
495 return ctx->func->impl->ssa_alloc + dst->reg.reg->index;
496 }
497 }
498
499 static unsigned
500 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
501 {
502 return nir_src_index(ctx, &src->src);
503 }
504
505 static bool
506 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
507 {
508 unsigned comp = src->swizzle[0];
509
510 for (unsigned c = 1; c < nr_components; ++c) {
511 if (src->swizzle[c] != comp)
512 return true;
513 }
514
515 return false;
516 }
517
518 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
519 * output of a conditional test) into that register */
520
521 static void
522 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
523 {
524 int condition = nir_src_index(ctx, src);
525
526 /* Source to swizzle the desired component into w */
527
528 const midgard_vector_alu_src alu_src = {
529 .swizzle = SWIZZLE(component, component, component, component),
530 };
531
532 /* There is no boolean move instruction. Instead, we simulate a move by
533 * ANDing the condition with itself to get it into r31.w */
534
535 midgard_instruction ins = {
536 .type = TAG_ALU_4,
537
538 /* We need to set the conditional as close as possible */
539 .precede_break = true,
540 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
541
542 .ssa_args = {
543 .src0 = condition,
544 .src1 = condition,
545 .dest = SSA_FIXED_REGISTER(31),
546 },
547
548 .alu = {
549 .op = midgard_alu_op_iand,
550 .outmod = midgard_outmod_int_wrap,
551 .reg_mode = midgard_reg_mode_32,
552 .dest_override = midgard_dest_override_none,
553 .mask = (0x3 << 6), /* w */
554 .src1 = vector_alu_srco_unsigned(alu_src),
555 .src2 = vector_alu_srco_unsigned(alu_src)
556 },
557 };
558
559 emit_mir_instruction(ctx, ins);
560 }
561
562 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
563 * r31 instead */
564
565 static void
566 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
567 {
568 int condition = nir_src_index(ctx, &src->src);
569
570 /* Source to swizzle the desired component into w */
571
572 const midgard_vector_alu_src alu_src = {
573 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
574 };
575
576 /* There is no boolean move instruction. Instead, we simulate a move by
577 * ANDing the condition with itself to get it into r31.w */
578
579 midgard_instruction ins = {
580 .type = TAG_ALU_4,
581 .precede_break = true,
582 .ssa_args = {
583 .src0 = condition,
584 .src1 = condition,
585 .dest = SSA_FIXED_REGISTER(31),
586 },
587 .alu = {
588 .op = midgard_alu_op_iand,
589 .outmod = midgard_outmod_int_wrap,
590 .reg_mode = midgard_reg_mode_32,
591 .dest_override = midgard_dest_override_none,
592 .mask = expand_writemask((1 << nr_comp) - 1),
593 .src1 = vector_alu_srco_unsigned(alu_src),
594 .src2 = vector_alu_srco_unsigned(alu_src)
595 },
596 };
597
598 emit_mir_instruction(ctx, ins);
599 }
600
601
602
603 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
604 * pinning to eliminate this move in all known cases */
605
606 static void
607 emit_indirect_offset(compiler_context *ctx, nir_src *src)
608 {
609 int offset = nir_src_index(ctx, src);
610
611 midgard_instruction ins = {
612 .type = TAG_ALU_4,
613 .ssa_args = {
614 .src0 = SSA_UNUSED_1,
615 .src1 = offset,
616 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
617 },
618 .alu = {
619 .op = midgard_alu_op_imov,
620 .outmod = midgard_outmod_int_wrap,
621 .reg_mode = midgard_reg_mode_32,
622 .dest_override = midgard_dest_override_none,
623 .mask = (0x3 << 6), /* w */
624 .src1 = vector_alu_srco_unsigned(zero_alu_src),
625 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
626 },
627 };
628
629 emit_mir_instruction(ctx, ins);
630 }
631
632 #define ALU_CASE(nir, _op) \
633 case nir_op_##nir: \
634 op = midgard_alu_op_##_op; \
635 break;
636 static bool
637 nir_is_fzero_constant(nir_src src)
638 {
639 if (!nir_src_is_const(src))
640 return false;
641
642 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
643 if (nir_src_comp_as_float(src, c) != 0.0)
644 return false;
645 }
646
647 return true;
648 }
649
650 static void
651 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
652 {
653 bool is_ssa = instr->dest.dest.is_ssa;
654
655 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
656 unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components;
657 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
658
659 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
660 * supported. A few do not and are commented for now. Also, there are a
661 * number of NIR ops which Midgard does not support and need to be
662 * lowered, also TODO. This switch block emits the opcode and calling
663 * convention of the Midgard instruction; actual packing is done in
664 * emit_alu below */
665
666 unsigned op;
667
668 switch (instr->op) {
669 ALU_CASE(fadd, fadd);
670 ALU_CASE(fmul, fmul);
671 ALU_CASE(fmin, fmin);
672 ALU_CASE(fmax, fmax);
673 ALU_CASE(imin, imin);
674 ALU_CASE(imax, imax);
675 ALU_CASE(umin, umin);
676 ALU_CASE(umax, umax);
677 ALU_CASE(ffloor, ffloor);
678 ALU_CASE(fround_even, froundeven);
679 ALU_CASE(ftrunc, ftrunc);
680 ALU_CASE(fceil, fceil);
681 ALU_CASE(fdot3, fdot3);
682 ALU_CASE(fdot4, fdot4);
683 ALU_CASE(iadd, iadd);
684 ALU_CASE(isub, isub);
685 ALU_CASE(imul, imul);
686
687 /* Zero shoved as second-arg */
688 ALU_CASE(iabs, iabsdiff);
689
690 ALU_CASE(mov, imov);
691
692 ALU_CASE(feq32, feq);
693 ALU_CASE(fne32, fne);
694 ALU_CASE(flt32, flt);
695 ALU_CASE(ieq32, ieq);
696 ALU_CASE(ine32, ine);
697 ALU_CASE(ilt32, ilt);
698 ALU_CASE(ult32, ult);
699
700 /* We don't have a native b2f32 instruction. Instead, like many
701 * GPUs, we exploit booleans as 0/~0 for false/true, and
702 * correspondingly AND
703 * by 1.0 to do the type conversion. For the moment, prime us
704 * to emit:
705 *
706 * iand [whatever], #0
707 *
708 * At the end of emit_alu (as MIR), we'll fix-up the constant
709 */
710
711 ALU_CASE(b2f32, iand);
712 ALU_CASE(b2i32, iand);
713
714 /* Likewise, we don't have a dedicated f2b32 instruction, but
715 * we can do a "not equal to 0.0" test. */
716
717 ALU_CASE(f2b32, fne);
718 ALU_CASE(i2b32, ine);
719
720 ALU_CASE(frcp, frcp);
721 ALU_CASE(frsq, frsqrt);
722 ALU_CASE(fsqrt, fsqrt);
723 ALU_CASE(fexp2, fexp2);
724 ALU_CASE(flog2, flog2);
725
726 ALU_CASE(f2i32, f2i);
727 ALU_CASE(f2u32, f2u);
728 ALU_CASE(i2f32, i2f);
729 ALU_CASE(u2f32, u2f);
730
731 ALU_CASE(fsin, fsin);
732 ALU_CASE(fcos, fcos);
733
734 /* Second op implicit #0 */
735 ALU_CASE(inot, inor);
736 ALU_CASE(iand, iand);
737 ALU_CASE(ior, ior);
738 ALU_CASE(ixor, ixor);
739 ALU_CASE(ishl, ishl);
740 ALU_CASE(ishr, iasr);
741 ALU_CASE(ushr, ilsr);
742
743 ALU_CASE(b32all_fequal2, fball_eq);
744 ALU_CASE(b32all_fequal3, fball_eq);
745 ALU_CASE(b32all_fequal4, fball_eq);
746
747 ALU_CASE(b32any_fnequal2, fbany_neq);
748 ALU_CASE(b32any_fnequal3, fbany_neq);
749 ALU_CASE(b32any_fnequal4, fbany_neq);
750
751 ALU_CASE(b32all_iequal2, iball_eq);
752 ALU_CASE(b32all_iequal3, iball_eq);
753 ALU_CASE(b32all_iequal4, iball_eq);
754
755 ALU_CASE(b32any_inequal2, ibany_neq);
756 ALU_CASE(b32any_inequal3, ibany_neq);
757 ALU_CASE(b32any_inequal4, ibany_neq);
758
759 /* Source mods will be shoved in later */
760 ALU_CASE(fabs, fmov);
761 ALU_CASE(fneg, fmov);
762 ALU_CASE(fsat, fmov);
763
764 /* For greater-or-equal, we lower to less-or-equal and flip the
765 * arguments */
766
767 case nir_op_fge:
768 case nir_op_fge32:
769 case nir_op_ige32:
770 case nir_op_uge32: {
771 op =
772 instr->op == nir_op_fge ? midgard_alu_op_fle :
773 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
774 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
775 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
776 0;
777
778 /* Swap via temporary */
779 nir_alu_src temp = instr->src[1];
780 instr->src[1] = instr->src[0];
781 instr->src[0] = temp;
782
783 break;
784 }
785
786 case nir_op_b32csel: {
787 /* Midgard features both fcsel and icsel, depending on
788 * the type of the arguments/output. However, as long
789 * as we're careful we can _always_ use icsel and
790 * _never_ need fcsel, since the latter does additional
791 * floating-point-specific processing whereas the
792 * former just moves bits on the wire. It's not obvious
793 * why these are separate opcodes, save for the ability
794 * to do things like sat/pos/abs/neg for free */
795
796 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
797 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
798
799 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
800 nr_inputs = 2;
801
802 /* Emit the condition into r31 */
803
804 if (mixed)
805 emit_condition_mixed(ctx, &instr->src[0], nr_components);
806 else
807 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
808
809 /* The condition is the first argument; move the other
810 * arguments up one to be a binary instruction for
811 * Midgard */
812
813 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
814 break;
815 }
816
817 default:
818 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
819 assert(0);
820 return;
821 }
822
823 /* Midgard can perform certain modifiers on output of an ALU op */
824 unsigned outmod;
825
826 if (midgard_is_integer_out_op(op)) {
827 outmod = midgard_outmod_int_wrap;
828 } else {
829 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
830 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
831 }
832
833 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
834
835 if (instr->op == nir_op_fmax) {
836 if (nir_is_fzero_constant(instr->src[0].src)) {
837 op = midgard_alu_op_fmov;
838 nr_inputs = 1;
839 outmod = midgard_outmod_pos;
840 instr->src[0] = instr->src[1];
841 } else if (nir_is_fzero_constant(instr->src[1].src)) {
842 op = midgard_alu_op_fmov;
843 nr_inputs = 1;
844 outmod = midgard_outmod_pos;
845 }
846 }
847
848 /* Fetch unit, quirks, etc information */
849 unsigned opcode_props = alu_opcode_props[op].props;
850 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
851
852 /* src0 will always exist afaik, but src1 will not for 1-argument
853 * instructions. The latter can only be fetched if the instruction
854 * needs it, or else we may segfault. */
855
856 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
857 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
858
859 /* Rather than use the instruction generation helpers, we do it
860 * ourselves here to avoid the mess */
861
862 midgard_instruction ins = {
863 .type = TAG_ALU_4,
864 .ssa_args = {
865 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
866 .src1 = quirk_flipped_r24 ? src0 : src1,
867 .dest = dest,
868 }
869 };
870
871 nir_alu_src *nirmods[2] = { NULL };
872
873 if (nr_inputs == 2) {
874 nirmods[0] = &instr->src[0];
875 nirmods[1] = &instr->src[1];
876 } else if (nr_inputs == 1) {
877 nirmods[quirk_flipped_r24] = &instr->src[0];
878 } else {
879 assert(0);
880 }
881
882 /* These were lowered to a move, so apply the corresponding mod */
883
884 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
885 nir_alu_src *s = nirmods[quirk_flipped_r24];
886
887 if (instr->op == nir_op_fneg)
888 s->negate = !s->negate;
889
890 if (instr->op == nir_op_fabs)
891 s->abs = !s->abs;
892 }
893
894 bool is_int = midgard_is_integer_op(op);
895
896 midgard_vector_alu alu = {
897 .op = op,
898 .reg_mode = midgard_reg_mode_32,
899 .dest_override = midgard_dest_override_none,
900 .outmod = outmod,
901
902 /* Writemask only valid for non-SSA NIR */
903 .mask = expand_writemask((1 << nr_components) - 1),
904
905 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int)),
906 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int)),
907 };
908
909 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
910
911 if (!is_ssa)
912 alu.mask &= expand_writemask(instr->dest.write_mask);
913
914 ins.alu = alu;
915
916 /* Late fixup for emulated instructions */
917
918 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
919 /* Presently, our second argument is an inline #0 constant.
920 * Switch over to an embedded 1.0 constant (that can't fit
921 * inline, since we're 32-bit, not 16-bit like the inline
922 * constants) */
923
924 ins.ssa_args.inline_constant = false;
925 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
926 ins.has_constants = true;
927
928 if (instr->op == nir_op_b2f32) {
929 ins.constants[0] = 1.0f;
930 } else {
931 /* Type pun it into place */
932 uint32_t one = 0x1;
933 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
934 }
935
936 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
937 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
938 /* Lots of instructions need a 0 plonked in */
939 ins.ssa_args.inline_constant = false;
940 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
941 ins.has_constants = true;
942 ins.constants[0] = 0.0f;
943 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
944 } else if (instr->op == nir_op_inot) {
945 /* ~b = ~(b & b), so duplicate the source */
946 ins.ssa_args.src1 = ins.ssa_args.src0;
947 ins.alu.src2 = ins.alu.src1;
948 }
949
950 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
951 /* To avoid duplicating the lookup tables (probably), true LUT
952 * instructions can only operate as if they were scalars. Lower
953 * them here by changing the component. */
954
955 uint8_t original_swizzle[4];
956 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
957
958 for (int i = 0; i < nr_components; ++i) {
959 ins.alu.mask = (0x3) << (2 * i); /* Mask the associated component */
960
961 for (int j = 0; j < 4; ++j)
962 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
963
964 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int));
965 emit_mir_instruction(ctx, ins);
966 }
967 } else {
968 emit_mir_instruction(ctx, ins);
969 }
970 }
971
972 #undef ALU_CASE
973
974 static void
975 emit_uniform_read(compiler_context *ctx, unsigned dest, unsigned offset, nir_src *indirect_offset)
976 {
977 /* TODO: half-floats */
978
979 if (!indirect_offset && offset < ctx->uniform_cutoff) {
980 /* Fast path: For the first 16 uniforms, direct accesses are
981 * 0-cycle, since they're just a register fetch in the usual
982 * case. So, we alias the registers while we're still in
983 * SSA-space */
984
985 int reg_slot = 23 - offset;
986 alias_ssa(ctx, dest, SSA_FIXED_REGISTER(reg_slot));
987 } else {
988 /* Otherwise, read from the 'special' UBO to access
989 * higher-indexed uniforms, at a performance cost. More
990 * generally, we're emitting a UBO read instruction. */
991
992 midgard_instruction ins = m_ld_uniform_32(dest, offset);
993
994 /* TODO: Don't split */
995 ins.load_store.varying_parameters = (offset & 7) << 7;
996 ins.load_store.address = offset >> 3;
997
998 if (indirect_offset) {
999 emit_indirect_offset(ctx, indirect_offset);
1000 ins.load_store.unknown = 0x8700; /* xxx: what is this? */
1001 } else {
1002 ins.load_store.unknown = 0x1E00; /* xxx: what is this? */
1003 }
1004
1005 emit_mir_instruction(ctx, ins);
1006 }
1007 }
1008
1009 static void
1010 emit_varying_read(
1011 compiler_context *ctx,
1012 unsigned dest, unsigned offset,
1013 unsigned nr_comp, unsigned component,
1014 nir_src *indirect_offset)
1015 {
1016 /* XXX: Half-floats? */
1017 /* TODO: swizzle, mask */
1018
1019 midgard_instruction ins = m_ld_vary_32(dest, offset);
1020 ins.load_store.mask = (1 << nr_comp) - 1;
1021 ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component);
1022
1023 midgard_varying_parameter p = {
1024 .is_varying = 1,
1025 .interpolation = midgard_interp_default,
1026 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1027 };
1028
1029 unsigned u;
1030 memcpy(&u, &p, sizeof(p));
1031 ins.load_store.varying_parameters = u;
1032
1033 if (indirect_offset) {
1034 /* We need to add in the dynamic index, moved to r27.w */
1035 emit_indirect_offset(ctx, indirect_offset);
1036 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1037 } else {
1038 /* Just a direct load */
1039 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1040 }
1041
1042 emit_mir_instruction(ctx, ins);
1043 }
1044
1045 static void
1046 emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
1047 {
1048 /* First, pull out the destination */
1049 unsigned dest = nir_dest_index(ctx, &instr->dest);
1050
1051 /* Now, figure out which uniform this is */
1052 int sysval = midgard_nir_sysval_for_intrinsic(instr);
1053 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1054
1055 /* Sysvals are prefix uniforms */
1056 unsigned uniform = ((uintptr_t) val) - 1;
1057
1058 /* Emit the read itself -- this is never indirect */
1059 emit_uniform_read(ctx, dest, uniform, NULL);
1060 }
1061
1062 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1063 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1064 * generations have faster vectorized reads. This operation is for blend
1065 * shaders in particular; reading the tilebuffer from the fragment shader
1066 * remains an open problem. */
1067
1068 static void
1069 emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
1070 {
1071 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1072 ins.load_store.swizzle = 0; /* xxxx */
1073
1074 /* Read each component sequentially */
1075
1076 for (unsigned c = 0; c < 4; ++c) {
1077 ins.load_store.mask = (1 << c);
1078 ins.load_store.unknown = c;
1079 emit_mir_instruction(ctx, ins);
1080 }
1081
1082 /* vadd.u2f hr2, zext(hr2), #0 */
1083
1084 midgard_vector_alu_src alu_src = blank_alu_src;
1085 alu_src.mod = midgard_int_zero_extend;
1086 alu_src.half = true;
1087
1088 midgard_instruction u2f = {
1089 .type = TAG_ALU_4,
1090 .ssa_args = {
1091 .src0 = reg,
1092 .src1 = SSA_UNUSED_0,
1093 .dest = reg,
1094 .inline_constant = true
1095 },
1096 .alu = {
1097 .op = midgard_alu_op_u2f,
1098 .reg_mode = midgard_reg_mode_16,
1099 .dest_override = midgard_dest_override_none,
1100 .mask = 0xF,
1101 .src1 = vector_alu_srco_unsigned(alu_src),
1102 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1103 }
1104 };
1105
1106 emit_mir_instruction(ctx, u2f);
1107
1108 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1109
1110 alu_src.mod = 0;
1111
1112 midgard_instruction fmul = {
1113 .type = TAG_ALU_4,
1114 .inline_constant = _mesa_float_to_half(1.0 / 255.0),
1115 .ssa_args = {
1116 .src0 = reg,
1117 .dest = reg,
1118 .src1 = SSA_UNUSED_0,
1119 .inline_constant = true
1120 },
1121 .alu = {
1122 .op = midgard_alu_op_fmul,
1123 .reg_mode = midgard_reg_mode_32,
1124 .dest_override = midgard_dest_override_none,
1125 .outmod = midgard_outmod_sat,
1126 .mask = 0xFF,
1127 .src1 = vector_alu_srco_unsigned(alu_src),
1128 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1129 }
1130 };
1131
1132 emit_mir_instruction(ctx, fmul);
1133 }
1134
1135 static void
1136 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1137 {
1138 unsigned offset, reg;
1139
1140 switch (instr->intrinsic) {
1141 case nir_intrinsic_discard_if:
1142 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1143
1144 /* fallthrough */
1145
1146 case nir_intrinsic_discard: {
1147 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1148 struct midgard_instruction discard = v_branch(conditional, false);
1149 discard.branch.target_type = TARGET_DISCARD;
1150 emit_mir_instruction(ctx, discard);
1151
1152 ctx->can_discard = true;
1153 break;
1154 }
1155
1156 case nir_intrinsic_load_uniform:
1157 case nir_intrinsic_load_input:
1158 offset = nir_intrinsic_base(instr);
1159
1160 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1161 bool direct = nir_src_is_const(instr->src[0]);
1162
1163 if (direct) {
1164 offset += nir_src_as_uint(instr->src[0]);
1165 }
1166
1167 /* We may need to apply a fractional offset */
1168 int component = instr->intrinsic == nir_intrinsic_load_input ?
1169 nir_intrinsic_component(instr) : 0;
1170 reg = nir_dest_index(ctx, &instr->dest);
1171
1172 if (instr->intrinsic == nir_intrinsic_load_uniform && !ctx->is_blend) {
1173 emit_uniform_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL);
1174 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1175 emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL);
1176 } else if (ctx->is_blend) {
1177 /* For blend shaders, load the input color, which is
1178 * preloaded to r0 */
1179
1180 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1181 emit_mir_instruction(ctx, move);
1182 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1183 midgard_instruction ins = m_ld_attr_32(reg, offset);
1184 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1185 ins.load_store.mask = (1 << nr_comp) - 1;
1186 emit_mir_instruction(ctx, ins);
1187 } else {
1188 DBG("Unknown load\n");
1189 assert(0);
1190 }
1191
1192 break;
1193
1194 case nir_intrinsic_load_output:
1195 assert(nir_src_is_const(instr->src[0]));
1196 reg = nir_dest_index(ctx, &instr->dest);
1197
1198 if (ctx->is_blend) {
1199 /* TODO: MRT */
1200 emit_fb_read_blend_scalar(ctx, reg);
1201 } else {
1202 DBG("Unknown output load\n");
1203 assert(0);
1204 }
1205
1206 break;
1207
1208 case nir_intrinsic_load_blend_const_color_rgba: {
1209 assert(ctx->is_blend);
1210 reg = nir_dest_index(ctx, &instr->dest);
1211
1212 /* Blend constants are embedded directly in the shader and
1213 * patched in, so we use some magic routing */
1214
1215 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1216 ins.has_constants = true;
1217 ins.has_blend_constant = true;
1218 emit_mir_instruction(ctx, ins);
1219 break;
1220 }
1221
1222 case nir_intrinsic_store_output:
1223 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1224
1225 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1226
1227 reg = nir_src_index(ctx, &instr->src[0]);
1228
1229 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1230 /* gl_FragColor is not emitted with load/store
1231 * instructions. Instead, it gets plonked into
1232 * r0 at the end of the shader and we do the
1233 * framebuffer writeout dance. TODO: Defer
1234 * writes */
1235
1236 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1237 emit_mir_instruction(ctx, move);
1238
1239 /* Save the index we're writing to for later reference
1240 * in the epilogue */
1241
1242 ctx->fragment_output = reg;
1243 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1244 /* Varyings are written into one of two special
1245 * varying register, r26 or r27. The register itself is
1246 * selected as the register in the st_vary instruction,
1247 * minus the base of 26. E.g. write into r27 and then
1248 * call st_vary(1) */
1249
1250 midgard_instruction ins = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(26));
1251 emit_mir_instruction(ctx, ins);
1252
1253 /* We should have been vectorized. That also lets us
1254 * ignore the mask. because the mask component on
1255 * st_vary is (as far as I can tell) ignored [the blob
1256 * sets it to zero] */
1257 assert(nir_intrinsic_component(instr) == 0);
1258
1259 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset);
1260 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1261 emit_mir_instruction(ctx, st);
1262 } else {
1263 DBG("Unknown store\n");
1264 assert(0);
1265 }
1266
1267 break;
1268
1269 case nir_intrinsic_load_alpha_ref_float:
1270 assert(instr->dest.is_ssa);
1271
1272 float ref_value = ctx->alpha_ref;
1273
1274 float *v = ralloc_array(NULL, float, 4);
1275 memcpy(v, &ref_value, sizeof(float));
1276 _mesa_hash_table_u64_insert(ctx->ssa_constants, instr->dest.ssa.index + 1, v);
1277 break;
1278
1279 case nir_intrinsic_load_viewport_scale:
1280 case nir_intrinsic_load_viewport_offset:
1281 emit_sysval_read(ctx, instr);
1282 break;
1283
1284 default:
1285 printf ("Unhandled intrinsic\n");
1286 assert(0);
1287 break;
1288 }
1289 }
1290
1291 static unsigned
1292 midgard_tex_format(enum glsl_sampler_dim dim)
1293 {
1294 switch (dim) {
1295 case GLSL_SAMPLER_DIM_2D:
1296 case GLSL_SAMPLER_DIM_EXTERNAL:
1297 return TEXTURE_2D;
1298
1299 case GLSL_SAMPLER_DIM_3D:
1300 return TEXTURE_3D;
1301
1302 case GLSL_SAMPLER_DIM_CUBE:
1303 return TEXTURE_CUBE;
1304
1305 default:
1306 DBG("Unknown sampler dim type\n");
1307 assert(0);
1308 return 0;
1309 }
1310 }
1311
1312 static void
1313 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1314 {
1315 /* TODO */
1316 //assert (!instr->sampler);
1317 //assert (!instr->texture_array_size);
1318 assert (instr->op == nir_texop_tex);
1319
1320 /* Allocate registers via a round robin scheme to alternate between the two registers */
1321 int reg = ctx->texture_op_count & 1;
1322 int in_reg = reg, out_reg = reg;
1323
1324 /* Make room for the reg */
1325
1326 if (ctx->texture_index[reg] > -1)
1327 unalias_ssa(ctx, ctx->texture_index[reg]);
1328
1329 int texture_index = instr->texture_index;
1330 int sampler_index = texture_index;
1331
1332 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1333 switch (instr->src[i].src_type) {
1334 case nir_tex_src_coord: {
1335 int index = nir_src_index(ctx, &instr->src[i].src);
1336
1337 midgard_vector_alu_src alu_src = blank_alu_src;
1338
1339 int reg = SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + in_reg);
1340
1341 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1342 /* For cubemaps, we need to load coords into
1343 * special r27, and then use a special ld/st op
1344 * to copy into the texture register */
1345
1346 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X);
1347
1348 midgard_instruction move = v_fmov(index, alu_src, SSA_FIXED_REGISTER(27));
1349 emit_mir_instruction(ctx, move);
1350
1351 midgard_instruction st = m_st_cubemap_coords(reg, 0);
1352 st.load_store.unknown = 0x24; /* XXX: What is this? */
1353 st.load_store.mask = 0x3; /* xy? */
1354 st.load_store.swizzle = alu_src.swizzle;
1355 emit_mir_instruction(ctx, st);
1356
1357 } else {
1358 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X);
1359
1360 midgard_instruction ins = v_fmov(index, alu_src, reg);
1361 emit_mir_instruction(ctx, ins);
1362 }
1363
1364 break;
1365 }
1366
1367 default: {
1368 DBG("Unknown source type\n");
1369 //assert(0);
1370 break;
1371 }
1372 }
1373 }
1374
1375 /* No helper to build texture words -- we do it all here */
1376 midgard_instruction ins = {
1377 .type = TAG_TEXTURE_4,
1378 .texture = {
1379 .op = TEXTURE_OP_NORMAL,
1380 .format = midgard_tex_format(instr->sampler_dim),
1381 .texture_handle = texture_index,
1382 .sampler_handle = sampler_index,
1383
1384 /* TODO: Regalloc it in */
1385 .swizzle = SWIZZLE_XYZW,
1386 .mask = 0xF,
1387
1388 /* TODO: half */
1389 .in_reg_full = 1,
1390 .in_reg_swizzle = SWIZZLE_XYZW,
1391 .out_full = 1,
1392
1393 /* Always 1 */
1394 .unknown7 = 1,
1395
1396 /* Assume we can continue; hint it out later */
1397 .cont = 1,
1398 }
1399 };
1400
1401 /* Set registers to read and write from the same place */
1402 ins.texture.in_reg_select = in_reg;
1403 ins.texture.out_reg_select = out_reg;
1404
1405 emit_mir_instruction(ctx, ins);
1406
1407 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1408
1409 int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest);
1410 alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg));
1411 ctx->texture_index[reg] = o_index;
1412
1413 midgard_instruction ins2 = v_fmov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index);
1414 emit_mir_instruction(ctx, ins2);
1415
1416 /* Used for .cont and .last hinting */
1417 ctx->texture_op_count++;
1418 }
1419
1420 static void
1421 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1422 {
1423 switch (instr->type) {
1424 case nir_jump_break: {
1425 /* Emit a branch out of the loop */
1426 struct midgard_instruction br = v_branch(false, false);
1427 br.branch.target_type = TARGET_BREAK;
1428 br.branch.target_break = ctx->current_loop_depth;
1429 emit_mir_instruction(ctx, br);
1430
1431 DBG("break..\n");
1432 break;
1433 }
1434
1435 default:
1436 DBG("Unknown jump type %d\n", instr->type);
1437 break;
1438 }
1439 }
1440
1441 static void
1442 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1443 {
1444 switch (instr->type) {
1445 case nir_instr_type_load_const:
1446 emit_load_const(ctx, nir_instr_as_load_const(instr));
1447 break;
1448
1449 case nir_instr_type_intrinsic:
1450 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1451 break;
1452
1453 case nir_instr_type_alu:
1454 emit_alu(ctx, nir_instr_as_alu(instr));
1455 break;
1456
1457 case nir_instr_type_tex:
1458 emit_tex(ctx, nir_instr_as_tex(instr));
1459 break;
1460
1461 case nir_instr_type_jump:
1462 emit_jump(ctx, nir_instr_as_jump(instr));
1463 break;
1464
1465 case nir_instr_type_ssa_undef:
1466 /* Spurious */
1467 break;
1468
1469 default:
1470 DBG("Unhandled instruction type\n");
1471 break;
1472 }
1473 }
1474
1475
1476 /* ALU instructions can inline or embed constants, which decreases register
1477 * pressure and saves space. */
1478
1479 #define CONDITIONAL_ATTACH(src) { \
1480 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1481 \
1482 if (entry) { \
1483 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1484 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1485 } \
1486 }
1487
1488 static void
1489 inline_alu_constants(compiler_context *ctx)
1490 {
1491 mir_foreach_instr(ctx, alu) {
1492 /* Other instructions cannot inline constants */
1493 if (alu->type != TAG_ALU_4) continue;
1494
1495 /* If there is already a constant here, we can do nothing */
1496 if (alu->has_constants) continue;
1497
1498 /* It makes no sense to inline constants on a branch */
1499 if (alu->compact_branch || alu->prepacked_branch) continue;
1500
1501 CONDITIONAL_ATTACH(src0);
1502
1503 if (!alu->has_constants) {
1504 CONDITIONAL_ATTACH(src1)
1505 } else if (!alu->inline_constant) {
1506 /* Corner case: _two_ vec4 constants, for instance with a
1507 * csel. For this case, we can only use a constant
1508 * register for one, we'll have to emit a move for the
1509 * other. Note, if both arguments are constants, then
1510 * necessarily neither argument depends on the value of
1511 * any particular register. As the destination register
1512 * will be wiped, that means we can spill the constant
1513 * to the destination register.
1514 */
1515
1516 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
1517 unsigned scratch = alu->ssa_args.dest;
1518
1519 if (entry) {
1520 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
1521 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
1522
1523 /* Force a break XXX Defer r31 writes */
1524 ins.unit = UNIT_VLUT;
1525
1526 /* Set the source */
1527 alu->ssa_args.src1 = scratch;
1528
1529 /* Inject us -before- the last instruction which set r31 */
1530 mir_insert_instruction_before(mir_prev_op(alu), ins);
1531 }
1532 }
1533 }
1534 }
1535
1536 /* Midgard supports two types of constants, embedded constants (128-bit) and
1537 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1538 * constants can be demoted to inline constants, for space savings and
1539 * sometimes a performance boost */
1540
1541 static void
1542 embedded_to_inline_constant(compiler_context *ctx)
1543 {
1544 mir_foreach_instr(ctx, ins) {
1545 if (!ins->has_constants) continue;
1546
1547 if (ins->ssa_args.inline_constant) continue;
1548
1549 /* Blend constants must not be inlined by definition */
1550 if (ins->has_blend_constant) continue;
1551
1552 /* src1 cannot be an inline constant due to encoding
1553 * restrictions. So, if possible we try to flip the arguments
1554 * in that case */
1555
1556 int op = ins->alu.op;
1557
1558 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1559 switch (op) {
1560 /* These ops require an operational change to flip
1561 * their arguments TODO */
1562 case midgard_alu_op_flt:
1563 case midgard_alu_op_fle:
1564 case midgard_alu_op_ilt:
1565 case midgard_alu_op_ile:
1566 case midgard_alu_op_fcsel:
1567 case midgard_alu_op_icsel:
1568 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
1569 default:
1570 break;
1571 }
1572
1573 if (alu_opcode_props[op].props & OP_COMMUTES) {
1574 /* Flip the SSA numbers */
1575 ins->ssa_args.src0 = ins->ssa_args.src1;
1576 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1577
1578 /* And flip the modifiers */
1579
1580 unsigned src_temp;
1581
1582 src_temp = ins->alu.src2;
1583 ins->alu.src2 = ins->alu.src1;
1584 ins->alu.src1 = src_temp;
1585 }
1586 }
1587
1588 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1589 /* Extract the source information */
1590
1591 midgard_vector_alu_src *src;
1592 int q = ins->alu.src2;
1593 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1594 src = m;
1595
1596 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1597 int component = src->swizzle & 3;
1598
1599 /* Scale constant appropriately, if we can legally */
1600 uint16_t scaled_constant = 0;
1601
1602 if (midgard_is_integer_op(op)) {
1603 unsigned int *iconstants = (unsigned int *) ins->constants;
1604 scaled_constant = (uint16_t) iconstants[component];
1605
1606 /* Constant overflow after resize */
1607 if (scaled_constant != iconstants[component])
1608 continue;
1609 } else {
1610 float original = (float) ins->constants[component];
1611 scaled_constant = _mesa_float_to_half(original);
1612
1613 /* Check for loss of precision. If this is
1614 * mediump, we don't care, but for a highp
1615 * shader, we need to pay attention. NIR
1616 * doesn't yet tell us which mode we're in!
1617 * Practically this prevents most constants
1618 * from being inlined, sadly. */
1619
1620 float fp32 = _mesa_half_to_float(scaled_constant);
1621
1622 if (fp32 != original)
1623 continue;
1624 }
1625
1626 /* We don't know how to handle these with a constant */
1627
1628 if (src->mod || src->half || src->rep_low || src->rep_high) {
1629 DBG("Bailing inline constant...\n");
1630 continue;
1631 }
1632
1633 /* Make sure that the constant is not itself a
1634 * vector by checking if all accessed values
1635 * (by the swizzle) are the same. */
1636
1637 uint32_t *cons = (uint32_t *) ins->constants;
1638 uint32_t value = cons[component];
1639
1640 bool is_vector = false;
1641 unsigned mask = effective_writemask(&ins->alu);
1642
1643 for (int c = 1; c < 4; ++c) {
1644 /* We only care if this component is actually used */
1645 if (!(mask & (1 << c)))
1646 continue;
1647
1648 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
1649
1650 if (test != value) {
1651 is_vector = true;
1652 break;
1653 }
1654 }
1655
1656 if (is_vector)
1657 continue;
1658
1659 /* Get rid of the embedded constant */
1660 ins->has_constants = false;
1661 ins->ssa_args.src1 = SSA_UNUSED_0;
1662 ins->ssa_args.inline_constant = true;
1663 ins->inline_constant = scaled_constant;
1664 }
1665 }
1666 }
1667
1668 /* Map normal SSA sources to other SSA sources / fixed registers (like
1669 * uniforms) */
1670
1671 static void
1672 map_ssa_to_alias(compiler_context *ctx, int *ref)
1673 {
1674 /* Sign is used quite deliberately for unused */
1675 if (*ref < 0)
1676 return;
1677
1678 unsigned int alias = (uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_to_alias, *ref + 1);
1679
1680 if (alias) {
1681 /* Remove entry in leftovers to avoid a redunant fmov */
1682
1683 struct set_entry *leftover = _mesa_set_search(ctx->leftover_ssa_to_alias, ((void *) (uintptr_t) (*ref + 1)));
1684
1685 if (leftover)
1686 _mesa_set_remove(ctx->leftover_ssa_to_alias, leftover);
1687
1688 /* Assign the alias map */
1689 *ref = alias - 1;
1690 return;
1691 }
1692 }
1693
1694 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1695 * texture pipeline */
1696
1697 static bool
1698 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
1699 {
1700 bool progress = false;
1701
1702 mir_foreach_instr_in_block_safe(block, ins) {
1703 if (ins->type != TAG_ALU_4) continue;
1704 if (ins->compact_branch) continue;
1705
1706 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
1707 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
1708
1709 mir_remove_instruction(ins);
1710 progress = true;
1711 }
1712
1713 return progress;
1714 }
1715
1716 /* Dead code elimination for branches at the end of a block - only one branch
1717 * per block is legal semantically */
1718
1719 static void
1720 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
1721 {
1722 bool branched = false;
1723
1724 mir_foreach_instr_in_block_safe(block, ins) {
1725 if (!midgard_is_branch_unit(ins->unit)) continue;
1726
1727 /* We ignore prepacked branches since the fragment epilogue is
1728 * just generally special */
1729 if (ins->prepacked_branch) continue;
1730
1731 /* Discards are similarly special and may not correspond to the
1732 * end of a block */
1733
1734 if (ins->branch.target_type == TARGET_DISCARD) continue;
1735
1736 if (branched) {
1737 /* We already branched, so this is dead */
1738 mir_remove_instruction(ins);
1739 }
1740
1741 branched = true;
1742 }
1743 }
1744
1745 static bool
1746 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
1747 {
1748 /* abs or neg */
1749 if (!is_int && src.mod) return true;
1750
1751 /* swizzle */
1752 for (unsigned c = 0; c < 4; ++c) {
1753 if (!(mask & (1 << c))) continue;
1754 if (((src.swizzle >> (2*c)) & 3) != c) return true;
1755 }
1756
1757 return false;
1758 }
1759
1760 static bool
1761 mir_nontrivial_source2_mod(midgard_instruction *ins)
1762 {
1763 unsigned mask = squeeze_writemask(ins->alu.mask);
1764 bool is_int = midgard_is_integer_op(ins->alu.op);
1765
1766 midgard_vector_alu_src src2 =
1767 vector_alu_from_unsigned(ins->alu.src2);
1768
1769 return mir_nontrivial_mod(src2, is_int, mask);
1770 }
1771
1772 static bool
1773 mir_nontrivial_outmod(midgard_instruction *ins)
1774 {
1775 bool is_int = midgard_is_integer_op(ins->alu.op);
1776 unsigned mod = ins->alu.outmod;
1777
1778 if (is_int)
1779 return mod != midgard_outmod_int_wrap;
1780 else
1781 return mod != midgard_outmod_none;
1782 }
1783
1784 static bool
1785 midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
1786 {
1787 bool progress = false;
1788
1789 mir_foreach_instr_in_block_safe(block, ins) {
1790 if (ins->type != TAG_ALU_4) continue;
1791 if (!OP_IS_MOVE(ins->alu.op)) continue;
1792
1793 unsigned from = ins->ssa_args.src1;
1794 unsigned to = ins->ssa_args.dest;
1795
1796 /* We only work on pure SSA */
1797
1798 if (to >= SSA_FIXED_MINIMUM) continue;
1799 if (from >= SSA_FIXED_MINIMUM) continue;
1800 if (to >= ctx->func->impl->ssa_alloc) continue;
1801 if (from >= ctx->func->impl->ssa_alloc) continue;
1802
1803 /* Constant propagation is not handled here, either */
1804 if (ins->ssa_args.inline_constant) continue;
1805 if (ins->has_constants) continue;
1806
1807 if (mir_nontrivial_source2_mod(ins)) continue;
1808 if (mir_nontrivial_outmod(ins)) continue;
1809
1810 /* We're clear -- rewrite */
1811 mir_rewrite_index_src(ctx, to, from);
1812 mir_remove_instruction(ins);
1813 progress |= true;
1814 }
1815
1816 return progress;
1817 }
1818
1819 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1820 * the move can be propagated away entirely */
1821
1822 static bool
1823 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
1824 {
1825 /* Nothing to do */
1826 if (comp == midgard_outmod_none)
1827 return true;
1828
1829 if (*outmod == midgard_outmod_none) {
1830 *outmod = comp;
1831 return true;
1832 }
1833
1834 /* TODO: Compose rules */
1835 return false;
1836 }
1837
1838 static bool
1839 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
1840 {
1841 bool progress = false;
1842
1843 mir_foreach_instr_in_block_safe(block, ins) {
1844 if (ins->type != TAG_ALU_4) continue;
1845 if (ins->alu.op != midgard_alu_op_fmov) continue;
1846 if (ins->alu.outmod != midgard_outmod_pos) continue;
1847
1848 /* TODO: Registers? */
1849 unsigned src = ins->ssa_args.src1;
1850 if (src >= ctx->func->impl->ssa_alloc) continue;
1851 assert(!mir_has_multiple_writes(ctx, src));
1852
1853 /* There might be a source modifier, too */
1854 if (mir_nontrivial_source2_mod(ins)) continue;
1855
1856 /* Backpropagate the modifier */
1857 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1858 if (v->type != TAG_ALU_4) continue;
1859 if (v->ssa_args.dest != src) continue;
1860
1861 /* Can we even take a float outmod? */
1862 if (midgard_is_integer_out_op(v->alu.op)) continue;
1863
1864 midgard_outmod_float temp = v->alu.outmod;
1865 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
1866
1867 /* Throw in the towel.. */
1868 if (!progress) break;
1869
1870 /* Otherwise, transfer the modifier */
1871 v->alu.outmod = temp;
1872 ins->alu.outmod = midgard_outmod_none;
1873
1874 break;
1875 }
1876 }
1877
1878 return progress;
1879 }
1880
1881 static bool
1882 midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
1883 {
1884 bool progress = false;
1885
1886 mir_foreach_instr_in_block_safe(block, ins) {
1887 if (ins->type != TAG_ALU_4) continue;
1888 if (!OP_IS_MOVE(ins->alu.op)) continue;
1889
1890 unsigned from = ins->ssa_args.src1;
1891 unsigned to = ins->ssa_args.dest;
1892
1893 /* Make sure it's simple enough for us to handle */
1894
1895 if (from >= SSA_FIXED_MINIMUM) continue;
1896 if (from >= ctx->func->impl->ssa_alloc) continue;
1897 if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
1898 if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
1899
1900 bool eliminated = false;
1901
1902 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1903 /* The texture registers are not SSA so be careful.
1904 * Conservatively, just stop if we hit a texture op
1905 * (even if it may not write) to where we are */
1906
1907 if (v->type != TAG_ALU_4)
1908 break;
1909
1910 if (v->ssa_args.dest == from) {
1911 /* We don't want to track partial writes ... */
1912 if (v->alu.mask == 0xF) {
1913 v->ssa_args.dest = to;
1914 eliminated = true;
1915 }
1916
1917 break;
1918 }
1919 }
1920
1921 if (eliminated)
1922 mir_remove_instruction(ins);
1923
1924 progress |= eliminated;
1925 }
1926
1927 return progress;
1928 }
1929
1930 /* The following passes reorder MIR instructions to enable better scheduling */
1931
1932 static void
1933 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
1934 {
1935 mir_foreach_instr_in_block_safe(block, ins) {
1936 if (ins->type != TAG_LOAD_STORE_4) continue;
1937
1938 /* We've found a load/store op. Check if next is also load/store. */
1939 midgard_instruction *next_op = mir_next_op(ins);
1940 if (&next_op->link != &block->instructions) {
1941 if (next_op->type == TAG_LOAD_STORE_4) {
1942 /* If so, we're done since we're a pair */
1943 ins = mir_next_op(ins);
1944 continue;
1945 }
1946
1947 /* Maximum search distance to pair, to avoid register pressure disasters */
1948 int search_distance = 8;
1949
1950 /* Otherwise, we have an orphaned load/store -- search for another load */
1951 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
1952 /* Terminate search if necessary */
1953 if (!(search_distance--)) break;
1954
1955 if (c->type != TAG_LOAD_STORE_4) continue;
1956
1957 /* Stores cannot be reordered, since they have
1958 * dependencies. For the same reason, indirect
1959 * loads cannot be reordered as their index is
1960 * loaded in r27.w */
1961
1962 if (OP_IS_STORE(c->load_store.op)) continue;
1963
1964 /* It appears the 0x800 bit is set whenever a
1965 * load is direct, unset when it is indirect.
1966 * Skip indirect loads. */
1967
1968 if (!(c->load_store.unknown & 0x800)) continue;
1969
1970 /* We found one! Move it up to pair and remove it from the old location */
1971
1972 mir_insert_instruction_before(ins, *c);
1973 mir_remove_instruction(c);
1974
1975 break;
1976 }
1977 }
1978 }
1979 }
1980
1981 /* If there are leftovers after the below pass, emit actual fmov
1982 * instructions for the slow-but-correct path */
1983
1984 static void
1985 emit_leftover_move(compiler_context *ctx)
1986 {
1987 set_foreach(ctx->leftover_ssa_to_alias, leftover) {
1988 int base = ((uintptr_t) leftover->key) - 1;
1989 int mapped = base;
1990
1991 map_ssa_to_alias(ctx, &mapped);
1992 EMIT(fmov, mapped, blank_alu_src, base);
1993 }
1994 }
1995
1996 static void
1997 actualise_ssa_to_alias(compiler_context *ctx)
1998 {
1999 mir_foreach_instr(ctx, ins) {
2000 map_ssa_to_alias(ctx, &ins->ssa_args.src0);
2001 map_ssa_to_alias(ctx, &ins->ssa_args.src1);
2002 }
2003
2004 emit_leftover_move(ctx);
2005 }
2006
2007 static void
2008 emit_fragment_epilogue(compiler_context *ctx)
2009 {
2010 /* Special case: writing out constants requires us to include the move
2011 * explicitly now, so shove it into r0 */
2012
2013 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, ctx->fragment_output + 1);
2014
2015 if (constant_value) {
2016 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(0));
2017 attach_constants(ctx, &ins, constant_value, ctx->fragment_output + 1);
2018 emit_mir_instruction(ctx, ins);
2019 }
2020
2021 /* Perform the actual fragment writeout. We have two writeout/branch
2022 * instructions, forming a loop until writeout is successful as per the
2023 * docs. TODO: gl_FragDepth */
2024
2025 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2026 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2027 }
2028
2029 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2030 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2031 * with the int8 analogue to the fragment epilogue */
2032
2033 static void
2034 emit_blend_epilogue(compiler_context *ctx)
2035 {
2036 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2037
2038 midgard_instruction scale = {
2039 .type = TAG_ALU_4,
2040 .unit = UNIT_VMUL,
2041 .inline_constant = _mesa_float_to_half(255.0),
2042 .ssa_args = {
2043 .src0 = SSA_FIXED_REGISTER(0),
2044 .src1 = SSA_UNUSED_0,
2045 .dest = SSA_FIXED_REGISTER(24),
2046 .inline_constant = true
2047 },
2048 .alu = {
2049 .op = midgard_alu_op_fmul,
2050 .reg_mode = midgard_reg_mode_32,
2051 .dest_override = midgard_dest_override_lower,
2052 .mask = 0xFF,
2053 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2054 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2055 }
2056 };
2057
2058 emit_mir_instruction(ctx, scale);
2059
2060 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2061
2062 midgard_vector_alu_src alu_src = blank_alu_src;
2063 alu_src.half = true;
2064
2065 midgard_instruction f2u8 = {
2066 .type = TAG_ALU_4,
2067 .ssa_args = {
2068 .src0 = SSA_FIXED_REGISTER(24),
2069 .src1 = SSA_UNUSED_0,
2070 .dest = SSA_FIXED_REGISTER(0),
2071 .inline_constant = true
2072 },
2073 .alu = {
2074 .op = midgard_alu_op_f2u8,
2075 .reg_mode = midgard_reg_mode_16,
2076 .dest_override = midgard_dest_override_lower,
2077 .outmod = midgard_outmod_pos,
2078 .mask = 0xF,
2079 .src1 = vector_alu_srco_unsigned(alu_src),
2080 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2081 }
2082 };
2083
2084 emit_mir_instruction(ctx, f2u8);
2085
2086 /* vmul.imov.quarter r0, r0, r0 */
2087
2088 midgard_instruction imov_8 = {
2089 .type = TAG_ALU_4,
2090 .ssa_args = {
2091 .src0 = SSA_UNUSED_1,
2092 .src1 = SSA_FIXED_REGISTER(0),
2093 .dest = SSA_FIXED_REGISTER(0),
2094 },
2095 .alu = {
2096 .op = midgard_alu_op_imov,
2097 .reg_mode = midgard_reg_mode_8,
2098 .dest_override = midgard_dest_override_none,
2099 .outmod = midgard_outmod_int_wrap,
2100 .mask = 0xFF,
2101 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2102 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2103 }
2104 };
2105
2106 /* Emit branch epilogue with the 8-bit move as the source */
2107
2108 emit_mir_instruction(ctx, imov_8);
2109 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2110
2111 emit_mir_instruction(ctx, imov_8);
2112 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2113 }
2114
2115 static midgard_block *
2116 emit_block(compiler_context *ctx, nir_block *block)
2117 {
2118 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2119 list_addtail(&this_block->link, &ctx->blocks);
2120
2121 this_block->is_scheduled = false;
2122 ++ctx->block_count;
2123
2124 ctx->texture_index[0] = -1;
2125 ctx->texture_index[1] = -1;
2126
2127 /* Add us as a successor to the block we are following */
2128 if (ctx->current_block)
2129 midgard_block_add_successor(ctx->current_block, this_block);
2130
2131 /* Set up current block */
2132 list_inithead(&this_block->instructions);
2133 ctx->current_block = this_block;
2134
2135 nir_foreach_instr(instr, block) {
2136 emit_instr(ctx, instr);
2137 ++ctx->instruction_count;
2138 }
2139
2140 inline_alu_constants(ctx);
2141 embedded_to_inline_constant(ctx);
2142
2143 /* Perform heavylifting for aliasing */
2144 actualise_ssa_to_alias(ctx);
2145
2146 midgard_pair_load_store(ctx, this_block);
2147
2148 /* Append fragment shader epilogue (value writeout) */
2149 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2150 if (block == nir_impl_last_block(ctx->func->impl)) {
2151 if (ctx->is_blend)
2152 emit_blend_epilogue(ctx);
2153 else
2154 emit_fragment_epilogue(ctx);
2155 }
2156 }
2157
2158 if (block == nir_start_block(ctx->func->impl))
2159 ctx->initial_block = this_block;
2160
2161 if (block == nir_impl_last_block(ctx->func->impl))
2162 ctx->final_block = this_block;
2163
2164 /* Allow the next control flow to access us retroactively, for
2165 * branching etc */
2166 ctx->current_block = this_block;
2167
2168 /* Document the fallthrough chain */
2169 ctx->previous_source_block = this_block;
2170
2171 return this_block;
2172 }
2173
2174 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2175
2176 static void
2177 emit_if(struct compiler_context *ctx, nir_if *nif)
2178 {
2179 /* Conditional branches expect the condition in r31.w; emit a move for
2180 * that in the _previous_ block (which is the current block). */
2181 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2182
2183 /* Speculatively emit the branch, but we can't fill it in until later */
2184 EMIT(branch, true, true);
2185 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2186
2187 /* Emit the two subblocks */
2188 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2189
2190 /* Emit a jump from the end of the then block to the end of the else */
2191 EMIT(branch, false, false);
2192 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2193
2194 /* Emit second block, and check if it's empty */
2195
2196 int else_idx = ctx->block_count;
2197 int count_in = ctx->instruction_count;
2198 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2199 int after_else_idx = ctx->block_count;
2200
2201 /* Now that we have the subblocks emitted, fix up the branches */
2202
2203 assert(then_block);
2204 assert(else_block);
2205
2206 if (ctx->instruction_count == count_in) {
2207 /* The else block is empty, so don't emit an exit jump */
2208 mir_remove_instruction(then_exit);
2209 then_branch->branch.target_block = after_else_idx;
2210 } else {
2211 then_branch->branch.target_block = else_idx;
2212 then_exit->branch.target_block = after_else_idx;
2213 }
2214 }
2215
2216 static void
2217 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2218 {
2219 /* Remember where we are */
2220 midgard_block *start_block = ctx->current_block;
2221
2222 /* Allocate a loop number, growing the current inner loop depth */
2223 int loop_idx = ++ctx->current_loop_depth;
2224
2225 /* Get index from before the body so we can loop back later */
2226 int start_idx = ctx->block_count;
2227
2228 /* Emit the body itself */
2229 emit_cf_list(ctx, &nloop->body);
2230
2231 /* Branch back to loop back */
2232 struct midgard_instruction br_back = v_branch(false, false);
2233 br_back.branch.target_block = start_idx;
2234 emit_mir_instruction(ctx, br_back);
2235
2236 /* Mark down that branch in the graph. Note that we're really branching
2237 * to the block *after* we started in. TODO: Why doesn't the branch
2238 * itself have an off-by-one then...? */
2239 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2240
2241 /* Find the index of the block about to follow us (note: we don't add
2242 * one; blocks are 0-indexed so we get a fencepost problem) */
2243 int break_block_idx = ctx->block_count;
2244
2245 /* Fix up the break statements we emitted to point to the right place,
2246 * now that we can allocate a block number for them */
2247
2248 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2249 mir_foreach_instr_in_block(block, ins) {
2250 if (ins->type != TAG_ALU_4) continue;
2251 if (!ins->compact_branch) continue;
2252 if (ins->prepacked_branch) continue;
2253
2254 /* We found a branch -- check the type to see if we need to do anything */
2255 if (ins->branch.target_type != TARGET_BREAK) continue;
2256
2257 /* It's a break! Check if it's our break */
2258 if (ins->branch.target_break != loop_idx) continue;
2259
2260 /* Okay, cool, we're breaking out of this loop.
2261 * Rewrite from a break to a goto */
2262
2263 ins->branch.target_type = TARGET_GOTO;
2264 ins->branch.target_block = break_block_idx;
2265 }
2266 }
2267
2268 /* Now that we've finished emitting the loop, free up the depth again
2269 * so we play nice with recursion amid nested loops */
2270 --ctx->current_loop_depth;
2271 }
2272
2273 static midgard_block *
2274 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2275 {
2276 midgard_block *start_block = NULL;
2277
2278 foreach_list_typed(nir_cf_node, node, node, list) {
2279 switch (node->type) {
2280 case nir_cf_node_block: {
2281 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2282
2283 if (!start_block)
2284 start_block = block;
2285
2286 break;
2287 }
2288
2289 case nir_cf_node_if:
2290 emit_if(ctx, nir_cf_node_as_if(node));
2291 break;
2292
2293 case nir_cf_node_loop:
2294 emit_loop(ctx, nir_cf_node_as_loop(node));
2295 break;
2296
2297 case nir_cf_node_function:
2298 assert(0);
2299 break;
2300 }
2301 }
2302
2303 return start_block;
2304 }
2305
2306 /* Due to lookahead, we need to report the first tag executed in the command
2307 * stream and in branch targets. An initial block might be empty, so iterate
2308 * until we find one that 'works' */
2309
2310 static unsigned
2311 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2312 {
2313 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2314
2315 unsigned first_tag = 0;
2316
2317 do {
2318 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
2319
2320 if (initial_bundle) {
2321 first_tag = initial_bundle->tag;
2322 break;
2323 }
2324
2325 /* Initial block is empty, try the next block */
2326 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
2327 } while(initial_block != NULL);
2328
2329 assert(first_tag);
2330 return first_tag;
2331 }
2332
2333 int
2334 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend)
2335 {
2336 struct util_dynarray *compiled = &program->compiled;
2337
2338 midgard_debug = debug_get_option_midgard_debug();
2339
2340 compiler_context ictx = {
2341 .nir = nir,
2342 .stage = nir->info.stage,
2343
2344 .is_blend = is_blend,
2345 .blend_constant_offset = -1,
2346
2347 .alpha_ref = program->alpha_ref
2348 };
2349
2350 compiler_context *ctx = &ictx;
2351
2352 /* TODO: Decide this at runtime */
2353 ctx->uniform_cutoff = 8;
2354
2355 /* Initialize at a global (not block) level hash tables */
2356
2357 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2358 ctx->ssa_to_alias = _mesa_hash_table_u64_create(NULL);
2359 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2360 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2361 ctx->leftover_ssa_to_alias = _mesa_set_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
2362
2363 /* Record the varying mapping for the command stream's bookkeeping */
2364
2365 struct exec_list *varyings =
2366 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2367
2368 unsigned max_varying = 0;
2369 nir_foreach_variable(var, varyings) {
2370 unsigned loc = var->data.driver_location;
2371 unsigned sz = glsl_type_size(var->type, FALSE);
2372
2373 for (int c = loc; c < (loc + sz); ++c) {
2374 program->varyings[c] = var->data.location;
2375 max_varying = MAX2(max_varying, c);
2376 }
2377 }
2378
2379 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2380 * (so we don't accidentally duplicate the epilogue since mesa/st has
2381 * messed with our I/O quite a bit already) */
2382
2383 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2384
2385 if (ctx->stage == MESA_SHADER_VERTEX)
2386 NIR_PASS_V(nir, nir_lower_viewport_transform);
2387
2388 NIR_PASS_V(nir, nir_lower_var_copies);
2389 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2390 NIR_PASS_V(nir, nir_split_var_copies);
2391 NIR_PASS_V(nir, nir_lower_var_copies);
2392 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2393 NIR_PASS_V(nir, nir_lower_var_copies);
2394 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2395
2396 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2397
2398 /* Optimisation passes */
2399
2400 optimise_nir(nir);
2401
2402 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2403 nir_print_shader(nir, stdout);
2404 }
2405
2406 /* Assign sysvals and counts, now that we're sure
2407 * (post-optimisation) */
2408
2409 midgard_nir_assign_sysvals(ctx, nir);
2410
2411 program->uniform_count = nir->num_uniforms;
2412 program->sysval_count = ctx->sysval_count;
2413 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2414
2415 program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_inputs : 0;
2416 program->varying_count = max_varying + 1; /* Fencepost off-by-one */
2417
2418 nir_foreach_function(func, nir) {
2419 if (!func->impl)
2420 continue;
2421
2422 list_inithead(&ctx->blocks);
2423 ctx->block_count = 0;
2424 ctx->func = func;
2425
2426 emit_cf_list(ctx, &func->impl->body);
2427 emit_block(ctx, func->impl->end_block);
2428
2429 break; /* TODO: Multi-function shaders */
2430 }
2431
2432 util_dynarray_init(compiled, NULL);
2433
2434 /* MIR-level optimizations */
2435
2436 bool progress = false;
2437
2438 do {
2439 progress = false;
2440
2441 mir_foreach_block(ctx, block) {
2442 progress |= midgard_opt_pos_propagate(ctx, block);
2443 progress |= midgard_opt_copy_prop(ctx, block);
2444 progress |= midgard_opt_copy_prop_tex(ctx, block);
2445 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2446 }
2447 } while (progress);
2448
2449 /* Nested control-flow can result in dead branches at the end of the
2450 * block. This messes with our analysis and is just dead code, so cull
2451 * them */
2452 mir_foreach_block(ctx, block) {
2453 midgard_opt_cull_dead_branch(ctx, block);
2454 }
2455
2456 /* Schedule! */
2457 schedule_program(ctx);
2458
2459 /* Now that all the bundles are scheduled and we can calculate block
2460 * sizes, emit actual branch instructions rather than placeholders */
2461
2462 int br_block_idx = 0;
2463
2464 mir_foreach_block(ctx, block) {
2465 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2466 for (int c = 0; c < bundle->instruction_count; ++c) {
2467 midgard_instruction *ins = bundle->instructions[c];
2468
2469 if (!midgard_is_branch_unit(ins->unit)) continue;
2470
2471 if (ins->prepacked_branch) continue;
2472
2473 /* Parse some basic branch info */
2474 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2475 bool is_conditional = ins->branch.conditional;
2476 bool is_inverted = ins->branch.invert_conditional;
2477 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2478
2479 /* Determine the block we're jumping to */
2480 int target_number = ins->branch.target_block;
2481
2482 /* Report the destination tag */
2483 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2484
2485 /* Count up the number of quadwords we're
2486 * jumping over = number of quadwords until
2487 * (br_block_idx, target_number) */
2488
2489 int quadword_offset = 0;
2490
2491 if (is_discard) {
2492 /* Jump to the end of the shader. We
2493 * need to include not only the
2494 * following blocks, but also the
2495 * contents of our current block (since
2496 * discard can come in the middle of
2497 * the block) */
2498
2499 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
2500
2501 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
2502 quadword_offset += quadword_size(bun->tag);
2503 }
2504
2505 mir_foreach_block_from(ctx, blk, b) {
2506 quadword_offset += b->quadword_count;
2507 }
2508
2509 } else if (target_number > br_block_idx) {
2510 /* Jump forward */
2511
2512 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2513 midgard_block *blk = mir_get_block(ctx, idx);
2514 assert(blk);
2515
2516 quadword_offset += blk->quadword_count;
2517 }
2518 } else {
2519 /* Jump backwards */
2520
2521 for (int idx = br_block_idx; idx >= target_number; --idx) {
2522 midgard_block *blk = mir_get_block(ctx, idx);
2523 assert(blk);
2524
2525 quadword_offset -= blk->quadword_count;
2526 }
2527 }
2528
2529 /* Unconditional extended branches (far jumps)
2530 * have issues, so we always use a conditional
2531 * branch, setting the condition to always for
2532 * unconditional. For compact unconditional
2533 * branches, cond isn't used so it doesn't
2534 * matter what we pick. */
2535
2536 midgard_condition cond =
2537 !is_conditional ? midgard_condition_always :
2538 is_inverted ? midgard_condition_false :
2539 midgard_condition_true;
2540
2541 midgard_jmp_writeout_op op =
2542 is_discard ? midgard_jmp_writeout_op_discard :
2543 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2544 midgard_jmp_writeout_op_branch_cond;
2545
2546 if (!is_compact) {
2547 midgard_branch_extended branch =
2548 midgard_create_branch_extended(
2549 cond, op,
2550 dest_tag,
2551 quadword_offset);
2552
2553 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2554 } else if (is_conditional || is_discard) {
2555 midgard_branch_cond branch = {
2556 .op = op,
2557 .dest_tag = dest_tag,
2558 .offset = quadword_offset,
2559 .cond = cond
2560 };
2561
2562 assert(branch.offset == quadword_offset);
2563
2564 memcpy(&ins->br_compact, &branch, sizeof(branch));
2565 } else {
2566 assert(op == midgard_jmp_writeout_op_branch_uncond);
2567
2568 midgard_branch_uncond branch = {
2569 .op = op,
2570 .dest_tag = dest_tag,
2571 .offset = quadword_offset,
2572 .unknown = 1
2573 };
2574
2575 assert(branch.offset == quadword_offset);
2576
2577 memcpy(&ins->br_compact, &branch, sizeof(branch));
2578 }
2579 }
2580 }
2581
2582 ++br_block_idx;
2583 }
2584
2585 /* Emit flat binary from the instruction arrays. Iterate each block in
2586 * sequence. Save instruction boundaries such that lookahead tags can
2587 * be assigned easily */
2588
2589 /* Cache _all_ bundles in source order for lookahead across failed branches */
2590
2591 int bundle_count = 0;
2592 mir_foreach_block(ctx, block) {
2593 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2594 }
2595 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2596 int bundle_idx = 0;
2597 mir_foreach_block(ctx, block) {
2598 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2599 source_order_bundles[bundle_idx++] = bundle;
2600 }
2601 }
2602
2603 int current_bundle = 0;
2604
2605 /* Midgard prefetches instruction types, so during emission we
2606 * need to lookahead. Unless this is the last instruction, in
2607 * which we return 1. Or if this is the second to last and the
2608 * last is an ALU, then it's also 1... */
2609
2610 mir_foreach_block(ctx, block) {
2611 mir_foreach_bundle_in_block(block, bundle) {
2612 int lookahead = 1;
2613
2614 if (current_bundle + 1 < bundle_count) {
2615 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2616
2617 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2618 lookahead = 1;
2619 } else {
2620 lookahead = next;
2621 }
2622 }
2623
2624 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2625 ++current_bundle;
2626 }
2627
2628 /* TODO: Free deeper */
2629 //util_dynarray_fini(&block->instructions);
2630 }
2631
2632 free(source_order_bundles);
2633
2634 /* Report the very first tag executed */
2635 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2636
2637 /* Deal with off-by-one related to the fencepost problem */
2638 program->work_register_count = ctx->work_registers + 1;
2639
2640 program->can_discard = ctx->can_discard;
2641 program->uniform_cutoff = ctx->uniform_cutoff;
2642
2643 program->blend_patch_offset = ctx->blend_constant_offset;
2644
2645 if (midgard_debug & MIDGARD_DBG_SHADERS)
2646 disassemble_midgard(program->compiled.data, program->compiled.size);
2647
2648 return 0;
2649 }