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panfrost/midgard: Misc. cleanup for readibility
[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value debug_options[] = {
54 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
56 DEBUG_NAMED_VALUE_END
57 };
58
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
60
61 int midgard_debug = 0;
62
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67
68 static bool
69 midgard_is_branch_unit(unsigned unit)
70 {
71 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
72 }
73
74 static void
75 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
76 {
77 block->successors[block->nr_successors++] = successor;
78 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
79 }
80
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
83
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
91 .ssa_args = { \
92 .rname = ssa, \
93 .uname = -1, \
94 .src1 = -1 \
95 }, \
96 .load_store = { \
97 .op = midgard_op_##name, \
98 .mask = 0xF, \
99 .swizzle = SWIZZLE_XYZW, \
100 .address = address \
101 } \
102 }; \
103 \
104 return i; \
105 }
106
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
109
110 const midgard_vector_alu_src blank_alu_src = {
111 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
112 };
113
114 const midgard_vector_alu_src blank_alu_src_xxxx = {
115 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
116 };
117
118 const midgard_scalar_alu_src blank_scalar_alu_src = {
119 .full = true
120 };
121
122 /* Used for encoding the unused source of 1-op instructions */
123 const midgard_vector_alu_src zero_alu_src = { 0 };
124
125 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
126 * the corresponding Midgard source */
127
128 static midgard_vector_alu_src
129 vector_alu_modifiers(nir_alu_src *src, bool is_int)
130 {
131 if (!src) return blank_alu_src;
132
133 midgard_vector_alu_src alu_src = {
134 .rep_low = 0,
135 .rep_high = 0,
136 .half = 0, /* TODO */
137 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
138 };
139
140 if (is_int) {
141 /* TODO: sign-extend/zero-extend */
142 alu_src.mod = midgard_int_normal;
143
144 /* These should have been lowered away */
145 assert(!(src->abs || src->negate));
146 } else {
147 alu_src.mod = (src->abs << 0) | (src->negate << 1);
148 }
149
150 return alu_src;
151 }
152
153 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
154
155 static midgard_instruction
156 v_fmov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
157 {
158 midgard_instruction ins = {
159 .type = TAG_ALU_4,
160 .ssa_args = {
161 .src0 = SSA_UNUSED_1,
162 .src1 = src,
163 .dest = dest,
164 },
165 .alu = {
166 .op = midgard_alu_op_fmov,
167 .reg_mode = midgard_reg_mode_32,
168 .dest_override = midgard_dest_override_none,
169 .mask = 0xFF,
170 .src1 = vector_alu_srco_unsigned(zero_alu_src),
171 .src2 = vector_alu_srco_unsigned(mod)
172 },
173 };
174
175 return ins;
176 }
177
178 /* load/store instructions have both 32-bit and 16-bit variants, depending on
179 * whether we are using vectors composed of highp or mediump. At the moment, we
180 * don't support half-floats -- this requires changes in other parts of the
181 * compiler -- therefore the 16-bit versions are commented out. */
182
183 //M_LOAD(ld_attr_16);
184 M_LOAD(ld_attr_32);
185 //M_LOAD(ld_vary_16);
186 M_LOAD(ld_vary_32);
187 //M_LOAD(ld_uniform_16);
188 M_LOAD(ld_uniform_32);
189 M_LOAD(ld_color_buffer_8);
190 //M_STORE(st_vary_16);
191 M_STORE(st_vary_32);
192 M_STORE(st_cubemap_coords);
193
194 static midgard_instruction
195 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
196 {
197 midgard_branch_cond branch = {
198 .op = op,
199 .dest_tag = tag,
200 .offset = offset,
201 .cond = cond
202 };
203
204 uint16_t compact;
205 memcpy(&compact, &branch, sizeof(branch));
206
207 midgard_instruction ins = {
208 .type = TAG_ALU_4,
209 .unit = ALU_ENAB_BR_COMPACT,
210 .prepacked_branch = true,
211 .compact_branch = true,
212 .br_compact = compact
213 };
214
215 if (op == midgard_jmp_writeout_op_writeout)
216 ins.writeout = true;
217
218 return ins;
219 }
220
221 static midgard_instruction
222 v_branch(bool conditional, bool invert)
223 {
224 midgard_instruction ins = {
225 .type = TAG_ALU_4,
226 .unit = ALU_ENAB_BRANCH,
227 .compact_branch = true,
228 .branch = {
229 .conditional = conditional,
230 .invert_conditional = invert
231 }
232 };
233
234 return ins;
235 }
236
237 static midgard_branch_extended
238 midgard_create_branch_extended( midgard_condition cond,
239 midgard_jmp_writeout_op op,
240 unsigned dest_tag,
241 signed quadword_offset)
242 {
243 /* For unclear reasons, the condition code is repeated 8 times */
244 uint16_t duplicated_cond =
245 (cond << 14) |
246 (cond << 12) |
247 (cond << 10) |
248 (cond << 8) |
249 (cond << 6) |
250 (cond << 4) |
251 (cond << 2) |
252 (cond << 0);
253
254 midgard_branch_extended branch = {
255 .op = op,
256 .dest_tag = dest_tag,
257 .offset = quadword_offset,
258 .cond = duplicated_cond
259 };
260
261 return branch;
262 }
263
264 static void
265 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
266 {
267 ins->has_constants = true;
268 memcpy(&ins->constants, constants, 16);
269 }
270
271 static int
272 glsl_type_size(const struct glsl_type *type, bool bindless)
273 {
274 return glsl_count_attribute_slots(type, false);
275 }
276
277 /* Lower fdot2 to a vector multiplication followed by channel addition */
278 static void
279 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
280 {
281 if (alu->op != nir_op_fdot2)
282 return;
283
284 b->cursor = nir_before_instr(&alu->instr);
285
286 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
287 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
288
289 nir_ssa_def *product = nir_fmul(b, src0, src1);
290
291 nir_ssa_def *sum = nir_fadd(b,
292 nir_channel(b, product, 0),
293 nir_channel(b, product, 1));
294
295 /* Replace the fdot2 with this sum */
296 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
297 }
298
299 static int
300 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
301 {
302 switch (instr->intrinsic) {
303 case nir_intrinsic_load_viewport_scale:
304 return PAN_SYSVAL_VIEWPORT_SCALE;
305 case nir_intrinsic_load_viewport_offset:
306 return PAN_SYSVAL_VIEWPORT_OFFSET;
307 default:
308 return -1;
309 }
310 }
311
312 static void
313 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
314 {
315 int sysval = -1;
316
317 if (instr->type == nir_instr_type_intrinsic) {
318 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
319 sysval = midgard_nir_sysval_for_intrinsic(intr);
320 }
321
322 if (sysval < 0)
323 return;
324
325 /* We have a sysval load; check if it's already been assigned */
326
327 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
328 return;
329
330 /* It hasn't -- so assign it now! */
331
332 unsigned id = ctx->sysval_count++;
333 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
334 ctx->sysvals[id] = sysval;
335 }
336
337 static void
338 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
339 {
340 ctx->sysval_count = 0;
341
342 nir_foreach_function(function, shader) {
343 if (!function->impl) continue;
344
345 nir_foreach_block(block, function->impl) {
346 nir_foreach_instr_safe(instr, block) {
347 midgard_nir_assign_sysval_body(ctx, instr);
348 }
349 }
350 }
351 }
352
353 static bool
354 midgard_nir_lower_fdot2(nir_shader *shader)
355 {
356 bool progress = false;
357
358 nir_foreach_function(function, shader) {
359 if (!function->impl) continue;
360
361 nir_builder _b;
362 nir_builder *b = &_b;
363 nir_builder_init(b, function->impl);
364
365 nir_foreach_block(block, function->impl) {
366 nir_foreach_instr_safe(instr, block) {
367 if (instr->type != nir_instr_type_alu) continue;
368
369 nir_alu_instr *alu = nir_instr_as_alu(instr);
370 midgard_nir_lower_fdot2_body(b, alu);
371
372 progress |= true;
373 }
374 }
375
376 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
377
378 }
379
380 return progress;
381 }
382
383 static void
384 optimise_nir(nir_shader *nir)
385 {
386 bool progress;
387 unsigned lower_flrp =
388 (nir->options->lower_flrp16 ? 16 : 0) |
389 (nir->options->lower_flrp32 ? 32 : 0) |
390 (nir->options->lower_flrp64 ? 64 : 0);
391
392 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
393 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
394
395 nir_lower_tex_options lower_tex_options = {
396 .lower_rect = true
397 };
398
399 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
400
401 do {
402 progress = false;
403
404 NIR_PASS(progress, nir, nir_lower_var_copies);
405 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
406
407 NIR_PASS(progress, nir, nir_copy_prop);
408 NIR_PASS(progress, nir, nir_opt_dce);
409 NIR_PASS(progress, nir, nir_opt_dead_cf);
410 NIR_PASS(progress, nir, nir_opt_cse);
411 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
412 NIR_PASS(progress, nir, nir_opt_algebraic);
413 NIR_PASS(progress, nir, nir_opt_constant_folding);
414
415 if (lower_flrp != 0) {
416 bool lower_flrp_progress = false;
417 NIR_PASS(lower_flrp_progress,
418 nir,
419 nir_lower_flrp,
420 lower_flrp,
421 false /* always_precise */,
422 nir->options->lower_ffma);
423 if (lower_flrp_progress) {
424 NIR_PASS(progress, nir,
425 nir_opt_constant_folding);
426 progress = true;
427 }
428
429 /* Nothing should rematerialize any flrps, so we only
430 * need to do this lowering once.
431 */
432 lower_flrp = 0;
433 }
434
435 NIR_PASS(progress, nir, nir_opt_undef);
436 NIR_PASS(progress, nir, nir_opt_loop_unroll,
437 nir_var_shader_in |
438 nir_var_shader_out |
439 nir_var_function_temp);
440
441 /* TODO: Enable vectorize when merged upstream */
442 // NIR_PASS(progress, nir, nir_opt_vectorize);
443 } while (progress);
444
445 /* Must be run at the end to prevent creation of fsin/fcos ops */
446 NIR_PASS(progress, nir, midgard_nir_scale_trig);
447
448 do {
449 progress = false;
450
451 NIR_PASS(progress, nir, nir_opt_dce);
452 NIR_PASS(progress, nir, nir_opt_algebraic);
453 NIR_PASS(progress, nir, nir_opt_constant_folding);
454 NIR_PASS(progress, nir, nir_copy_prop);
455 } while (progress);
456
457 NIR_PASS(progress, nir, nir_opt_algebraic_late);
458
459 /* We implement booleans as 32-bit 0/~0 */
460 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
461
462 /* Now that booleans are lowered, we can run out late opts */
463 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
464
465 /* Lower mods for float ops only. Integer ops don't support modifiers
466 * (saturate doesn't make sense on integers, neg/abs require dedicated
467 * instructions) */
468
469 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
470 NIR_PASS(progress, nir, nir_copy_prop);
471 NIR_PASS(progress, nir, nir_opt_dce);
472
473 /* Take us out of SSA */
474 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
475 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
476
477 /* We are a vector architecture; write combine where possible */
478 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
479 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
480
481 NIR_PASS(progress, nir, nir_opt_dce);
482 }
483
484 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
485 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
486 * r0. See the comments in compiler_context */
487
488 static void
489 alias_ssa(compiler_context *ctx, int dest, int src)
490 {
491 _mesa_hash_table_u64_insert(ctx->ssa_to_alias, dest + 1, (void *) ((uintptr_t) src + 1));
492 _mesa_set_add(ctx->leftover_ssa_to_alias, (void *) (uintptr_t) (dest + 1));
493 }
494
495 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
496
497 static void
498 unalias_ssa(compiler_context *ctx, int dest)
499 {
500 _mesa_hash_table_u64_remove(ctx->ssa_to_alias, dest + 1);
501 /* TODO: Remove from leftover or no? */
502 }
503
504 /* Do not actually emit a load; instead, cache the constant for inlining */
505
506 static void
507 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
508 {
509 nir_ssa_def def = instr->def;
510
511 float *v = rzalloc_array(NULL, float, 4);
512 nir_const_load_to_arr(v, instr, f32);
513 _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
514 }
515
516 static unsigned
517 nir_src_index(compiler_context *ctx, nir_src *src)
518 {
519 if (src->is_ssa)
520 return src->ssa->index;
521 else {
522 assert(!src->reg.indirect);
523 return ctx->func->impl->ssa_alloc + src->reg.reg->index;
524 }
525 }
526
527 static unsigned
528 nir_dest_index(compiler_context *ctx, nir_dest *dst)
529 {
530 if (dst->is_ssa)
531 return dst->ssa.index;
532 else {
533 assert(!dst->reg.indirect);
534 return ctx->func->impl->ssa_alloc + dst->reg.reg->index;
535 }
536 }
537
538 static unsigned
539 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
540 {
541 return nir_src_index(ctx, &src->src);
542 }
543
544 static bool
545 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
546 {
547 unsigned comp = src->swizzle[0];
548
549 for (unsigned c = 1; c < nr_components; ++c) {
550 if (src->swizzle[c] != comp)
551 return true;
552 }
553
554 return false;
555 }
556
557 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
558 * output of a conditional test) into that register */
559
560 static void
561 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
562 {
563 int condition = nir_src_index(ctx, src);
564
565 /* Source to swizzle the desired component into w */
566
567 const midgard_vector_alu_src alu_src = {
568 .swizzle = SWIZZLE(component, component, component, component),
569 };
570
571 /* There is no boolean move instruction. Instead, we simulate a move by
572 * ANDing the condition with itself to get it into r31.w */
573
574 midgard_instruction ins = {
575 .type = TAG_ALU_4,
576
577 /* We need to set the conditional as close as possible */
578 .precede_break = true,
579 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
580
581 .ssa_args = {
582
583 .src0 = condition,
584 .src1 = condition,
585 .dest = SSA_FIXED_REGISTER(31),
586 },
587 .alu = {
588 .op = midgard_alu_op_iand,
589 .outmod = midgard_outmod_int,
590 .reg_mode = midgard_reg_mode_32,
591 .dest_override = midgard_dest_override_none,
592 .mask = (0x3 << 6), /* w */
593 .src1 = vector_alu_srco_unsigned(alu_src),
594 .src2 = vector_alu_srco_unsigned(alu_src)
595 },
596 };
597
598 emit_mir_instruction(ctx, ins);
599 }
600
601 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
602 * r31 instead */
603
604 static void
605 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
606 {
607 int condition = nir_src_index(ctx, &src->src);
608
609 /* Source to swizzle the desired component into w */
610
611 const midgard_vector_alu_src alu_src = {
612 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
613 };
614
615 /* There is no boolean move instruction. Instead, we simulate a move by
616 * ANDing the condition with itself to get it into r31.w */
617
618 midgard_instruction ins = {
619 .type = TAG_ALU_4,
620 .precede_break = true,
621 .ssa_args = {
622 .src0 = condition,
623 .src1 = condition,
624 .dest = SSA_FIXED_REGISTER(31),
625 },
626 .alu = {
627 .op = midgard_alu_op_iand,
628 .outmod = midgard_outmod_int,
629 .reg_mode = midgard_reg_mode_32,
630 .dest_override = midgard_dest_override_none,
631 .mask = expand_writemask((1 << nr_comp) - 1),
632 .src1 = vector_alu_srco_unsigned(alu_src),
633 .src2 = vector_alu_srco_unsigned(alu_src)
634 },
635 };
636
637 emit_mir_instruction(ctx, ins);
638 }
639
640
641
642 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
643 * pinning to eliminate this move in all known cases */
644
645 static void
646 emit_indirect_offset(compiler_context *ctx, nir_src *src)
647 {
648 int offset = nir_src_index(ctx, src);
649
650 midgard_instruction ins = {
651 .type = TAG_ALU_4,
652 .ssa_args = {
653 .src0 = SSA_UNUSED_1,
654 .src1 = offset,
655 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
656 },
657 .alu = {
658 .op = midgard_alu_op_imov,
659 .outmod = midgard_outmod_int,
660 .reg_mode = midgard_reg_mode_32,
661 .dest_override = midgard_dest_override_none,
662 .mask = (0x3 << 6), /* w */
663 .src1 = vector_alu_srco_unsigned(zero_alu_src),
664 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
665 },
666 };
667
668 emit_mir_instruction(ctx, ins);
669 }
670
671 #define ALU_CASE(nir, _op) \
672 case nir_op_##nir: \
673 op = midgard_alu_op_##_op; \
674 break;
675 static bool
676 nir_is_fzero_constant(nir_src src)
677 {
678 if (!nir_src_is_const(src))
679 return false;
680
681 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
682 if (nir_src_comp_as_float(src, c) != 0.0)
683 return false;
684 }
685
686 return true;
687 }
688
689 static void
690 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
691 {
692 bool is_ssa = instr->dest.dest.is_ssa;
693
694 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
695 unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components;
696 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
697
698 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
699 * supported. A few do not and are commented for now. Also, there are a
700 * number of NIR ops which Midgard does not support and need to be
701 * lowered, also TODO. This switch block emits the opcode and calling
702 * convention of the Midgard instruction; actual packing is done in
703 * emit_alu below */
704
705 unsigned op;
706
707 switch (instr->op) {
708 ALU_CASE(fadd, fadd);
709 ALU_CASE(fmul, fmul);
710 ALU_CASE(fmin, fmin);
711 ALU_CASE(fmax, fmax);
712 ALU_CASE(imin, imin);
713 ALU_CASE(imax, imax);
714 ALU_CASE(umin, umin);
715 ALU_CASE(umax, umax);
716 ALU_CASE(ffloor, ffloor);
717 ALU_CASE(fround_even, froundeven);
718 ALU_CASE(ftrunc, ftrunc);
719 ALU_CASE(fceil, fceil);
720 ALU_CASE(fdot3, fdot3);
721 ALU_CASE(fdot4, fdot4);
722 ALU_CASE(iadd, iadd);
723 ALU_CASE(isub, isub);
724 ALU_CASE(imul, imul);
725 ALU_CASE(iabs, iabs);
726 ALU_CASE(mov, imov);
727
728 ALU_CASE(feq32, feq);
729 ALU_CASE(fne32, fne);
730 ALU_CASE(flt32, flt);
731 ALU_CASE(ieq32, ieq);
732 ALU_CASE(ine32, ine);
733 ALU_CASE(ilt32, ilt);
734 ALU_CASE(ult32, ult);
735
736 /* We don't have a native b2f32 instruction. Instead, like many
737 * GPUs, we exploit booleans as 0/~0 for false/true, and
738 * correspondingly AND
739 * by 1.0 to do the type conversion. For the moment, prime us
740 * to emit:
741 *
742 * iand [whatever], #0
743 *
744 * At the end of emit_alu (as MIR), we'll fix-up the constant
745 */
746
747 ALU_CASE(b2f32, iand);
748 ALU_CASE(b2i32, iand);
749
750 /* Likewise, we don't have a dedicated f2b32 instruction, but
751 * we can do a "not equal to 0.0" test. */
752
753 ALU_CASE(f2b32, fne);
754 ALU_CASE(i2b32, ine);
755
756 ALU_CASE(frcp, frcp);
757 ALU_CASE(frsq, frsqrt);
758 ALU_CASE(fsqrt, fsqrt);
759 ALU_CASE(fexp2, fexp2);
760 ALU_CASE(flog2, flog2);
761
762 ALU_CASE(f2i32, f2i);
763 ALU_CASE(f2u32, f2u);
764 ALU_CASE(i2f32, i2f);
765 ALU_CASE(u2f32, u2f);
766
767 ALU_CASE(fsin, fsin);
768 ALU_CASE(fcos, fcos);
769
770 ALU_CASE(iand, iand);
771 ALU_CASE(ior, ior);
772 ALU_CASE(ixor, ixor);
773 ALU_CASE(inot, inand);
774 ALU_CASE(ishl, ishl);
775 ALU_CASE(ishr, iasr);
776 ALU_CASE(ushr, ilsr);
777
778 ALU_CASE(b32all_fequal2, fball_eq);
779 ALU_CASE(b32all_fequal3, fball_eq);
780 ALU_CASE(b32all_fequal4, fball_eq);
781
782 ALU_CASE(b32any_fnequal2, fbany_neq);
783 ALU_CASE(b32any_fnequal3, fbany_neq);
784 ALU_CASE(b32any_fnequal4, fbany_neq);
785
786 ALU_CASE(b32all_iequal2, iball_eq);
787 ALU_CASE(b32all_iequal3, iball_eq);
788 ALU_CASE(b32all_iequal4, iball_eq);
789
790 ALU_CASE(b32any_inequal2, ibany_neq);
791 ALU_CASE(b32any_inequal3, ibany_neq);
792 ALU_CASE(b32any_inequal4, ibany_neq);
793
794 /* Source mods will be shoved in later */
795 ALU_CASE(fabs, fmov);
796 ALU_CASE(fneg, fmov);
797 ALU_CASE(fsat, fmov);
798
799 /* For greater-or-equal, we lower to less-or-equal and flip the
800 * arguments */
801
802 case nir_op_fge:
803 case nir_op_fge32:
804 case nir_op_ige32:
805 case nir_op_uge32: {
806 op =
807 instr->op == nir_op_fge ? midgard_alu_op_fle :
808 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
809 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
810 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
811 0;
812
813 /* Swap via temporary */
814 nir_alu_src temp = instr->src[1];
815 instr->src[1] = instr->src[0];
816 instr->src[0] = temp;
817
818 break;
819 }
820
821 case nir_op_b32csel: {
822 /* Midgard features both fcsel and icsel, depending on
823 * the type of the arguments/output. However, as long
824 * as we're careful we can _always_ use icsel and
825 * _never_ need fcsel, since the latter does additional
826 * floating-point-specific processing whereas the
827 * former just moves bits on the wire. It's not obvious
828 * why these are separate opcodes, save for the ability
829 * to do things like sat/pos/abs/neg for free */
830
831 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
832 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
833
834 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
835 nr_inputs = 2;
836
837 /* Emit the condition into r31 */
838
839 if (mixed)
840 emit_condition_mixed(ctx, &instr->src[0], nr_components);
841 else
842 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
843
844 /* The condition is the first argument; move the other
845 * arguments up one to be a binary instruction for
846 * Midgard */
847
848 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
849 break;
850 }
851
852 default:
853 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
854 assert(0);
855 return;
856 }
857
858 /* Midgard can perform certain modifiers on output of an ALU op */
859 midgard_outmod outmod =
860 midgard_is_integer_out_op(op) ? midgard_outmod_int :
861 instr->dest.saturate ? midgard_outmod_sat : midgard_outmod_none;
862
863 if (instr->op == nir_op_fsat)
864 outmod = midgard_outmod_sat;
865
866 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
867
868 if (instr->op == nir_op_fmax) {
869 if (nir_is_fzero_constant(instr->src[0].src)) {
870 op = midgard_alu_op_fmov;
871 nr_inputs = 1;
872 outmod = midgard_outmod_pos;
873 instr->src[0] = instr->src[1];
874 } else if (nir_is_fzero_constant(instr->src[1].src)) {
875 op = midgard_alu_op_fmov;
876 nr_inputs = 1;
877 outmod = midgard_outmod_pos;
878 }
879 }
880
881 /* Fetch unit, quirks, etc information */
882 unsigned opcode_props = alu_opcode_props[op].props;
883 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
884
885 /* src0 will always exist afaik, but src1 will not for 1-argument
886 * instructions. The latter can only be fetched if the instruction
887 * needs it, or else we may segfault. */
888
889 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
890 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
891
892 /* Rather than use the instruction generation helpers, we do it
893 * ourselves here to avoid the mess */
894
895 midgard_instruction ins = {
896 .type = TAG_ALU_4,
897 .ssa_args = {
898 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
899 .src1 = quirk_flipped_r24 ? src0 : src1,
900 .dest = dest,
901 }
902 };
903
904 nir_alu_src *nirmods[2] = { NULL };
905
906 if (nr_inputs == 2) {
907 nirmods[0] = &instr->src[0];
908 nirmods[1] = &instr->src[1];
909 } else if (nr_inputs == 1) {
910 nirmods[quirk_flipped_r24] = &instr->src[0];
911 } else {
912 assert(0);
913 }
914
915 /* These were lowered to a move, so apply the corresponding mod */
916
917 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
918 nir_alu_src *s = nirmods[quirk_flipped_r24];
919
920 if (instr->op == nir_op_fneg)
921 s->negate = !s->negate;
922
923 if (instr->op == nir_op_fabs)
924 s->abs = !s->abs;
925 }
926
927 bool is_int = midgard_is_integer_op(op);
928
929 midgard_vector_alu alu = {
930 .op = op,
931 .reg_mode = midgard_reg_mode_32,
932 .dest_override = midgard_dest_override_none,
933 .outmod = outmod,
934
935 /* Writemask only valid for non-SSA NIR */
936 .mask = expand_writemask((1 << nr_components) - 1),
937
938 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int)),
939 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int)),
940 };
941
942 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
943
944 if (!is_ssa)
945 alu.mask &= expand_writemask(instr->dest.write_mask);
946
947 ins.alu = alu;
948
949 /* Late fixup for emulated instructions */
950
951 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
952 /* Presently, our second argument is an inline #0 constant.
953 * Switch over to an embedded 1.0 constant (that can't fit
954 * inline, since we're 32-bit, not 16-bit like the inline
955 * constants) */
956
957 ins.ssa_args.inline_constant = false;
958 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
959 ins.has_constants = true;
960
961 if (instr->op == nir_op_b2f32) {
962 ins.constants[0] = 1.0f;
963 } else {
964 /* Type pun it into place */
965 uint32_t one = 0x1;
966 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
967 }
968
969 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
970 } else if (instr->op == nir_op_f2b32 || instr->op == nir_op_i2b32) {
971 ins.ssa_args.inline_constant = false;
972 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
973 ins.has_constants = true;
974 ins.constants[0] = 0.0f;
975 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
976 } else if (instr->op == nir_op_inot) {
977 /* ~b = ~(b & b), so duplicate the source */
978 ins.ssa_args.src1 = ins.ssa_args.src0;
979 ins.alu.src2 = ins.alu.src1;
980 }
981
982 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
983 /* To avoid duplicating the lookup tables (probably), true LUT
984 * instructions can only operate as if they were scalars. Lower
985 * them here by changing the component. */
986
987 uint8_t original_swizzle[4];
988 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
989
990 for (int i = 0; i < nr_components; ++i) {
991 ins.alu.mask = (0x3) << (2 * i); /* Mask the associated component */
992
993 for (int j = 0; j < 4; ++j)
994 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
995
996 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int));
997 emit_mir_instruction(ctx, ins);
998 }
999 } else {
1000 emit_mir_instruction(ctx, ins);
1001 }
1002 }
1003
1004 #undef ALU_CASE
1005
1006 static void
1007 emit_uniform_read(compiler_context *ctx, unsigned dest, unsigned offset, nir_src *indirect_offset)
1008 {
1009 /* TODO: half-floats */
1010
1011 if (!indirect_offset && offset < ctx->uniform_cutoff) {
1012 /* Fast path: For the first 16 uniforms, direct accesses are
1013 * 0-cycle, since they're just a register fetch in the usual
1014 * case. So, we alias the registers while we're still in
1015 * SSA-space */
1016
1017 int reg_slot = 23 - offset;
1018 alias_ssa(ctx, dest, SSA_FIXED_REGISTER(reg_slot));
1019 } else {
1020 /* Otherwise, read from the 'special' UBO to access
1021 * higher-indexed uniforms, at a performance cost. More
1022 * generally, we're emitting a UBO read instruction. */
1023
1024 midgard_instruction ins = m_ld_uniform_32(dest, offset);
1025
1026 /* TODO: Don't split */
1027 ins.load_store.varying_parameters = (offset & 7) << 7;
1028 ins.load_store.address = offset >> 3;
1029
1030 if (indirect_offset) {
1031 emit_indirect_offset(ctx, indirect_offset);
1032 ins.load_store.unknown = 0x8700; /* xxx: what is this? */
1033 } else {
1034 ins.load_store.unknown = 0x1E00; /* xxx: what is this? */
1035 }
1036
1037 emit_mir_instruction(ctx, ins);
1038 }
1039 }
1040
1041 static void
1042 emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
1043 {
1044 /* First, pull out the destination */
1045 unsigned dest = nir_dest_index(ctx, &instr->dest);
1046
1047 /* Now, figure out which uniform this is */
1048 int sysval = midgard_nir_sysval_for_intrinsic(instr);
1049 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1050
1051 /* Sysvals are prefix uniforms */
1052 unsigned uniform = ((uintptr_t) val) - 1;
1053
1054 /* Emit the read itself -- this is never indirect */
1055 emit_uniform_read(ctx, dest, uniform, NULL);
1056 }
1057
1058 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1059 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1060 * generations have faster vectorized reads. This operation is for blend
1061 * shaders in particular; reading the tilebuffer from the fragment shader
1062 * remains an open problem. */
1063
1064 static void
1065 emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
1066 {
1067 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1068 ins.load_store.swizzle = 0; /* xxxx */
1069
1070 /* Read each component sequentially */
1071
1072 for (unsigned c = 0; c < 4; ++c) {
1073 ins.load_store.mask = (1 << c);
1074 ins.load_store.unknown = c;
1075 emit_mir_instruction(ctx, ins);
1076 }
1077
1078 /* vadd.u2f hr2, zext(hr2), #0 */
1079
1080 midgard_vector_alu_src alu_src = blank_alu_src;
1081 alu_src.mod = midgard_int_zero_extend;
1082 alu_src.half = true;
1083
1084 midgard_instruction u2f = {
1085 .type = TAG_ALU_4,
1086 .ssa_args = {
1087 .src0 = reg,
1088 .src1 = SSA_UNUSED_0,
1089 .dest = reg,
1090 .inline_constant = true
1091 },
1092 .alu = {
1093 .op = midgard_alu_op_u2f,
1094 .reg_mode = midgard_reg_mode_16,
1095 .dest_override = midgard_dest_override_none,
1096 .mask = 0xF,
1097 .src1 = vector_alu_srco_unsigned(alu_src),
1098 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1099 }
1100 };
1101
1102 emit_mir_instruction(ctx, u2f);
1103
1104 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1105
1106 alu_src.mod = 0;
1107
1108 midgard_instruction fmul = {
1109 .type = TAG_ALU_4,
1110 .inline_constant = _mesa_float_to_half(1.0 / 255.0),
1111 .ssa_args = {
1112 .src0 = reg,
1113 .dest = reg,
1114 .src1 = SSA_UNUSED_0,
1115 .inline_constant = true
1116 },
1117 .alu = {
1118 .op = midgard_alu_op_fmul,
1119 .reg_mode = midgard_reg_mode_32,
1120 .dest_override = midgard_dest_override_none,
1121 .outmod = midgard_outmod_sat,
1122 .mask = 0xFF,
1123 .src1 = vector_alu_srco_unsigned(alu_src),
1124 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1125 }
1126 };
1127
1128 emit_mir_instruction(ctx, fmul);
1129 }
1130
1131 static void
1132 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1133 {
1134 unsigned offset, reg;
1135
1136 switch (instr->intrinsic) {
1137 case nir_intrinsic_discard_if:
1138 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1139
1140 /* fallthrough */
1141
1142 case nir_intrinsic_discard: {
1143 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1144 struct midgard_instruction discard = v_branch(conditional, false);
1145 discard.branch.target_type = TARGET_DISCARD;
1146 emit_mir_instruction(ctx, discard);
1147
1148 ctx->can_discard = true;
1149 break;
1150 }
1151
1152 case nir_intrinsic_load_uniform:
1153 case nir_intrinsic_load_input:
1154 offset = nir_intrinsic_base(instr);
1155
1156 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1157 bool direct = nir_src_is_const(instr->src[0]);
1158
1159 if (direct) {
1160 offset += nir_src_as_uint(instr->src[0]);
1161 }
1162
1163 reg = nir_dest_index(ctx, &instr->dest);
1164
1165 if (instr->intrinsic == nir_intrinsic_load_uniform && !ctx->is_blend) {
1166 emit_uniform_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL);
1167 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1168 /* XXX: Half-floats? */
1169 /* TODO: swizzle, mask */
1170
1171 midgard_instruction ins = m_ld_vary_32(reg, offset);
1172 ins.load_store.mask = (1 << nr_comp) - 1;
1173
1174 midgard_varying_parameter p = {
1175 .is_varying = 1,
1176 .interpolation = midgard_interp_default,
1177 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1178 };
1179
1180 unsigned u;
1181 memcpy(&u, &p, sizeof(p));
1182 ins.load_store.varying_parameters = u;
1183
1184 if (direct) {
1185 /* We have the offset totally ready */
1186 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1187 } else {
1188 /* We have it partially ready, but we need to
1189 * add in the dynamic index, moved to r27.w */
1190 emit_indirect_offset(ctx, &instr->src[0]);
1191 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1192 }
1193
1194 emit_mir_instruction(ctx, ins);
1195 } else if (ctx->is_blend) {
1196 /* For blend shaders, load the input color, which is
1197 * preloaded to r0 */
1198
1199 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1200 emit_mir_instruction(ctx, move);
1201 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1202 midgard_instruction ins = m_ld_attr_32(reg, offset);
1203 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1204 ins.load_store.mask = (1 << nr_comp) - 1;
1205 emit_mir_instruction(ctx, ins);
1206 } else {
1207 DBG("Unknown load\n");
1208 assert(0);
1209 }
1210
1211 break;
1212
1213 case nir_intrinsic_load_output:
1214 assert(nir_src_is_const(instr->src[0]));
1215 reg = nir_dest_index(ctx, &instr->dest);
1216
1217 if (ctx->is_blend) {
1218 /* TODO: MRT */
1219 emit_fb_read_blend_scalar(ctx, reg);
1220 } else {
1221 DBG("Unknown output load\n");
1222 assert(0);
1223 }
1224
1225 break;
1226
1227 case nir_intrinsic_load_blend_const_color_rgba: {
1228 assert(ctx->is_blend);
1229 reg = nir_dest_index(ctx, &instr->dest);
1230
1231 /* Blend constants are embedded directly in the shader and
1232 * patched in, so we use some magic routing */
1233
1234 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1235 ins.has_constants = true;
1236 ins.has_blend_constant = true;
1237 emit_mir_instruction(ctx, ins);
1238 break;
1239 }
1240
1241 case nir_intrinsic_store_output:
1242 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1243
1244 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1245
1246 reg = nir_src_index(ctx, &instr->src[0]);
1247
1248 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1249 /* gl_FragColor is not emitted with load/store
1250 * instructions. Instead, it gets plonked into
1251 * r0 at the end of the shader and we do the
1252 * framebuffer writeout dance. TODO: Defer
1253 * writes */
1254
1255 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1256 emit_mir_instruction(ctx, move);
1257
1258 /* Save the index we're writing to for later reference
1259 * in the epilogue */
1260
1261 ctx->fragment_output = reg;
1262 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1263 /* Varyings are written into one of two special
1264 * varying register, r26 or r27. The register itself is selected as the register
1265 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1266 *
1267 * Normally emitting fmov's is frowned upon,
1268 * but due to unique constraints of
1269 * REGISTER_VARYING, fmov emission + a
1270 * dedicated cleanup pass is the only way to
1271 * guarantee correctness when considering some
1272 * (common) edge cases XXX: FIXME */
1273
1274 /* If this varying corresponds to a constant (why?!),
1275 * emit that now since it won't get picked up by
1276 * hoisting (since there is no corresponding move
1277 * emitted otherwise) */
1278
1279 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, reg + 1);
1280
1281 if (constant_value) {
1282 /* Special case: emit the varying write
1283 * directly to r26 (looks funny in asm but it's
1284 * fine) and emit the store _now_. Possibly
1285 * slightly slower, but this is a really stupid
1286 * special case anyway (why on earth would you
1287 * have a constant varying? Your own fault for
1288 * slightly worse perf :P) */
1289
1290 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(26));
1291 attach_constants(ctx, &ins, constant_value, reg + 1);
1292 emit_mir_instruction(ctx, ins);
1293
1294 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset);
1295 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1296 emit_mir_instruction(ctx, st);
1297 } else {
1298 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1299
1300 _mesa_hash_table_u64_insert(ctx->ssa_varyings, reg + 1, (void *) ((uintptr_t) (offset + 1)));
1301 }
1302 } else {
1303 DBG("Unknown store\n");
1304 assert(0);
1305 }
1306
1307 break;
1308
1309 case nir_intrinsic_load_alpha_ref_float:
1310 assert(instr->dest.is_ssa);
1311
1312 float ref_value = ctx->alpha_ref;
1313
1314 float *v = ralloc_array(NULL, float, 4);
1315 memcpy(v, &ref_value, sizeof(float));
1316 _mesa_hash_table_u64_insert(ctx->ssa_constants, instr->dest.ssa.index + 1, v);
1317 break;
1318
1319 case nir_intrinsic_load_viewport_scale:
1320 case nir_intrinsic_load_viewport_offset:
1321 emit_sysval_read(ctx, instr);
1322 break;
1323
1324 default:
1325 printf ("Unhandled intrinsic\n");
1326 assert(0);
1327 break;
1328 }
1329 }
1330
1331 static unsigned
1332 midgard_tex_format(enum glsl_sampler_dim dim)
1333 {
1334 switch (dim) {
1335 case GLSL_SAMPLER_DIM_2D:
1336 case GLSL_SAMPLER_DIM_EXTERNAL:
1337 return TEXTURE_2D;
1338
1339 case GLSL_SAMPLER_DIM_3D:
1340 return TEXTURE_3D;
1341
1342 case GLSL_SAMPLER_DIM_CUBE:
1343 return TEXTURE_CUBE;
1344
1345 default:
1346 DBG("Unknown sampler dim type\n");
1347 assert(0);
1348 return 0;
1349 }
1350 }
1351
1352 static void
1353 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1354 {
1355 /* TODO */
1356 //assert (!instr->sampler);
1357 //assert (!instr->texture_array_size);
1358 assert (instr->op == nir_texop_tex);
1359
1360 /* Allocate registers via a round robin scheme to alternate between the two registers */
1361 int reg = ctx->texture_op_count & 1;
1362 int in_reg = reg, out_reg = reg;
1363
1364 /* Make room for the reg */
1365
1366 if (ctx->texture_index[reg] > -1)
1367 unalias_ssa(ctx, ctx->texture_index[reg]);
1368
1369 int texture_index = instr->texture_index;
1370 int sampler_index = texture_index;
1371
1372 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1373 switch (instr->src[i].src_type) {
1374 case nir_tex_src_coord: {
1375 int index = nir_src_index(ctx, &instr->src[i].src);
1376
1377 midgard_vector_alu_src alu_src = blank_alu_src;
1378
1379 int reg = SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + in_reg);
1380
1381 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1382 /* For cubemaps, we need to load coords into
1383 * special r27, and then use a special ld/st op
1384 * to copy into the texture register */
1385
1386 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X);
1387
1388 midgard_instruction move = v_fmov(index, alu_src, SSA_FIXED_REGISTER(27));
1389 emit_mir_instruction(ctx, move);
1390
1391 midgard_instruction st = m_st_cubemap_coords(reg, 0);
1392 st.load_store.unknown = 0x24; /* XXX: What is this? */
1393 st.load_store.mask = 0x3; /* xy? */
1394 st.load_store.swizzle = alu_src.swizzle;
1395 emit_mir_instruction(ctx, st);
1396
1397 } else {
1398 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X);
1399
1400 midgard_instruction ins = v_fmov(index, alu_src, reg);
1401 emit_mir_instruction(ctx, ins);
1402 }
1403
1404 break;
1405 }
1406
1407 default: {
1408 DBG("Unknown source type\n");
1409 //assert(0);
1410 break;
1411 }
1412 }
1413 }
1414
1415 /* No helper to build texture words -- we do it all here */
1416 midgard_instruction ins = {
1417 .type = TAG_TEXTURE_4,
1418 .texture = {
1419 .op = TEXTURE_OP_NORMAL,
1420 .format = midgard_tex_format(instr->sampler_dim),
1421 .texture_handle = texture_index,
1422 .sampler_handle = sampler_index,
1423
1424 /* TODO: Don't force xyzw */
1425 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
1426 .mask = 0xF,
1427
1428 /* TODO: half */
1429 //.in_reg_full = 1,
1430 .out_full = 1,
1431
1432 .filter = 1,
1433
1434 /* Always 1 */
1435 .unknown7 = 1,
1436
1437 /* Assume we can continue; hint it out later */
1438 .cont = 1,
1439 }
1440 };
1441
1442 /* Set registers to read and write from the same place */
1443 ins.texture.in_reg_select = in_reg;
1444 ins.texture.out_reg_select = out_reg;
1445
1446 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1447 if (instr->sampler_dim == GLSL_SAMPLER_DIM_3D) {
1448 ins.texture.in_reg_swizzle_right = COMPONENT_X;
1449 ins.texture.in_reg_swizzle_left = COMPONENT_Y;
1450 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1451 } else {
1452 ins.texture.in_reg_swizzle_left = COMPONENT_X;
1453 ins.texture.in_reg_swizzle_right = COMPONENT_Y;
1454 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1455 }
1456
1457 emit_mir_instruction(ctx, ins);
1458
1459 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1460
1461 int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest);
1462 alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg));
1463 ctx->texture_index[reg] = o_index;
1464
1465 midgard_instruction ins2 = v_fmov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index);
1466 emit_mir_instruction(ctx, ins2);
1467
1468 /* Used for .cont and .last hinting */
1469 ctx->texture_op_count++;
1470 }
1471
1472 static void
1473 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1474 {
1475 switch (instr->type) {
1476 case nir_jump_break: {
1477 /* Emit a branch out of the loop */
1478 struct midgard_instruction br = v_branch(false, false);
1479 br.branch.target_type = TARGET_BREAK;
1480 br.branch.target_break = ctx->current_loop_depth;
1481 emit_mir_instruction(ctx, br);
1482
1483 DBG("break..\n");
1484 break;
1485 }
1486
1487 default:
1488 DBG("Unknown jump type %d\n", instr->type);
1489 break;
1490 }
1491 }
1492
1493 static void
1494 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1495 {
1496 switch (instr->type) {
1497 case nir_instr_type_load_const:
1498 emit_load_const(ctx, nir_instr_as_load_const(instr));
1499 break;
1500
1501 case nir_instr_type_intrinsic:
1502 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1503 break;
1504
1505 case nir_instr_type_alu:
1506 emit_alu(ctx, nir_instr_as_alu(instr));
1507 break;
1508
1509 case nir_instr_type_tex:
1510 emit_tex(ctx, nir_instr_as_tex(instr));
1511 break;
1512
1513 case nir_instr_type_jump:
1514 emit_jump(ctx, nir_instr_as_jump(instr));
1515 break;
1516
1517 case nir_instr_type_ssa_undef:
1518 /* Spurious */
1519 break;
1520
1521 default:
1522 DBG("Unhandled instruction type\n");
1523 break;
1524 }
1525 }
1526
1527 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1528 * use scalar ALU instructions, for functional or performance reasons. To do
1529 * this, we just demote vector ALU payloads to scalar. */
1530
1531 static int
1532 component_from_mask(unsigned mask)
1533 {
1534 for (int c = 0; c < 4; ++c) {
1535 if (mask & (3 << (2 * c)))
1536 return c;
1537 }
1538
1539 assert(0);
1540 return 0;
1541 }
1542
1543 static bool
1544 is_single_component_mask(unsigned mask)
1545 {
1546 int components = 0;
1547
1548 for (int c = 0; c < 4; ++c)
1549 if (mask & (3 << (2 * c)))
1550 components++;
1551
1552 return components == 1;
1553 }
1554
1555 /* Create a mask of accessed components from a swizzle to figure out vector
1556 * dependencies */
1557
1558 static unsigned
1559 swizzle_to_access_mask(unsigned swizzle)
1560 {
1561 unsigned component_mask = 0;
1562
1563 for (int i = 0; i < 4; ++i) {
1564 unsigned c = (swizzle >> (2 * i)) & 3;
1565 component_mask |= (1 << c);
1566 }
1567
1568 return component_mask;
1569 }
1570
1571 static unsigned
1572 vector_to_scalar_source(unsigned u, bool is_int)
1573 {
1574 midgard_vector_alu_src v;
1575 memcpy(&v, &u, sizeof(v));
1576
1577 /* TODO: Integers */
1578
1579 midgard_scalar_alu_src s = {
1580 .full = !v.half,
1581 .component = (v.swizzle & 3) << 1
1582 };
1583
1584 if (is_int) {
1585 /* TODO */
1586 } else {
1587 s.abs = v.mod & MIDGARD_FLOAT_MOD_ABS;
1588 s.negate = v.mod & MIDGARD_FLOAT_MOD_NEG;
1589 }
1590
1591 unsigned o;
1592 memcpy(&o, &s, sizeof(s));
1593
1594 return o & ((1 << 6) - 1);
1595 }
1596
1597 static midgard_scalar_alu
1598 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
1599 {
1600 bool is_int = midgard_is_integer_op(v.op);
1601
1602 /* The output component is from the mask */
1603 midgard_scalar_alu s = {
1604 .op = v.op,
1605 .src1 = vector_to_scalar_source(v.src1, is_int),
1606 .src2 = vector_to_scalar_source(v.src2, is_int),
1607 .unknown = 0,
1608 .outmod = v.outmod,
1609 .output_full = 1, /* TODO: Half */
1610 .output_component = component_from_mask(v.mask) << 1,
1611 };
1612
1613 /* Inline constant is passed along rather than trying to extract it
1614 * from v */
1615
1616 if (ins->ssa_args.inline_constant) {
1617 uint16_t imm = 0;
1618 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
1619 imm |= (lower_11 >> 9) & 3;
1620 imm |= (lower_11 >> 6) & 4;
1621 imm |= (lower_11 >> 2) & 0x38;
1622 imm |= (lower_11 & 63) << 6;
1623
1624 s.src2 = imm;
1625 }
1626
1627 return s;
1628 }
1629
1630 /* Midgard prefetches instruction types, so during emission we need to
1631 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1632 * if this is the second to last and the last is an ALU, then it's also 1... */
1633
1634 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1635 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1636
1637 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
1638 bytes_emitted += sizeof(type)
1639
1640 static void
1641 emit_binary_vector_instruction(midgard_instruction *ains,
1642 uint16_t *register_words, int *register_words_count,
1643 uint64_t *body_words, size_t *body_size, int *body_words_count,
1644 size_t *bytes_emitted)
1645 {
1646 memcpy(&register_words[(*register_words_count)++], &ains->registers, sizeof(ains->registers));
1647 *bytes_emitted += sizeof(midgard_reg_info);
1648
1649 body_size[*body_words_count] = sizeof(midgard_vector_alu);
1650 memcpy(&body_words[(*body_words_count)++], &ains->alu, sizeof(ains->alu));
1651 *bytes_emitted += sizeof(midgard_vector_alu);
1652 }
1653
1654 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
1655 * mind that we are a vector architecture and we can write to different
1656 * components simultaneously */
1657
1658 static bool
1659 can_run_concurrent_ssa(midgard_instruction *first, midgard_instruction *second)
1660 {
1661 /* Each instruction reads some registers and writes to a register. See
1662 * where the first writes */
1663
1664 /* Figure out where exactly we wrote to */
1665 int source = first->ssa_args.dest;
1666 int source_mask = first->type == TAG_ALU_4 ? squeeze_writemask(first->alu.mask) : 0xF;
1667
1668 /* As long as the second doesn't read from the first, we're okay */
1669 if (second->ssa_args.src0 == source) {
1670 if (first->type == TAG_ALU_4) {
1671 /* Figure out which components we just read from */
1672
1673 int q = second->alu.src1;
1674 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1675
1676 /* Check if there are components in common, and fail if so */
1677 if (swizzle_to_access_mask(m->swizzle) & source_mask)
1678 return false;
1679 } else
1680 return false;
1681
1682 }
1683
1684 if (second->ssa_args.src1 == source)
1685 return false;
1686
1687 /* Otherwise, it's safe in that regard. Another data hazard is both
1688 * writing to the same place, of course */
1689
1690 if (second->ssa_args.dest == source) {
1691 /* ...but only if the components overlap */
1692 int dest_mask = second->type == TAG_ALU_4 ? squeeze_writemask(second->alu.mask) : 0xF;
1693
1694 if (dest_mask & source_mask)
1695 return false;
1696 }
1697
1698 /* ...That's it */
1699 return true;
1700 }
1701
1702 static bool
1703 midgard_has_hazard(
1704 midgard_instruction **segment, unsigned segment_size,
1705 midgard_instruction *ains)
1706 {
1707 for (int s = 0; s < segment_size; ++s)
1708 if (!can_run_concurrent_ssa(segment[s], ains))
1709 return true;
1710
1711 return false;
1712
1713
1714 }
1715
1716 /* Schedules, but does not emit, a single basic block. After scheduling, the
1717 * final tag and size of the block are known, which are necessary for branching
1718 * */
1719
1720 static midgard_bundle
1721 schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction *ins, int *skip)
1722 {
1723 int instructions_emitted = 0, instructions_consumed = -1;
1724 midgard_bundle bundle = { 0 };
1725
1726 uint8_t tag = ins->type;
1727
1728 /* Default to the instruction's tag */
1729 bundle.tag = tag;
1730
1731 switch (ins->type) {
1732 case TAG_ALU_4: {
1733 uint32_t control = 0;
1734 size_t bytes_emitted = sizeof(control);
1735
1736 /* TODO: Constant combining */
1737 int index = 0, last_unit = 0;
1738
1739 /* Previous instructions, for the purpose of parallelism */
1740 midgard_instruction *segment[4] = {0};
1741 int segment_size = 0;
1742
1743 instructions_emitted = -1;
1744 midgard_instruction *pins = ins;
1745
1746 for (;;) {
1747 midgard_instruction *ains = pins;
1748
1749 /* Advance instruction pointer */
1750 if (index) {
1751 ains = mir_next_op(pins);
1752 pins = ains;
1753 }
1754
1755 /* Out-of-work condition */
1756 if ((struct list_head *) ains == &block->instructions)
1757 break;
1758
1759 /* Ensure that the chain can continue */
1760 if (ains->type != TAG_ALU_4) break;
1761
1762 /* If there's already something in the bundle and we
1763 * have weird scheduler constraints, break now */
1764 if (ains->precede_break && index) break;
1765
1766 /* According to the presentation "The ARM
1767 * Mali-T880 Mobile GPU" from HotChips 27,
1768 * there are two pipeline stages. Branching
1769 * position determined experimentally. Lines
1770 * are executed in parallel:
1771 *
1772 * [ VMUL ] [ SADD ]
1773 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
1774 *
1775 * Verify that there are no ordering dependencies here.
1776 *
1777 * TODO: Allow for parallelism!!!
1778 */
1779
1780 /* Pick a unit for it if it doesn't force a particular unit */
1781
1782 int unit = ains->unit;
1783
1784 if (!unit) {
1785 int op = ains->alu.op;
1786 int units = alu_opcode_props[op].props;
1787
1788 bool vectorable = units & UNITS_ANY_VECTOR;
1789 bool scalarable = units & UNITS_SCALAR;
1790 bool could_scalar = is_single_component_mask(ains->alu.mask);
1791 bool vector = vectorable && !(could_scalar && scalarable);
1792
1793 if (!vector)
1794 assert(units & UNITS_SCALAR);
1795
1796 if (vector) {
1797 if (last_unit >= UNIT_VADD) {
1798 if (units & UNIT_VLUT)
1799 unit = UNIT_VLUT;
1800 else
1801 break;
1802 } else {
1803 if ((units & UNIT_VMUL) && !(control & UNIT_VMUL))
1804 unit = UNIT_VMUL;
1805 else if ((units & UNIT_VADD) && !(control & UNIT_VADD))
1806 unit = UNIT_VADD;
1807 else if (units & UNIT_VLUT)
1808 unit = UNIT_VLUT;
1809 else
1810 break;
1811 }
1812 } else {
1813 if (last_unit >= UNIT_VADD) {
1814 if ((units & UNIT_SMUL) && !(control & UNIT_SMUL))
1815 unit = UNIT_SMUL;
1816 else if (units & UNIT_VLUT)
1817 unit = UNIT_VLUT;
1818 else
1819 break;
1820 } else {
1821 if ((units & UNIT_SADD) && !(control & UNIT_SADD) && !midgard_has_hazard(segment, segment_size, ains))
1822 unit = UNIT_SADD;
1823 else if (units & UNIT_SMUL)
1824 unit = ((units & UNIT_VMUL) && !(control & UNIT_VMUL)) ? UNIT_VMUL : UNIT_SMUL;
1825 else if ((units & UNIT_VADD) && !(control & UNIT_VADD))
1826 unit = UNIT_VADD;
1827 else
1828 break;
1829 }
1830 }
1831
1832 assert(unit & units);
1833 }
1834
1835 /* Late unit check, this time for encoding (not parallelism) */
1836 if (unit <= last_unit) break;
1837
1838 /* Clear the segment */
1839 if (last_unit < UNIT_VADD && unit >= UNIT_VADD)
1840 segment_size = 0;
1841
1842 if (midgard_has_hazard(segment, segment_size, ains))
1843 break;
1844
1845 /* We're good to go -- emit the instruction */
1846 ains->unit = unit;
1847
1848 segment[segment_size++] = ains;
1849
1850 /* Only one set of embedded constants per
1851 * bundle possible; if we have more, we must
1852 * break the chain early, unfortunately */
1853
1854 if (ains->has_constants) {
1855 if (bundle.has_embedded_constants) {
1856 /* The blend constant needs to be
1857 * alone, since it conflicts with
1858 * everything by definition*/
1859
1860 if (ains->has_blend_constant || bundle.has_blend_constant)
1861 break;
1862
1863 /* ...but if there are already
1864 * constants but these are the
1865 * *same* constants, we let it
1866 * through */
1867
1868 if (memcmp(bundle.constants, ains->constants, sizeof(bundle.constants)))
1869 break;
1870 } else {
1871 bundle.has_embedded_constants = true;
1872 memcpy(bundle.constants, ains->constants, sizeof(bundle.constants));
1873
1874 /* If this is a blend shader special constant, track it for patching */
1875 bundle.has_blend_constant |= ains->has_blend_constant;
1876 }
1877 }
1878
1879 if (ains->unit & UNITS_ANY_VECTOR) {
1880 emit_binary_vector_instruction(ains, bundle.register_words,
1881 &bundle.register_words_count, bundle.body_words,
1882 bundle.body_size, &bundle.body_words_count, &bytes_emitted);
1883 } else if (ains->compact_branch) {
1884 /* All of r0 has to be written out
1885 * along with the branch writeout.
1886 * (slow!) */
1887
1888 if (ains->writeout) {
1889 if (index == 0) {
1890 midgard_instruction ins = v_fmov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
1891 ins.unit = UNIT_VMUL;
1892
1893 control |= ins.unit;
1894
1895 emit_binary_vector_instruction(&ins, bundle.register_words,
1896 &bundle.register_words_count, bundle.body_words,
1897 bundle.body_size, &bundle.body_words_count, &bytes_emitted);
1898 } else {
1899 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
1900 bool written_late = false;
1901 bool components[4] = { 0 };
1902 uint16_t register_dep_mask = 0;
1903 uint16_t written_mask = 0;
1904
1905 midgard_instruction *qins = ins;
1906 for (int t = 0; t < index; ++t) {
1907 if (qins->registers.out_reg != 0) {
1908 /* Mark down writes */
1909
1910 written_mask |= (1 << qins->registers.out_reg);
1911 } else {
1912 /* Mark down the register dependencies for errata check */
1913
1914 if (qins->registers.src1_reg < 16)
1915 register_dep_mask |= (1 << qins->registers.src1_reg);
1916
1917 if (qins->registers.src2_reg < 16)
1918 register_dep_mask |= (1 << qins->registers.src2_reg);
1919
1920 int mask = qins->alu.mask;
1921
1922 for (int c = 0; c < 4; ++c)
1923 if (mask & (0x3 << (2 * c)))
1924 components[c] = true;
1925
1926 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
1927
1928 if (qins->unit == UNIT_VLUT)
1929 written_late = true;
1930 }
1931
1932 /* Advance instruction pointer */
1933 qins = mir_next_op(qins);
1934 }
1935
1936
1937 /* Register dependencies of r0 must be out of fragment writeout bundle */
1938 if (register_dep_mask & written_mask)
1939 break;
1940
1941 if (written_late)
1942 break;
1943
1944 /* If even a single component is not written, break it up (conservative check). */
1945 bool breakup = false;
1946
1947 for (int c = 0; c < 4; ++c)
1948 if (!components[c])
1949 breakup = true;
1950
1951 if (breakup)
1952 break;
1953
1954 /* Otherwise, we're free to proceed */
1955 }
1956 }
1957
1958 if (ains->unit == ALU_ENAB_BRANCH) {
1959 bundle.body_size[bundle.body_words_count] = sizeof(midgard_branch_extended);
1960 memcpy(&bundle.body_words[bundle.body_words_count++], &ains->branch_extended, sizeof(midgard_branch_extended));
1961 bytes_emitted += sizeof(midgard_branch_extended);
1962 } else {
1963 bundle.body_size[bundle.body_words_count] = sizeof(ains->br_compact);
1964 memcpy(&bundle.body_words[bundle.body_words_count++], &ains->br_compact, sizeof(ains->br_compact));
1965 bytes_emitted += sizeof(ains->br_compact);
1966 }
1967 } else {
1968 memcpy(&bundle.register_words[bundle.register_words_count++], &ains->registers, sizeof(ains->registers));
1969 bytes_emitted += sizeof(midgard_reg_info);
1970
1971 bundle.body_size[bundle.body_words_count] = sizeof(midgard_scalar_alu);
1972 bundle.body_words_count++;
1973 bytes_emitted += sizeof(midgard_scalar_alu);
1974 }
1975
1976 /* Defer marking until after writing to allow for break */
1977 control |= ains->unit;
1978 last_unit = ains->unit;
1979 ++instructions_emitted;
1980 ++index;
1981 }
1982
1983 /* Bubble up the number of instructions for skipping */
1984 instructions_consumed = index - 1;
1985
1986 int padding = 0;
1987
1988 /* Pad ALU op to nearest word */
1989
1990 if (bytes_emitted & 15) {
1991 padding = 16 - (bytes_emitted & 15);
1992 bytes_emitted += padding;
1993 }
1994
1995 /* Constants must always be quadwords */
1996 if (bundle.has_embedded_constants)
1997 bytes_emitted += 16;
1998
1999 /* Size ALU instruction for tag */
2000 bundle.tag = (TAG_ALU_4) + (bytes_emitted / 16) - 1;
2001 bundle.padding = padding;
2002 bundle.control = bundle.tag | control;
2003
2004 break;
2005 }
2006
2007 case TAG_LOAD_STORE_4: {
2008 /* Load store instructions have two words at once. If
2009 * we only have one queued up, we need to NOP pad.
2010 * Otherwise, we store both in succession to save space
2011 * and cycles -- letting them go in parallel -- skip
2012 * the next. The usefulness of this optimisation is
2013 * greatly dependent on the quality of the instruction
2014 * scheduler.
2015 */
2016
2017 midgard_instruction *next_op = mir_next_op(ins);
2018
2019 if ((struct list_head *) next_op != &block->instructions && next_op->type == TAG_LOAD_STORE_4) {
2020 /* As the two operate concurrently, make sure
2021 * they are not dependent */
2022
2023 if (can_run_concurrent_ssa(ins, next_op) || true) {
2024 /* Skip ahead, since it's redundant with the pair */
2025 instructions_consumed = 1 + (instructions_emitted++);
2026 }
2027 }
2028
2029 break;
2030 }
2031
2032 default:
2033 /* Texture ops default to single-op-per-bundle scheduling */
2034 break;
2035 }
2036
2037 /* Copy the instructions into the bundle */
2038 bundle.instruction_count = instructions_emitted + 1;
2039
2040 int used_idx = 0;
2041
2042 midgard_instruction *uins = ins;
2043 for (int i = 0; used_idx < bundle.instruction_count; ++i) {
2044 bundle.instructions[used_idx++] = *uins;
2045 uins = mir_next_op(uins);
2046 }
2047
2048 *skip = (instructions_consumed == -1) ? instructions_emitted : instructions_consumed;
2049
2050 return bundle;
2051 }
2052
2053 static int
2054 quadword_size(int tag)
2055 {
2056 switch (tag) {
2057 case TAG_ALU_4:
2058 return 1;
2059
2060 case TAG_ALU_8:
2061 return 2;
2062
2063 case TAG_ALU_12:
2064 return 3;
2065
2066 case TAG_ALU_16:
2067 return 4;
2068
2069 case TAG_LOAD_STORE_4:
2070 return 1;
2071
2072 case TAG_TEXTURE_4:
2073 return 1;
2074
2075 default:
2076 assert(0);
2077 return 0;
2078 }
2079 }
2080
2081 /* Schedule a single block by iterating its instruction to create bundles.
2082 * While we go, tally about the bundle sizes to compute the block size. */
2083
2084 static void
2085 schedule_block(compiler_context *ctx, midgard_block *block)
2086 {
2087 util_dynarray_init(&block->bundles, NULL);
2088
2089 block->quadword_count = 0;
2090
2091 mir_foreach_instr_in_block(block, ins) {
2092 int skip;
2093 midgard_bundle bundle = schedule_bundle(ctx, block, ins, &skip);
2094 util_dynarray_append(&block->bundles, midgard_bundle, bundle);
2095
2096 if (bundle.has_blend_constant) {
2097 /* TODO: Multiblock? */
2098 int quadwords_within_block = block->quadword_count + quadword_size(bundle.tag) - 1;
2099 ctx->blend_constant_offset = quadwords_within_block * 0x10;
2100 }
2101
2102 while(skip--)
2103 ins = mir_next_op(ins);
2104
2105 block->quadword_count += quadword_size(bundle.tag);
2106 }
2107
2108 block->is_scheduled = true;
2109 }
2110
2111 static void
2112 schedule_program(compiler_context *ctx)
2113 {
2114 /* We run RA prior to scheduling */
2115 struct ra_graph *g = allocate_registers(ctx);
2116 install_registers(ctx, g);
2117
2118 mir_foreach_block(ctx, block) {
2119 schedule_block(ctx, block);
2120 }
2121 }
2122
2123 /* After everything is scheduled, emit whole bundles at a time */
2124
2125 static void
2126 emit_binary_bundle(compiler_context *ctx, midgard_bundle *bundle, struct util_dynarray *emission, int next_tag)
2127 {
2128 int lookahead = next_tag << 4;
2129
2130 switch (bundle->tag) {
2131 case TAG_ALU_4:
2132 case TAG_ALU_8:
2133 case TAG_ALU_12:
2134 case TAG_ALU_16: {
2135 /* Actually emit each component */
2136 util_dynarray_append(emission, uint32_t, bundle->control | lookahead);
2137
2138 for (int i = 0; i < bundle->register_words_count; ++i)
2139 util_dynarray_append(emission, uint16_t, bundle->register_words[i]);
2140
2141 /* Emit body words based on the instructions bundled */
2142 for (int i = 0; i < bundle->instruction_count; ++i) {
2143 midgard_instruction *ins = &bundle->instructions[i];
2144
2145 if (ins->unit & UNITS_ANY_VECTOR) {
2146 memcpy(util_dynarray_grow(emission, sizeof(midgard_vector_alu)), &ins->alu, sizeof(midgard_vector_alu));
2147 } else if (ins->compact_branch) {
2148 /* Dummy move, XXX DRY */
2149 if ((i == 0) && ins->writeout) {
2150 midgard_instruction ins = v_fmov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
2151 memcpy(util_dynarray_grow(emission, sizeof(midgard_vector_alu)), &ins.alu, sizeof(midgard_vector_alu));
2152 }
2153
2154 if (ins->unit == ALU_ENAB_BR_COMPACT) {
2155 memcpy(util_dynarray_grow(emission, sizeof(ins->br_compact)), &ins->br_compact, sizeof(ins->br_compact));
2156 } else {
2157 memcpy(util_dynarray_grow(emission, sizeof(ins->branch_extended)), &ins->branch_extended, sizeof(ins->branch_extended));
2158 }
2159 } else {
2160 /* Scalar */
2161 midgard_scalar_alu scalarised = vector_to_scalar_alu(ins->alu, ins);
2162 memcpy(util_dynarray_grow(emission, sizeof(scalarised)), &scalarised, sizeof(scalarised));
2163 }
2164 }
2165
2166 /* Emit padding (all zero) */
2167 memset(util_dynarray_grow(emission, bundle->padding), 0, bundle->padding);
2168
2169 /* Tack on constants */
2170
2171 if (bundle->has_embedded_constants) {
2172 util_dynarray_append(emission, float, bundle->constants[0]);
2173 util_dynarray_append(emission, float, bundle->constants[1]);
2174 util_dynarray_append(emission, float, bundle->constants[2]);
2175 util_dynarray_append(emission, float, bundle->constants[3]);
2176 }
2177
2178 break;
2179 }
2180
2181 case TAG_LOAD_STORE_4: {
2182 /* One or two composing instructions */
2183
2184 uint64_t current64, next64 = LDST_NOP;
2185
2186 memcpy(&current64, &bundle->instructions[0].load_store, sizeof(current64));
2187
2188 if (bundle->instruction_count == 2)
2189 memcpy(&next64, &bundle->instructions[1].load_store, sizeof(next64));
2190
2191 midgard_load_store instruction = {
2192 .type = bundle->tag,
2193 .next_type = next_tag,
2194 .word1 = current64,
2195 .word2 = next64
2196 };
2197
2198 util_dynarray_append(emission, midgard_load_store, instruction);
2199
2200 break;
2201 }
2202
2203 case TAG_TEXTURE_4: {
2204 /* Texture instructions are easy, since there is no
2205 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2206
2207 midgard_instruction *ins = &bundle->instructions[0];
2208
2209 ins->texture.type = TAG_TEXTURE_4;
2210 ins->texture.next_type = next_tag;
2211
2212 ctx->texture_op_count--;
2213
2214 if (!ctx->texture_op_count) {
2215 ins->texture.cont = 0;
2216 ins->texture.last = 1;
2217 }
2218
2219 util_dynarray_append(emission, midgard_texture_word, ins->texture);
2220 break;
2221 }
2222
2223 default:
2224 DBG("Unknown midgard instruction type\n");
2225 assert(0);
2226 break;
2227 }
2228 }
2229
2230
2231 /* ALU instructions can inline or embed constants, which decreases register
2232 * pressure and saves space. */
2233
2234 #define CONDITIONAL_ATTACH(src) { \
2235 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2236 \
2237 if (entry) { \
2238 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2239 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2240 } \
2241 }
2242
2243 static void
2244 inline_alu_constants(compiler_context *ctx)
2245 {
2246 mir_foreach_instr(ctx, alu) {
2247 /* Other instructions cannot inline constants */
2248 if (alu->type != TAG_ALU_4) continue;
2249
2250 /* If there is already a constant here, we can do nothing */
2251 if (alu->has_constants) continue;
2252
2253 /* It makes no sense to inline constants on a branch */
2254 if (alu->compact_branch || alu->prepacked_branch) continue;
2255
2256 CONDITIONAL_ATTACH(src0);
2257
2258 if (!alu->has_constants) {
2259 CONDITIONAL_ATTACH(src1)
2260 } else if (!alu->inline_constant) {
2261 /* Corner case: _two_ vec4 constants, for instance with a
2262 * csel. For this case, we can only use a constant
2263 * register for one, we'll have to emit a move for the
2264 * other. Note, if both arguments are constants, then
2265 * necessarily neither argument depends on the value of
2266 * any particular register. As the destination register
2267 * will be wiped, that means we can spill the constant
2268 * to the destination register.
2269 */
2270
2271 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
2272 unsigned scratch = alu->ssa_args.dest;
2273
2274 if (entry) {
2275 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
2276 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
2277
2278 /* Force a break XXX Defer r31 writes */
2279 ins.unit = UNIT_VLUT;
2280
2281 /* Set the source */
2282 alu->ssa_args.src1 = scratch;
2283
2284 /* Inject us -before- the last instruction which set r31 */
2285 mir_insert_instruction_before(mir_prev_op(alu), ins);
2286 }
2287 }
2288 }
2289 }
2290
2291 /* Midgard supports two types of constants, embedded constants (128-bit) and
2292 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2293 * constants can be demoted to inline constants, for space savings and
2294 * sometimes a performance boost */
2295
2296 static void
2297 embedded_to_inline_constant(compiler_context *ctx)
2298 {
2299 mir_foreach_instr(ctx, ins) {
2300 if (!ins->has_constants) continue;
2301
2302 if (ins->ssa_args.inline_constant) continue;
2303
2304 /* Blend constants must not be inlined by definition */
2305 if (ins->has_blend_constant) continue;
2306
2307 /* src1 cannot be an inline constant due to encoding
2308 * restrictions. So, if possible we try to flip the arguments
2309 * in that case */
2310
2311 int op = ins->alu.op;
2312
2313 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2314 switch (op) {
2315 /* These ops require an operational change to flip
2316 * their arguments TODO */
2317 case midgard_alu_op_flt:
2318 case midgard_alu_op_fle:
2319 case midgard_alu_op_ilt:
2320 case midgard_alu_op_ile:
2321 case midgard_alu_op_fcsel:
2322 case midgard_alu_op_icsel:
2323 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2324 default:
2325 break;
2326 }
2327
2328 if (alu_opcode_props[op].props & OP_COMMUTES) {
2329 /* Flip the SSA numbers */
2330 ins->ssa_args.src0 = ins->ssa_args.src1;
2331 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
2332
2333 /* And flip the modifiers */
2334
2335 unsigned src_temp;
2336
2337 src_temp = ins->alu.src2;
2338 ins->alu.src2 = ins->alu.src1;
2339 ins->alu.src1 = src_temp;
2340 }
2341 }
2342
2343 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2344 /* Extract the source information */
2345
2346 midgard_vector_alu_src *src;
2347 int q = ins->alu.src2;
2348 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2349 src = m;
2350
2351 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2352 int component = src->swizzle & 3;
2353
2354 /* Scale constant appropriately, if we can legally */
2355 uint16_t scaled_constant = 0;
2356
2357 if (midgard_is_integer_op(op)) {
2358 unsigned int *iconstants = (unsigned int *) ins->constants;
2359 scaled_constant = (uint16_t) iconstants[component];
2360
2361 /* Constant overflow after resize */
2362 if (scaled_constant != iconstants[component])
2363 continue;
2364 } else {
2365 float original = (float) ins->constants[component];
2366 scaled_constant = _mesa_float_to_half(original);
2367
2368 /* Check for loss of precision. If this is
2369 * mediump, we don't care, but for a highp
2370 * shader, we need to pay attention. NIR
2371 * doesn't yet tell us which mode we're in!
2372 * Practically this prevents most constants
2373 * from being inlined, sadly. */
2374
2375 float fp32 = _mesa_half_to_float(scaled_constant);
2376
2377 if (fp32 != original)
2378 continue;
2379 }
2380
2381 /* We don't know how to handle these with a constant */
2382
2383 if (src->mod || src->half || src->rep_low || src->rep_high) {
2384 DBG("Bailing inline constant...\n");
2385 continue;
2386 }
2387
2388 /* Make sure that the constant is not itself a
2389 * vector by checking if all accessed values
2390 * (by the swizzle) are the same. */
2391
2392 uint32_t *cons = (uint32_t *) ins->constants;
2393 uint32_t value = cons[component];
2394
2395 bool is_vector = false;
2396 unsigned mask = effective_writemask(&ins->alu);
2397
2398 for (int c = 1; c < 4; ++c) {
2399 /* We only care if this component is actually used */
2400 if (!(mask & (1 << c)))
2401 continue;
2402
2403 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
2404
2405 if (test != value) {
2406 is_vector = true;
2407 break;
2408 }
2409 }
2410
2411 if (is_vector)
2412 continue;
2413
2414 /* Get rid of the embedded constant */
2415 ins->has_constants = false;
2416 ins->ssa_args.src1 = SSA_UNUSED_0;
2417 ins->ssa_args.inline_constant = true;
2418 ins->inline_constant = scaled_constant;
2419 }
2420 }
2421 }
2422
2423 /* Map normal SSA sources to other SSA sources / fixed registers (like
2424 * uniforms) */
2425
2426 static void
2427 map_ssa_to_alias(compiler_context *ctx, int *ref)
2428 {
2429 unsigned int alias = (uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_to_alias, *ref + 1);
2430
2431 if (alias) {
2432 /* Remove entry in leftovers to avoid a redunant fmov */
2433
2434 struct set_entry *leftover = _mesa_set_search(ctx->leftover_ssa_to_alias, ((void *) (uintptr_t) (*ref + 1)));
2435
2436 if (leftover)
2437 _mesa_set_remove(ctx->leftover_ssa_to_alias, leftover);
2438
2439 /* Assign the alias map */
2440 *ref = alias - 1;
2441 return;
2442 }
2443 }
2444
2445 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
2446 * texture pipeline */
2447
2448 static bool
2449 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
2450 {
2451 bool progress = false;
2452
2453 mir_foreach_instr_in_block_safe(block, ins) {
2454 if (ins->type != TAG_ALU_4) continue;
2455 if (ins->compact_branch) continue;
2456
2457 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
2458 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
2459
2460 mir_remove_instruction(ins);
2461 progress = true;
2462 }
2463
2464 return progress;
2465 }
2466
2467 static bool
2468 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
2469 {
2470 /* abs or neg */
2471 if (!is_int && src.mod) return true;
2472
2473 /* swizzle */
2474 for (unsigned c = 0; c < 4; ++c) {
2475 if (!(mask & (1 << c))) continue;
2476 if (((src.swizzle >> (2*c)) & 3) != c) return true;
2477 }
2478
2479 return false;
2480 }
2481
2482 static bool
2483 midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
2484 {
2485 bool progress = false;
2486
2487 mir_foreach_instr_in_block_safe(block, ins) {
2488 if (ins->type != TAG_ALU_4) continue;
2489 if (!OP_IS_MOVE(ins->alu.op)) continue;
2490
2491 unsigned from = ins->ssa_args.src1;
2492 unsigned to = ins->ssa_args.dest;
2493
2494 /* We only work on pure SSA */
2495
2496 if (to >= SSA_FIXED_MINIMUM) continue;
2497 if (from >= SSA_FIXED_MINIMUM) continue;
2498 if (to >= ctx->func->impl->ssa_alloc) continue;
2499 if (from >= ctx->func->impl->ssa_alloc) continue;
2500
2501 /* Constant propagation is not handled here, either */
2502 if (ins->ssa_args.inline_constant) continue;
2503 if (ins->has_constants) continue;
2504
2505 /* Also, if the move has side effects, we're helpless */
2506
2507 midgard_vector_alu_src src =
2508 vector_alu_from_unsigned(ins->alu.src2);
2509 unsigned mask = squeeze_writemask(ins->alu.mask);
2510 bool is_int = midgard_is_integer_op(ins->alu.op);
2511
2512 if (mir_nontrivial_mod(src, is_int, mask)) continue;
2513 if (ins->alu.outmod != midgard_outmod_none) continue;
2514
2515 mir_foreach_instr_in_block_from(block, v, mir_next_op(ins)) {
2516 if (v->ssa_args.src0 == to) {
2517 v->ssa_args.src0 = from;
2518 progress = true;
2519 }
2520
2521 if (v->ssa_args.src1 == to && !v->ssa_args.inline_constant) {
2522 v->ssa_args.src1 = from;
2523 progress = true;
2524 }
2525 }
2526 }
2527
2528 return progress;
2529 }
2530
2531 static bool
2532 midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
2533 {
2534 bool progress = false;
2535
2536 mir_foreach_instr_in_block_safe(block, ins) {
2537 if (ins->type != TAG_ALU_4) continue;
2538 if (!OP_IS_MOVE(ins->alu.op)) continue;
2539
2540 unsigned from = ins->ssa_args.src1;
2541 unsigned to = ins->ssa_args.dest;
2542
2543 /* Make sure it's simple enough for us to handle */
2544
2545 if (from >= SSA_FIXED_MINIMUM) continue;
2546 if (from >= ctx->func->impl->ssa_alloc) continue;
2547 if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
2548 if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
2549
2550 bool eliminated = false;
2551
2552 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2553 /* The texture registers are not SSA so be careful.
2554 * Conservatively, just stop if we hit a texture op
2555 * (even if it may not write) to where we are */
2556
2557 if (v->type != TAG_ALU_4)
2558 break;
2559
2560 if (v->ssa_args.dest == from) {
2561 /* We don't want to track partial writes ... */
2562 if (v->alu.mask == 0xF) {
2563 v->ssa_args.dest = to;
2564 eliminated = true;
2565 }
2566
2567 break;
2568 }
2569 }
2570
2571 if (eliminated)
2572 mir_remove_instruction(ins);
2573
2574 progress |= eliminated;
2575 }
2576
2577 return progress;
2578 }
2579
2580 /* The following passes reorder MIR instructions to enable better scheduling */
2581
2582 static void
2583 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
2584 {
2585 mir_foreach_instr_in_block_safe(block, ins) {
2586 if (ins->type != TAG_LOAD_STORE_4) continue;
2587
2588 /* We've found a load/store op. Check if next is also load/store. */
2589 midgard_instruction *next_op = mir_next_op(ins);
2590 if (&next_op->link != &block->instructions) {
2591 if (next_op->type == TAG_LOAD_STORE_4) {
2592 /* If so, we're done since we're a pair */
2593 ins = mir_next_op(ins);
2594 continue;
2595 }
2596
2597 /* Maximum search distance to pair, to avoid register pressure disasters */
2598 int search_distance = 8;
2599
2600 /* Otherwise, we have an orphaned load/store -- search for another load */
2601 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
2602 /* Terminate search if necessary */
2603 if (!(search_distance--)) break;
2604
2605 if (c->type != TAG_LOAD_STORE_4) continue;
2606
2607 /* Stores cannot be reordered, since they have
2608 * dependencies. For the same reason, indirect
2609 * loads cannot be reordered as their index is
2610 * loaded in r27.w */
2611
2612 if (OP_IS_STORE(c->load_store.op)) continue;
2613
2614 /* It appears the 0x800 bit is set whenever a
2615 * load is direct, unset when it is indirect.
2616 * Skip indirect loads. */
2617
2618 if (!(c->load_store.unknown & 0x800)) continue;
2619
2620 /* We found one! Move it up to pair and remove it from the old location */
2621
2622 mir_insert_instruction_before(ins, *c);
2623 mir_remove_instruction(c);
2624
2625 break;
2626 }
2627 }
2628 }
2629 }
2630
2631 /* Emit varying stores late */
2632
2633 static void
2634 midgard_emit_store(compiler_context *ctx, midgard_block *block) {
2635 /* Iterate in reverse to get the final write, rather than the first */
2636
2637 mir_foreach_instr_in_block_safe_rev(block, ins) {
2638 /* Check if what we just wrote needs a store */
2639 int idx = ins->ssa_args.dest;
2640 uintptr_t varying = ((uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_varyings, idx + 1));
2641
2642 if (!varying) continue;
2643
2644 varying -= 1;
2645
2646 /* We need to store to the appropriate varying, so emit the
2647 * move/store */
2648
2649 /* TODO: Integrate with special purpose RA (and scheduler?) */
2650 bool high_varying_register = false;
2651
2652 midgard_instruction mov = v_fmov(idx, blank_alu_src, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE + high_varying_register));
2653
2654 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(high_varying_register), varying);
2655 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
2656
2657 mir_insert_instruction_before(mir_next_op(ins), st);
2658 mir_insert_instruction_before(mir_next_op(ins), mov);
2659
2660 /* We no longer need to store this varying */
2661 _mesa_hash_table_u64_remove(ctx->ssa_varyings, idx + 1);
2662 }
2663 }
2664
2665 /* If there are leftovers after the below pass, emit actual fmov
2666 * instructions for the slow-but-correct path */
2667
2668 static void
2669 emit_leftover_move(compiler_context *ctx)
2670 {
2671 set_foreach(ctx->leftover_ssa_to_alias, leftover) {
2672 int base = ((uintptr_t) leftover->key) - 1;
2673 int mapped = base;
2674
2675 map_ssa_to_alias(ctx, &mapped);
2676 EMIT(fmov, mapped, blank_alu_src, base);
2677 }
2678 }
2679
2680 static void
2681 actualise_ssa_to_alias(compiler_context *ctx)
2682 {
2683 mir_foreach_instr(ctx, ins) {
2684 map_ssa_to_alias(ctx, &ins->ssa_args.src0);
2685 map_ssa_to_alias(ctx, &ins->ssa_args.src1);
2686 }
2687
2688 emit_leftover_move(ctx);
2689 }
2690
2691 static void
2692 emit_fragment_epilogue(compiler_context *ctx)
2693 {
2694 /* Special case: writing out constants requires us to include the move
2695 * explicitly now, so shove it into r0 */
2696
2697 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, ctx->fragment_output + 1);
2698
2699 if (constant_value) {
2700 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(0));
2701 attach_constants(ctx, &ins, constant_value, ctx->fragment_output + 1);
2702 emit_mir_instruction(ctx, ins);
2703 }
2704
2705 /* Perform the actual fragment writeout. We have two writeout/branch
2706 * instructions, forming a loop until writeout is successful as per the
2707 * docs. TODO: gl_FragDepth */
2708
2709 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2710 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2711 }
2712
2713 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2714 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2715 * with the int8 analogue to the fragment epilogue */
2716
2717 static void
2718 emit_blend_epilogue(compiler_context *ctx)
2719 {
2720 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2721
2722 midgard_instruction scale = {
2723 .type = TAG_ALU_4,
2724 .unit = UNIT_VMUL,
2725 .inline_constant = _mesa_float_to_half(255.0),
2726 .ssa_args = {
2727 .src0 = SSA_FIXED_REGISTER(0),
2728 .src1 = SSA_UNUSED_0,
2729 .dest = SSA_FIXED_REGISTER(24),
2730 .inline_constant = true
2731 },
2732 .alu = {
2733 .op = midgard_alu_op_fmul,
2734 .reg_mode = midgard_reg_mode_32,
2735 .dest_override = midgard_dest_override_lower,
2736 .mask = 0xFF,
2737 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2738 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2739 }
2740 };
2741
2742 emit_mir_instruction(ctx, scale);
2743
2744 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2745
2746 midgard_vector_alu_src alu_src = blank_alu_src;
2747 alu_src.half = true;
2748
2749 midgard_instruction f2u8 = {
2750 .type = TAG_ALU_4,
2751 .ssa_args = {
2752 .src0 = SSA_FIXED_REGISTER(24),
2753 .src1 = SSA_UNUSED_0,
2754 .dest = SSA_FIXED_REGISTER(0),
2755 .inline_constant = true
2756 },
2757 .alu = {
2758 .op = midgard_alu_op_f2u8,
2759 .reg_mode = midgard_reg_mode_16,
2760 .dest_override = midgard_dest_override_lower,
2761 .outmod = midgard_outmod_pos,
2762 .mask = 0xF,
2763 .src1 = vector_alu_srco_unsigned(alu_src),
2764 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2765 }
2766 };
2767
2768 emit_mir_instruction(ctx, f2u8);
2769
2770 /* vmul.imov.quarter r0, r0, r0 */
2771
2772 midgard_instruction imov_8 = {
2773 .type = TAG_ALU_4,
2774 .ssa_args = {
2775 .src0 = SSA_UNUSED_1,
2776 .src1 = SSA_FIXED_REGISTER(0),
2777 .dest = SSA_FIXED_REGISTER(0),
2778 },
2779 .alu = {
2780 .op = midgard_alu_op_imov,
2781 .reg_mode = midgard_reg_mode_8,
2782 .dest_override = midgard_dest_override_none,
2783 .outmod = midgard_outmod_int,
2784 .mask = 0xFF,
2785 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2786 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2787 }
2788 };
2789
2790 /* Emit branch epilogue with the 8-bit move as the source */
2791
2792 emit_mir_instruction(ctx, imov_8);
2793 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2794
2795 emit_mir_instruction(ctx, imov_8);
2796 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2797 }
2798
2799 static midgard_block *
2800 emit_block(compiler_context *ctx, nir_block *block)
2801 {
2802 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2803 list_addtail(&this_block->link, &ctx->blocks);
2804
2805 this_block->is_scheduled = false;
2806 ++ctx->block_count;
2807
2808 ctx->texture_index[0] = -1;
2809 ctx->texture_index[1] = -1;
2810
2811 /* Add us as a successor to the block we are following */
2812 if (ctx->current_block)
2813 midgard_block_add_successor(ctx->current_block, this_block);
2814
2815 /* Set up current block */
2816 list_inithead(&this_block->instructions);
2817 ctx->current_block = this_block;
2818
2819 nir_foreach_instr(instr, block) {
2820 emit_instr(ctx, instr);
2821 ++ctx->instruction_count;
2822 }
2823
2824 inline_alu_constants(ctx);
2825 embedded_to_inline_constant(ctx);
2826
2827 /* Perform heavylifting for aliasing */
2828 actualise_ssa_to_alias(ctx);
2829
2830 midgard_emit_store(ctx, this_block);
2831 midgard_pair_load_store(ctx, this_block);
2832
2833 /* Append fragment shader epilogue (value writeout) */
2834 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2835 if (block == nir_impl_last_block(ctx->func->impl)) {
2836 if (ctx->is_blend)
2837 emit_blend_epilogue(ctx);
2838 else
2839 emit_fragment_epilogue(ctx);
2840 }
2841 }
2842
2843 if (block == nir_start_block(ctx->func->impl))
2844 ctx->initial_block = this_block;
2845
2846 if (block == nir_impl_last_block(ctx->func->impl))
2847 ctx->final_block = this_block;
2848
2849 /* Allow the next control flow to access us retroactively, for
2850 * branching etc */
2851 ctx->current_block = this_block;
2852
2853 /* Document the fallthrough chain */
2854 ctx->previous_source_block = this_block;
2855
2856 return this_block;
2857 }
2858
2859 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2860
2861 static void
2862 emit_if(struct compiler_context *ctx, nir_if *nif)
2863 {
2864 /* Conditional branches expect the condition in r31.w; emit a move for
2865 * that in the _previous_ block (which is the current block). */
2866 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2867
2868 /* Speculatively emit the branch, but we can't fill it in until later */
2869 EMIT(branch, true, true);
2870 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2871
2872 /* Emit the two subblocks */
2873 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2874
2875 /* Emit a jump from the end of the then block to the end of the else */
2876 EMIT(branch, false, false);
2877 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2878
2879 /* Emit second block, and check if it's empty */
2880
2881 int else_idx = ctx->block_count;
2882 int count_in = ctx->instruction_count;
2883 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2884 int after_else_idx = ctx->block_count;
2885
2886 /* Now that we have the subblocks emitted, fix up the branches */
2887
2888 assert(then_block);
2889 assert(else_block);
2890
2891 if (ctx->instruction_count == count_in) {
2892 /* The else block is empty, so don't emit an exit jump */
2893 mir_remove_instruction(then_exit);
2894 then_branch->branch.target_block = after_else_idx;
2895 } else {
2896 then_branch->branch.target_block = else_idx;
2897 then_exit->branch.target_block = after_else_idx;
2898 }
2899 }
2900
2901 static void
2902 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2903 {
2904 /* Remember where we are */
2905 midgard_block *start_block = ctx->current_block;
2906
2907 /* Allocate a loop number, growing the current inner loop depth */
2908 int loop_idx = ++ctx->current_loop_depth;
2909
2910 /* Get index from before the body so we can loop back later */
2911 int start_idx = ctx->block_count;
2912
2913 /* Emit the body itself */
2914 emit_cf_list(ctx, &nloop->body);
2915
2916 /* Branch back to loop back */
2917 struct midgard_instruction br_back = v_branch(false, false);
2918 br_back.branch.target_block = start_idx;
2919 emit_mir_instruction(ctx, br_back);
2920
2921 /* Mark down that branch in the graph. Note that we're really branching
2922 * to the block *after* we started in. TODO: Why doesn't the branch
2923 * itself have an off-by-one then...? */
2924 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2925
2926 /* Find the index of the block about to follow us (note: we don't add
2927 * one; blocks are 0-indexed so we get a fencepost problem) */
2928 int break_block_idx = ctx->block_count;
2929
2930 /* Fix up the break statements we emitted to point to the right place,
2931 * now that we can allocate a block number for them */
2932
2933 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2934 mir_foreach_instr_in_block(block, ins) {
2935 if (ins->type != TAG_ALU_4) continue;
2936 if (!ins->compact_branch) continue;
2937 if (ins->prepacked_branch) continue;
2938
2939 /* We found a branch -- check the type to see if we need to do anything */
2940 if (ins->branch.target_type != TARGET_BREAK) continue;
2941
2942 /* It's a break! Check if it's our break */
2943 if (ins->branch.target_break != loop_idx) continue;
2944
2945 /* Okay, cool, we're breaking out of this loop.
2946 * Rewrite from a break to a goto */
2947
2948 ins->branch.target_type = TARGET_GOTO;
2949 ins->branch.target_block = break_block_idx;
2950 }
2951 }
2952
2953 /* Now that we've finished emitting the loop, free up the depth again
2954 * so we play nice with recursion amid nested loops */
2955 --ctx->current_loop_depth;
2956 }
2957
2958 static midgard_block *
2959 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2960 {
2961 midgard_block *start_block = NULL;
2962
2963 foreach_list_typed(nir_cf_node, node, node, list) {
2964 switch (node->type) {
2965 case nir_cf_node_block: {
2966 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2967
2968 if (!start_block)
2969 start_block = block;
2970
2971 break;
2972 }
2973
2974 case nir_cf_node_if:
2975 emit_if(ctx, nir_cf_node_as_if(node));
2976 break;
2977
2978 case nir_cf_node_loop:
2979 emit_loop(ctx, nir_cf_node_as_loop(node));
2980 break;
2981
2982 case nir_cf_node_function:
2983 assert(0);
2984 break;
2985 }
2986 }
2987
2988 return start_block;
2989 }
2990
2991 /* Due to lookahead, we need to report the first tag executed in the command
2992 * stream and in branch targets. An initial block might be empty, so iterate
2993 * until we find one that 'works' */
2994
2995 static unsigned
2996 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2997 {
2998 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2999
3000 unsigned first_tag = 0;
3001
3002 do {
3003 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
3004
3005 if (initial_bundle) {
3006 first_tag = initial_bundle->tag;
3007 break;
3008 }
3009
3010 /* Initial block is empty, try the next block */
3011 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
3012 } while(initial_block != NULL);
3013
3014 assert(first_tag);
3015 return first_tag;
3016 }
3017
3018 int
3019 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend)
3020 {
3021 struct util_dynarray *compiled = &program->compiled;
3022
3023 midgard_debug = debug_get_option_midgard_debug();
3024
3025 compiler_context ictx = {
3026 .nir = nir,
3027 .stage = nir->info.stage,
3028
3029 .is_blend = is_blend,
3030 .blend_constant_offset = -1,
3031
3032 .alpha_ref = program->alpha_ref
3033 };
3034
3035 compiler_context *ctx = &ictx;
3036
3037 /* TODO: Decide this at runtime */
3038 ctx->uniform_cutoff = 8;
3039
3040 /* Assign var locations early, so the epilogue can use them if necessary */
3041
3042 nir_assign_var_locations(&nir->outputs, &nir->num_outputs, glsl_type_size);
3043 nir_assign_var_locations(&nir->inputs, &nir->num_inputs, glsl_type_size);
3044 nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms, glsl_type_size);
3045
3046 /* Initialize at a global (not block) level hash tables */
3047
3048 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
3049 ctx->ssa_varyings = _mesa_hash_table_u64_create(NULL);
3050 ctx->ssa_to_alias = _mesa_hash_table_u64_create(NULL);
3051 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
3052 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
3053 ctx->leftover_ssa_to_alias = _mesa_set_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
3054
3055 /* Record the varying mapping for the command stream's bookkeeping */
3056
3057 struct exec_list *varyings =
3058 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
3059
3060 nir_foreach_variable(var, varyings) {
3061 unsigned loc = var->data.driver_location;
3062 unsigned sz = glsl_type_size(var->type, FALSE);
3063
3064 for (int c = 0; c < sz; ++c) {
3065 program->varyings[loc + c] = var->data.location;
3066 }
3067 }
3068
3069 /* Lower gl_Position pre-optimisation */
3070
3071 if (ctx->stage == MESA_SHADER_VERTEX)
3072 NIR_PASS_V(nir, nir_lower_viewport_transform);
3073
3074 NIR_PASS_V(nir, nir_lower_var_copies);
3075 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
3076 NIR_PASS_V(nir, nir_split_var_copies);
3077 NIR_PASS_V(nir, nir_lower_var_copies);
3078 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
3079 NIR_PASS_V(nir, nir_lower_var_copies);
3080 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
3081
3082 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
3083
3084 /* Optimisation passes */
3085
3086 optimise_nir(nir);
3087
3088 if (midgard_debug & MIDGARD_DBG_SHADERS) {
3089 nir_print_shader(nir, stdout);
3090 }
3091
3092 /* Assign sysvals and counts, now that we're sure
3093 * (post-optimisation) */
3094
3095 midgard_nir_assign_sysvals(ctx, nir);
3096
3097 program->uniform_count = nir->num_uniforms;
3098 program->sysval_count = ctx->sysval_count;
3099 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
3100
3101 program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_inputs : 0;
3102 program->varying_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_outputs : ((ctx->stage == MESA_SHADER_FRAGMENT) ? nir->num_inputs : 0);
3103
3104 nir_foreach_function(func, nir) {
3105 if (!func->impl)
3106 continue;
3107
3108 list_inithead(&ctx->blocks);
3109 ctx->block_count = 0;
3110 ctx->func = func;
3111
3112 emit_cf_list(ctx, &func->impl->body);
3113 emit_block(ctx, func->impl->end_block);
3114
3115 break; /* TODO: Multi-function shaders */
3116 }
3117
3118 util_dynarray_init(compiled, NULL);
3119
3120 /* MIR-level optimizations */
3121
3122 bool progress = false;
3123
3124 do {
3125 progress = false;
3126
3127 mir_foreach_block(ctx, block) {
3128 progress |= midgard_opt_copy_prop(ctx, block);
3129 progress |= midgard_opt_copy_prop_tex(ctx, block);
3130 progress |= midgard_opt_dead_code_eliminate(ctx, block);
3131 }
3132 } while (progress);
3133
3134 /* Schedule! */
3135 schedule_program(ctx);
3136
3137 /* Now that all the bundles are scheduled and we can calculate block
3138 * sizes, emit actual branch instructions rather than placeholders */
3139
3140 int br_block_idx = 0;
3141
3142 mir_foreach_block(ctx, block) {
3143 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3144 for (int c = 0; c < bundle->instruction_count; ++c) {
3145 midgard_instruction *ins = &bundle->instructions[c];
3146
3147 if (!midgard_is_branch_unit(ins->unit)) continue;
3148
3149 if (ins->prepacked_branch) continue;
3150
3151 /* Parse some basic branch info */
3152 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
3153 bool is_conditional = ins->branch.conditional;
3154 bool is_inverted = ins->branch.invert_conditional;
3155 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
3156
3157 /* Determine the block we're jumping to */
3158 int target_number = ins->branch.target_block;
3159
3160 /* Report the destination tag. Discards don't need this */
3161 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
3162
3163 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3164 int quadword_offset = 0;
3165
3166 if (is_discard) {
3167 /* Jump to the end of the shader. We
3168 * need to include not only the
3169 * following blocks, but also the
3170 * contents of our current block (since
3171 * discard can come in the middle of
3172 * the block) */
3173
3174 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
3175
3176 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
3177 quadword_offset += quadword_size(bun->tag);
3178 }
3179
3180 mir_foreach_block_from(ctx, blk, b) {
3181 quadword_offset += b->quadword_count;
3182 }
3183
3184 } else if (target_number > br_block_idx) {
3185 /* Jump forward */
3186
3187 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
3188 midgard_block *blk = mir_get_block(ctx, idx);
3189 assert(blk);
3190
3191 quadword_offset += blk->quadword_count;
3192 }
3193 } else {
3194 /* Jump backwards */
3195
3196 for (int idx = br_block_idx; idx >= target_number; --idx) {
3197 midgard_block *blk = mir_get_block(ctx, idx);
3198 assert(blk);
3199
3200 quadword_offset -= blk->quadword_count;
3201 }
3202 }
3203
3204 /* Unconditional extended branches (far jumps)
3205 * have issues, so we always use a conditional
3206 * branch, setting the condition to always for
3207 * unconditional. For compact unconditional
3208 * branches, cond isn't used so it doesn't
3209 * matter what we pick. */
3210
3211 midgard_condition cond =
3212 !is_conditional ? midgard_condition_always :
3213 is_inverted ? midgard_condition_false :
3214 midgard_condition_true;
3215
3216 midgard_jmp_writeout_op op =
3217 is_discard ? midgard_jmp_writeout_op_discard :
3218 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
3219 midgard_jmp_writeout_op_branch_cond;
3220
3221 if (!is_compact) {
3222 midgard_branch_extended branch =
3223 midgard_create_branch_extended(
3224 cond, op,
3225 dest_tag,
3226 quadword_offset);
3227
3228 memcpy(&ins->branch_extended, &branch, sizeof(branch));
3229 } else if (is_conditional || is_discard) {
3230 midgard_branch_cond branch = {
3231 .op = op,
3232 .dest_tag = dest_tag,
3233 .offset = quadword_offset,
3234 .cond = cond
3235 };
3236
3237 assert(branch.offset == quadword_offset);
3238
3239 memcpy(&ins->br_compact, &branch, sizeof(branch));
3240 } else {
3241 assert(op == midgard_jmp_writeout_op_branch_uncond);
3242
3243 midgard_branch_uncond branch = {
3244 .op = op,
3245 .dest_tag = dest_tag,
3246 .offset = quadword_offset,
3247 .unknown = 1
3248 };
3249
3250 assert(branch.offset == quadword_offset);
3251
3252 memcpy(&ins->br_compact, &branch, sizeof(branch));
3253 }
3254 }
3255 }
3256
3257 ++br_block_idx;
3258 }
3259
3260 /* Emit flat binary from the instruction arrays. Iterate each block in
3261 * sequence. Save instruction boundaries such that lookahead tags can
3262 * be assigned easily */
3263
3264 /* Cache _all_ bundles in source order for lookahead across failed branches */
3265
3266 int bundle_count = 0;
3267 mir_foreach_block(ctx, block) {
3268 bundle_count += block->bundles.size / sizeof(midgard_bundle);
3269 }
3270 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
3271 int bundle_idx = 0;
3272 mir_foreach_block(ctx, block) {
3273 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3274 source_order_bundles[bundle_idx++] = bundle;
3275 }
3276 }
3277
3278 int current_bundle = 0;
3279
3280 mir_foreach_block(ctx, block) {
3281 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3282 int lookahead = 1;
3283
3284 if (current_bundle + 1 < bundle_count) {
3285 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
3286
3287 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
3288 lookahead = 1;
3289 } else {
3290 lookahead = next;
3291 }
3292 }
3293
3294 emit_binary_bundle(ctx, bundle, compiled, lookahead);
3295 ++current_bundle;
3296 }
3297
3298 /* TODO: Free deeper */
3299 //util_dynarray_fini(&block->instructions);
3300 }
3301
3302 free(source_order_bundles);
3303
3304 /* Report the very first tag executed */
3305 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
3306
3307 /* Deal with off-by-one related to the fencepost problem */
3308 program->work_register_count = ctx->work_registers + 1;
3309
3310 program->can_discard = ctx->can_discard;
3311 program->uniform_cutoff = ctx->uniform_cutoff;
3312
3313 program->blend_patch_offset = ctx->blend_constant_offset;
3314
3315 if (midgard_debug & MIDGARD_DBG_SHADERS)
3316 disassemble_midgard(program->compiled.data, program->compiled.size);
3317
3318 return 0;
3319 }