2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 struct midgard_block
*next_fallthrough
;
175 /* Helpers to generate midgard_instruction's using macro magic, since every
176 * driver seems to do it that way */
178 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
180 #define M_LOAD_STORE(name, rname, uname) \
181 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
182 midgard_instruction i = { \
183 .type = TAG_LOAD_STORE_4, \
190 .op = midgard_op_##name, \
192 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
200 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
201 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
203 const midgard_vector_alu_src blank_alu_src
= {
204 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
207 const midgard_scalar_alu_src blank_scalar_alu_src
= {
211 /* Used for encoding the unused source of 1-op instructions */
212 const midgard_vector_alu_src zero_alu_src
= { 0 };
214 /* Coerce structs to integer */
217 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
220 memcpy(&u
, &src
, sizeof(src
));
224 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
225 * the corresponding Midgard source */
227 static midgard_vector_alu_src
228 vector_alu_modifiers(nir_alu_src
*src
)
230 if (!src
) return blank_alu_src
;
232 midgard_vector_alu_src alu_src
= {
234 .negate
= src
->negate
,
237 .half
= 0, /* TODO */
238 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
244 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
246 static midgard_instruction
247 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
249 midgard_instruction ins
= {
252 .src0
= SSA_UNUSED_1
,
257 .op
= midgard_alu_op_fmov
,
258 .reg_mode
= midgard_reg_mode_full
,
259 .dest_override
= midgard_dest_override_none
,
261 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
262 .src2
= vector_alu_srco_unsigned(mod
)
269 /* load/store instructions have both 32-bit and 16-bit variants, depending on
270 * whether we are using vectors composed of highp or mediump. At the moment, we
271 * don't support half-floats -- this requires changes in other parts of the
272 * compiler -- therefore the 16-bit versions are commented out. */
274 //M_LOAD(load_attr_16);
275 M_LOAD(load_attr_32
);
276 //M_LOAD(load_vary_16);
277 M_LOAD(load_vary_32
);
278 //M_LOAD(load_uniform_16);
279 M_LOAD(load_uniform_32
);
280 M_LOAD(load_color_buffer_8
);
281 //M_STORE(store_vary_16);
282 M_STORE(store_vary_32
);
284 static midgard_instruction
285 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
287 midgard_branch_cond branch
= {
295 memcpy(&compact
, &branch
, sizeof(branch
));
297 midgard_instruction ins
= {
299 .unit
= ALU_ENAB_BR_COMPACT
,
300 .prepacked_branch
= true,
301 .compact_branch
= true,
302 .br_compact
= compact
305 if (op
== midgard_jmp_writeout_op_writeout
)
311 static midgard_instruction
312 v_branch(bool conditional
, bool invert
)
314 midgard_instruction ins
= {
316 .unit
= ALU_ENAB_BRANCH
,
317 .compact_branch
= true,
319 .conditional
= conditional
,
320 .invert_conditional
= invert
327 static midgard_branch_extended
328 midgard_create_branch_extended( midgard_condition cond
,
329 midgard_jmp_writeout_op op
,
331 signed quadword_offset
)
333 /* For unclear reasons, the condition code is repeated 8 times */
334 uint16_t duplicated_cond
=
344 midgard_branch_extended branch
= {
346 .dest_tag
= dest_tag
,
347 .offset
= quadword_offset
,
348 .cond
= duplicated_cond
354 typedef struct midgard_bundle
{
355 /* Tag for the overall bundle */
358 /* Instructions contained by the bundle */
359 int instruction_count
;
360 midgard_instruction instructions
[5];
362 /* Bundle-wide ALU configuration */
365 bool has_embedded_constants
;
367 bool has_blend_constant
;
369 uint16_t register_words
[8];
370 int register_words_count
;
372 uint64_t body_words
[8];
374 int body_words_count
;
377 typedef struct compiler_context
{
379 gl_shader_stage stage
;
381 /* Is internally a blend shader? Depends on stage == FRAGMENT */
384 /* Tracking for blend constant patching */
385 int blend_constant_number
;
386 int blend_constant_offset
;
388 /* Current NIR function */
391 /* Unordered list of midgard_blocks */
393 struct list_head blocks
;
395 midgard_block
*initial_block
;
396 midgard_block
*previous_source_block
;
397 midgard_block
*final_block
;
399 /* List of midgard_instructions emitted for the current block */
400 midgard_block
*current_block
;
402 /* The index corresponding to the current loop, e.g. for breaks/contineus */
405 /* Constants which have been loaded, for later inlining */
406 struct hash_table_u64
*ssa_constants
;
408 /* SSA indices to be outputted to corresponding varying offset */
409 struct hash_table_u64
*ssa_varyings
;
411 /* SSA values / registers which have been aliased. Naively, these
412 * demand a fmov output; instead, we alias them in a later pass to
413 * avoid the wasted op.
415 * A note on encoding: to avoid dynamic memory management here, rather
416 * than ampping to a pointer, we map to the source index; the key
417 * itself is just the destination index. */
419 struct hash_table_u64
*ssa_to_alias
;
420 struct set
*leftover_ssa_to_alias
;
422 /* Actual SSA-to-register for RA */
423 struct hash_table_u64
*ssa_to_register
;
425 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
426 struct hash_table_u64
*hash_to_temp
;
430 /* Uniform IDs for mdg */
431 struct hash_table_u64
*uniform_nir_to_mdg
;
434 struct hash_table_u64
*varying_nir_to_mdg
;
437 /* Just the count of the max register used. Higher count => higher
438 * register pressure */
441 /* Used for cont/last hinting. Increase when a tex op is added.
442 * Decrease when a tex op is removed. */
443 int texture_op_count
;
445 /* Mapping of texture register -> SSA index for unaliasing */
446 int texture_index
[2];
448 /* Count of special uniforms (viewport, etc) in vec4 units */
449 int special_uniforms
;
451 /* If any path hits a discard instruction */
454 /* The number of uniforms allowable for the fast path */
457 /* Count of instructions emitted from NIR overall, across all blocks */
458 int instruction_count
;
460 /* Alpha ref value passed in */
463 /* The index corresponding to the fragment output */
464 unsigned fragment_output
;
467 /* Append instruction to end of current block */
469 static midgard_instruction
*
470 mir_upload_ins(struct midgard_instruction ins
)
472 midgard_instruction
*heap
= malloc(sizeof(ins
));
473 memcpy(heap
, &ins
, sizeof(ins
));
478 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
480 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
484 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
486 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
490 mir_remove_instruction(struct midgard_instruction
*ins
)
492 list_del(&ins
->link
);
495 static midgard_instruction
*
496 mir_prev_op(struct midgard_instruction
*ins
)
498 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
501 static midgard_instruction
*
502 mir_next_op(struct midgard_instruction
*ins
)
504 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
507 static midgard_block
*
508 mir_next_block(struct midgard_block
*blk
)
510 return list_first_entry(&(blk
->link
), midgard_block
, link
);
514 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
515 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
517 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
518 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
519 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
520 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
521 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
522 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
525 static midgard_instruction
*
526 mir_last_in_block(struct midgard_block
*block
)
528 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
531 static midgard_block
*
532 mir_get_block(compiler_context
*ctx
, int idx
)
534 struct list_head
*lst
= &ctx
->blocks
;
539 return (struct midgard_block
*) lst
;
542 /* Pretty printer for internal Midgard IR */
545 print_mir_source(int source
)
547 if (source
>= SSA_FIXED_MINIMUM
) {
548 /* Specific register */
549 int reg
= SSA_REG_FROM_FIXED(source
);
551 /* TODO: Moving threshold */
552 if (reg
> 16 && reg
< 24)
553 printf("u%d", 23 - reg
);
557 printf("%d", source
);
562 print_mir_instruction(midgard_instruction
*ins
)
568 midgard_alu_op op
= ins
->alu
.op
;
569 const char *name
= alu_opcode_names
[op
];
572 printf("%d.", ins
->unit
);
574 printf("%s", name
? name
: "??");
578 case TAG_LOAD_STORE_4
: {
579 midgard_load_store_op op
= ins
->load_store
.op
;
580 const char *name
= load_store_opcode_names
[op
];
587 case TAG_TEXTURE_4
: {
596 ssa_args
*args
= &ins
->ssa_args
;
598 printf(" %d, ", args
->dest
);
600 print_mir_source(args
->src0
);
603 if (args
->inline_constant
)
604 printf("#%d", ins
->inline_constant
);
606 print_mir_source(args
->src1
);
608 if (ins
->has_constants
)
609 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
615 print_mir_block(midgard_block
*block
)
619 mir_foreach_instr_in_block(block
, ins
) {
620 print_mir_instruction(ins
);
629 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
631 ins
->has_constants
= true;
632 memcpy(&ins
->constants
, constants
, 16);
634 /* If this is the special blend constant, mark this instruction */
636 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
637 ins
->has_blend_constant
= true;
641 glsl_type_size(const struct glsl_type
*type
)
643 return glsl_count_attribute_slots(type
, false);
646 /* Lower fdot2 to a vector multiplication followed by channel addition */
648 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
650 if (alu
->op
!= nir_op_fdot2
)
653 b
->cursor
= nir_before_instr(&alu
->instr
);
655 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
656 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
658 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
660 nir_ssa_def
*sum
= nir_fadd(b
,
661 nir_channel(b
, product
, 0),
662 nir_channel(b
, product
, 1));
664 /* Replace the fdot2 with this sum */
665 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
669 midgard_nir_lower_fdot2(nir_shader
*shader
)
671 bool progress
= false;
673 nir_foreach_function(function
, shader
) {
674 if (!function
->impl
) continue;
677 nir_builder
*b
= &_b
;
678 nir_builder_init(b
, function
->impl
);
680 nir_foreach_block(block
, function
->impl
) {
681 nir_foreach_instr_safe(instr
, block
) {
682 if (instr
->type
!= nir_instr_type_alu
) continue;
684 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
685 midgard_nir_lower_fdot2_body(b
, alu
);
691 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
699 optimise_nir(nir_shader
*nir
)
703 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
704 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
706 nir_lower_tex_options lower_tex_options
= {
710 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
715 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
716 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
717 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
718 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
720 NIR_PASS(progress
, nir
, nir_copy_prop
);
721 NIR_PASS(progress
, nir
, nir_opt_dce
);
722 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
723 NIR_PASS(progress
, nir
, nir_opt_cse
);
724 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
725 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
726 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
727 NIR_PASS(progress
, nir
, nir_opt_undef
);
728 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
731 nir_var_function_temp
);
733 /* TODO: Enable vectorize when merged upstream */
734 // NIR_PASS(progress, nir, nir_opt_vectorize);
737 /* Must be run at the end to prevent creation of fsin/fcos ops */
738 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
743 NIR_PASS(progress
, nir
, nir_opt_dce
);
744 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
745 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
746 NIR_PASS(progress
, nir
, nir_copy_prop
);
749 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
752 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_all_source_mods
);
753 NIR_PASS(progress
, nir
, nir_copy_prop
);
754 NIR_PASS(progress
, nir
, nir_opt_dce
);
756 /* Take us out of SSA */
757 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
758 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
760 /* We are a vector architecture; write combine where possible */
761 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
762 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
764 NIR_PASS(progress
, nir
, nir_opt_dce
);
767 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
768 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
769 * r0. See the comments in compiler_context */
772 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
774 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
775 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
778 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
781 unalias_ssa(compiler_context
*ctx
, int dest
)
783 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
784 /* TODO: Remove from leftover or no? */
788 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
790 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
794 midgard_is_pinned(compiler_context
*ctx
, int index
)
796 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
799 /* Do not actually emit a load; instead, cache the constant for inlining */
802 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
804 nir_ssa_def def
= instr
->def
;
806 float *v
= ralloc_array(NULL
, float, 4);
807 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
808 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
811 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
815 expand_writemask(unsigned mask
)
819 for (int i
= 0; i
< 4; ++i
)
827 squeeze_writemask(unsigned mask
)
831 for (int i
= 0; i
< 4; ++i
)
832 if (mask
& (3 << (2 * i
)))
839 /* Determines effective writemask, taking quirks and expansion into account */
841 effective_writemask(midgard_vector_alu
*alu
)
843 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
846 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
848 /* If there is a fixed channel count, construct the appropriate mask */
851 return (1 << channel_count
) - 1;
853 /* Otherwise, just squeeze the existing mask */
854 return squeeze_writemask(alu
->mask
);
858 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
860 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
863 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
868 /* If no temp is find, allocate one */
869 temp
= ctx
->temp_count
++;
870 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
872 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
878 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
881 return src
->ssa
->index
;
883 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
887 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
890 return dst
->ssa
.index
;
892 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
896 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
898 return nir_src_index(ctx
, &src
->src
);
901 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
902 * a conditional test) into that register */
905 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
907 /* XXX: Force component correct */
908 int condition
= nir_src_index(ctx
, src
);
910 const midgard_vector_alu_src alu_src
= {
911 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
914 /* There is no boolean move instruction. Instead, we simulate a move by
915 * ANDing the condition with itself to get it into r31.w */
917 midgard_instruction ins
= {
919 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
923 .dest
= SSA_FIXED_REGISTER(31),
926 .op
= midgard_alu_op_iand
,
927 .reg_mode
= midgard_reg_mode_full
,
928 .dest_override
= midgard_dest_override_none
,
929 .mask
= (0x3 << 6), /* w */
930 .src1
= vector_alu_srco_unsigned(alu_src
),
931 .src2
= vector_alu_srco_unsigned(alu_src
)
935 emit_mir_instruction(ctx
, ins
);
938 #define ALU_CASE(nir, _op) \
940 op = midgard_alu_op_##_op; \
944 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
946 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
948 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
949 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
950 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
952 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
953 * supported. A few do not and are commented for now. Also, there are a
954 * number of NIR ops which Midgard does not support and need to be
955 * lowered, also TODO. This switch block emits the opcode and calling
956 * convention of the Midgard instruction; actual packing is done in
962 ALU_CASE(fadd
, fadd
);
963 ALU_CASE(fmul
, fmul
);
964 ALU_CASE(fmin
, fmin
);
965 ALU_CASE(fmax
, fmax
);
966 ALU_CASE(imin
, imin
);
967 ALU_CASE(imax
, imax
);
968 ALU_CASE(fmov
, fmov
);
969 ALU_CASE(ffloor
, ffloor
);
970 ALU_CASE(fround_even
, froundeven
);
971 ALU_CASE(ftrunc
, ftrunc
);
972 ALU_CASE(fceil
, fceil
);
973 ALU_CASE(fdot3
, fdot3
);
974 ALU_CASE(fdot4
, fdot4
);
975 ALU_CASE(iadd
, iadd
);
976 ALU_CASE(isub
, isub
);
977 ALU_CASE(imul
, imul
);
979 /* XXX: Use fmov, not imov, since imov was causing major
980 * issues with texture precision? XXX research */
981 ALU_CASE(imov
, fmov
);
990 ALU_CASE(frcp
, frcp
);
991 ALU_CASE(frsq
, frsqrt
);
992 ALU_CASE(fsqrt
, fsqrt
);
993 ALU_CASE(fpow
, fpow
);
994 ALU_CASE(fexp2
, fexp2
);
995 ALU_CASE(flog2
, flog2
);
997 ALU_CASE(f2i32
, f2i
);
998 ALU_CASE(f2u32
, f2u
);
999 ALU_CASE(i2f32
, i2f
);
1000 ALU_CASE(u2f32
, u2f
);
1002 ALU_CASE(fsin
, fsin
);
1003 ALU_CASE(fcos
, fcos
);
1005 ALU_CASE(iand
, iand
);
1007 ALU_CASE(ixor
, ixor
);
1008 ALU_CASE(inot
, inot
);
1009 ALU_CASE(ishl
, ishl
);
1010 ALU_CASE(ishr
, iasr
);
1011 ALU_CASE(ushr
, ilsr
);
1013 ALU_CASE(ball_fequal4
, fball_eq
);
1014 ALU_CASE(bany_fnequal4
, fbany_neq
);
1015 ALU_CASE(ball_iequal4
, iball_eq
);
1016 ALU_CASE(bany_inequal4
, ibany_neq
);
1018 /* For greater-or-equal, we use less-or-equal and flip the
1022 op
= midgard_alu_op_ile
;
1024 /* Swap via temporary */
1025 nir_alu_src temp
= instr
->src
[1];
1026 instr
->src
[1] = instr
->src
[0];
1027 instr
->src
[0] = temp
;
1032 case nir_op_bcsel
: {
1033 op
= midgard_alu_op_fcsel
;
1035 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1038 emit_condition(ctx
, &instr
->src
[0].src
, false);
1040 /* The condition is the first argument; move the other
1041 * arguments up one to be a binary instruction for
1044 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1048 /* We don't have a native b2f32 instruction. Instead, like many GPUs,
1049 * we exploit booleans as 0/~0 for false/true, and correspondingly AND
1050 * by 1.0 to do the type conversion. For the moment, prime us to emit:
1052 * iand [whatever], #0
1054 * At the end of emit_alu (as MIR), we'll fix-up the constant */
1056 case nir_op_b2f32
: {
1057 op
= midgard_alu_op_iand
;
1062 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1067 /* Fetch unit, quirks, etc information */
1068 unsigned opcode_props
= alu_opcode_props
[op
];
1069 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1071 /* Initialise fields common between scalar/vector instructions */
1072 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1074 /* src0 will always exist afaik, but src1 will not for 1-argument
1075 * instructions. The latter can only be fetched if the instruction
1076 * needs it, or else we may segfault. */
1078 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1079 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1081 /* Rather than use the instruction generation helpers, we do it
1082 * ourselves here to avoid the mess */
1084 midgard_instruction ins
= {
1087 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1088 .src1
= quirk_flipped_r24
? src0
: src1
,
1093 nir_alu_src
*nirmods
[2] = { NULL
};
1095 if (nr_inputs
== 2) {
1096 nirmods
[0] = &instr
->src
[0];
1097 nirmods
[1] = &instr
->src
[1];
1098 } else if (nr_inputs
== 1) {
1099 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1104 midgard_vector_alu alu
= {
1106 .reg_mode
= midgard_reg_mode_full
,
1107 .dest_override
= midgard_dest_override_none
,
1110 /* Writemask only valid for non-SSA NIR */
1111 .mask
= expand_writemask((1 << nr_components
) - 1),
1113 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1114 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1117 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1120 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1124 /* Late fixup for emulated instructions */
1126 if (instr
->op
== nir_op_b2f32
) {
1127 /* Presently, our second argument is an inline #0 constant.
1128 * Switch over to an embedded 1.0 constant (that can't fit
1129 * inline, since we're 32-bit, not 16-bit like the inline
1132 ins
.ssa_args
.inline_constant
= false;
1133 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1134 ins
.has_constants
= true;
1135 ins
.constants
[0] = 1.0;
1138 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1139 /* To avoid duplicating the lookup tables (probably), true LUT
1140 * instructions can only operate as if they were scalars. Lower
1141 * them here by changing the component. */
1143 uint8_t original_swizzle
[4];
1144 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1146 for (int i
= 0; i
< nr_components
; ++i
) {
1147 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1149 for (int j
= 0; j
< 4; ++j
)
1150 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1152 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1153 emit_mir_instruction(ctx
, ins
);
1156 emit_mir_instruction(ctx
, ins
);
1163 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1165 nir_const_value
*const_offset
;
1166 unsigned offset
, reg
;
1168 switch (instr
->intrinsic
) {
1169 case nir_intrinsic_discard_if
:
1170 emit_condition(ctx
, &instr
->src
[0], true);
1174 case nir_intrinsic_discard
: {
1175 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1176 struct midgard_instruction discard
= v_branch(conditional
, false);
1177 discard
.branch
.target_type
= TARGET_DISCARD
;
1178 emit_mir_instruction(ctx
, discard
);
1180 ctx
->can_discard
= true;
1184 case nir_intrinsic_load_uniform
:
1185 case nir_intrinsic_load_input
:
1186 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1187 assert (const_offset
&& "no indirect inputs");
1189 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1191 reg
= nir_dest_index(ctx
, &instr
->dest
);
1193 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1194 /* TODO: half-floats */
1196 int uniform_offset
= 0;
1198 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1199 /* XXX: Resolve which uniform */
1202 /* Offset away from the special
1205 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1209 DBG("WARNING: Unknown uniform %d\n", offset
);
1213 uniform_offset
= (uintptr_t) (entry
) - 1;
1214 uniform_offset
+= ctx
->special_uniforms
;
1217 if (uniform_offset
< ctx
->uniform_cutoff
) {
1218 /* Fast path: For the first 16 uniform,
1219 * accesses are 0-cycle, since they're
1220 * just a register fetch in the usual
1221 * case. So, we alias the registers
1222 * while we're still in SSA-space */
1224 int reg_slot
= 23 - uniform_offset
;
1225 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1227 /* Otherwise, read from the 'special'
1228 * UBO to access higher-indexed
1229 * uniforms, at a performance cost */
1231 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1233 /* TODO: Don't split */
1234 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1235 ins
.load_store
.address
= uniform_offset
>> 3;
1237 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1238 emit_mir_instruction(ctx
, ins
);
1240 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1241 /* XXX: Half-floats? */
1242 /* TODO: swizzle, mask */
1244 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1246 midgard_varying_parameter p
= {
1248 .interpolation
= midgard_interp_default
,
1249 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1253 memcpy(&u
, &p
, sizeof(p
));
1254 ins
.load_store
.varying_parameters
= u
;
1256 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1257 emit_mir_instruction(ctx
, ins
);
1258 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1259 /* Constant encoded as a pinned constant */
1261 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1262 ins
.has_constants
= true;
1263 ins
.has_blend_constant
= true;
1264 emit_mir_instruction(ctx
, ins
);
1265 } else if (ctx
->is_blend
) {
1266 /* For blend shaders, a load might be
1267 * translated various ways depending on what
1268 * we're loading. Figure out how this is used */
1270 nir_variable
*out
= NULL
;
1272 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1273 int drvloc
= var
->data
.driver_location
;
1275 if (nir_intrinsic_base(instr
) == drvloc
) {
1283 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1284 /* Source color preloaded to r0 */
1286 midgard_pin_output(ctx
, reg
, 0);
1287 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1288 /* Destination color must be read from framebuffer */
1290 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1291 ins
.load_store
.swizzle
= 0; /* xxxx */
1293 /* Read each component sequentially */
1295 for (int c
= 0; c
< 4; ++c
) {
1296 ins
.load_store
.mask
= (1 << c
);
1297 ins
.load_store
.unknown
= c
;
1298 emit_mir_instruction(ctx
, ins
);
1301 /* vadd.u2f hr2, abs(hr2), #0 */
1303 midgard_vector_alu_src alu_src
= blank_alu_src
;
1305 alu_src
.half
= true;
1307 midgard_instruction u2f
= {
1311 .src1
= SSA_UNUSED_0
,
1313 .inline_constant
= true
1316 .op
= midgard_alu_op_u2f
,
1317 .reg_mode
= midgard_reg_mode_half
,
1318 .dest_override
= midgard_dest_override_none
,
1320 .src1
= vector_alu_srco_unsigned(alu_src
),
1321 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1325 emit_mir_instruction(ctx
, u2f
);
1327 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1329 alu_src
.abs
= false;
1331 midgard_instruction fmul
= {
1333 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1337 .src1
= SSA_UNUSED_0
,
1338 .inline_constant
= true
1341 .op
= midgard_alu_op_fmul
,
1342 .reg_mode
= midgard_reg_mode_full
,
1343 .dest_override
= midgard_dest_override_none
,
1344 .outmod
= midgard_outmod_sat
,
1346 .src1
= vector_alu_srco_unsigned(alu_src
),
1347 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1351 emit_mir_instruction(ctx
, fmul
);
1353 DBG("Unknown input in blend shader\n");
1356 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1357 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1358 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1359 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1360 emit_mir_instruction(ctx
, ins
);
1362 DBG("Unknown load\n");
1368 case nir_intrinsic_store_output
:
1369 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1370 assert(const_offset
&& "no indirect outputs");
1372 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1374 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1376 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1377 /* gl_FragColor is not emitted with load/store
1378 * instructions. Instead, it gets plonked into
1379 * r0 at the end of the shader and we do the
1380 * framebuffer writeout dance. TODO: Defer
1383 midgard_pin_output(ctx
, reg
, 0);
1385 /* Save the index we're writing to for later reference
1386 * in the epilogue */
1388 ctx
->fragment_output
= reg
;
1389 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1390 /* Varyings are written into one of two special
1391 * varying register, r26 or r27. The register itself is selected as the register
1392 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1394 * Normally emitting fmov's is frowned upon,
1395 * but due to unique constraints of
1396 * REGISTER_VARYING, fmov emission + a
1397 * dedicated cleanup pass is the only way to
1398 * guarantee correctness when considering some
1399 * (common) edge cases XXX: FIXME */
1401 /* Look up how it was actually laid out */
1403 void *entry
= _mesa_hash_table_u64_search(ctx
->varying_nir_to_mdg
, offset
+ 1);
1406 DBG("WARNING: skipping varying\n");
1410 offset
= (uintptr_t) (entry
) - 1;
1412 /* If this varying corresponds to a constant (why?!),
1413 * emit that now since it won't get picked up by
1414 * hoisting (since there is no corresponding move
1415 * emitted otherwise) */
1417 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1419 if (constant_value
) {
1420 /* Special case: emit the varying write
1421 * directly to r26 (looks funny in asm but it's
1422 * fine) and emit the store _now_. Possibly
1423 * slightly slower, but this is a really stupid
1424 * special case anyway (why on earth would you
1425 * have a constant varying? Your own fault for
1426 * slightly worse perf :P) */
1428 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1429 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1430 emit_mir_instruction(ctx
, ins
);
1432 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1433 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1434 emit_mir_instruction(ctx
, st
);
1436 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1438 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1441 DBG("Unknown store\n");
1447 case nir_intrinsic_load_alpha_ref_float
:
1448 assert(instr
->dest
.is_ssa
);
1450 float ref_value
= ctx
->alpha_ref
;
1452 float *v
= ralloc_array(NULL
, float, 4);
1453 memcpy(v
, &ref_value
, sizeof(float));
1454 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1459 printf ("Unhandled intrinsic\n");
1466 midgard_tex_format(enum glsl_sampler_dim dim
)
1469 case GLSL_SAMPLER_DIM_2D
:
1470 case GLSL_SAMPLER_DIM_EXTERNAL
:
1473 case GLSL_SAMPLER_DIM_3D
:
1476 case GLSL_SAMPLER_DIM_CUBE
:
1477 return TEXTURE_CUBE
;
1480 DBG("Unknown sampler dim type\n");
1487 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1490 //assert (!instr->sampler);
1491 //assert (!instr->texture_array_size);
1492 assert (instr
->op
== nir_texop_tex
);
1494 /* Allocate registers via a round robin scheme to alternate between the two registers */
1495 int reg
= ctx
->texture_op_count
& 1;
1496 int in_reg
= reg
, out_reg
= reg
;
1498 /* Make room for the reg */
1500 if (ctx
->texture_index
[reg
] > -1)
1501 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1503 int texture_index
= instr
->texture_index
;
1504 int sampler_index
= texture_index
;
1506 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1507 switch (instr
->src
[i
].src_type
) {
1508 case nir_tex_src_coord
: {
1509 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1511 midgard_vector_alu_src alu_src
= blank_alu_src
;
1512 alu_src
.swizzle
= (COMPONENT_Y
<< 2);
1514 midgard_instruction ins
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
));
1515 emit_mir_instruction(ctx
, ins
);
1517 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1523 DBG("Unknown source type\n");
1530 /* No helper to build texture words -- we do it all here */
1531 midgard_instruction ins
= {
1532 .type
= TAG_TEXTURE_4
,
1534 .op
= TEXTURE_OP_NORMAL
,
1535 .format
= midgard_tex_format(instr
->sampler_dim
),
1536 .texture_handle
= texture_index
,
1537 .sampler_handle
= sampler_index
,
1539 /* TODO: Don't force xyzw */
1540 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1552 /* Assume we can continue; hint it out later */
1557 /* Set registers to read and write from the same place */
1558 ins
.texture
.in_reg_select
= in_reg
;
1559 ins
.texture
.out_reg_select
= out_reg
;
1561 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1562 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1563 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1564 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1565 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1567 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1568 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1569 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1572 emit_mir_instruction(ctx
, ins
);
1574 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1576 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1577 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1578 ctx
->texture_index
[reg
] = o_index
;
1580 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1581 emit_mir_instruction(ctx
, ins2
);
1583 /* Used for .cont and .last hinting */
1584 ctx
->texture_op_count
++;
1588 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1590 switch (instr
->type
) {
1591 case nir_jump_break
: {
1592 /* Emit a branch out of the loop */
1593 struct midgard_instruction br
= v_branch(false, false);
1594 br
.branch
.target_type
= TARGET_BREAK
;
1595 br
.branch
.target_break
= ctx
->current_loop
;
1596 emit_mir_instruction(ctx
, br
);
1603 DBG("Unknown jump type %d\n", instr
->type
);
1609 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1611 switch (instr
->type
) {
1612 case nir_instr_type_load_const
:
1613 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1616 case nir_instr_type_intrinsic
:
1617 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1620 case nir_instr_type_alu
:
1621 emit_alu(ctx
, nir_instr_as_alu(instr
));
1624 case nir_instr_type_tex
:
1625 emit_tex(ctx
, nir_instr_as_tex(instr
));
1628 case nir_instr_type_jump
:
1629 emit_jump(ctx
, nir_instr_as_jump(instr
));
1632 case nir_instr_type_ssa_undef
:
1637 DBG("Unhandled instruction type\n");
1642 /* Determine the actual hardware from the index based on the RA results or special values */
1645 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1647 if (reg
>= SSA_FIXED_MINIMUM
)
1648 return SSA_REG_FROM_FIXED(reg
);
1651 assert(reg
< maxreg
);
1652 int r
= ra_get_node_reg(g
, reg
);
1653 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1658 /* fmov style unused */
1660 return REGISTER_UNUSED
;
1662 /* lut style unused */
1664 return REGISTER_UNUSED
;
1667 DBG("Unknown SSA register alias %d\n", reg
);
1674 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1676 /* Choose the first available register to minimise reported register pressure */
1678 for (int i
= 0; i
< 16; ++i
) {
1679 if (BITSET_TEST(regs
, i
)) {
1689 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1691 if (ins
->ssa_args
.src0
== src
) return true;
1692 if (ins
->ssa_args
.src1
== src
) return true;
1698 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1700 /* Check the rest of the block for liveness */
1701 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1702 if (midgard_is_live_in_instr(ins
, src
))
1706 /* Check the rest of the blocks for liveness */
1707 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1708 mir_foreach_instr_in_block(b
, ins
) {
1709 if (midgard_is_live_in_instr(ins
, src
))
1714 /* TODO: How does control flow interact in complex shaders? */
1720 allocate_registers(compiler_context
*ctx
)
1722 /* First, initialize the RA */
1723 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1725 /* Create a primary (general purpose) class, as well as special purpose
1726 * pipeline register classes */
1728 int primary_class
= ra_alloc_reg_class(regs
);
1729 int varying_class
= ra_alloc_reg_class(regs
);
1731 /* Add the full set of work registers */
1732 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1733 for (int i
= 0; i
< work_count
; ++i
)
1734 ra_class_add_reg(regs
, primary_class
, i
);
1736 /* Add special registers */
1737 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1738 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1740 /* We're done setting up */
1741 ra_set_finalize(regs
, NULL
);
1743 /* Transform the MIR into squeezed index form */
1744 mir_foreach_block(ctx
, block
) {
1745 mir_foreach_instr_in_block(block
, ins
) {
1746 if (ins
->compact_branch
) continue;
1748 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1749 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1750 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1752 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1753 print_mir_block(block
);
1756 /* Let's actually do register allocation */
1757 int nodes
= ctx
->temp_count
;
1758 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1760 /* Set everything to the work register class, unless it has somewhere
1763 mir_foreach_block(ctx
, block
) {
1764 mir_foreach_instr_in_block(block
, ins
) {
1765 if (ins
->compact_branch
) continue;
1767 if (ins
->ssa_args
.dest
< 0) continue;
1769 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1771 int class = primary_class
;
1773 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1777 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1778 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1781 unsigned reg
= temp
- 1;
1782 int t
= find_or_allocate_temp(ctx
, index
);
1783 ra_set_node_reg(g
, t
, reg
);
1787 /* Determine liveness */
1789 int *live_start
= malloc(nodes
* sizeof(int));
1790 int *live_end
= malloc(nodes
* sizeof(int));
1792 /* Initialize as non-existent */
1794 for (int i
= 0; i
< nodes
; ++i
) {
1795 live_start
[i
] = live_end
[i
] = -1;
1800 mir_foreach_block(ctx
, block
) {
1801 mir_foreach_instr_in_block(block
, ins
) {
1802 if (ins
->compact_branch
) continue;
1804 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1805 /* If this destination is not yet live, it is now since we just wrote it */
1807 int dest
= ins
->ssa_args
.dest
;
1809 if (live_start
[dest
] == -1)
1810 live_start
[dest
] = d
;
1813 /* Since we just used a source, the source might be
1814 * dead now. Scan the rest of the block for
1815 * invocations, and if there are none, the source dies
1818 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1820 for (int src
= 0; src
< 2; ++src
) {
1821 int s
= sources
[src
];
1823 if (s
< 0) continue;
1825 if (s
>= SSA_FIXED_MINIMUM
) continue;
1827 if (!is_live_after(ctx
, block
, ins
, s
)) {
1836 /* If a node still hasn't been killed, kill it now */
1838 for (int i
= 0; i
< nodes
; ++i
) {
1839 /* live_start == -1 most likely indicates a pinned output */
1841 if (live_end
[i
] == -1)
1845 /* Setup interference between nodes that are live at the same time */
1847 for (int i
= 0; i
< nodes
; ++i
) {
1848 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1849 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1850 ra_add_node_interference(g
, i
, j
);
1854 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1856 if (!ra_allocate(g
)) {
1857 DBG("Error allocating registers\n");
1865 mir_foreach_block(ctx
, block
) {
1866 mir_foreach_instr_in_block(block
, ins
) {
1867 if (ins
->compact_branch
) continue;
1869 ssa_args args
= ins
->ssa_args
;
1871 switch (ins
->type
) {
1873 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1875 ins
->registers
.src2_imm
= args
.inline_constant
;
1877 if (args
.inline_constant
) {
1878 /* Encode inline 16-bit constant as a vector by default */
1880 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1882 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1884 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1885 ins
->alu
.src2
= imm
<< 2;
1887 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1890 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1894 case TAG_LOAD_STORE_4
: {
1895 if (OP_IS_STORE(ins
->load_store
.op
)) {
1896 /* TODO: use ssa_args for store_vary */
1897 ins
->load_store
.reg
= 0;
1899 bool has_dest
= args
.dest
>= 0;
1900 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1902 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1915 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1916 * use scalar ALU instructions, for functional or performance reasons. To do
1917 * this, we just demote vector ALU payloads to scalar. */
1920 component_from_mask(unsigned mask
)
1922 for (int c
= 0; c
< 4; ++c
) {
1923 if (mask
& (3 << (2 * c
)))
1932 is_single_component_mask(unsigned mask
)
1936 for (int c
= 0; c
< 4; ++c
)
1937 if (mask
& (3 << (2 * c
)))
1940 return components
== 1;
1943 /* Create a mask of accessed components from a swizzle to figure out vector
1947 swizzle_to_access_mask(unsigned swizzle
)
1949 unsigned component_mask
= 0;
1951 for (int i
= 0; i
< 4; ++i
) {
1952 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1953 component_mask
|= (1 << c
);
1956 return component_mask
;
1960 vector_to_scalar_source(unsigned u
)
1962 midgard_vector_alu_src v
;
1963 memcpy(&v
, &u
, sizeof(v
));
1965 midgard_scalar_alu_src s
= {
1969 .component
= (v
.swizzle
& 3) << 1
1973 memcpy(&o
, &s
, sizeof(s
));
1975 return o
& ((1 << 6) - 1);
1978 static midgard_scalar_alu
1979 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1981 /* The output component is from the mask */
1982 midgard_scalar_alu s
= {
1984 .src1
= vector_to_scalar_source(v
.src1
),
1985 .src2
= vector_to_scalar_source(v
.src2
),
1988 .output_full
= 1, /* TODO: Half */
1989 .output_component
= component_from_mask(v
.mask
) << 1,
1992 /* Inline constant is passed along rather than trying to extract it
1995 if (ins
->ssa_args
.inline_constant
) {
1997 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1998 imm
|= (lower_11
>> 9) & 3;
1999 imm
|= (lower_11
>> 6) & 4;
2000 imm
|= (lower_11
>> 2) & 0x38;
2001 imm
|= (lower_11
& 63) << 6;
2009 /* Midgard prefetches instruction types, so during emission we need to
2010 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2011 * if this is the second to last and the last is an ALU, then it's also 1... */
2013 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2014 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2016 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2017 bytes_emitted += sizeof(type)
2020 emit_binary_vector_instruction(midgard_instruction
*ains
,
2021 uint16_t *register_words
, int *register_words_count
,
2022 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2023 size_t *bytes_emitted
)
2025 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2026 *bytes_emitted
+= sizeof(midgard_reg_info
);
2028 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2029 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2030 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2033 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2034 * mind that we are a vector architecture and we can write to different
2035 * components simultaneously */
2038 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2040 /* Each instruction reads some registers and writes to a register. See
2041 * where the first writes */
2043 /* Figure out where exactly we wrote to */
2044 int source
= first
->ssa_args
.dest
;
2045 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2047 /* As long as the second doesn't read from the first, we're okay */
2048 if (second
->ssa_args
.src0
== source
) {
2049 if (first
->type
== TAG_ALU_4
) {
2050 /* Figure out which components we just read from */
2052 int q
= second
->alu
.src1
;
2053 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2055 /* Check if there are components in common, and fail if so */
2056 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2063 if (second
->ssa_args
.src1
== source
)
2066 /* Otherwise, it's safe in that regard. Another data hazard is both
2067 * writing to the same place, of course */
2069 if (second
->ssa_args
.dest
== source
) {
2070 /* ...but only if the components overlap */
2071 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2073 if (dest_mask
& source_mask
)
2083 midgard_instruction
**segment
, unsigned segment_size
,
2084 midgard_instruction
*ains
)
2086 for (int s
= 0; s
< segment_size
; ++s
)
2087 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2095 /* Schedules, but does not emit, a single basic block. After scheduling, the
2096 * final tag and size of the block are known, which are necessary for branching
2099 static midgard_bundle
2100 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2102 int instructions_emitted
= 0, instructions_consumed
= -1;
2103 midgard_bundle bundle
= { 0 };
2105 uint8_t tag
= ins
->type
;
2107 /* Default to the instruction's tag */
2110 switch (ins
->type
) {
2112 uint32_t control
= 0;
2113 size_t bytes_emitted
= sizeof(control
);
2115 /* TODO: Constant combining */
2116 int index
= 0, last_unit
= 0;
2118 /* Previous instructions, for the purpose of parallelism */
2119 midgard_instruction
*segment
[4] = {0};
2120 int segment_size
= 0;
2122 instructions_emitted
= -1;
2123 midgard_instruction
*pins
= ins
;
2126 midgard_instruction
*ains
= pins
;
2128 /* Advance instruction pointer */
2130 ains
= mir_next_op(pins
);
2134 /* Out-of-work condition */
2135 if ((struct list_head
*) ains
== &block
->instructions
)
2138 /* Ensure that the chain can continue */
2139 if (ains
->type
!= TAG_ALU_4
) break;
2141 /* According to the presentation "The ARM
2142 * Mali-T880 Mobile GPU" from HotChips 27,
2143 * there are two pipeline stages. Branching
2144 * position determined experimentally. Lines
2145 * are executed in parallel:
2148 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2150 * Verify that there are no ordering dependencies here.
2152 * TODO: Allow for parallelism!!!
2155 /* Pick a unit for it if it doesn't force a particular unit */
2157 int unit
= ains
->unit
;
2160 int op
= ains
->alu
.op
;
2161 int units
= alu_opcode_props
[op
];
2163 /* TODO: Promotion of scalars to vectors */
2164 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2167 assert(units
& UNITS_SCALAR
);
2170 if (last_unit
>= UNIT_VADD
) {
2171 if (units
& UNIT_VLUT
)
2176 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2178 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2180 else if (units
& UNIT_VLUT
)
2186 if (last_unit
>= UNIT_VADD
) {
2187 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2189 else if (units
& UNIT_VLUT
)
2194 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2196 else if (units
& UNIT_SMUL
)
2197 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2198 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2205 assert(unit
& units
);
2208 /* Late unit check, this time for encoding (not parallelism) */
2209 if (unit
<= last_unit
) break;
2211 /* Clear the segment */
2212 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2215 if (midgard_has_hazard(segment
, segment_size
, ains
))
2218 /* We're good to go -- emit the instruction */
2221 segment
[segment_size
++] = ains
;
2223 /* Only one set of embedded constants per
2224 * bundle possible; if we have more, we must
2225 * break the chain early, unfortunately */
2227 if (ains
->has_constants
) {
2228 if (bundle
.has_embedded_constants
) {
2229 /* ...but if there are already
2230 * constants but these are the
2231 * *same* constants, we let it
2234 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2237 bundle
.has_embedded_constants
= true;
2238 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2240 /* If this is a blend shader special constant, track it for patching */
2241 if (ains
->has_blend_constant
)
2242 bundle
.has_blend_constant
= true;
2246 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2247 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2248 &bundle
.register_words_count
, bundle
.body_words
,
2249 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2250 } else if (ains
->compact_branch
) {
2251 /* All of r0 has to be written out
2252 * along with the branch writeout.
2255 if (ains
->writeout
) {
2257 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2258 ins
.unit
= UNIT_VMUL
;
2260 control
|= ins
.unit
;
2262 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2263 &bundle
.register_words_count
, bundle
.body_words
,
2264 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2266 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2267 bool written_late
= false;
2268 bool components
[4] = { 0 };
2269 uint16_t register_dep_mask
= 0;
2270 uint16_t written_mask
= 0;
2272 midgard_instruction
*qins
= ins
;
2273 for (int t
= 0; t
< index
; ++t
) {
2274 if (qins
->registers
.out_reg
!= 0) {
2275 /* Mark down writes */
2277 written_mask
|= (1 << qins
->registers
.out_reg
);
2279 /* Mark down the register dependencies for errata check */
2281 if (qins
->registers
.src1_reg
< 16)
2282 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2284 if (qins
->registers
.src2_reg
< 16)
2285 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2287 int mask
= qins
->alu
.mask
;
2289 for (int c
= 0; c
< 4; ++c
)
2290 if (mask
& (0x3 << (2 * c
)))
2291 components
[c
] = true;
2293 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2295 if (qins
->unit
== UNIT_VLUT
)
2296 written_late
= true;
2299 /* Advance instruction pointer */
2300 qins
= mir_next_op(qins
);
2304 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2305 if (register_dep_mask
& written_mask
) {
2306 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2313 /* If even a single component is not written, break it up (conservative check). */
2314 bool breakup
= false;
2316 for (int c
= 0; c
< 4; ++c
)
2323 /* Otherwise, we're free to proceed */
2327 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2328 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2329 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2330 bytes_emitted
+= sizeof(midgard_branch_extended
);
2332 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2333 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2334 bytes_emitted
+= sizeof(ains
->br_compact
);
2337 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2338 bytes_emitted
+= sizeof(midgard_reg_info
);
2340 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2341 bundle
.body_words_count
++;
2342 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2345 /* Defer marking until after writing to allow for break */
2346 control
|= ains
->unit
;
2347 last_unit
= ains
->unit
;
2348 ++instructions_emitted
;
2352 /* Bubble up the number of instructions for skipping */
2353 instructions_consumed
= index
- 1;
2357 /* Pad ALU op to nearest word */
2359 if (bytes_emitted
& 15) {
2360 padding
= 16 - (bytes_emitted
& 15);
2361 bytes_emitted
+= padding
;
2364 /* Constants must always be quadwords */
2365 if (bundle
.has_embedded_constants
)
2366 bytes_emitted
+= 16;
2368 /* Size ALU instruction for tag */
2369 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2370 bundle
.padding
= padding
;
2371 bundle
.control
= bundle
.tag
| control
;
2376 case TAG_LOAD_STORE_4
: {
2377 /* Load store instructions have two words at once. If
2378 * we only have one queued up, we need to NOP pad.
2379 * Otherwise, we store both in succession to save space
2380 * and cycles -- letting them go in parallel -- skip
2381 * the next. The usefulness of this optimisation is
2382 * greatly dependent on the quality of the instruction
2386 midgard_instruction
*next_op
= mir_next_op(ins
);
2388 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2389 /* As the two operate concurrently, make sure
2390 * they are not dependent */
2392 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2393 /* Skip ahead, since it's redundant with the pair */
2394 instructions_consumed
= 1 + (instructions_emitted
++);
2402 /* Texture ops default to single-op-per-bundle scheduling */
2406 /* Copy the instructions into the bundle */
2407 bundle
.instruction_count
= instructions_emitted
+ 1;
2411 midgard_instruction
*uins
= ins
;
2412 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2413 bundle
.instructions
[used_idx
++] = *uins
;
2414 uins
= mir_next_op(uins
);
2417 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2423 quadword_size(int tag
)
2438 case TAG_LOAD_STORE_4
:
2450 /* Schedule a single block by iterating its instruction to create bundles.
2451 * While we go, tally about the bundle sizes to compute the block size. */
2454 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2456 util_dynarray_init(&block
->bundles
, NULL
);
2458 block
->quadword_count
= 0;
2460 mir_foreach_instr_in_block(block
, ins
) {
2462 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2463 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2465 if (bundle
.has_blend_constant
) {
2466 /* TODO: Multiblock? */
2467 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2468 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2472 ins
= mir_next_op(ins
);
2474 block
->quadword_count
+= quadword_size(bundle
.tag
);
2477 block
->is_scheduled
= true;
2481 schedule_program(compiler_context
*ctx
)
2483 allocate_registers(ctx
);
2485 mir_foreach_block(ctx
, block
) {
2486 schedule_block(ctx
, block
);
2490 /* After everything is scheduled, emit whole bundles at a time */
2493 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2495 int lookahead
= next_tag
<< 4;
2497 switch (bundle
->tag
) {
2502 /* Actually emit each component */
2503 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2505 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2506 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2508 /* Emit body words based on the instructions bundled */
2509 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2510 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2512 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2513 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2514 } else if (ins
->compact_branch
) {
2515 /* Dummy move, XXX DRY */
2516 if ((i
== 0) && ins
->writeout
) {
2517 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2518 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2521 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2522 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2524 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2528 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2529 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2533 /* Emit padding (all zero) */
2534 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2536 /* Tack on constants */
2538 if (bundle
->has_embedded_constants
) {
2539 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2540 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2541 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2542 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2548 case TAG_LOAD_STORE_4
: {
2549 /* One or two composing instructions */
2551 uint64_t current64
, next64
= LDST_NOP
;
2553 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2555 if (bundle
->instruction_count
== 2)
2556 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2558 midgard_load_store instruction
= {
2559 .type
= bundle
->tag
,
2560 .next_type
= next_tag
,
2565 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2570 case TAG_TEXTURE_4
: {
2571 /* Texture instructions are easy, since there is no
2572 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2574 midgard_instruction
*ins
= &bundle
->instructions
[0];
2576 ins
->texture
.type
= TAG_TEXTURE_4
;
2577 ins
->texture
.next_type
= next_tag
;
2579 ctx
->texture_op_count
--;
2581 if (!ctx
->texture_op_count
) {
2582 ins
->texture
.cont
= 0;
2583 ins
->texture
.last
= 1;
2586 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2591 DBG("Unknown midgard instruction type\n");
2598 /* ALU instructions can inline or embed constants, which decreases register
2599 * pressure and saves space. */
2601 #define CONDITIONAL_ATTACH(src) { \
2602 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2605 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2606 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2611 inline_alu_constants(compiler_context
*ctx
)
2613 mir_foreach_instr(ctx
, alu
) {
2614 /* Other instructions cannot inline constants */
2615 if (alu
->type
!= TAG_ALU_4
) continue;
2617 /* If there is already a constant here, we can do nothing */
2618 if (alu
->has_constants
) continue;
2620 CONDITIONAL_ATTACH(src0
);
2622 if (!alu
->has_constants
) {
2623 CONDITIONAL_ATTACH(src1
)
2624 } else if (!alu
->inline_constant
) {
2625 /* Corner case: _two_ vec4 constants, for instance with a
2626 * csel. For this case, we can only use a constant
2627 * register for one, we'll have to emit a move for the
2628 * other. Note, if both arguments are constants, then
2629 * necessarily neither argument depends on the value of
2630 * any particular register. As the destination register
2631 * will be wiped, that means we can spill the constant
2632 * to the destination register.
2635 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2636 unsigned scratch
= alu
->ssa_args
.dest
;
2639 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2640 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2642 /* Force a break XXX Defer r31 writes */
2643 ins
.unit
= UNIT_VLUT
;
2645 /* Set the source */
2646 alu
->ssa_args
.src1
= scratch
;
2648 /* Inject us -before- the last instruction which set r31 */
2649 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2655 /* Midgard supports two types of constants, embedded constants (128-bit) and
2656 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2657 * constants can be demoted to inline constants, for space savings and
2658 * sometimes a performance boost */
2661 embedded_to_inline_constant(compiler_context
*ctx
)
2663 mir_foreach_instr(ctx
, ins
) {
2664 if (!ins
->has_constants
) continue;
2666 if (ins
->ssa_args
.inline_constant
) continue;
2668 /* Blend constants must not be inlined by definition */
2669 if (ins
->has_blend_constant
) continue;
2671 /* src1 cannot be an inline constant due to encoding
2672 * restrictions. So, if possible we try to flip the arguments
2675 int op
= ins
->alu
.op
;
2677 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2678 /* Flip based on op. Fallthrough intentional */
2681 /* These ops require an operational change to flip their arguments TODO */
2682 case midgard_alu_op_flt
:
2683 case midgard_alu_op_fle
:
2684 case midgard_alu_op_ilt
:
2685 case midgard_alu_op_ile
:
2686 case midgard_alu_op_fcsel
:
2687 case midgard_alu_op_icsel
:
2688 case midgard_alu_op_isub
:
2689 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2692 /* These ops are commutative and Just Flip */
2693 case midgard_alu_op_fne
:
2694 case midgard_alu_op_fadd
:
2695 case midgard_alu_op_fmul
:
2696 case midgard_alu_op_fmin
:
2697 case midgard_alu_op_fmax
:
2698 case midgard_alu_op_iadd
:
2699 case midgard_alu_op_imul
:
2700 case midgard_alu_op_feq
:
2701 case midgard_alu_op_ieq
:
2702 case midgard_alu_op_ine
:
2703 case midgard_alu_op_iand
:
2704 case midgard_alu_op_ior
:
2705 case midgard_alu_op_ixor
:
2706 /* Flip the SSA numbers */
2707 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2708 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2710 /* And flip the modifiers */
2714 src_temp
= ins
->alu
.src2
;
2715 ins
->alu
.src2
= ins
->alu
.src1
;
2716 ins
->alu
.src1
= src_temp
;
2723 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2724 /* Extract the source information */
2726 midgard_vector_alu_src
*src
;
2727 int q
= ins
->alu
.src2
;
2728 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2731 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2732 int component
= src
->swizzle
& 3;
2734 /* Scale constant appropriately, if we can legally */
2735 uint16_t scaled_constant
= 0;
2737 /* XXX: Check legality */
2738 if (midgard_is_integer_op(op
)) {
2739 /* TODO: Inline integer */
2742 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2743 scaled_constant
= (uint16_t) iconstants
[component
];
2745 /* Constant overflow after resize */
2746 if (scaled_constant
!= iconstants
[component
])
2749 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2752 /* We don't know how to handle these with a constant */
2754 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2755 DBG("Bailing inline constant...\n");
2759 /* Make sure that the constant is not itself a
2760 * vector by checking if all accessed values
2761 * (by the swizzle) are the same. */
2763 uint32_t *cons
= (uint32_t *) ins
->constants
;
2764 uint32_t value
= cons
[component
];
2766 bool is_vector
= false;
2767 unsigned mask
= effective_writemask(&ins
->alu
);
2769 for (int c
= 1; c
< 4; ++c
) {
2770 /* We only care if this component is actually used */
2771 if (!(mask
& (1 << c
)))
2774 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2776 if (test
!= value
) {
2785 /* Get rid of the embedded constant */
2786 ins
->has_constants
= false;
2787 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2788 ins
->ssa_args
.inline_constant
= true;
2789 ins
->inline_constant
= scaled_constant
;
2794 /* Map normal SSA sources to other SSA sources / fixed registers (like
2798 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2800 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2803 /* Remove entry in leftovers to avoid a redunant fmov */
2805 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2808 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2810 /* Assign the alias map */
2816 #define AS_SRC(to, u) \
2817 int q##to = ins->alu.src2; \
2818 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2820 /* Removing unused moves is necessary to clean up the texture pipeline results.
2822 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2825 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2827 mir_foreach_instr_in_block_safe(block
, ins
) {
2828 if (ins
->type
!= TAG_ALU_4
) continue;
2830 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2832 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2834 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2836 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2838 mir_remove_instruction(ins
);
2842 /* The following passes reorder MIR instructions to enable better scheduling */
2845 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2847 mir_foreach_instr_in_block_safe(block
, ins
) {
2848 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2850 /* We've found a load/store op. Check if next is also load/store. */
2851 midgard_instruction
*next_op
= mir_next_op(ins
);
2852 if (&next_op
->link
!= &block
->instructions
) {
2853 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2854 /* If so, we're done since we're a pair */
2855 ins
= mir_next_op(ins
);
2859 /* Maximum search distance to pair, to avoid register pressure disasters */
2860 int search_distance
= 8;
2862 /* Otherwise, we have an orphaned load/store -- search for another load */
2863 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2864 /* Terminate search if necessary */
2865 if (!(search_distance
--)) break;
2867 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2869 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2871 /* We found one! Move it up to pair and remove it from the old location */
2873 mir_insert_instruction_before(ins
, *c
);
2874 mir_remove_instruction(c
);
2882 /* Emit varying stores late */
2885 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2886 /* Iterate in reverse to get the final write, rather than the first */
2888 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2889 /* Check if what we just wrote needs a store */
2890 int idx
= ins
->ssa_args
.dest
;
2891 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2893 if (!varying
) continue;
2897 /* We need to store to the appropriate varying, so emit the
2900 /* TODO: Integrate with special purpose RA (and scheduler?) */
2901 bool high_varying_register
= false;
2903 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2905 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2906 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2908 mir_insert_instruction_before(mir_next_op(ins
), st
);
2909 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2911 /* We no longer need to store this varying */
2912 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2916 /* If there are leftovers after the below pass, emit actual fmov
2917 * instructions for the slow-but-correct path */
2920 emit_leftover_move(compiler_context
*ctx
)
2922 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2923 int base
= ((uintptr_t) leftover
->key
) - 1;
2926 map_ssa_to_alias(ctx
, &mapped
);
2927 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2932 actualise_ssa_to_alias(compiler_context
*ctx
)
2934 mir_foreach_instr(ctx
, ins
) {
2935 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2936 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2939 emit_leftover_move(ctx
);
2942 /* Vertex shaders do not write gl_Position as is; instead, they write a
2943 * transformed screen space position as a varying. See section 12.5 "Coordinate
2944 * Transformation" of the ES 3.2 full specification for details.
2946 * This transformation occurs early on, as NIR and prior to optimisation, in
2947 * order to take advantage of NIR optimisation passes of the transform itself.
2951 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
2953 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
2955 /* Get viewport from the uniforms */
2956 nir_intrinsic_instr
*load
;
2957 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
2958 load
->num_components
= 4;
2959 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
2960 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
2961 nir_builder_instr_insert(b
, &load
->instr
);
2963 /* Formatted as <width, height, centerx, centery> */
2964 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
2965 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
2966 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
2967 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
2969 /* XXX: From uniforms? */
2970 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
2971 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
2973 /* World space to normalised device coordinates */
2975 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
2976 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
2978 /* Normalised device coordinates to screen space */
2980 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
2981 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
2983 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2984 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2985 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
2987 /* gl_Position will be written out in screenspace xyz, with w set to
2988 * the reciprocal we computed earlier. The transformed w component is
2989 * then used for perspective-correct varying interpolation. The
2990 * transformed w component must preserve its original sign; this is
2991 * used in depth clipping computations */
2993 nir_ssa_def
*screen_space
= nir_vec4(b
,
2994 nir_channel(b
, viewport_xy
, 0),
2995 nir_channel(b
, viewport_xy
, 1),
2999 /* Finally, write out the transformed values to the varying */
3001 nir_intrinsic_instr
*store
;
3002 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
3003 store
->num_components
= 4;
3004 nir_intrinsic_set_base(store
, 0);
3005 nir_intrinsic_set_write_mask(store
, 0xf);
3006 store
->src
[0].ssa
= screen_space
;
3007 store
->src
[0].is_ssa
= true;
3008 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
3009 nir_builder_instr_insert(b
, &store
->instr
);
3013 transform_position_writes(nir_shader
*shader
)
3015 nir_foreach_function(func
, shader
) {
3016 nir_foreach_block(block
, func
->impl
) {
3017 nir_foreach_instr_safe(instr
, block
) {
3018 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
3020 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
3021 nir_variable
*out
= NULL
;
3023 switch (intr
->intrinsic
) {
3024 case nir_intrinsic_store_output
:
3025 /* already had i/o lowered.. lookup the matching output var: */
3026 nir_foreach_variable(var
, &shader
->outputs
) {
3027 int drvloc
= var
->data
.driver_location
;
3029 if (nir_intrinsic_base(intr
) == drvloc
) {
3043 if (out
->data
.mode
!= nir_var_shader_out
)
3046 if (out
->data
.location
!= VARYING_SLOT_POS
)
3050 nir_builder_init(&b
, func
->impl
);
3051 b
.cursor
= nir_before_instr(instr
);
3053 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
3054 nir_instr_remove(instr
);
3061 emit_fragment_epilogue(compiler_context
*ctx
)
3063 /* Special case: writing out constants requires us to include the move
3064 * explicitly now, so shove it into r0 */
3066 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3068 if (constant_value
) {
3069 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3070 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3071 emit_mir_instruction(ctx
, ins
);
3074 /* Perform the actual fragment writeout. We have two writeout/branch
3075 * instructions, forming a loop until writeout is successful as per the
3076 * docs. TODO: gl_FragDepth */
3078 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3079 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3082 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3083 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3084 * with the int8 analogue to the fragment epilogue */
3087 emit_blend_epilogue(compiler_context
*ctx
)
3089 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3091 midgard_instruction scale
= {
3094 .inline_constant
= _mesa_float_to_half(255.0),
3096 .src0
= SSA_FIXED_REGISTER(0),
3097 .src1
= SSA_UNUSED_0
,
3098 .dest
= SSA_FIXED_REGISTER(24),
3099 .inline_constant
= true
3102 .op
= midgard_alu_op_fmul
,
3103 .reg_mode
= midgard_reg_mode_full
,
3104 .dest_override
= midgard_dest_override_lower
,
3106 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3107 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3111 emit_mir_instruction(ctx
, scale
);
3113 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3115 midgard_vector_alu_src alu_src
= blank_alu_src
;
3116 alu_src
.half
= true;
3118 midgard_instruction f2u8
= {
3121 .src0
= SSA_FIXED_REGISTER(24),
3122 .src1
= SSA_UNUSED_0
,
3123 .dest
= SSA_FIXED_REGISTER(0),
3124 .inline_constant
= true
3127 .op
= midgard_alu_op_f2u8
,
3128 .reg_mode
= midgard_reg_mode_half
,
3129 .dest_override
= midgard_dest_override_lower
,
3130 .outmod
= midgard_outmod_pos
,
3132 .src1
= vector_alu_srco_unsigned(alu_src
),
3133 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3137 emit_mir_instruction(ctx
, f2u8
);
3139 /* vmul.imov.quarter r0, r0, r0 */
3141 midgard_instruction imov_8
= {
3144 .src0
= SSA_UNUSED_1
,
3145 .src1
= SSA_FIXED_REGISTER(0),
3146 .dest
= SSA_FIXED_REGISTER(0),
3149 .op
= midgard_alu_op_imov
,
3150 .reg_mode
= midgard_reg_mode_quarter
,
3151 .dest_override
= midgard_dest_override_none
,
3153 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3154 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3158 /* Emit branch epilogue with the 8-bit move as the source */
3160 emit_mir_instruction(ctx
, imov_8
);
3161 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3163 emit_mir_instruction(ctx
, imov_8
);
3164 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3167 static midgard_block
*
3168 emit_block(compiler_context
*ctx
, nir_block
*block
)
3170 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3171 list_addtail(&this_block
->link
, &ctx
->blocks
);
3173 this_block
->is_scheduled
= false;
3176 ctx
->texture_index
[0] = -1;
3177 ctx
->texture_index
[1] = -1;
3179 /* Set up current block */
3180 list_inithead(&this_block
->instructions
);
3181 ctx
->current_block
= this_block
;
3183 nir_foreach_instr(instr
, block
) {
3184 emit_instr(ctx
, instr
);
3185 ++ctx
->instruction_count
;
3188 inline_alu_constants(ctx
);
3189 embedded_to_inline_constant(ctx
);
3191 /* Perform heavylifting for aliasing */
3192 actualise_ssa_to_alias(ctx
);
3194 midgard_emit_store(ctx
, this_block
);
3195 midgard_eliminate_orphan_moves(ctx
, this_block
);
3196 midgard_pair_load_store(ctx
, this_block
);
3198 /* Append fragment shader epilogue (value writeout) */
3199 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3200 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3202 emit_blend_epilogue(ctx
);
3204 emit_fragment_epilogue(ctx
);
3208 /* Fallthrough save */
3209 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3211 if (block
== nir_start_block(ctx
->func
->impl
))
3212 ctx
->initial_block
= this_block
;
3214 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3215 ctx
->final_block
= this_block
;
3217 /* Allow the next control flow to access us retroactively, for
3219 ctx
->current_block
= this_block
;
3221 /* Document the fallthrough chain */
3222 ctx
->previous_source_block
= this_block
;
3227 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3230 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3232 /* Conditional branches expect the condition in r31.w; emit a move for
3233 * that in the _previous_ block (which is the current block). */
3234 emit_condition(ctx
, &nif
->condition
, true);
3236 /* Speculatively emit the branch, but we can't fill it in until later */
3237 EMIT(branch
, true, true);
3238 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3240 /* Emit the two subblocks */
3241 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3243 /* Emit a jump from the end of the then block to the end of the else */
3244 EMIT(branch
, false, false);
3245 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3247 /* Emit second block, and check if it's empty */
3249 int else_idx
= ctx
->block_count
;
3250 int count_in
= ctx
->instruction_count
;
3251 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3252 int after_else_idx
= ctx
->block_count
;
3254 /* Now that we have the subblocks emitted, fix up the branches */
3259 if (ctx
->instruction_count
== count_in
) {
3260 /* The else block is empty, so don't emit an exit jump */
3261 mir_remove_instruction(then_exit
);
3262 then_branch
->branch
.target_block
= after_else_idx
;
3264 then_branch
->branch
.target_block
= else_idx
;
3265 then_exit
->branch
.target_block
= after_else_idx
;
3270 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3272 /* Remember where we are */
3273 midgard_block
*start_block
= ctx
->current_block
;
3275 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3276 * single current_loop variable, maybe we need a stack */
3278 int loop_idx
= ++ctx
->current_loop
;
3280 /* Get index from before the body so we can loop back later */
3281 int start_idx
= ctx
->block_count
;
3283 /* Emit the body itself */
3284 emit_cf_list(ctx
, &nloop
->body
);
3286 /* Branch back to loop back */
3287 struct midgard_instruction br_back
= v_branch(false, false);
3288 br_back
.branch
.target_block
= start_idx
;
3289 emit_mir_instruction(ctx
, br_back
);
3291 /* Find the index of the block about to follow us (note: we don't add
3292 * one; blocks are 0-indexed so we get a fencepost problem) */
3293 int break_block_idx
= ctx
->block_count
;
3295 /* Fix up the break statements we emitted to point to the right place,
3296 * now that we can allocate a block number for them */
3298 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3299 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3300 print_mir_block(block
);
3301 mir_foreach_instr_in_block(block
, ins
) {
3302 if (ins
->type
!= TAG_ALU_4
) continue;
3303 if (!ins
->compact_branch
) continue;
3304 if (ins
->prepacked_branch
) continue;
3306 /* We found a branch -- check the type to see if we need to do anything */
3307 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3309 /* It's a break! Check if it's our break */
3310 if (ins
->branch
.target_break
!= loop_idx
) continue;
3312 /* Okay, cool, we're breaking out of this loop.
3313 * Rewrite from a break to a goto */
3315 ins
->branch
.target_type
= TARGET_GOTO
;
3316 ins
->branch
.target_block
= break_block_idx
;
3321 static midgard_block
*
3322 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3324 midgard_block
*start_block
= NULL
;
3326 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3327 switch (node
->type
) {
3328 case nir_cf_node_block
: {
3329 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3332 start_block
= block
;
3337 case nir_cf_node_if
:
3338 emit_if(ctx
, nir_cf_node_as_if(node
));
3341 case nir_cf_node_loop
:
3342 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3345 case nir_cf_node_function
:
3354 /* Due to lookahead, we need to report the first tag executed in the command
3355 * stream and in branch targets. An initial block might be empty, so iterate
3356 * until we find one that 'works' */
3359 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3361 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3363 unsigned first_tag
= 0;
3366 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3368 if (initial_bundle
) {
3369 first_tag
= initial_bundle
->tag
;
3373 /* Initial block is empty, try the next block */
3374 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3375 } while(initial_block
!= NULL
);
3382 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3384 struct util_dynarray
*compiled
= &program
->compiled
;
3386 midgard_debug
= debug_get_option_midgard_debug();
3388 compiler_context ictx
= {
3390 .stage
= nir
->info
.stage
,
3392 .is_blend
= is_blend
,
3393 .blend_constant_offset
= -1,
3395 .alpha_ref
= program
->alpha_ref
3398 compiler_context
*ctx
= &ictx
;
3400 /* TODO: Decide this at runtime */
3401 ctx
->uniform_cutoff
= 8;
3403 switch (ctx
->stage
) {
3404 case MESA_SHADER_VERTEX
:
3405 ctx
->special_uniforms
= 1;
3409 ctx
->special_uniforms
= 0;
3413 /* Append epilogue uniforms if necessary. The cmdstream depends on
3414 * these being at the -end-; see assign_var_locations. */
3416 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3417 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3420 /* Assign var locations early, so the epilogue can use them if necessary */
3422 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3423 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3424 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3426 /* Initialize at a global (not block) level hash tables */
3428 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3429 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3430 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3431 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3432 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3433 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3435 /* Assign actual uniform location, skipping over samplers */
3437 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3439 nir_foreach_variable(var
, &nir
->uniforms
) {
3440 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3442 unsigned length
= glsl_get_aoa_size(var
->type
);
3445 length
= glsl_get_length(var
->type
);
3449 length
= glsl_get_matrix_columns(var
->type
);
3452 for (int col
= 0; col
< length
; ++col
) {
3453 int id
= ctx
->uniform_count
++;
3454 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3458 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3459 ctx
->varying_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3461 /* First, collect the special varyings */
3462 nir_foreach_variable(var
, &nir
->outputs
) {
3463 if (var
->data
.location
== VARYING_SLOT_POS
) {
3464 /* Set position first, always. It takes up two
3465 * spots, the latter one is de facto unused (at
3466 * least from the shader's perspective), we
3467 * just need to skip over the spot*/
3469 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (0 + 1)));
3470 ctx
->varying_count
= MAX2(ctx
->varying_count
, 2);
3471 } else if (var
->data
.location
== VARYING_SLOT_PSIZ
) {
3472 /* Set point size second (third, see above) */
3473 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (2 + 1)));
3474 ctx
->varying_count
= MAX2(ctx
->varying_count
, 3);
3476 program
->writes_point_size
= true;
3480 /* Now, collect normal varyings */
3482 nir_foreach_variable(var
, &nir
->outputs
) {
3483 if (var
->data
.location
== VARYING_SLOT_POS
|| var
->data
.location
== VARYING_SLOT_PSIZ
) continue;
3485 for (int col
= 0; col
< glsl_get_matrix_columns(var
->type
); ++col
) {
3486 int id
= ctx
->varying_count
++;
3487 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3494 /* Lower vars -- not I/O -- before epilogue */
3496 NIR_PASS_V(nir
, nir_lower_var_copies
);
3497 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3498 NIR_PASS_V(nir
, nir_split_var_copies
);
3499 NIR_PASS_V(nir
, nir_lower_var_copies
);
3500 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3501 NIR_PASS_V(nir
, nir_lower_var_copies
);
3502 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3503 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3505 /* Append vertex epilogue before optimisation, so the epilogue itself
3508 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3509 transform_position_writes(nir
);
3511 /* Optimisation passes */
3515 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3516 nir_print_shader(nir
, stdout
);
3519 /* Assign counts, now that we're sure (post-optimisation) */
3520 program
->uniform_count
= nir
->num_uniforms
;
3522 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3523 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3526 nir_foreach_function(func
, nir
) {
3530 list_inithead(&ctx
->blocks
);
3531 ctx
->block_count
= 0;
3534 emit_cf_list(ctx
, &func
->impl
->body
);
3535 emit_block(ctx
, func
->impl
->end_block
);
3537 break; /* TODO: Multi-function shaders */
3540 util_dynarray_init(compiled
, NULL
);
3543 schedule_program(ctx
);
3545 /* Now that all the bundles are scheduled and we can calculate block
3546 * sizes, emit actual branch instructions rather than placeholders */
3548 int br_block_idx
= 0;
3550 mir_foreach_block(ctx
, block
) {
3551 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3552 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3553 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3555 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3557 if (ins
->prepacked_branch
) continue;
3559 /* Parse some basic branch info */
3560 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3561 bool is_conditional
= ins
->branch
.conditional
;
3562 bool is_inverted
= ins
->branch
.invert_conditional
;
3563 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3565 /* Determine the block we're jumping to */
3566 int target_number
= ins
->branch
.target_block
;
3568 /* Report the destination tag. Discards don't need this */
3569 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3571 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3572 int quadword_offset
= 0;
3575 /* Jump to the end of the shader. We
3576 * need to include not only the
3577 * following blocks, but also the
3578 * contents of our current block (since
3579 * discard can come in the middle of
3582 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3584 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3585 quadword_offset
+= quadword_size(bun
->tag
);
3588 mir_foreach_block_from(ctx
, blk
, b
) {
3589 quadword_offset
+= b
->quadword_count
;
3592 } else if (target_number
> br_block_idx
) {
3595 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3596 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3599 quadword_offset
+= blk
->quadword_count
;
3602 /* Jump backwards */
3604 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3605 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3608 quadword_offset
-= blk
->quadword_count
;
3612 /* Unconditional extended branches (far jumps)
3613 * have issues, so we always use a conditional
3614 * branch, setting the condition to always for
3615 * unconditional. For compact unconditional
3616 * branches, cond isn't used so it doesn't
3617 * matter what we pick. */
3619 midgard_condition cond
=
3620 !is_conditional
? midgard_condition_always
:
3621 is_inverted
? midgard_condition_false
:
3622 midgard_condition_true
;
3624 midgard_jmp_writeout_op op
=
3625 is_discard
? midgard_jmp_writeout_op_discard
:
3626 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3627 midgard_jmp_writeout_op_branch_cond
;
3630 midgard_branch_extended branch
=
3631 midgard_create_branch_extended(
3636 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3637 } else if (is_conditional
|| is_discard
) {
3638 midgard_branch_cond branch
= {
3640 .dest_tag
= dest_tag
,
3641 .offset
= quadword_offset
,
3645 assert(branch
.offset
== quadword_offset
);
3647 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3649 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3651 midgard_branch_uncond branch
= {
3653 .dest_tag
= dest_tag
,
3654 .offset
= quadword_offset
,
3658 assert(branch
.offset
== quadword_offset
);
3660 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3668 /* Emit flat binary from the instruction arrays. Iterate each block in
3669 * sequence. Save instruction boundaries such that lookahead tags can
3670 * be assigned easily */
3672 /* Cache _all_ bundles in source order for lookahead across failed branches */
3674 int bundle_count
= 0;
3675 mir_foreach_block(ctx
, block
) {
3676 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3678 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3680 mir_foreach_block(ctx
, block
) {
3681 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3682 source_order_bundles
[bundle_idx
++] = bundle
;
3686 int current_bundle
= 0;
3688 mir_foreach_block(ctx
, block
) {
3689 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3692 if (current_bundle
+ 1 < bundle_count
) {
3693 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3695 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3702 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3706 /* TODO: Free deeper */
3707 //util_dynarray_fini(&block->instructions);
3710 free(source_order_bundles
);
3712 /* Report the very first tag executed */
3713 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3715 /* Deal with off-by-one related to the fencepost problem */
3716 program
->work_register_count
= ctx
->work_registers
+ 1;
3718 program
->can_discard
= ctx
->can_discard
;
3719 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3721 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3723 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3724 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);