2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
111 midgard_is_branch_unit(unsigned unit
)
113 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
116 /* Generic in-memory data type repesenting a single logical instruction, rather
117 * than a single instruction group. This is the preferred form for code gen.
118 * Multiple midgard_insturctions will later be combined during scheduling,
119 * though this is not represented in this structure. Its format bridges
120 * the low-level binary representation with the higher level semantic meaning.
122 * Notably, it allows registers to be specified as block local SSA, for code
123 * emitted before the register allocation pass.
126 typedef struct midgard_instruction
{
127 /* Must be first for casting */
128 struct list_head link
;
130 unsigned type
; /* ALU, load/store, texture */
132 /* If the register allocator has not run yet... */
135 /* Special fields for an ALU instruction */
136 midgard_reg_info registers
;
138 /* I.e. (1 << alu_bit) */
141 /* When emitting bundle, should this instruction have a break forced
142 * before it? Used for r31 writes which are valid only within a single
143 * bundle and *need* to happen as early as possible... this is a hack,
144 * TODO remove when we have a scheduler */
149 uint16_t inline_constant
;
150 bool has_blend_constant
;
154 bool prepacked_branch
;
157 midgard_load_store_word load_store
;
158 midgard_vector_alu alu
;
159 midgard_texture_word texture
;
160 midgard_branch_extended branch_extended
;
163 /* General branch, rather than packed br_compact. Higher level
164 * than the other components */
165 midgard_branch branch
;
167 } midgard_instruction
;
169 typedef struct midgard_block
{
170 /* Link to next block. Must be first for mir_get_block */
171 struct list_head link
;
173 /* List of midgard_instructions emitted for the current block */
174 struct list_head instructions
;
178 /* List of midgard_bundles emitted (after the scheduler has run) */
179 struct util_dynarray bundles
;
181 /* Number of quadwords _actually_ emitted, as determined after scheduling */
182 unsigned quadword_count
;
184 /* Successors: always one forward (the block after us), maybe
185 * one backwards (for a backward branch). No need for a second
186 * forward, since graph traversal would get there eventually
188 struct midgard_block
*successors
[2];
189 unsigned nr_successors
;
191 /* The successors pointer form a graph, and in the case of
192 * complex control flow, this graph has a cycles. To aid
193 * traversal during liveness analysis, we have a visited?
194 * boolean for passes to use as they see fit, provided they
200 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
202 block
->successors
[block
->nr_successors
++] = successor
;
203 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
206 /* Helpers to generate midgard_instruction's using macro magic, since every
207 * driver seems to do it that way */
209 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
210 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
212 #define M_LOAD_STORE(name, rname, uname) \
213 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
214 midgard_instruction i = { \
215 .type = TAG_LOAD_STORE_4, \
222 .op = midgard_op_##name, \
224 .swizzle = SWIZZLE_XYZW, \
232 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
233 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
235 const midgard_vector_alu_src blank_alu_src
= {
236 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
239 const midgard_vector_alu_src blank_alu_src_xxxx
= {
240 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
243 const midgard_scalar_alu_src blank_scalar_alu_src
= {
247 /* Used for encoding the unused source of 1-op instructions */
248 const midgard_vector_alu_src zero_alu_src
= { 0 };
250 /* Coerce structs to integer */
253 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
256 memcpy(&u
, &src
, sizeof(src
));
260 static midgard_vector_alu_src
261 vector_alu_from_unsigned(unsigned u
)
263 midgard_vector_alu_src s
;
264 memcpy(&s
, &u
, sizeof(s
));
268 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
269 * the corresponding Midgard source */
271 static midgard_vector_alu_src
272 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
274 if (!src
) return blank_alu_src
;
276 midgard_vector_alu_src alu_src
= {
279 .half
= 0, /* TODO */
280 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
284 /* TODO: sign-extend/zero-extend */
285 alu_src
.mod
= midgard_int_normal
;
287 /* These should have been lowered away */
288 assert(!(src
->abs
|| src
->negate
));
290 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
296 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
298 static midgard_instruction
299 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
301 midgard_instruction ins
= {
304 .src0
= SSA_UNUSED_1
,
309 .op
= midgard_alu_op_fmov
,
310 .reg_mode
= midgard_reg_mode_32
,
311 .dest_override
= midgard_dest_override_none
,
313 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
314 .src2
= vector_alu_srco_unsigned(mod
)
321 /* load/store instructions have both 32-bit and 16-bit variants, depending on
322 * whether we are using vectors composed of highp or mediump. At the moment, we
323 * don't support half-floats -- this requires changes in other parts of the
324 * compiler -- therefore the 16-bit versions are commented out. */
326 //M_LOAD(ld_attr_16);
328 //M_LOAD(ld_vary_16);
330 //M_LOAD(ld_uniform_16);
331 M_LOAD(ld_uniform_32
);
332 M_LOAD(ld_color_buffer_8
);
333 //M_STORE(st_vary_16);
335 M_STORE(st_cubemap_coords
);
337 static midgard_instruction
338 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
340 midgard_branch_cond branch
= {
348 memcpy(&compact
, &branch
, sizeof(branch
));
350 midgard_instruction ins
= {
352 .unit
= ALU_ENAB_BR_COMPACT
,
353 .prepacked_branch
= true,
354 .compact_branch
= true,
355 .br_compact
= compact
358 if (op
== midgard_jmp_writeout_op_writeout
)
364 static midgard_instruction
365 v_branch(bool conditional
, bool invert
)
367 midgard_instruction ins
= {
369 .unit
= ALU_ENAB_BRANCH
,
370 .compact_branch
= true,
372 .conditional
= conditional
,
373 .invert_conditional
= invert
380 static midgard_branch_extended
381 midgard_create_branch_extended( midgard_condition cond
,
382 midgard_jmp_writeout_op op
,
384 signed quadword_offset
)
386 /* For unclear reasons, the condition code is repeated 8 times */
387 uint16_t duplicated_cond
=
397 midgard_branch_extended branch
= {
399 .dest_tag
= dest_tag
,
400 .offset
= quadword_offset
,
401 .cond
= duplicated_cond
407 typedef struct midgard_bundle
{
408 /* Tag for the overall bundle */
411 /* Instructions contained by the bundle */
412 int instruction_count
;
413 midgard_instruction instructions
[5];
415 /* Bundle-wide ALU configuration */
418 bool has_embedded_constants
;
420 bool has_blend_constant
;
422 uint16_t register_words
[8];
423 int register_words_count
;
425 uint64_t body_words
[8];
427 int body_words_count
;
430 typedef struct compiler_context
{
432 gl_shader_stage stage
;
434 /* Is internally a blend shader? Depends on stage == FRAGMENT */
437 /* Tracking for blend constant patching */
438 int blend_constant_offset
;
440 /* Current NIR function */
443 /* Unordered list of midgard_blocks */
445 struct list_head blocks
;
447 midgard_block
*initial_block
;
448 midgard_block
*previous_source_block
;
449 midgard_block
*final_block
;
451 /* List of midgard_instructions emitted for the current block */
452 midgard_block
*current_block
;
454 /* The current "depth" of the loop, for disambiguating breaks/continues
455 * when using nested loops */
456 int current_loop_depth
;
458 /* Constants which have been loaded, for later inlining */
459 struct hash_table_u64
*ssa_constants
;
461 /* SSA indices to be outputted to corresponding varying offset */
462 struct hash_table_u64
*ssa_varyings
;
464 /* SSA values / registers which have been aliased. Naively, these
465 * demand a fmov output; instead, we alias them in a later pass to
466 * avoid the wasted op.
468 * A note on encoding: to avoid dynamic memory management here, rather
469 * than ampping to a pointer, we map to the source index; the key
470 * itself is just the destination index. */
472 struct hash_table_u64
*ssa_to_alias
;
473 struct set
*leftover_ssa_to_alias
;
475 /* Actual SSA-to-register for RA */
476 struct hash_table_u64
*ssa_to_register
;
478 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
479 struct hash_table_u64
*hash_to_temp
;
483 /* Just the count of the max register used. Higher count => higher
484 * register pressure */
487 /* Used for cont/last hinting. Increase when a tex op is added.
488 * Decrease when a tex op is removed. */
489 int texture_op_count
;
491 /* Mapping of texture register -> SSA index for unaliasing */
492 int texture_index
[2];
494 /* If any path hits a discard instruction */
497 /* The number of uniforms allowable for the fast path */
500 /* Count of instructions emitted from NIR overall, across all blocks */
501 int instruction_count
;
503 /* Alpha ref value passed in */
506 /* The index corresponding to the fragment output */
507 unsigned fragment_output
;
509 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
510 unsigned sysvals
[MAX_SYSVAL_COUNT
];
511 unsigned sysval_count
;
512 struct hash_table_u64
*sysval_to_id
;
515 /* Append instruction to end of current block */
517 static midgard_instruction
*
518 mir_upload_ins(struct midgard_instruction ins
)
520 midgard_instruction
*heap
= malloc(sizeof(ins
));
521 memcpy(heap
, &ins
, sizeof(ins
));
526 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
528 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
532 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
534 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
538 mir_remove_instruction(struct midgard_instruction
*ins
)
540 list_del(&ins
->link
);
543 static midgard_instruction
*
544 mir_prev_op(struct midgard_instruction
*ins
)
546 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
549 static midgard_instruction
*
550 mir_next_op(struct midgard_instruction
*ins
)
552 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
555 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
556 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
558 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
559 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
560 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
561 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
562 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
563 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
564 #define mir_foreach_instr_in_block_from_rev(block, v, from) list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
567 static midgard_instruction
*
568 mir_last_in_block(struct midgard_block
*block
)
570 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
573 static midgard_block
*
574 mir_get_block(compiler_context
*ctx
, int idx
)
576 struct list_head
*lst
= &ctx
->blocks
;
581 return (struct midgard_block
*) lst
;
584 /* Pretty printer for internal Midgard IR */
587 print_mir_source(int source
)
589 if (source
>= SSA_FIXED_MINIMUM
) {
590 /* Specific register */
591 int reg
= SSA_REG_FROM_FIXED(source
);
593 /* TODO: Moving threshold */
594 if (reg
> 16 && reg
< 24)
595 printf("u%d", 23 - reg
);
599 printf("%d", source
);
604 print_mir_instruction(midgard_instruction
*ins
)
610 midgard_alu_op op
= ins
->alu
.op
;
611 const char *name
= alu_opcode_props
[op
].name
;
614 printf("%d.", ins
->unit
);
616 printf("%s", name
? name
: "??");
620 case TAG_LOAD_STORE_4
: {
621 midgard_load_store_op op
= ins
->load_store
.op
;
622 const char *name
= load_store_opcode_names
[op
];
629 case TAG_TEXTURE_4
: {
638 ssa_args
*args
= &ins
->ssa_args
;
640 printf(" %d, ", args
->dest
);
642 print_mir_source(args
->src0
);
645 if (args
->inline_constant
)
646 printf("#%d", ins
->inline_constant
);
648 print_mir_source(args
->src1
);
650 if (ins
->has_constants
)
651 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
657 print_mir_block(midgard_block
*block
)
661 mir_foreach_instr_in_block(block
, ins
) {
662 print_mir_instruction(ins
);
669 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
671 ins
->has_constants
= true;
672 memcpy(&ins
->constants
, constants
, 16);
676 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
678 return glsl_count_attribute_slots(type
, false);
681 /* Lower fdot2 to a vector multiplication followed by channel addition */
683 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
685 if (alu
->op
!= nir_op_fdot2
)
688 b
->cursor
= nir_before_instr(&alu
->instr
);
690 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
691 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
693 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
695 nir_ssa_def
*sum
= nir_fadd(b
,
696 nir_channel(b
, product
, 0),
697 nir_channel(b
, product
, 1));
699 /* Replace the fdot2 with this sum */
700 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
704 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
706 switch (instr
->intrinsic
) {
707 case nir_intrinsic_load_viewport_scale
:
708 return PAN_SYSVAL_VIEWPORT_SCALE
;
709 case nir_intrinsic_load_viewport_offset
:
710 return PAN_SYSVAL_VIEWPORT_OFFSET
;
717 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
721 if (instr
->type
== nir_instr_type_intrinsic
) {
722 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
723 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
729 /* We have a sysval load; check if it's already been assigned */
731 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
734 /* It hasn't -- so assign it now! */
736 unsigned id
= ctx
->sysval_count
++;
737 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
738 ctx
->sysvals
[id
] = sysval
;
742 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
744 ctx
->sysval_count
= 0;
746 nir_foreach_function(function
, shader
) {
747 if (!function
->impl
) continue;
749 nir_foreach_block(block
, function
->impl
) {
750 nir_foreach_instr_safe(instr
, block
) {
751 midgard_nir_assign_sysval_body(ctx
, instr
);
758 midgard_nir_lower_fdot2(nir_shader
*shader
)
760 bool progress
= false;
762 nir_foreach_function(function
, shader
) {
763 if (!function
->impl
) continue;
766 nir_builder
*b
= &_b
;
767 nir_builder_init(b
, function
->impl
);
769 nir_foreach_block(block
, function
->impl
) {
770 nir_foreach_instr_safe(instr
, block
) {
771 if (instr
->type
!= nir_instr_type_alu
) continue;
773 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
774 midgard_nir_lower_fdot2_body(b
, alu
);
780 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
788 optimise_nir(nir_shader
*nir
)
791 unsigned lower_flrp
=
792 (nir
->options
->lower_flrp16
? 16 : 0) |
793 (nir
->options
->lower_flrp32
? 32 : 0) |
794 (nir
->options
->lower_flrp64
? 64 : 0);
796 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
797 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
799 nir_lower_tex_options lower_tex_options
= {
803 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
808 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
809 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
811 NIR_PASS(progress
, nir
, nir_copy_prop
);
812 NIR_PASS(progress
, nir
, nir_opt_dce
);
813 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
814 NIR_PASS(progress
, nir
, nir_opt_cse
);
815 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
816 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
817 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
819 if (lower_flrp
!= 0) {
820 bool lower_flrp_progress
= false;
821 NIR_PASS(lower_flrp_progress
,
825 false /* always_precise */,
826 nir
->options
->lower_ffma
);
827 if (lower_flrp_progress
) {
828 NIR_PASS(progress
, nir
,
829 nir_opt_constant_folding
);
833 /* Nothing should rematerialize any flrps, so we only
834 * need to do this lowering once.
839 NIR_PASS(progress
, nir
, nir_opt_undef
);
840 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
843 nir_var_function_temp
);
845 /* TODO: Enable vectorize when merged upstream */
846 // NIR_PASS(progress, nir, nir_opt_vectorize);
849 /* Must be run at the end to prevent creation of fsin/fcos ops */
850 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
855 NIR_PASS(progress
, nir
, nir_opt_dce
);
856 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
857 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
858 NIR_PASS(progress
, nir
, nir_copy_prop
);
861 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
863 /* We implement booleans as 32-bit 0/~0 */
864 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
866 /* Now that booleans are lowered, we can run out late opts */
867 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
869 /* Lower mods for float ops only. Integer ops don't support modifiers
870 * (saturate doesn't make sense on integers, neg/abs require dedicated
873 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
874 NIR_PASS(progress
, nir
, nir_copy_prop
);
875 NIR_PASS(progress
, nir
, nir_opt_dce
);
877 /* Take us out of SSA */
878 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
879 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
881 /* We are a vector architecture; write combine where possible */
882 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
883 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
885 NIR_PASS(progress
, nir
, nir_opt_dce
);
888 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
889 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
890 * r0. See the comments in compiler_context */
893 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
895 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
896 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
899 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
902 unalias_ssa(compiler_context
*ctx
, int dest
)
904 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
905 /* TODO: Remove from leftover or no? */
909 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
911 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
915 midgard_is_pinned(compiler_context
*ctx
, int index
)
917 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
920 /* Do not actually emit a load; instead, cache the constant for inlining */
923 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
925 nir_ssa_def def
= instr
->def
;
927 float *v
= rzalloc_array(NULL
, float, 4);
928 nir_const_load_to_arr(v
, instr
, f32
);
929 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
932 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
936 expand_writemask(unsigned mask
)
940 for (int i
= 0; i
< 4; ++i
)
948 squeeze_writemask(unsigned mask
)
952 for (int i
= 0; i
< 4; ++i
)
953 if (mask
& (3 << (2 * i
)))
960 /* Determines effective writemask, taking quirks and expansion into account */
962 effective_writemask(midgard_vector_alu
*alu
)
964 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
967 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
].props
);
969 /* If there is a fixed channel count, construct the appropriate mask */
972 return (1 << channel_count
) - 1;
974 /* Otherwise, just squeeze the existing mask */
975 return squeeze_writemask(alu
->mask
);
979 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
981 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
984 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
989 /* If no temp is find, allocate one */
990 temp
= ctx
->temp_count
++;
991 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
993 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
999 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
1002 return src
->ssa
->index
;
1004 assert(!src
->reg
.indirect
);
1005 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
1010 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
1013 return dst
->ssa
.index
;
1015 assert(!dst
->reg
.indirect
);
1016 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
1021 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
1023 return nir_src_index(ctx
, &src
->src
);
1027 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
1029 unsigned comp
= src
->swizzle
[0];
1031 for (unsigned c
= 1; c
< nr_components
; ++c
) {
1032 if (src
->swizzle
[c
] != comp
)
1039 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
1040 * output of a conditional test) into that register */
1043 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
1045 int condition
= nir_src_index(ctx
, src
);
1047 /* Source to swizzle the desired component into w */
1049 const midgard_vector_alu_src alu_src
= {
1050 .swizzle
= SWIZZLE(component
, component
, component
, component
),
1053 /* There is no boolean move instruction. Instead, we simulate a move by
1054 * ANDing the condition with itself to get it into r31.w */
1056 midgard_instruction ins
= {
1059 /* We need to set the conditional as close as possible */
1060 .precede_break
= true,
1061 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
1067 .dest
= SSA_FIXED_REGISTER(31),
1070 .op
= midgard_alu_op_iand
,
1071 .reg_mode
= midgard_reg_mode_32
,
1072 .dest_override
= midgard_dest_override_none
,
1073 .mask
= (0x3 << 6), /* w */
1074 .src1
= vector_alu_srco_unsigned(alu_src
),
1075 .src2
= vector_alu_srco_unsigned(alu_src
)
1079 emit_mir_instruction(ctx
, ins
);
1082 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
1086 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
1088 int condition
= nir_src_index(ctx
, &src
->src
);
1090 /* Source to swizzle the desired component into w */
1092 const midgard_vector_alu_src alu_src
= {
1093 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
1096 /* There is no boolean move instruction. Instead, we simulate a move by
1097 * ANDing the condition with itself to get it into r31.w */
1099 midgard_instruction ins
= {
1101 .precede_break
= true,
1105 .dest
= SSA_FIXED_REGISTER(31),
1108 .op
= midgard_alu_op_iand
,
1109 .reg_mode
= midgard_reg_mode_32
,
1110 .dest_override
= midgard_dest_override_none
,
1111 .mask
= expand_writemask((1 << nr_comp
) - 1),
1112 .src1
= vector_alu_srco_unsigned(alu_src
),
1113 .src2
= vector_alu_srco_unsigned(alu_src
)
1117 emit_mir_instruction(ctx
, ins
);
1122 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1123 * pinning to eliminate this move in all known cases */
1126 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1128 int offset
= nir_src_index(ctx
, src
);
1130 midgard_instruction ins
= {
1133 .src0
= SSA_UNUSED_1
,
1135 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1138 .op
= midgard_alu_op_imov
,
1139 .reg_mode
= midgard_reg_mode_32
,
1140 .dest_override
= midgard_dest_override_none
,
1141 .mask
= (0x3 << 6), /* w */
1142 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1143 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1147 emit_mir_instruction(ctx
, ins
);
1150 #define ALU_CASE(nir, _op) \
1151 case nir_op_##nir: \
1152 op = midgard_alu_op_##_op; \
1155 nir_is_fzero_constant(nir_src src
)
1157 if (!nir_src_is_const(src
))
1160 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
1161 if (nir_src_comp_as_float(src
, c
) != 0.0)
1169 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1171 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1173 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1174 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1175 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1177 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1178 * supported. A few do not and are commented for now. Also, there are a
1179 * number of NIR ops which Midgard does not support and need to be
1180 * lowered, also TODO. This switch block emits the opcode and calling
1181 * convention of the Midgard instruction; actual packing is done in
1186 switch (instr
->op
) {
1187 ALU_CASE(fadd
, fadd
);
1188 ALU_CASE(fmul
, fmul
);
1189 ALU_CASE(fmin
, fmin
);
1190 ALU_CASE(fmax
, fmax
);
1191 ALU_CASE(imin
, imin
);
1192 ALU_CASE(imax
, imax
);
1193 ALU_CASE(umin
, umin
);
1194 ALU_CASE(umax
, umax
);
1195 ALU_CASE(fmov
, fmov
);
1196 ALU_CASE(ffloor
, ffloor
);
1197 ALU_CASE(fround_even
, froundeven
);
1198 ALU_CASE(ftrunc
, ftrunc
);
1199 ALU_CASE(fceil
, fceil
);
1200 ALU_CASE(fdot3
, fdot3
);
1201 ALU_CASE(fdot4
, fdot4
);
1202 ALU_CASE(iadd
, iadd
);
1203 ALU_CASE(isub
, isub
);
1204 ALU_CASE(imul
, imul
);
1205 ALU_CASE(iabs
, iabs
);
1206 ALU_CASE(imov
, imov
);
1208 ALU_CASE(feq32
, feq
);
1209 ALU_CASE(fne32
, fne
);
1210 ALU_CASE(flt32
, flt
);
1211 ALU_CASE(ieq32
, ieq
);
1212 ALU_CASE(ine32
, ine
);
1213 ALU_CASE(ilt32
, ilt
);
1214 ALU_CASE(ult32
, ult
);
1216 /* We don't have a native b2f32 instruction. Instead, like many
1217 * GPUs, we exploit booleans as 0/~0 for false/true, and
1218 * correspondingly AND
1219 * by 1.0 to do the type conversion. For the moment, prime us
1222 * iand [whatever], #0
1224 * At the end of emit_alu (as MIR), we'll fix-up the constant
1227 ALU_CASE(b2f32
, iand
);
1228 ALU_CASE(b2i32
, iand
);
1230 /* Likewise, we don't have a dedicated f2b32 instruction, but
1231 * we can do a "not equal to 0.0" test. */
1233 ALU_CASE(f2b32
, fne
);
1234 ALU_CASE(i2b32
, ine
);
1236 ALU_CASE(frcp
, frcp
);
1237 ALU_CASE(frsq
, frsqrt
);
1238 ALU_CASE(fsqrt
, fsqrt
);
1239 ALU_CASE(fexp2
, fexp2
);
1240 ALU_CASE(flog2
, flog2
);
1242 ALU_CASE(f2i32
, f2i
);
1243 ALU_CASE(f2u32
, f2u
);
1244 ALU_CASE(i2f32
, i2f
);
1245 ALU_CASE(u2f32
, u2f
);
1247 ALU_CASE(fsin
, fsin
);
1248 ALU_CASE(fcos
, fcos
);
1250 ALU_CASE(iand
, iand
);
1252 ALU_CASE(ixor
, ixor
);
1253 ALU_CASE(inot
, inand
);
1254 ALU_CASE(ishl
, ishl
);
1255 ALU_CASE(ishr
, iasr
);
1256 ALU_CASE(ushr
, ilsr
);
1258 ALU_CASE(b32all_fequal2
, fball_eq
);
1259 ALU_CASE(b32all_fequal3
, fball_eq
);
1260 ALU_CASE(b32all_fequal4
, fball_eq
);
1262 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1263 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1264 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1266 ALU_CASE(b32all_iequal2
, iball_eq
);
1267 ALU_CASE(b32all_iequal3
, iball_eq
);
1268 ALU_CASE(b32all_iequal4
, iball_eq
);
1270 ALU_CASE(b32any_inequal2
, ibany_neq
);
1271 ALU_CASE(b32any_inequal3
, ibany_neq
);
1272 ALU_CASE(b32any_inequal4
, ibany_neq
);
1274 /* For greater-or-equal, we lower to less-or-equal and flip the
1280 case nir_op_uge32
: {
1282 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1283 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1284 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1285 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1288 /* Swap via temporary */
1289 nir_alu_src temp
= instr
->src
[1];
1290 instr
->src
[1] = instr
->src
[0];
1291 instr
->src
[0] = temp
;
1296 case nir_op_b32csel
: {
1297 /* Midgard features both fcsel and icsel, depending on
1298 * the type of the arguments/output. However, as long
1299 * as we're careful we can _always_ use icsel and
1300 * _never_ need fcsel, since the latter does additional
1301 * floating-point-specific processing whereas the
1302 * former just moves bits on the wire. It's not obvious
1303 * why these are separate opcodes, save for the ability
1304 * to do things like sat/pos/abs/neg for free */
1306 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
1307 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
1309 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1312 /* Emit the condition into r31 */
1315 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
1317 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
1319 /* The condition is the first argument; move the other
1320 * arguments up one to be a binary instruction for
1323 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1328 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1333 /* Midgard can perform certain modifiers on output of an ALU op */
1334 midgard_outmod outmod
=
1335 midgard_is_integer_out_op(op
) ? midgard_outmod_int
:
1336 instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1338 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1340 if (instr
->op
== nir_op_fmax
) {
1341 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1342 op
= midgard_alu_op_fmov
;
1344 outmod
= midgard_outmod_pos
;
1345 instr
->src
[0] = instr
->src
[1];
1346 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1347 op
= midgard_alu_op_fmov
;
1349 outmod
= midgard_outmod_pos
;
1353 /* Fetch unit, quirks, etc information */
1354 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1355 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1357 /* src0 will always exist afaik, but src1 will not for 1-argument
1358 * instructions. The latter can only be fetched if the instruction
1359 * needs it, or else we may segfault. */
1361 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1362 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1364 /* Rather than use the instruction generation helpers, we do it
1365 * ourselves here to avoid the mess */
1367 midgard_instruction ins
= {
1370 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1371 .src1
= quirk_flipped_r24
? src0
: src1
,
1376 nir_alu_src
*nirmods
[2] = { NULL
};
1378 if (nr_inputs
== 2) {
1379 nirmods
[0] = &instr
->src
[0];
1380 nirmods
[1] = &instr
->src
[1];
1381 } else if (nr_inputs
== 1) {
1382 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1387 bool is_int
= midgard_is_integer_op(op
);
1389 midgard_vector_alu alu
= {
1391 .reg_mode
= midgard_reg_mode_32
,
1392 .dest_override
= midgard_dest_override_none
,
1395 /* Writemask only valid for non-SSA NIR */
1396 .mask
= expand_writemask((1 << nr_components
) - 1),
1398 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
1399 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
1402 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1405 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1409 /* Late fixup for emulated instructions */
1411 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1412 /* Presently, our second argument is an inline #0 constant.
1413 * Switch over to an embedded 1.0 constant (that can't fit
1414 * inline, since we're 32-bit, not 16-bit like the inline
1417 ins
.ssa_args
.inline_constant
= false;
1418 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1419 ins
.has_constants
= true;
1421 if (instr
->op
== nir_op_b2f32
) {
1422 ins
.constants
[0] = 1.0f
;
1424 /* Type pun it into place */
1426 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1429 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1430 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1431 ins
.ssa_args
.inline_constant
= false;
1432 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1433 ins
.has_constants
= true;
1434 ins
.constants
[0] = 0.0f
;
1435 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1436 } else if (instr
->op
== nir_op_inot
) {
1437 /* ~b = ~(b & b), so duplicate the source */
1438 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1439 ins
.alu
.src2
= ins
.alu
.src1
;
1442 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1443 /* To avoid duplicating the lookup tables (probably), true LUT
1444 * instructions can only operate as if they were scalars. Lower
1445 * them here by changing the component. */
1447 uint8_t original_swizzle
[4];
1448 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1450 for (int i
= 0; i
< nr_components
; ++i
) {
1451 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1453 for (int j
= 0; j
< 4; ++j
)
1454 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1456 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
1457 emit_mir_instruction(ctx
, ins
);
1460 emit_mir_instruction(ctx
, ins
);
1467 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1469 /* TODO: half-floats */
1471 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1472 /* Fast path: For the first 16 uniforms, direct accesses are
1473 * 0-cycle, since they're just a register fetch in the usual
1474 * case. So, we alias the registers while we're still in
1477 int reg_slot
= 23 - offset
;
1478 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1480 /* Otherwise, read from the 'special' UBO to access
1481 * higher-indexed uniforms, at a performance cost. More
1482 * generally, we're emitting a UBO read instruction. */
1484 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1486 /* TODO: Don't split */
1487 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1488 ins
.load_store
.address
= offset
>> 3;
1490 if (indirect_offset
) {
1491 emit_indirect_offset(ctx
, indirect_offset
);
1492 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1494 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1497 emit_mir_instruction(ctx
, ins
);
1502 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1504 /* First, pull out the destination */
1505 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1507 /* Now, figure out which uniform this is */
1508 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1509 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1511 /* Sysvals are prefix uniforms */
1512 unsigned uniform
= ((uintptr_t) val
) - 1;
1514 /* Emit the read itself -- this is never indirect */
1515 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1518 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1519 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1520 * generations have faster vectorized reads. This operation is for blend
1521 * shaders in particular; reading the tilebuffer from the fragment shader
1522 * remains an open problem. */
1525 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1527 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1528 ins
.load_store
.swizzle
= 0; /* xxxx */
1530 /* Read each component sequentially */
1532 for (unsigned c
= 0; c
< 4; ++c
) {
1533 ins
.load_store
.mask
= (1 << c
);
1534 ins
.load_store
.unknown
= c
;
1535 emit_mir_instruction(ctx
, ins
);
1538 /* vadd.u2f hr2, zext(hr2), #0 */
1540 midgard_vector_alu_src alu_src
= blank_alu_src
;
1541 alu_src
.mod
= midgard_int_zero_extend
;
1542 alu_src
.half
= true;
1544 midgard_instruction u2f
= {
1548 .src1
= SSA_UNUSED_0
,
1550 .inline_constant
= true
1553 .op
= midgard_alu_op_u2f
,
1554 .reg_mode
= midgard_reg_mode_16
,
1555 .dest_override
= midgard_dest_override_none
,
1557 .src1
= vector_alu_srco_unsigned(alu_src
),
1558 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1562 emit_mir_instruction(ctx
, u2f
);
1564 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1568 midgard_instruction fmul
= {
1570 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1574 .src1
= SSA_UNUSED_0
,
1575 .inline_constant
= true
1578 .op
= midgard_alu_op_fmul
,
1579 .reg_mode
= midgard_reg_mode_32
,
1580 .dest_override
= midgard_dest_override_none
,
1581 .outmod
= midgard_outmod_sat
,
1583 .src1
= vector_alu_srco_unsigned(alu_src
),
1584 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1588 emit_mir_instruction(ctx
, fmul
);
1592 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1594 unsigned offset
, reg
;
1596 switch (instr
->intrinsic
) {
1597 case nir_intrinsic_discard_if
:
1598 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1602 case nir_intrinsic_discard
: {
1603 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1604 struct midgard_instruction discard
= v_branch(conditional
, false);
1605 discard
.branch
.target_type
= TARGET_DISCARD
;
1606 emit_mir_instruction(ctx
, discard
);
1608 ctx
->can_discard
= true;
1612 case nir_intrinsic_load_uniform
:
1613 case nir_intrinsic_load_input
:
1614 offset
= nir_intrinsic_base(instr
);
1616 bool direct
= nir_src_is_const(instr
->src
[0]);
1619 offset
+= nir_src_as_uint(instr
->src
[0]);
1622 reg
= nir_dest_index(ctx
, &instr
->dest
);
1624 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1625 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1626 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1627 /* XXX: Half-floats? */
1628 /* TODO: swizzle, mask */
1630 midgard_instruction ins
= m_ld_vary_32(reg
, offset
);
1632 midgard_varying_parameter p
= {
1634 .interpolation
= midgard_interp_default
,
1635 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1639 memcpy(&u
, &p
, sizeof(p
));
1640 ins
.load_store
.varying_parameters
= u
;
1643 /* We have the offset totally ready */
1644 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1646 /* We have it partially ready, but we need to
1647 * add in the dynamic index, moved to r27.w */
1648 emit_indirect_offset(ctx
, &instr
->src
[0]);
1649 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1652 emit_mir_instruction(ctx
, ins
);
1653 } else if (ctx
->is_blend
) {
1654 /* For blend shaders, load the input color, which is
1655 * preloaded to r0 */
1657 midgard_pin_output(ctx
, reg
, 0);
1658 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1659 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1660 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1661 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1662 emit_mir_instruction(ctx
, ins
);
1664 DBG("Unknown load\n");
1670 case nir_intrinsic_load_output
:
1671 assert(nir_src_is_const(instr
->src
[0]));
1672 reg
= nir_dest_index(ctx
, &instr
->dest
);
1674 if (ctx
->is_blend
) {
1676 emit_fb_read_blend_scalar(ctx
, reg
);
1678 DBG("Unknown output load\n");
1684 case nir_intrinsic_load_blend_const_color_rgba
: {
1685 assert(ctx
->is_blend
);
1686 reg
= nir_dest_index(ctx
, &instr
->dest
);
1688 /* Blend constants are embedded directly in the shader and
1689 * patched in, so we use some magic routing */
1691 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1692 ins
.has_constants
= true;
1693 ins
.has_blend_constant
= true;
1694 emit_mir_instruction(ctx
, ins
);
1698 case nir_intrinsic_store_output
:
1699 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1701 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1703 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1705 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1706 /* gl_FragColor is not emitted with load/store
1707 * instructions. Instead, it gets plonked into
1708 * r0 at the end of the shader and we do the
1709 * framebuffer writeout dance. TODO: Defer
1712 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1713 emit_mir_instruction(ctx
, move
);
1715 //midgard_pin_output(ctx, reg, 0);
1717 /* Save the index we're writing to for later reference
1718 * in the epilogue */
1720 ctx
->fragment_output
= reg
;
1721 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1722 /* Varyings are written into one of two special
1723 * varying register, r26 or r27. The register itself is selected as the register
1724 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1726 * Normally emitting fmov's is frowned upon,
1727 * but due to unique constraints of
1728 * REGISTER_VARYING, fmov emission + a
1729 * dedicated cleanup pass is the only way to
1730 * guarantee correctness when considering some
1731 * (common) edge cases XXX: FIXME */
1733 /* If this varying corresponds to a constant (why?!),
1734 * emit that now since it won't get picked up by
1735 * hoisting (since there is no corresponding move
1736 * emitted otherwise) */
1738 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1740 if (constant_value
) {
1741 /* Special case: emit the varying write
1742 * directly to r26 (looks funny in asm but it's
1743 * fine) and emit the store _now_. Possibly
1744 * slightly slower, but this is a really stupid
1745 * special case anyway (why on earth would you
1746 * have a constant varying? Your own fault for
1747 * slightly worse perf :P) */
1749 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1750 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1751 emit_mir_instruction(ctx
, ins
);
1753 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1754 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1755 emit_mir_instruction(ctx
, st
);
1757 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1759 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1762 DBG("Unknown store\n");
1768 case nir_intrinsic_load_alpha_ref_float
:
1769 assert(instr
->dest
.is_ssa
);
1771 float ref_value
= ctx
->alpha_ref
;
1773 float *v
= ralloc_array(NULL
, float, 4);
1774 memcpy(v
, &ref_value
, sizeof(float));
1775 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1778 case nir_intrinsic_load_viewport_scale
:
1779 case nir_intrinsic_load_viewport_offset
:
1780 emit_sysval_read(ctx
, instr
);
1784 printf ("Unhandled intrinsic\n");
1791 midgard_tex_format(enum glsl_sampler_dim dim
)
1794 case GLSL_SAMPLER_DIM_2D
:
1795 case GLSL_SAMPLER_DIM_EXTERNAL
:
1798 case GLSL_SAMPLER_DIM_3D
:
1801 case GLSL_SAMPLER_DIM_CUBE
:
1802 return TEXTURE_CUBE
;
1805 DBG("Unknown sampler dim type\n");
1812 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1815 //assert (!instr->sampler);
1816 //assert (!instr->texture_array_size);
1817 assert (instr
->op
== nir_texop_tex
);
1819 /* Allocate registers via a round robin scheme to alternate between the two registers */
1820 int reg
= ctx
->texture_op_count
& 1;
1821 int in_reg
= reg
, out_reg
= reg
;
1823 /* Make room for the reg */
1825 if (ctx
->texture_index
[reg
] > -1)
1826 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1828 int texture_index
= instr
->texture_index
;
1829 int sampler_index
= texture_index
;
1831 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1832 switch (instr
->src
[i
].src_type
) {
1833 case nir_tex_src_coord
: {
1834 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1836 midgard_vector_alu_src alu_src
= blank_alu_src
;
1838 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1840 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1841 /* For cubemaps, we need to load coords into
1842 * special r27, and then use a special ld/st op
1843 * to copy into the texture register */
1845 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1847 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1848 emit_mir_instruction(ctx
, move
);
1850 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1851 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1852 st
.load_store
.mask
= 0x3; /* xy? */
1853 st
.load_store
.swizzle
= alu_src
.swizzle
;
1854 emit_mir_instruction(ctx
, st
);
1857 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1859 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1860 emit_mir_instruction(ctx
, ins
);
1867 DBG("Unknown source type\n");
1874 /* No helper to build texture words -- we do it all here */
1875 midgard_instruction ins
= {
1876 .type
= TAG_TEXTURE_4
,
1878 .op
= TEXTURE_OP_NORMAL
,
1879 .format
= midgard_tex_format(instr
->sampler_dim
),
1880 .texture_handle
= texture_index
,
1881 .sampler_handle
= sampler_index
,
1883 /* TODO: Don't force xyzw */
1884 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1896 /* Assume we can continue; hint it out later */
1901 /* Set registers to read and write from the same place */
1902 ins
.texture
.in_reg_select
= in_reg
;
1903 ins
.texture
.out_reg_select
= out_reg
;
1905 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1906 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1907 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1908 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1909 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1911 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1912 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1913 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1916 emit_mir_instruction(ctx
, ins
);
1918 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1920 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1921 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1922 ctx
->texture_index
[reg
] = o_index
;
1924 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1925 emit_mir_instruction(ctx
, ins2
);
1927 /* Used for .cont and .last hinting */
1928 ctx
->texture_op_count
++;
1932 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1934 switch (instr
->type
) {
1935 case nir_jump_break
: {
1936 /* Emit a branch out of the loop */
1937 struct midgard_instruction br
= v_branch(false, false);
1938 br
.branch
.target_type
= TARGET_BREAK
;
1939 br
.branch
.target_break
= ctx
->current_loop_depth
;
1940 emit_mir_instruction(ctx
, br
);
1947 DBG("Unknown jump type %d\n", instr
->type
);
1953 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1955 switch (instr
->type
) {
1956 case nir_instr_type_load_const
:
1957 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1960 case nir_instr_type_intrinsic
:
1961 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1964 case nir_instr_type_alu
:
1965 emit_alu(ctx
, nir_instr_as_alu(instr
));
1968 case nir_instr_type_tex
:
1969 emit_tex(ctx
, nir_instr_as_tex(instr
));
1972 case nir_instr_type_jump
:
1973 emit_jump(ctx
, nir_instr_as_jump(instr
));
1976 case nir_instr_type_ssa_undef
:
1981 DBG("Unhandled instruction type\n");
1986 /* Determine the actual hardware from the index based on the RA results or special values */
1989 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1991 if (reg
>= SSA_FIXED_MINIMUM
)
1992 return SSA_REG_FROM_FIXED(reg
);
1995 assert(reg
< maxreg
);
1997 int r
= ra_get_node_reg(g
, reg
);
1998 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
2003 /* fmov style unused */
2005 return REGISTER_UNUSED
;
2007 /* lut style unused */
2009 return REGISTER_UNUSED
;
2012 DBG("Unknown SSA register alias %d\n", reg
);
2019 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
2021 /* Choose the first available register to minimise reported register pressure */
2023 for (int i
= 0; i
< 16; ++i
) {
2024 if (BITSET_TEST(regs
, i
)) {
2034 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
2036 if (ins
->ssa_args
.src0
== src
) return true;
2037 if (ins
->ssa_args
.src1
== src
) return true;
2042 /* Determine if a variable is live in the successors of a block */
2044 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
2046 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
2047 midgard_block
*succ
= bl
->successors
[i
];
2049 /* If we already visited, the value we're seeking
2050 * isn't down this path (or we would have short
2053 if (succ
->visited
) continue;
2055 /* Otherwise (it's visited *now*), check the block */
2057 succ
->visited
= true;
2059 mir_foreach_instr_in_block(succ
, ins
) {
2060 if (midgard_is_live_in_instr(ins
, src
))
2064 /* ...and also, check *its* successors */
2065 if (is_live_after_successors(ctx
, succ
, src
))
2070 /* Welp. We're really not live. */
2076 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
2078 /* Check the rest of the block for liveness */
2080 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
2081 if (midgard_is_live_in_instr(ins
, src
))
2085 /* Check the rest of the blocks for liveness recursively */
2087 bool succ
= is_live_after_successors(ctx
, block
, src
);
2089 mir_foreach_block(ctx
, block
) {
2090 block
->visited
= false;
2096 /* Once registers have been decided via register allocation
2097 * (allocate_registers), we need to rewrite the MIR to use registers instead of
2101 install_registers(compiler_context
*ctx
, struct ra_graph
*g
)
2103 mir_foreach_block(ctx
, block
) {
2104 mir_foreach_instr_in_block(block
, ins
) {
2105 if (ins
->compact_branch
) continue;
2107 ssa_args args
= ins
->ssa_args
;
2109 switch (ins
->type
) {
2111 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, ctx
->temp_count
);
2113 ins
->registers
.src2_imm
= args
.inline_constant
;
2115 if (args
.inline_constant
) {
2116 /* Encode inline 16-bit constant as a vector by default */
2118 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2120 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2122 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2123 ins
->alu
.src2
= imm
<< 2;
2125 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, ctx
->temp_count
);
2128 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, ctx
->temp_count
);
2132 case TAG_LOAD_STORE_4
: {
2133 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2134 /* TODO: use ssa_args for st_vary */
2135 ins
->load_store
.reg
= 0;
2137 bool has_dest
= args
.dest
>= 0;
2138 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2140 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, ctx
->temp_count
);
2154 /* This routine performs the actual register allocation. It should be succeeded
2155 * by install_registers */
2157 static struct ra_graph
*
2158 allocate_registers(compiler_context
*ctx
)
2160 /* First, initialize the RA */
2161 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
2163 /* Create a primary (general purpose) class, as well as special purpose
2164 * pipeline register classes */
2166 int primary_class
= ra_alloc_reg_class(regs
);
2167 int varying_class
= ra_alloc_reg_class(regs
);
2169 /* Add the full set of work registers */
2170 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
2171 for (int i
= 0; i
< work_count
; ++i
)
2172 ra_class_add_reg(regs
, primary_class
, i
);
2174 /* Add special registers */
2175 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
2176 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
2178 /* We're done setting up */
2179 ra_set_finalize(regs
, NULL
);
2181 /* Transform the MIR into squeezed index form */
2182 mir_foreach_block(ctx
, block
) {
2183 mir_foreach_instr_in_block(block
, ins
) {
2184 if (ins
->compact_branch
) continue;
2186 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
2187 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
2188 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
2190 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2191 print_mir_block(block
);
2194 /* No register allocation to do with no SSA */
2196 if (!ctx
->temp_count
)
2199 /* Let's actually do register allocation */
2200 int nodes
= ctx
->temp_count
;
2201 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
2203 /* Set everything to the work register class, unless it has somewhere
2206 mir_foreach_block(ctx
, block
) {
2207 mir_foreach_instr_in_block(block
, ins
) {
2208 if (ins
->compact_branch
) continue;
2210 if (ins
->ssa_args
.dest
< 0) continue;
2212 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2214 int class = primary_class
;
2216 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2220 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2221 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2224 unsigned reg
= temp
- 1;
2225 int t
= find_or_allocate_temp(ctx
, index
);
2226 ra_set_node_reg(g
, t
, reg
);
2230 /* Determine liveness */
2232 int *live_start
= malloc(nodes
* sizeof(int));
2233 int *live_end
= malloc(nodes
* sizeof(int));
2235 /* Initialize as non-existent */
2237 for (int i
= 0; i
< nodes
; ++i
) {
2238 live_start
[i
] = live_end
[i
] = -1;
2243 mir_foreach_block(ctx
, block
) {
2244 mir_foreach_instr_in_block(block
, ins
) {
2245 if (ins
->compact_branch
) continue;
2247 /* Dest is < 0 for st_vary instructions, which break
2248 * the usual SSA conventions. Liveness analysis doesn't
2249 * make sense on these instructions, so skip them to
2250 * avoid memory corruption */
2252 if (ins
->ssa_args
.dest
< 0) continue;
2254 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2255 /* If this destination is not yet live, it is now since we just wrote it */
2257 int dest
= ins
->ssa_args
.dest
;
2259 if (live_start
[dest
] == -1)
2260 live_start
[dest
] = d
;
2263 /* Since we just used a source, the source might be
2264 * dead now. Scan the rest of the block for
2265 * invocations, and if there are none, the source dies
2268 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2270 for (int src
= 0; src
< 2; ++src
) {
2271 int s
= sources
[src
];
2273 if (s
< 0) continue;
2275 if (s
>= SSA_FIXED_MINIMUM
) continue;
2277 if (!is_live_after(ctx
, block
, ins
, s
)) {
2286 /* If a node still hasn't been killed, kill it now */
2288 for (int i
= 0; i
< nodes
; ++i
) {
2289 /* live_start == -1 most likely indicates a pinned output */
2291 if (live_end
[i
] == -1)
2295 /* Setup interference between nodes that are live at the same time */
2297 for (int i
= 0; i
< nodes
; ++i
) {
2298 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2299 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2300 ra_add_node_interference(g
, i
, j
);
2304 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2306 if (!ra_allocate(g
)) {
2307 DBG("Error allocating registers\n");
2318 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2319 * use scalar ALU instructions, for functional or performance reasons. To do
2320 * this, we just demote vector ALU payloads to scalar. */
2323 component_from_mask(unsigned mask
)
2325 for (int c
= 0; c
< 4; ++c
) {
2326 if (mask
& (3 << (2 * c
)))
2335 is_single_component_mask(unsigned mask
)
2339 for (int c
= 0; c
< 4; ++c
)
2340 if (mask
& (3 << (2 * c
)))
2343 return components
== 1;
2346 /* Create a mask of accessed components from a swizzle to figure out vector
2350 swizzle_to_access_mask(unsigned swizzle
)
2352 unsigned component_mask
= 0;
2354 for (int i
= 0; i
< 4; ++i
) {
2355 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2356 component_mask
|= (1 << c
);
2359 return component_mask
;
2363 vector_to_scalar_source(unsigned u
, bool is_int
)
2365 midgard_vector_alu_src v
;
2366 memcpy(&v
, &u
, sizeof(v
));
2368 /* TODO: Integers */
2370 midgard_scalar_alu_src s
= {
2372 .component
= (v
.swizzle
& 3) << 1
2378 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
2379 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
2383 memcpy(&o
, &s
, sizeof(s
));
2385 return o
& ((1 << 6) - 1);
2388 static midgard_scalar_alu
2389 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2391 bool is_int
= midgard_is_integer_op(v
.op
);
2393 /* The output component is from the mask */
2394 midgard_scalar_alu s
= {
2396 .src1
= vector_to_scalar_source(v
.src1
, is_int
),
2397 .src2
= vector_to_scalar_source(v
.src2
, is_int
),
2400 .output_full
= 1, /* TODO: Half */
2401 .output_component
= component_from_mask(v
.mask
) << 1,
2404 /* Inline constant is passed along rather than trying to extract it
2407 if (ins
->ssa_args
.inline_constant
) {
2409 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2410 imm
|= (lower_11
>> 9) & 3;
2411 imm
|= (lower_11
>> 6) & 4;
2412 imm
|= (lower_11
>> 2) & 0x38;
2413 imm
|= (lower_11
& 63) << 6;
2421 /* Midgard prefetches instruction types, so during emission we need to
2422 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2423 * if this is the second to last and the last is an ALU, then it's also 1... */
2425 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2426 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2428 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2429 bytes_emitted += sizeof(type)
2432 emit_binary_vector_instruction(midgard_instruction
*ains
,
2433 uint16_t *register_words
, int *register_words_count
,
2434 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2435 size_t *bytes_emitted
)
2437 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2438 *bytes_emitted
+= sizeof(midgard_reg_info
);
2440 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2441 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2442 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2445 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2446 * mind that we are a vector architecture and we can write to different
2447 * components simultaneously */
2450 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2452 /* Each instruction reads some registers and writes to a register. See
2453 * where the first writes */
2455 /* Figure out where exactly we wrote to */
2456 int source
= first
->ssa_args
.dest
;
2457 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2459 /* As long as the second doesn't read from the first, we're okay */
2460 if (second
->ssa_args
.src0
== source
) {
2461 if (first
->type
== TAG_ALU_4
) {
2462 /* Figure out which components we just read from */
2464 int q
= second
->alu
.src1
;
2465 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2467 /* Check if there are components in common, and fail if so */
2468 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2475 if (second
->ssa_args
.src1
== source
)
2478 /* Otherwise, it's safe in that regard. Another data hazard is both
2479 * writing to the same place, of course */
2481 if (second
->ssa_args
.dest
== source
) {
2482 /* ...but only if the components overlap */
2483 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2485 if (dest_mask
& source_mask
)
2495 midgard_instruction
**segment
, unsigned segment_size
,
2496 midgard_instruction
*ains
)
2498 for (int s
= 0; s
< segment_size
; ++s
)
2499 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2507 /* Schedules, but does not emit, a single basic block. After scheduling, the
2508 * final tag and size of the block are known, which are necessary for branching
2511 static midgard_bundle
2512 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2514 int instructions_emitted
= 0, instructions_consumed
= -1;
2515 midgard_bundle bundle
= { 0 };
2517 uint8_t tag
= ins
->type
;
2519 /* Default to the instruction's tag */
2522 switch (ins
->type
) {
2524 uint32_t control
= 0;
2525 size_t bytes_emitted
= sizeof(control
);
2527 /* TODO: Constant combining */
2528 int index
= 0, last_unit
= 0;
2530 /* Previous instructions, for the purpose of parallelism */
2531 midgard_instruction
*segment
[4] = {0};
2532 int segment_size
= 0;
2534 instructions_emitted
= -1;
2535 midgard_instruction
*pins
= ins
;
2538 midgard_instruction
*ains
= pins
;
2540 /* Advance instruction pointer */
2542 ains
= mir_next_op(pins
);
2546 /* Out-of-work condition */
2547 if ((struct list_head
*) ains
== &block
->instructions
)
2550 /* Ensure that the chain can continue */
2551 if (ains
->type
!= TAG_ALU_4
) break;
2553 /* If there's already something in the bundle and we
2554 * have weird scheduler constraints, break now */
2555 if (ains
->precede_break
&& index
) break;
2557 /* According to the presentation "The ARM
2558 * Mali-T880 Mobile GPU" from HotChips 27,
2559 * there are two pipeline stages. Branching
2560 * position determined experimentally. Lines
2561 * are executed in parallel:
2564 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2566 * Verify that there are no ordering dependencies here.
2568 * TODO: Allow for parallelism!!!
2571 /* Pick a unit for it if it doesn't force a particular unit */
2573 int unit
= ains
->unit
;
2576 int op
= ains
->alu
.op
;
2577 int units
= alu_opcode_props
[op
].props
;
2579 /* TODO: Promotion of scalars to vectors */
2580 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2583 assert(units
& UNITS_SCALAR
);
2586 if (last_unit
>= UNIT_VADD
) {
2587 if (units
& UNIT_VLUT
)
2592 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2594 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2596 else if (units
& UNIT_VLUT
)
2602 if (last_unit
>= UNIT_VADD
) {
2603 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2605 else if (units
& UNIT_VLUT
)
2610 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2612 else if (units
& UNIT_SMUL
)
2613 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2614 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2621 assert(unit
& units
);
2624 /* Late unit check, this time for encoding (not parallelism) */
2625 if (unit
<= last_unit
) break;
2627 /* Clear the segment */
2628 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2631 if (midgard_has_hazard(segment
, segment_size
, ains
))
2634 /* We're good to go -- emit the instruction */
2637 segment
[segment_size
++] = ains
;
2639 /* Only one set of embedded constants per
2640 * bundle possible; if we have more, we must
2641 * break the chain early, unfortunately */
2643 if (ains
->has_constants
) {
2644 if (bundle
.has_embedded_constants
) {
2645 /* The blend constant needs to be
2646 * alone, since it conflicts with
2647 * everything by definition*/
2649 if (ains
->has_blend_constant
|| bundle
.has_blend_constant
)
2652 /* ...but if there are already
2653 * constants but these are the
2654 * *same* constants, we let it
2657 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2660 bundle
.has_embedded_constants
= true;
2661 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2663 /* If this is a blend shader special constant, track it for patching */
2664 bundle
.has_blend_constant
|= ains
->has_blend_constant
;
2668 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2669 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2670 &bundle
.register_words_count
, bundle
.body_words
,
2671 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2672 } else if (ains
->compact_branch
) {
2673 /* All of r0 has to be written out
2674 * along with the branch writeout.
2677 if (ains
->writeout
) {
2679 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2680 ins
.unit
= UNIT_VMUL
;
2682 control
|= ins
.unit
;
2684 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2685 &bundle
.register_words_count
, bundle
.body_words
,
2686 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2688 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2689 bool written_late
= false;
2690 bool components
[4] = { 0 };
2691 uint16_t register_dep_mask
= 0;
2692 uint16_t written_mask
= 0;
2694 midgard_instruction
*qins
= ins
;
2695 for (int t
= 0; t
< index
; ++t
) {
2696 if (qins
->registers
.out_reg
!= 0) {
2697 /* Mark down writes */
2699 written_mask
|= (1 << qins
->registers
.out_reg
);
2701 /* Mark down the register dependencies for errata check */
2703 if (qins
->registers
.src1_reg
< 16)
2704 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2706 if (qins
->registers
.src2_reg
< 16)
2707 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2709 int mask
= qins
->alu
.mask
;
2711 for (int c
= 0; c
< 4; ++c
)
2712 if (mask
& (0x3 << (2 * c
)))
2713 components
[c
] = true;
2715 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2717 if (qins
->unit
== UNIT_VLUT
)
2718 written_late
= true;
2721 /* Advance instruction pointer */
2722 qins
= mir_next_op(qins
);
2726 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2727 if (register_dep_mask
& written_mask
) {
2728 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2735 /* If even a single component is not written, break it up (conservative check). */
2736 bool breakup
= false;
2738 for (int c
= 0; c
< 4; ++c
)
2745 /* Otherwise, we're free to proceed */
2749 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2750 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2751 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2752 bytes_emitted
+= sizeof(midgard_branch_extended
);
2754 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2755 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2756 bytes_emitted
+= sizeof(ains
->br_compact
);
2759 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2760 bytes_emitted
+= sizeof(midgard_reg_info
);
2762 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2763 bundle
.body_words_count
++;
2764 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2767 /* Defer marking until after writing to allow for break */
2768 control
|= ains
->unit
;
2769 last_unit
= ains
->unit
;
2770 ++instructions_emitted
;
2774 /* Bubble up the number of instructions for skipping */
2775 instructions_consumed
= index
- 1;
2779 /* Pad ALU op to nearest word */
2781 if (bytes_emitted
& 15) {
2782 padding
= 16 - (bytes_emitted
& 15);
2783 bytes_emitted
+= padding
;
2786 /* Constants must always be quadwords */
2787 if (bundle
.has_embedded_constants
)
2788 bytes_emitted
+= 16;
2790 /* Size ALU instruction for tag */
2791 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2792 bundle
.padding
= padding
;
2793 bundle
.control
= bundle
.tag
| control
;
2798 case TAG_LOAD_STORE_4
: {
2799 /* Load store instructions have two words at once. If
2800 * we only have one queued up, we need to NOP pad.
2801 * Otherwise, we store both in succession to save space
2802 * and cycles -- letting them go in parallel -- skip
2803 * the next. The usefulness of this optimisation is
2804 * greatly dependent on the quality of the instruction
2808 midgard_instruction
*next_op
= mir_next_op(ins
);
2810 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2811 /* As the two operate concurrently, make sure
2812 * they are not dependent */
2814 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2815 /* Skip ahead, since it's redundant with the pair */
2816 instructions_consumed
= 1 + (instructions_emitted
++);
2824 /* Texture ops default to single-op-per-bundle scheduling */
2828 /* Copy the instructions into the bundle */
2829 bundle
.instruction_count
= instructions_emitted
+ 1;
2833 midgard_instruction
*uins
= ins
;
2834 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2835 bundle
.instructions
[used_idx
++] = *uins
;
2836 uins
= mir_next_op(uins
);
2839 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2845 quadword_size(int tag
)
2860 case TAG_LOAD_STORE_4
:
2872 /* Schedule a single block by iterating its instruction to create bundles.
2873 * While we go, tally about the bundle sizes to compute the block size. */
2876 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2878 util_dynarray_init(&block
->bundles
, NULL
);
2880 block
->quadword_count
= 0;
2882 mir_foreach_instr_in_block(block
, ins
) {
2884 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2885 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2887 if (bundle
.has_blend_constant
) {
2888 /* TODO: Multiblock? */
2889 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2890 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2894 ins
= mir_next_op(ins
);
2896 block
->quadword_count
+= quadword_size(bundle
.tag
);
2899 block
->is_scheduled
= true;
2903 schedule_program(compiler_context
*ctx
)
2905 /* We run RA prior to scheduling */
2906 struct ra_graph
*g
= allocate_registers(ctx
);
2907 install_registers(ctx
, g
);
2909 mir_foreach_block(ctx
, block
) {
2910 schedule_block(ctx
, block
);
2914 /* After everything is scheduled, emit whole bundles at a time */
2917 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2919 int lookahead
= next_tag
<< 4;
2921 switch (bundle
->tag
) {
2926 /* Actually emit each component */
2927 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2929 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2930 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2932 /* Emit body words based on the instructions bundled */
2933 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2934 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2936 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2937 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2938 } else if (ins
->compact_branch
) {
2939 /* Dummy move, XXX DRY */
2940 if ((i
== 0) && ins
->writeout
) {
2941 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2942 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2945 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2946 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2948 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2952 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2953 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2957 /* Emit padding (all zero) */
2958 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2960 /* Tack on constants */
2962 if (bundle
->has_embedded_constants
) {
2963 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2964 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2965 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2966 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2972 case TAG_LOAD_STORE_4
: {
2973 /* One or two composing instructions */
2975 uint64_t current64
, next64
= LDST_NOP
;
2977 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2979 if (bundle
->instruction_count
== 2)
2980 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2982 midgard_load_store instruction
= {
2983 .type
= bundle
->tag
,
2984 .next_type
= next_tag
,
2989 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2994 case TAG_TEXTURE_4
: {
2995 /* Texture instructions are easy, since there is no
2996 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2998 midgard_instruction
*ins
= &bundle
->instructions
[0];
3000 ins
->texture
.type
= TAG_TEXTURE_4
;
3001 ins
->texture
.next_type
= next_tag
;
3003 ctx
->texture_op_count
--;
3005 if (!ctx
->texture_op_count
) {
3006 ins
->texture
.cont
= 0;
3007 ins
->texture
.last
= 1;
3010 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
3015 DBG("Unknown midgard instruction type\n");
3022 /* ALU instructions can inline or embed constants, which decreases register
3023 * pressure and saves space. */
3025 #define CONDITIONAL_ATTACH(src) { \
3026 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
3029 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
3030 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
3035 inline_alu_constants(compiler_context
*ctx
)
3037 mir_foreach_instr(ctx
, alu
) {
3038 /* Other instructions cannot inline constants */
3039 if (alu
->type
!= TAG_ALU_4
) continue;
3041 /* If there is already a constant here, we can do nothing */
3042 if (alu
->has_constants
) continue;
3044 /* It makes no sense to inline constants on a branch */
3045 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
3047 CONDITIONAL_ATTACH(src0
);
3049 if (!alu
->has_constants
) {
3050 CONDITIONAL_ATTACH(src1
)
3051 } else if (!alu
->inline_constant
) {
3052 /* Corner case: _two_ vec4 constants, for instance with a
3053 * csel. For this case, we can only use a constant
3054 * register for one, we'll have to emit a move for the
3055 * other. Note, if both arguments are constants, then
3056 * necessarily neither argument depends on the value of
3057 * any particular register. As the destination register
3058 * will be wiped, that means we can spill the constant
3059 * to the destination register.
3062 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
3063 unsigned scratch
= alu
->ssa_args
.dest
;
3066 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
3067 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
3069 /* Force a break XXX Defer r31 writes */
3070 ins
.unit
= UNIT_VLUT
;
3072 /* Set the source */
3073 alu
->ssa_args
.src1
= scratch
;
3075 /* Inject us -before- the last instruction which set r31 */
3076 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
3082 /* Midgard supports two types of constants, embedded constants (128-bit) and
3083 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
3084 * constants can be demoted to inline constants, for space savings and
3085 * sometimes a performance boost */
3088 embedded_to_inline_constant(compiler_context
*ctx
)
3090 mir_foreach_instr(ctx
, ins
) {
3091 if (!ins
->has_constants
) continue;
3093 if (ins
->ssa_args
.inline_constant
) continue;
3095 /* Blend constants must not be inlined by definition */
3096 if (ins
->has_blend_constant
) continue;
3098 /* src1 cannot be an inline constant due to encoding
3099 * restrictions. So, if possible we try to flip the arguments
3102 int op
= ins
->alu
.op
;
3104 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3106 /* These ops require an operational change to flip
3107 * their arguments TODO */
3108 case midgard_alu_op_flt
:
3109 case midgard_alu_op_fle
:
3110 case midgard_alu_op_ilt
:
3111 case midgard_alu_op_ile
:
3112 case midgard_alu_op_fcsel
:
3113 case midgard_alu_op_icsel
:
3114 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
3119 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
3120 /* Flip the SSA numbers */
3121 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
3122 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
3124 /* And flip the modifiers */
3128 src_temp
= ins
->alu
.src2
;
3129 ins
->alu
.src2
= ins
->alu
.src1
;
3130 ins
->alu
.src1
= src_temp
;
3134 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3135 /* Extract the source information */
3137 midgard_vector_alu_src
*src
;
3138 int q
= ins
->alu
.src2
;
3139 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
3142 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
3143 int component
= src
->swizzle
& 3;
3145 /* Scale constant appropriately, if we can legally */
3146 uint16_t scaled_constant
= 0;
3148 if (midgard_is_integer_op(op
)) {
3149 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
3150 scaled_constant
= (uint16_t) iconstants
[component
];
3152 /* Constant overflow after resize */
3153 if (scaled_constant
!= iconstants
[component
])
3156 float original
= (float) ins
->constants
[component
];
3157 scaled_constant
= _mesa_float_to_half(original
);
3159 /* Check for loss of precision. If this is
3160 * mediump, we don't care, but for a highp
3161 * shader, we need to pay attention. NIR
3162 * doesn't yet tell us which mode we're in!
3163 * Practically this prevents most constants
3164 * from being inlined, sadly. */
3166 float fp32
= _mesa_half_to_float(scaled_constant
);
3168 if (fp32
!= original
)
3172 /* We don't know how to handle these with a constant */
3174 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
3175 DBG("Bailing inline constant...\n");
3179 /* Make sure that the constant is not itself a
3180 * vector by checking if all accessed values
3181 * (by the swizzle) are the same. */
3183 uint32_t *cons
= (uint32_t *) ins
->constants
;
3184 uint32_t value
= cons
[component
];
3186 bool is_vector
= false;
3187 unsigned mask
= effective_writemask(&ins
->alu
);
3189 for (int c
= 1; c
< 4; ++c
) {
3190 /* We only care if this component is actually used */
3191 if (!(mask
& (1 << c
)))
3194 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3196 if (test
!= value
) {
3205 /* Get rid of the embedded constant */
3206 ins
->has_constants
= false;
3207 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3208 ins
->ssa_args
.inline_constant
= true;
3209 ins
->inline_constant
= scaled_constant
;
3214 /* Map normal SSA sources to other SSA sources / fixed registers (like
3218 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3220 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3223 /* Remove entry in leftovers to avoid a redunant fmov */
3225 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3228 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3230 /* Assign the alias map */
3236 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3237 * texture pipeline */
3240 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3242 bool progress
= false;
3244 mir_foreach_instr_in_block_safe(block
, ins
) {
3245 if (ins
->type
!= TAG_ALU_4
) continue;
3246 if (ins
->compact_branch
) continue;
3248 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3249 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3250 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3252 mir_remove_instruction(ins
);
3260 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
3263 if (!is_int
&& src
.mod
) return true;
3266 for (unsigned c
= 0; c
< 4; ++c
) {
3267 if (!(mask
& (1 << c
))) continue;
3268 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
3275 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
3277 bool progress
= false;
3279 mir_foreach_instr_in_block_safe(block
, ins
) {
3280 if (ins
->type
!= TAG_ALU_4
) continue;
3281 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3283 unsigned from
= ins
->ssa_args
.src1
;
3284 unsigned to
= ins
->ssa_args
.dest
;
3286 /* We only work on pure SSA */
3288 if (to
>= SSA_FIXED_MINIMUM
) continue;
3289 if (from
>= SSA_FIXED_MINIMUM
) continue;
3290 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
3291 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
3293 /* Constant propagation is not handled here, either */
3294 if (ins
->ssa_args
.inline_constant
) continue;
3295 if (ins
->has_constants
) continue;
3297 /* Also, if the move has side effects, we're helpless */
3299 midgard_vector_alu_src src
=
3300 vector_alu_from_unsigned(ins
->alu
.src2
);
3301 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
3302 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
3304 if (mir_nontrivial_mod(src
, is_int
, mask
)) continue;
3305 if (ins
->alu
.outmod
!= midgard_outmod_none
) continue;
3307 mir_foreach_instr_in_block_from(block
, v
, mir_next_op(ins
)) {
3308 if (v
->ssa_args
.src0
== to
) {
3309 v
->ssa_args
.src0
= from
;
3313 if (v
->ssa_args
.src1
== to
&& !v
->ssa_args
.inline_constant
) {
3314 v
->ssa_args
.src1
= from
;
3324 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
3326 bool progress
= false;
3328 mir_foreach_instr_in_block_safe(block
, ins
) {
3329 if (ins
->type
!= TAG_ALU_4
) continue;
3330 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3332 unsigned from
= ins
->ssa_args
.src1
;
3333 unsigned to
= ins
->ssa_args
.dest
;
3335 /* Make sure it's simple enough for us to handle */
3337 if (from
>= SSA_FIXED_MINIMUM
) continue;
3338 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
3339 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
3340 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
3342 bool eliminated
= false;
3344 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
3345 /* The texture registers are not SSA so be careful.
3346 * Conservatively, just stop if we hit a texture op
3347 * (even if it may not write) to where we are */
3349 if (v
->type
!= TAG_ALU_4
)
3352 if (v
->ssa_args
.dest
== from
) {
3353 /* We don't want to track partial writes ... */
3354 if (v
->alu
.mask
== 0xF) {
3355 v
->ssa_args
.dest
= to
;
3364 mir_remove_instruction(ins
);
3366 progress
|= eliminated
;
3372 /* The following passes reorder MIR instructions to enable better scheduling */
3375 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3377 mir_foreach_instr_in_block_safe(block
, ins
) {
3378 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3380 /* We've found a load/store op. Check if next is also load/store. */
3381 midgard_instruction
*next_op
= mir_next_op(ins
);
3382 if (&next_op
->link
!= &block
->instructions
) {
3383 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3384 /* If so, we're done since we're a pair */
3385 ins
= mir_next_op(ins
);
3389 /* Maximum search distance to pair, to avoid register pressure disasters */
3390 int search_distance
= 8;
3392 /* Otherwise, we have an orphaned load/store -- search for another load */
3393 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3394 /* Terminate search if necessary */
3395 if (!(search_distance
--)) break;
3397 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3399 /* Stores cannot be reordered, since they have
3400 * dependencies. For the same reason, indirect
3401 * loads cannot be reordered as their index is
3402 * loaded in r27.w */
3404 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3406 /* It appears the 0x800 bit is set whenever a
3407 * load is direct, unset when it is indirect.
3408 * Skip indirect loads. */
3410 if (!(c
->load_store
.unknown
& 0x800)) continue;
3412 /* We found one! Move it up to pair and remove it from the old location */
3414 mir_insert_instruction_before(ins
, *c
);
3415 mir_remove_instruction(c
);
3423 /* Emit varying stores late */
3426 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3427 /* Iterate in reverse to get the final write, rather than the first */
3429 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3430 /* Check if what we just wrote needs a store */
3431 int idx
= ins
->ssa_args
.dest
;
3432 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3434 if (!varying
) continue;
3438 /* We need to store to the appropriate varying, so emit the
3441 /* TODO: Integrate with special purpose RA (and scheduler?) */
3442 bool high_varying_register
= false;
3444 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3446 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3447 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3449 mir_insert_instruction_before(mir_next_op(ins
), st
);
3450 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3452 /* We no longer need to store this varying */
3453 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3457 /* If there are leftovers after the below pass, emit actual fmov
3458 * instructions for the slow-but-correct path */
3461 emit_leftover_move(compiler_context
*ctx
)
3463 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3464 int base
= ((uintptr_t) leftover
->key
) - 1;
3467 map_ssa_to_alias(ctx
, &mapped
);
3468 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3473 actualise_ssa_to_alias(compiler_context
*ctx
)
3475 mir_foreach_instr(ctx
, ins
) {
3476 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3477 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3480 emit_leftover_move(ctx
);
3484 emit_fragment_epilogue(compiler_context
*ctx
)
3486 /* Special case: writing out constants requires us to include the move
3487 * explicitly now, so shove it into r0 */
3489 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3491 if (constant_value
) {
3492 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3493 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3494 emit_mir_instruction(ctx
, ins
);
3497 /* Perform the actual fragment writeout. We have two writeout/branch
3498 * instructions, forming a loop until writeout is successful as per the
3499 * docs. TODO: gl_FragDepth */
3501 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3502 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3505 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3506 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3507 * with the int8 analogue to the fragment epilogue */
3510 emit_blend_epilogue(compiler_context
*ctx
)
3512 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3514 midgard_instruction scale
= {
3517 .inline_constant
= _mesa_float_to_half(255.0),
3519 .src0
= SSA_FIXED_REGISTER(0),
3520 .src1
= SSA_UNUSED_0
,
3521 .dest
= SSA_FIXED_REGISTER(24),
3522 .inline_constant
= true
3525 .op
= midgard_alu_op_fmul
,
3526 .reg_mode
= midgard_reg_mode_32
,
3527 .dest_override
= midgard_dest_override_lower
,
3529 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3530 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3534 emit_mir_instruction(ctx
, scale
);
3536 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3538 midgard_vector_alu_src alu_src
= blank_alu_src
;
3539 alu_src
.half
= true;
3541 midgard_instruction f2u8
= {
3544 .src0
= SSA_FIXED_REGISTER(24),
3545 .src1
= SSA_UNUSED_0
,
3546 .dest
= SSA_FIXED_REGISTER(0),
3547 .inline_constant
= true
3550 .op
= midgard_alu_op_f2u8
,
3551 .reg_mode
= midgard_reg_mode_16
,
3552 .dest_override
= midgard_dest_override_lower
,
3553 .outmod
= midgard_outmod_pos
,
3555 .src1
= vector_alu_srco_unsigned(alu_src
),
3556 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3560 emit_mir_instruction(ctx
, f2u8
);
3562 /* vmul.imov.quarter r0, r0, r0 */
3564 midgard_instruction imov_8
= {
3567 .src0
= SSA_UNUSED_1
,
3568 .src1
= SSA_FIXED_REGISTER(0),
3569 .dest
= SSA_FIXED_REGISTER(0),
3572 .op
= midgard_alu_op_imov
,
3573 .reg_mode
= midgard_reg_mode_8
,
3574 .dest_override
= midgard_dest_override_none
,
3576 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3577 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3581 /* Emit branch epilogue with the 8-bit move as the source */
3583 emit_mir_instruction(ctx
, imov_8
);
3584 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3586 emit_mir_instruction(ctx
, imov_8
);
3587 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3590 static midgard_block
*
3591 emit_block(compiler_context
*ctx
, nir_block
*block
)
3593 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3594 list_addtail(&this_block
->link
, &ctx
->blocks
);
3596 this_block
->is_scheduled
= false;
3599 ctx
->texture_index
[0] = -1;
3600 ctx
->texture_index
[1] = -1;
3602 /* Add us as a successor to the block we are following */
3603 if (ctx
->current_block
)
3604 midgard_block_add_successor(ctx
->current_block
, this_block
);
3606 /* Set up current block */
3607 list_inithead(&this_block
->instructions
);
3608 ctx
->current_block
= this_block
;
3610 nir_foreach_instr(instr
, block
) {
3611 emit_instr(ctx
, instr
);
3612 ++ctx
->instruction_count
;
3615 inline_alu_constants(ctx
);
3616 embedded_to_inline_constant(ctx
);
3618 /* Perform heavylifting for aliasing */
3619 actualise_ssa_to_alias(ctx
);
3621 midgard_emit_store(ctx
, this_block
);
3622 midgard_pair_load_store(ctx
, this_block
);
3624 /* Append fragment shader epilogue (value writeout) */
3625 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3626 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3628 emit_blend_epilogue(ctx
);
3630 emit_fragment_epilogue(ctx
);
3634 if (block
== nir_start_block(ctx
->func
->impl
))
3635 ctx
->initial_block
= this_block
;
3637 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3638 ctx
->final_block
= this_block
;
3640 /* Allow the next control flow to access us retroactively, for
3642 ctx
->current_block
= this_block
;
3644 /* Document the fallthrough chain */
3645 ctx
->previous_source_block
= this_block
;
3650 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3653 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3655 /* Conditional branches expect the condition in r31.w; emit a move for
3656 * that in the _previous_ block (which is the current block). */
3657 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3659 /* Speculatively emit the branch, but we can't fill it in until later */
3660 EMIT(branch
, true, true);
3661 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3663 /* Emit the two subblocks */
3664 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3666 /* Emit a jump from the end of the then block to the end of the else */
3667 EMIT(branch
, false, false);
3668 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3670 /* Emit second block, and check if it's empty */
3672 int else_idx
= ctx
->block_count
;
3673 int count_in
= ctx
->instruction_count
;
3674 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3675 int after_else_idx
= ctx
->block_count
;
3677 /* Now that we have the subblocks emitted, fix up the branches */
3682 if (ctx
->instruction_count
== count_in
) {
3683 /* The else block is empty, so don't emit an exit jump */
3684 mir_remove_instruction(then_exit
);
3685 then_branch
->branch
.target_block
= after_else_idx
;
3687 then_branch
->branch
.target_block
= else_idx
;
3688 then_exit
->branch
.target_block
= after_else_idx
;
3693 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3695 /* Remember where we are */
3696 midgard_block
*start_block
= ctx
->current_block
;
3698 /* Allocate a loop number, growing the current inner loop depth */
3699 int loop_idx
= ++ctx
->current_loop_depth
;
3701 /* Get index from before the body so we can loop back later */
3702 int start_idx
= ctx
->block_count
;
3704 /* Emit the body itself */
3705 emit_cf_list(ctx
, &nloop
->body
);
3707 /* Branch back to loop back */
3708 struct midgard_instruction br_back
= v_branch(false, false);
3709 br_back
.branch
.target_block
= start_idx
;
3710 emit_mir_instruction(ctx
, br_back
);
3712 /* Mark down that branch in the graph. Note that we're really branching
3713 * to the block *after* we started in. TODO: Why doesn't the branch
3714 * itself have an off-by-one then...? */
3715 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
3717 /* Find the index of the block about to follow us (note: we don't add
3718 * one; blocks are 0-indexed so we get a fencepost problem) */
3719 int break_block_idx
= ctx
->block_count
;
3721 /* Fix up the break statements we emitted to point to the right place,
3722 * now that we can allocate a block number for them */
3724 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3725 mir_foreach_instr_in_block(block
, ins
) {
3726 if (ins
->type
!= TAG_ALU_4
) continue;
3727 if (!ins
->compact_branch
) continue;
3728 if (ins
->prepacked_branch
) continue;
3730 /* We found a branch -- check the type to see if we need to do anything */
3731 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3733 /* It's a break! Check if it's our break */
3734 if (ins
->branch
.target_break
!= loop_idx
) continue;
3736 /* Okay, cool, we're breaking out of this loop.
3737 * Rewrite from a break to a goto */
3739 ins
->branch
.target_type
= TARGET_GOTO
;
3740 ins
->branch
.target_block
= break_block_idx
;
3744 /* Now that we've finished emitting the loop, free up the depth again
3745 * so we play nice with recursion amid nested loops */
3746 --ctx
->current_loop_depth
;
3749 static midgard_block
*
3750 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3752 midgard_block
*start_block
= NULL
;
3754 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3755 switch (node
->type
) {
3756 case nir_cf_node_block
: {
3757 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3760 start_block
= block
;
3765 case nir_cf_node_if
:
3766 emit_if(ctx
, nir_cf_node_as_if(node
));
3769 case nir_cf_node_loop
:
3770 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3773 case nir_cf_node_function
:
3782 /* Due to lookahead, we need to report the first tag executed in the command
3783 * stream and in branch targets. An initial block might be empty, so iterate
3784 * until we find one that 'works' */
3787 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3789 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3791 unsigned first_tag
= 0;
3794 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3796 if (initial_bundle
) {
3797 first_tag
= initial_bundle
->tag
;
3801 /* Initial block is empty, try the next block */
3802 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3803 } while(initial_block
!= NULL
);
3810 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3812 struct util_dynarray
*compiled
= &program
->compiled
;
3814 midgard_debug
= debug_get_option_midgard_debug();
3816 compiler_context ictx
= {
3818 .stage
= nir
->info
.stage
,
3820 .is_blend
= is_blend
,
3821 .blend_constant_offset
= -1,
3823 .alpha_ref
= program
->alpha_ref
3826 compiler_context
*ctx
= &ictx
;
3828 /* TODO: Decide this at runtime */
3829 ctx
->uniform_cutoff
= 8;
3831 /* Assign var locations early, so the epilogue can use them if necessary */
3833 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3834 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3835 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3837 /* Initialize at a global (not block) level hash tables */
3839 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3840 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3841 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3842 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3843 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3844 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3845 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3847 /* Record the varying mapping for the command stream's bookkeeping */
3849 struct exec_list
*varyings
=
3850 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3852 nir_foreach_variable(var
, varyings
) {
3853 unsigned loc
= var
->data
.driver_location
;
3854 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3856 for (int c
= 0; c
< sz
; ++c
) {
3857 program
->varyings
[loc
+ c
] = var
->data
.location
;
3861 /* Lower gl_Position pre-optimisation */
3863 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3864 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3866 NIR_PASS_V(nir
, nir_lower_var_copies
);
3867 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3868 NIR_PASS_V(nir
, nir_split_var_copies
);
3869 NIR_PASS_V(nir
, nir_lower_var_copies
);
3870 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3871 NIR_PASS_V(nir
, nir_lower_var_copies
);
3872 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3874 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3876 /* Optimisation passes */
3880 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3881 nir_print_shader(nir
, stdout
);
3884 /* Assign sysvals and counts, now that we're sure
3885 * (post-optimisation) */
3887 midgard_nir_assign_sysvals(ctx
, nir
);
3889 program
->uniform_count
= nir
->num_uniforms
;
3890 program
->sysval_count
= ctx
->sysval_count
;
3891 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3893 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3894 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3896 nir_foreach_function(func
, nir
) {
3900 list_inithead(&ctx
->blocks
);
3901 ctx
->block_count
= 0;
3904 emit_cf_list(ctx
, &func
->impl
->body
);
3905 emit_block(ctx
, func
->impl
->end_block
);
3907 break; /* TODO: Multi-function shaders */
3910 util_dynarray_init(compiled
, NULL
);
3912 /* MIR-level optimizations */
3914 bool progress
= false;
3919 mir_foreach_block(ctx
, block
) {
3920 progress
|= midgard_opt_copy_prop(ctx
, block
);
3921 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
3922 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
3927 schedule_program(ctx
);
3929 /* Now that all the bundles are scheduled and we can calculate block
3930 * sizes, emit actual branch instructions rather than placeholders */
3932 int br_block_idx
= 0;
3934 mir_foreach_block(ctx
, block
) {
3935 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3936 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3937 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3939 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3941 if (ins
->prepacked_branch
) continue;
3943 /* Parse some basic branch info */
3944 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3945 bool is_conditional
= ins
->branch
.conditional
;
3946 bool is_inverted
= ins
->branch
.invert_conditional
;
3947 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3949 /* Determine the block we're jumping to */
3950 int target_number
= ins
->branch
.target_block
;
3952 /* Report the destination tag. Discards don't need this */
3953 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3955 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3956 int quadword_offset
= 0;
3959 /* Jump to the end of the shader. We
3960 * need to include not only the
3961 * following blocks, but also the
3962 * contents of our current block (since
3963 * discard can come in the middle of
3966 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3968 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3969 quadword_offset
+= quadword_size(bun
->tag
);
3972 mir_foreach_block_from(ctx
, blk
, b
) {
3973 quadword_offset
+= b
->quadword_count
;
3976 } else if (target_number
> br_block_idx
) {
3979 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3980 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3983 quadword_offset
+= blk
->quadword_count
;
3986 /* Jump backwards */
3988 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3989 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3992 quadword_offset
-= blk
->quadword_count
;
3996 /* Unconditional extended branches (far jumps)
3997 * have issues, so we always use a conditional
3998 * branch, setting the condition to always for
3999 * unconditional. For compact unconditional
4000 * branches, cond isn't used so it doesn't
4001 * matter what we pick. */
4003 midgard_condition cond
=
4004 !is_conditional
? midgard_condition_always
:
4005 is_inverted
? midgard_condition_false
:
4006 midgard_condition_true
;
4008 midgard_jmp_writeout_op op
=
4009 is_discard
? midgard_jmp_writeout_op_discard
:
4010 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
4011 midgard_jmp_writeout_op_branch_cond
;
4014 midgard_branch_extended branch
=
4015 midgard_create_branch_extended(
4020 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
4021 } else if (is_conditional
|| is_discard
) {
4022 midgard_branch_cond branch
= {
4024 .dest_tag
= dest_tag
,
4025 .offset
= quadword_offset
,
4029 assert(branch
.offset
== quadword_offset
);
4031 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
4033 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
4035 midgard_branch_uncond branch
= {
4037 .dest_tag
= dest_tag
,
4038 .offset
= quadword_offset
,
4042 assert(branch
.offset
== quadword_offset
);
4044 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
4052 /* Emit flat binary from the instruction arrays. Iterate each block in
4053 * sequence. Save instruction boundaries such that lookahead tags can
4054 * be assigned easily */
4056 /* Cache _all_ bundles in source order for lookahead across failed branches */
4058 int bundle_count
= 0;
4059 mir_foreach_block(ctx
, block
) {
4060 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
4062 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
4064 mir_foreach_block(ctx
, block
) {
4065 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
4066 source_order_bundles
[bundle_idx
++] = bundle
;
4070 int current_bundle
= 0;
4072 mir_foreach_block(ctx
, block
) {
4073 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
4076 if (current_bundle
+ 1 < bundle_count
) {
4077 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
4079 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
4086 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
4090 /* TODO: Free deeper */
4091 //util_dynarray_fini(&block->instructions);
4094 free(source_order_bundles
);
4096 /* Report the very first tag executed */
4097 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
4099 /* Deal with off-by-one related to the fencepost problem */
4100 program
->work_register_count
= ctx
->work_registers
+ 1;
4102 program
->can_discard
= ctx
->can_discard
;
4103 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
4105 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
4107 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
4108 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);