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panfrost/midgard: Refactor schedule/emit pipeline
[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value debug_options[] = {
54 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
56 DEBUG_NAMED_VALUE_END
57 };
58
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
60
61 int midgard_debug = 0;
62
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67
68 static bool
69 midgard_is_branch_unit(unsigned unit)
70 {
71 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
72 }
73
74 static void
75 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
76 {
77 block->successors[block->nr_successors++] = successor;
78 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
79 }
80
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
83
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
91 .ssa_args = { \
92 .rname = ssa, \
93 .uname = -1, \
94 .src1 = -1 \
95 }, \
96 .load_store = { \
97 .op = midgard_op_##name, \
98 .mask = 0xF, \
99 .swizzle = SWIZZLE_XYZW, \
100 .address = address \
101 } \
102 }; \
103 \
104 return i; \
105 }
106
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
109
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
112
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src *src, bool is_int)
115 {
116 if (!src) return blank_alu_src;
117
118 midgard_vector_alu_src alu_src = {
119 .rep_low = 0,
120 .rep_high = 0,
121 .half = 0, /* TODO */
122 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
123 };
124
125 if (is_int) {
126 /* TODO: sign-extend/zero-extend */
127 alu_src.mod = midgard_int_normal;
128
129 /* These should have been lowered away */
130 assert(!(src->abs || src->negate));
131 } else {
132 alu_src.mod = (src->abs << 0) | (src->negate << 1);
133 }
134
135 return alu_src;
136 }
137
138 /* load/store instructions have both 32-bit and 16-bit variants, depending on
139 * whether we are using vectors composed of highp or mediump. At the moment, we
140 * don't support half-floats -- this requires changes in other parts of the
141 * compiler -- therefore the 16-bit versions are commented out. */
142
143 //M_LOAD(ld_attr_16);
144 M_LOAD(ld_attr_32);
145 //M_LOAD(ld_vary_16);
146 M_LOAD(ld_vary_32);
147 //M_LOAD(ld_uniform_16);
148 M_LOAD(ld_uniform_32);
149 M_LOAD(ld_color_buffer_8);
150 //M_STORE(st_vary_16);
151 M_STORE(st_vary_32);
152 M_STORE(st_cubemap_coords);
153
154 static midgard_instruction
155 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
156 {
157 midgard_branch_cond branch = {
158 .op = op,
159 .dest_tag = tag,
160 .offset = offset,
161 .cond = cond
162 };
163
164 uint16_t compact;
165 memcpy(&compact, &branch, sizeof(branch));
166
167 midgard_instruction ins = {
168 .type = TAG_ALU_4,
169 .unit = ALU_ENAB_BR_COMPACT,
170 .prepacked_branch = true,
171 .compact_branch = true,
172 .br_compact = compact
173 };
174
175 if (op == midgard_jmp_writeout_op_writeout)
176 ins.writeout = true;
177
178 return ins;
179 }
180
181 static midgard_instruction
182 v_branch(bool conditional, bool invert)
183 {
184 midgard_instruction ins = {
185 .type = TAG_ALU_4,
186 .unit = ALU_ENAB_BRANCH,
187 .compact_branch = true,
188 .branch = {
189 .conditional = conditional,
190 .invert_conditional = invert
191 }
192 };
193
194 return ins;
195 }
196
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond,
199 midgard_jmp_writeout_op op,
200 unsigned dest_tag,
201 signed quadword_offset)
202 {
203 /* For unclear reasons, the condition code is repeated 8 times */
204 uint16_t duplicated_cond =
205 (cond << 14) |
206 (cond << 12) |
207 (cond << 10) |
208 (cond << 8) |
209 (cond << 6) |
210 (cond << 4) |
211 (cond << 2) |
212 (cond << 0);
213
214 midgard_branch_extended branch = {
215 .op = op,
216 .dest_tag = dest_tag,
217 .offset = quadword_offset,
218 .cond = duplicated_cond
219 };
220
221 return branch;
222 }
223
224 static void
225 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
226 {
227 ins->has_constants = true;
228 memcpy(&ins->constants, constants, 16);
229 }
230
231 static int
232 glsl_type_size(const struct glsl_type *type, bool bindless)
233 {
234 return glsl_count_attribute_slots(type, false);
235 }
236
237 /* Lower fdot2 to a vector multiplication followed by channel addition */
238 static void
239 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
240 {
241 if (alu->op != nir_op_fdot2)
242 return;
243
244 b->cursor = nir_before_instr(&alu->instr);
245
246 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
247 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
248
249 nir_ssa_def *product = nir_fmul(b, src0, src1);
250
251 nir_ssa_def *sum = nir_fadd(b,
252 nir_channel(b, product, 0),
253 nir_channel(b, product, 1));
254
255 /* Replace the fdot2 with this sum */
256 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
257 }
258
259 static int
260 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
261 {
262 switch (instr->intrinsic) {
263 case nir_intrinsic_load_viewport_scale:
264 return PAN_SYSVAL_VIEWPORT_SCALE;
265 case nir_intrinsic_load_viewport_offset:
266 return PAN_SYSVAL_VIEWPORT_OFFSET;
267 default:
268 return -1;
269 }
270 }
271
272 static void
273 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
274 {
275 int sysval = -1;
276
277 if (instr->type == nir_instr_type_intrinsic) {
278 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
279 sysval = midgard_nir_sysval_for_intrinsic(intr);
280 }
281
282 if (sysval < 0)
283 return;
284
285 /* We have a sysval load; check if it's already been assigned */
286
287 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
288 return;
289
290 /* It hasn't -- so assign it now! */
291
292 unsigned id = ctx->sysval_count++;
293 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
294 ctx->sysvals[id] = sysval;
295 }
296
297 static void
298 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
299 {
300 ctx->sysval_count = 0;
301
302 nir_foreach_function(function, shader) {
303 if (!function->impl) continue;
304
305 nir_foreach_block(block, function->impl) {
306 nir_foreach_instr_safe(instr, block) {
307 midgard_nir_assign_sysval_body(ctx, instr);
308 }
309 }
310 }
311 }
312
313 static bool
314 midgard_nir_lower_fdot2(nir_shader *shader)
315 {
316 bool progress = false;
317
318 nir_foreach_function(function, shader) {
319 if (!function->impl) continue;
320
321 nir_builder _b;
322 nir_builder *b = &_b;
323 nir_builder_init(b, function->impl);
324
325 nir_foreach_block(block, function->impl) {
326 nir_foreach_instr_safe(instr, block) {
327 if (instr->type != nir_instr_type_alu) continue;
328
329 nir_alu_instr *alu = nir_instr_as_alu(instr);
330 midgard_nir_lower_fdot2_body(b, alu);
331
332 progress |= true;
333 }
334 }
335
336 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
337
338 }
339
340 return progress;
341 }
342
343 static void
344 optimise_nir(nir_shader *nir)
345 {
346 bool progress;
347 unsigned lower_flrp =
348 (nir->options->lower_flrp16 ? 16 : 0) |
349 (nir->options->lower_flrp32 ? 32 : 0) |
350 (nir->options->lower_flrp64 ? 64 : 0);
351
352 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
353 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
354
355 nir_lower_tex_options lower_tex_options = {
356 .lower_rect = true
357 };
358
359 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
360
361 do {
362 progress = false;
363
364 NIR_PASS(progress, nir, nir_lower_var_copies);
365 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
366
367 NIR_PASS(progress, nir, nir_copy_prop);
368 NIR_PASS(progress, nir, nir_opt_dce);
369 NIR_PASS(progress, nir, nir_opt_dead_cf);
370 NIR_PASS(progress, nir, nir_opt_cse);
371 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
372 NIR_PASS(progress, nir, nir_opt_algebraic);
373 NIR_PASS(progress, nir, nir_opt_constant_folding);
374
375 if (lower_flrp != 0) {
376 bool lower_flrp_progress = false;
377 NIR_PASS(lower_flrp_progress,
378 nir,
379 nir_lower_flrp,
380 lower_flrp,
381 false /* always_precise */,
382 nir->options->lower_ffma);
383 if (lower_flrp_progress) {
384 NIR_PASS(progress, nir,
385 nir_opt_constant_folding);
386 progress = true;
387 }
388
389 /* Nothing should rematerialize any flrps, so we only
390 * need to do this lowering once.
391 */
392 lower_flrp = 0;
393 }
394
395 NIR_PASS(progress, nir, nir_opt_undef);
396 NIR_PASS(progress, nir, nir_opt_loop_unroll,
397 nir_var_shader_in |
398 nir_var_shader_out |
399 nir_var_function_temp);
400
401 /* TODO: Enable vectorize when merged upstream */
402 // NIR_PASS(progress, nir, nir_opt_vectorize);
403 } while (progress);
404
405 /* Must be run at the end to prevent creation of fsin/fcos ops */
406 NIR_PASS(progress, nir, midgard_nir_scale_trig);
407
408 do {
409 progress = false;
410
411 NIR_PASS(progress, nir, nir_opt_dce);
412 NIR_PASS(progress, nir, nir_opt_algebraic);
413 NIR_PASS(progress, nir, nir_opt_constant_folding);
414 NIR_PASS(progress, nir, nir_copy_prop);
415 } while (progress);
416
417 NIR_PASS(progress, nir, nir_opt_algebraic_late);
418
419 /* We implement booleans as 32-bit 0/~0 */
420 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
421
422 /* Now that booleans are lowered, we can run out late opts */
423 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
424
425 /* Lower mods for float ops only. Integer ops don't support modifiers
426 * (saturate doesn't make sense on integers, neg/abs require dedicated
427 * instructions) */
428
429 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
430 NIR_PASS(progress, nir, nir_copy_prop);
431 NIR_PASS(progress, nir, nir_opt_dce);
432
433 /* Take us out of SSA */
434 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
435 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
436
437 /* We are a vector architecture; write combine where possible */
438 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
439 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
440
441 NIR_PASS(progress, nir, nir_opt_dce);
442 }
443
444 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
445 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
446 * r0. See the comments in compiler_context */
447
448 static void
449 alias_ssa(compiler_context *ctx, int dest, int src)
450 {
451 _mesa_hash_table_u64_insert(ctx->ssa_to_alias, dest + 1, (void *) ((uintptr_t) src + 1));
452 _mesa_set_add(ctx->leftover_ssa_to_alias, (void *) (uintptr_t) (dest + 1));
453 }
454
455 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
456
457 static void
458 unalias_ssa(compiler_context *ctx, int dest)
459 {
460 _mesa_hash_table_u64_remove(ctx->ssa_to_alias, dest + 1);
461 /* TODO: Remove from leftover or no? */
462 }
463
464 /* Do not actually emit a load; instead, cache the constant for inlining */
465
466 static void
467 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
468 {
469 nir_ssa_def def = instr->def;
470
471 float *v = rzalloc_array(NULL, float, 4);
472 nir_const_load_to_arr(v, instr, f32);
473 _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
474 }
475
476 static unsigned
477 nir_src_index(compiler_context *ctx, nir_src *src)
478 {
479 if (src->is_ssa)
480 return src->ssa->index;
481 else {
482 assert(!src->reg.indirect);
483 return ctx->func->impl->ssa_alloc + src->reg.reg->index;
484 }
485 }
486
487 static unsigned
488 nir_dest_index(compiler_context *ctx, nir_dest *dst)
489 {
490 if (dst->is_ssa)
491 return dst->ssa.index;
492 else {
493 assert(!dst->reg.indirect);
494 return ctx->func->impl->ssa_alloc + dst->reg.reg->index;
495 }
496 }
497
498 static unsigned
499 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
500 {
501 return nir_src_index(ctx, &src->src);
502 }
503
504 static bool
505 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
506 {
507 unsigned comp = src->swizzle[0];
508
509 for (unsigned c = 1; c < nr_components; ++c) {
510 if (src->swizzle[c] != comp)
511 return true;
512 }
513
514 return false;
515 }
516
517 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
518 * output of a conditional test) into that register */
519
520 static void
521 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
522 {
523 int condition = nir_src_index(ctx, src);
524
525 /* Source to swizzle the desired component into w */
526
527 const midgard_vector_alu_src alu_src = {
528 .swizzle = SWIZZLE(component, component, component, component),
529 };
530
531 /* There is no boolean move instruction. Instead, we simulate a move by
532 * ANDing the condition with itself to get it into r31.w */
533
534 midgard_instruction ins = {
535 .type = TAG_ALU_4,
536
537 /* We need to set the conditional as close as possible */
538 .precede_break = true,
539 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
540
541 .ssa_args = {
542
543 .src0 = condition,
544 .src1 = condition,
545 .dest = SSA_FIXED_REGISTER(31),
546 },
547 .alu = {
548 .op = midgard_alu_op_iand,
549 .outmod = midgard_outmod_int,
550 .reg_mode = midgard_reg_mode_32,
551 .dest_override = midgard_dest_override_none,
552 .mask = (0x3 << 6), /* w */
553 .src1 = vector_alu_srco_unsigned(alu_src),
554 .src2 = vector_alu_srco_unsigned(alu_src)
555 },
556 };
557
558 emit_mir_instruction(ctx, ins);
559 }
560
561 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
562 * r31 instead */
563
564 static void
565 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
566 {
567 int condition = nir_src_index(ctx, &src->src);
568
569 /* Source to swizzle the desired component into w */
570
571 const midgard_vector_alu_src alu_src = {
572 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
573 };
574
575 /* There is no boolean move instruction. Instead, we simulate a move by
576 * ANDing the condition with itself to get it into r31.w */
577
578 midgard_instruction ins = {
579 .type = TAG_ALU_4,
580 .precede_break = true,
581 .ssa_args = {
582 .src0 = condition,
583 .src1 = condition,
584 .dest = SSA_FIXED_REGISTER(31),
585 },
586 .alu = {
587 .op = midgard_alu_op_iand,
588 .outmod = midgard_outmod_int,
589 .reg_mode = midgard_reg_mode_32,
590 .dest_override = midgard_dest_override_none,
591 .mask = expand_writemask((1 << nr_comp) - 1),
592 .src1 = vector_alu_srco_unsigned(alu_src),
593 .src2 = vector_alu_srco_unsigned(alu_src)
594 },
595 };
596
597 emit_mir_instruction(ctx, ins);
598 }
599
600
601
602 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
603 * pinning to eliminate this move in all known cases */
604
605 static void
606 emit_indirect_offset(compiler_context *ctx, nir_src *src)
607 {
608 int offset = nir_src_index(ctx, src);
609
610 midgard_instruction ins = {
611 .type = TAG_ALU_4,
612 .ssa_args = {
613 .src0 = SSA_UNUSED_1,
614 .src1 = offset,
615 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
616 },
617 .alu = {
618 .op = midgard_alu_op_imov,
619 .outmod = midgard_outmod_int,
620 .reg_mode = midgard_reg_mode_32,
621 .dest_override = midgard_dest_override_none,
622 .mask = (0x3 << 6), /* w */
623 .src1 = vector_alu_srco_unsigned(zero_alu_src),
624 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
625 },
626 };
627
628 emit_mir_instruction(ctx, ins);
629 }
630
631 #define ALU_CASE(nir, _op) \
632 case nir_op_##nir: \
633 op = midgard_alu_op_##_op; \
634 break;
635 static bool
636 nir_is_fzero_constant(nir_src src)
637 {
638 if (!nir_src_is_const(src))
639 return false;
640
641 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
642 if (nir_src_comp_as_float(src, c) != 0.0)
643 return false;
644 }
645
646 return true;
647 }
648
649 static void
650 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
651 {
652 bool is_ssa = instr->dest.dest.is_ssa;
653
654 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
655 unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components;
656 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
657
658 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
659 * supported. A few do not and are commented for now. Also, there are a
660 * number of NIR ops which Midgard does not support and need to be
661 * lowered, also TODO. This switch block emits the opcode and calling
662 * convention of the Midgard instruction; actual packing is done in
663 * emit_alu below */
664
665 unsigned op;
666
667 switch (instr->op) {
668 ALU_CASE(fadd, fadd);
669 ALU_CASE(fmul, fmul);
670 ALU_CASE(fmin, fmin);
671 ALU_CASE(fmax, fmax);
672 ALU_CASE(imin, imin);
673 ALU_CASE(imax, imax);
674 ALU_CASE(umin, umin);
675 ALU_CASE(umax, umax);
676 ALU_CASE(ffloor, ffloor);
677 ALU_CASE(fround_even, froundeven);
678 ALU_CASE(ftrunc, ftrunc);
679 ALU_CASE(fceil, fceil);
680 ALU_CASE(fdot3, fdot3);
681 ALU_CASE(fdot4, fdot4);
682 ALU_CASE(iadd, iadd);
683 ALU_CASE(isub, isub);
684 ALU_CASE(imul, imul);
685 ALU_CASE(iabs, iabs);
686 ALU_CASE(mov, imov);
687
688 ALU_CASE(feq32, feq);
689 ALU_CASE(fne32, fne);
690 ALU_CASE(flt32, flt);
691 ALU_CASE(ieq32, ieq);
692 ALU_CASE(ine32, ine);
693 ALU_CASE(ilt32, ilt);
694 ALU_CASE(ult32, ult);
695
696 /* We don't have a native b2f32 instruction. Instead, like many
697 * GPUs, we exploit booleans as 0/~0 for false/true, and
698 * correspondingly AND
699 * by 1.0 to do the type conversion. For the moment, prime us
700 * to emit:
701 *
702 * iand [whatever], #0
703 *
704 * At the end of emit_alu (as MIR), we'll fix-up the constant
705 */
706
707 ALU_CASE(b2f32, iand);
708 ALU_CASE(b2i32, iand);
709
710 /* Likewise, we don't have a dedicated f2b32 instruction, but
711 * we can do a "not equal to 0.0" test. */
712
713 ALU_CASE(f2b32, fne);
714 ALU_CASE(i2b32, ine);
715
716 ALU_CASE(frcp, frcp);
717 ALU_CASE(frsq, frsqrt);
718 ALU_CASE(fsqrt, fsqrt);
719 ALU_CASE(fexp2, fexp2);
720 ALU_CASE(flog2, flog2);
721
722 ALU_CASE(f2i32, f2i);
723 ALU_CASE(f2u32, f2u);
724 ALU_CASE(i2f32, i2f);
725 ALU_CASE(u2f32, u2f);
726
727 ALU_CASE(fsin, fsin);
728 ALU_CASE(fcos, fcos);
729
730 ALU_CASE(iand, iand);
731 ALU_CASE(ior, ior);
732 ALU_CASE(ixor, ixor);
733 ALU_CASE(inot, inand);
734 ALU_CASE(ishl, ishl);
735 ALU_CASE(ishr, iasr);
736 ALU_CASE(ushr, ilsr);
737
738 ALU_CASE(b32all_fequal2, fball_eq);
739 ALU_CASE(b32all_fequal3, fball_eq);
740 ALU_CASE(b32all_fequal4, fball_eq);
741
742 ALU_CASE(b32any_fnequal2, fbany_neq);
743 ALU_CASE(b32any_fnequal3, fbany_neq);
744 ALU_CASE(b32any_fnequal4, fbany_neq);
745
746 ALU_CASE(b32all_iequal2, iball_eq);
747 ALU_CASE(b32all_iequal3, iball_eq);
748 ALU_CASE(b32all_iequal4, iball_eq);
749
750 ALU_CASE(b32any_inequal2, ibany_neq);
751 ALU_CASE(b32any_inequal3, ibany_neq);
752 ALU_CASE(b32any_inequal4, ibany_neq);
753
754 /* Source mods will be shoved in later */
755 ALU_CASE(fabs, fmov);
756 ALU_CASE(fneg, fmov);
757 ALU_CASE(fsat, fmov);
758
759 /* For greater-or-equal, we lower to less-or-equal and flip the
760 * arguments */
761
762 case nir_op_fge:
763 case nir_op_fge32:
764 case nir_op_ige32:
765 case nir_op_uge32: {
766 op =
767 instr->op == nir_op_fge ? midgard_alu_op_fle :
768 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
769 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
770 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
771 0;
772
773 /* Swap via temporary */
774 nir_alu_src temp = instr->src[1];
775 instr->src[1] = instr->src[0];
776 instr->src[0] = temp;
777
778 break;
779 }
780
781 case nir_op_b32csel: {
782 /* Midgard features both fcsel and icsel, depending on
783 * the type of the arguments/output. However, as long
784 * as we're careful we can _always_ use icsel and
785 * _never_ need fcsel, since the latter does additional
786 * floating-point-specific processing whereas the
787 * former just moves bits on the wire. It's not obvious
788 * why these are separate opcodes, save for the ability
789 * to do things like sat/pos/abs/neg for free */
790
791 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
792 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
793
794 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
795 nr_inputs = 2;
796
797 /* Emit the condition into r31 */
798
799 if (mixed)
800 emit_condition_mixed(ctx, &instr->src[0], nr_components);
801 else
802 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
803
804 /* The condition is the first argument; move the other
805 * arguments up one to be a binary instruction for
806 * Midgard */
807
808 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
809 break;
810 }
811
812 default:
813 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
814 assert(0);
815 return;
816 }
817
818 /* Midgard can perform certain modifiers on output of an ALU op */
819 midgard_outmod outmod =
820 midgard_is_integer_out_op(op) ? midgard_outmod_int :
821 instr->dest.saturate ? midgard_outmod_sat : midgard_outmod_none;
822
823 if (instr->op == nir_op_fsat)
824 outmod = midgard_outmod_sat;
825
826 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
827
828 if (instr->op == nir_op_fmax) {
829 if (nir_is_fzero_constant(instr->src[0].src)) {
830 op = midgard_alu_op_fmov;
831 nr_inputs = 1;
832 outmod = midgard_outmod_pos;
833 instr->src[0] = instr->src[1];
834 } else if (nir_is_fzero_constant(instr->src[1].src)) {
835 op = midgard_alu_op_fmov;
836 nr_inputs = 1;
837 outmod = midgard_outmod_pos;
838 }
839 }
840
841 /* Fetch unit, quirks, etc information */
842 unsigned opcode_props = alu_opcode_props[op].props;
843 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
844
845 /* src0 will always exist afaik, but src1 will not for 1-argument
846 * instructions. The latter can only be fetched if the instruction
847 * needs it, or else we may segfault. */
848
849 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
850 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
851
852 /* Rather than use the instruction generation helpers, we do it
853 * ourselves here to avoid the mess */
854
855 midgard_instruction ins = {
856 .type = TAG_ALU_4,
857 .ssa_args = {
858 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
859 .src1 = quirk_flipped_r24 ? src0 : src1,
860 .dest = dest,
861 }
862 };
863
864 nir_alu_src *nirmods[2] = { NULL };
865
866 if (nr_inputs == 2) {
867 nirmods[0] = &instr->src[0];
868 nirmods[1] = &instr->src[1];
869 } else if (nr_inputs == 1) {
870 nirmods[quirk_flipped_r24] = &instr->src[0];
871 } else {
872 assert(0);
873 }
874
875 /* These were lowered to a move, so apply the corresponding mod */
876
877 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
878 nir_alu_src *s = nirmods[quirk_flipped_r24];
879
880 if (instr->op == nir_op_fneg)
881 s->negate = !s->negate;
882
883 if (instr->op == nir_op_fabs)
884 s->abs = !s->abs;
885 }
886
887 bool is_int = midgard_is_integer_op(op);
888
889 midgard_vector_alu alu = {
890 .op = op,
891 .reg_mode = midgard_reg_mode_32,
892 .dest_override = midgard_dest_override_none,
893 .outmod = outmod,
894
895 /* Writemask only valid for non-SSA NIR */
896 .mask = expand_writemask((1 << nr_components) - 1),
897
898 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int)),
899 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int)),
900 };
901
902 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
903
904 if (!is_ssa)
905 alu.mask &= expand_writemask(instr->dest.write_mask);
906
907 ins.alu = alu;
908
909 /* Late fixup for emulated instructions */
910
911 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
912 /* Presently, our second argument is an inline #0 constant.
913 * Switch over to an embedded 1.0 constant (that can't fit
914 * inline, since we're 32-bit, not 16-bit like the inline
915 * constants) */
916
917 ins.ssa_args.inline_constant = false;
918 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
919 ins.has_constants = true;
920
921 if (instr->op == nir_op_b2f32) {
922 ins.constants[0] = 1.0f;
923 } else {
924 /* Type pun it into place */
925 uint32_t one = 0x1;
926 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
927 }
928
929 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
930 } else if (instr->op == nir_op_f2b32 || instr->op == nir_op_i2b32) {
931 ins.ssa_args.inline_constant = false;
932 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
933 ins.has_constants = true;
934 ins.constants[0] = 0.0f;
935 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
936 } else if (instr->op == nir_op_inot) {
937 /* ~b = ~(b & b), so duplicate the source */
938 ins.ssa_args.src1 = ins.ssa_args.src0;
939 ins.alu.src2 = ins.alu.src1;
940 }
941
942 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
943 /* To avoid duplicating the lookup tables (probably), true LUT
944 * instructions can only operate as if they were scalars. Lower
945 * them here by changing the component. */
946
947 uint8_t original_swizzle[4];
948 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
949
950 for (int i = 0; i < nr_components; ++i) {
951 ins.alu.mask = (0x3) << (2 * i); /* Mask the associated component */
952
953 for (int j = 0; j < 4; ++j)
954 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
955
956 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int));
957 emit_mir_instruction(ctx, ins);
958 }
959 } else {
960 emit_mir_instruction(ctx, ins);
961 }
962 }
963
964 #undef ALU_CASE
965
966 static void
967 emit_uniform_read(compiler_context *ctx, unsigned dest, unsigned offset, nir_src *indirect_offset)
968 {
969 /* TODO: half-floats */
970
971 if (!indirect_offset && offset < ctx->uniform_cutoff) {
972 /* Fast path: For the first 16 uniforms, direct accesses are
973 * 0-cycle, since they're just a register fetch in the usual
974 * case. So, we alias the registers while we're still in
975 * SSA-space */
976
977 int reg_slot = 23 - offset;
978 alias_ssa(ctx, dest, SSA_FIXED_REGISTER(reg_slot));
979 } else {
980 /* Otherwise, read from the 'special' UBO to access
981 * higher-indexed uniforms, at a performance cost. More
982 * generally, we're emitting a UBO read instruction. */
983
984 midgard_instruction ins = m_ld_uniform_32(dest, offset);
985
986 /* TODO: Don't split */
987 ins.load_store.varying_parameters = (offset & 7) << 7;
988 ins.load_store.address = offset >> 3;
989
990 if (indirect_offset) {
991 emit_indirect_offset(ctx, indirect_offset);
992 ins.load_store.unknown = 0x8700; /* xxx: what is this? */
993 } else {
994 ins.load_store.unknown = 0x1E00; /* xxx: what is this? */
995 }
996
997 emit_mir_instruction(ctx, ins);
998 }
999 }
1000
1001 static void
1002 emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
1003 {
1004 /* First, pull out the destination */
1005 unsigned dest = nir_dest_index(ctx, &instr->dest);
1006
1007 /* Now, figure out which uniform this is */
1008 int sysval = midgard_nir_sysval_for_intrinsic(instr);
1009 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1010
1011 /* Sysvals are prefix uniforms */
1012 unsigned uniform = ((uintptr_t) val) - 1;
1013
1014 /* Emit the read itself -- this is never indirect */
1015 emit_uniform_read(ctx, dest, uniform, NULL);
1016 }
1017
1018 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1019 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1020 * generations have faster vectorized reads. This operation is for blend
1021 * shaders in particular; reading the tilebuffer from the fragment shader
1022 * remains an open problem. */
1023
1024 static void
1025 emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
1026 {
1027 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1028 ins.load_store.swizzle = 0; /* xxxx */
1029
1030 /* Read each component sequentially */
1031
1032 for (unsigned c = 0; c < 4; ++c) {
1033 ins.load_store.mask = (1 << c);
1034 ins.load_store.unknown = c;
1035 emit_mir_instruction(ctx, ins);
1036 }
1037
1038 /* vadd.u2f hr2, zext(hr2), #0 */
1039
1040 midgard_vector_alu_src alu_src = blank_alu_src;
1041 alu_src.mod = midgard_int_zero_extend;
1042 alu_src.half = true;
1043
1044 midgard_instruction u2f = {
1045 .type = TAG_ALU_4,
1046 .ssa_args = {
1047 .src0 = reg,
1048 .src1 = SSA_UNUSED_0,
1049 .dest = reg,
1050 .inline_constant = true
1051 },
1052 .alu = {
1053 .op = midgard_alu_op_u2f,
1054 .reg_mode = midgard_reg_mode_16,
1055 .dest_override = midgard_dest_override_none,
1056 .mask = 0xF,
1057 .src1 = vector_alu_srco_unsigned(alu_src),
1058 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1059 }
1060 };
1061
1062 emit_mir_instruction(ctx, u2f);
1063
1064 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1065
1066 alu_src.mod = 0;
1067
1068 midgard_instruction fmul = {
1069 .type = TAG_ALU_4,
1070 .inline_constant = _mesa_float_to_half(1.0 / 255.0),
1071 .ssa_args = {
1072 .src0 = reg,
1073 .dest = reg,
1074 .src1 = SSA_UNUSED_0,
1075 .inline_constant = true
1076 },
1077 .alu = {
1078 .op = midgard_alu_op_fmul,
1079 .reg_mode = midgard_reg_mode_32,
1080 .dest_override = midgard_dest_override_none,
1081 .outmod = midgard_outmod_sat,
1082 .mask = 0xFF,
1083 .src1 = vector_alu_srco_unsigned(alu_src),
1084 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1085 }
1086 };
1087
1088 emit_mir_instruction(ctx, fmul);
1089 }
1090
1091 static void
1092 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1093 {
1094 unsigned offset, reg;
1095
1096 switch (instr->intrinsic) {
1097 case nir_intrinsic_discard_if:
1098 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1099
1100 /* fallthrough */
1101
1102 case nir_intrinsic_discard: {
1103 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1104 struct midgard_instruction discard = v_branch(conditional, false);
1105 discard.branch.target_type = TARGET_DISCARD;
1106 emit_mir_instruction(ctx, discard);
1107
1108 ctx->can_discard = true;
1109 break;
1110 }
1111
1112 case nir_intrinsic_load_uniform:
1113 case nir_intrinsic_load_input:
1114 offset = nir_intrinsic_base(instr);
1115
1116 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1117 bool direct = nir_src_is_const(instr->src[0]);
1118
1119 if (direct) {
1120 offset += nir_src_as_uint(instr->src[0]);
1121 }
1122
1123 reg = nir_dest_index(ctx, &instr->dest);
1124
1125 if (instr->intrinsic == nir_intrinsic_load_uniform && !ctx->is_blend) {
1126 emit_uniform_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL);
1127 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1128 /* XXX: Half-floats? */
1129 /* TODO: swizzle, mask */
1130
1131 midgard_instruction ins = m_ld_vary_32(reg, offset);
1132 ins.load_store.mask = (1 << nr_comp) - 1;
1133
1134 midgard_varying_parameter p = {
1135 .is_varying = 1,
1136 .interpolation = midgard_interp_default,
1137 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1138 };
1139
1140 unsigned u;
1141 memcpy(&u, &p, sizeof(p));
1142 ins.load_store.varying_parameters = u;
1143
1144 if (direct) {
1145 /* We have the offset totally ready */
1146 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1147 } else {
1148 /* We have it partially ready, but we need to
1149 * add in the dynamic index, moved to r27.w */
1150 emit_indirect_offset(ctx, &instr->src[0]);
1151 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1152 }
1153
1154 emit_mir_instruction(ctx, ins);
1155 } else if (ctx->is_blend) {
1156 /* For blend shaders, load the input color, which is
1157 * preloaded to r0 */
1158
1159 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1160 emit_mir_instruction(ctx, move);
1161 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1162 midgard_instruction ins = m_ld_attr_32(reg, offset);
1163 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1164 ins.load_store.mask = (1 << nr_comp) - 1;
1165 emit_mir_instruction(ctx, ins);
1166 } else {
1167 DBG("Unknown load\n");
1168 assert(0);
1169 }
1170
1171 break;
1172
1173 case nir_intrinsic_load_output:
1174 assert(nir_src_is_const(instr->src[0]));
1175 reg = nir_dest_index(ctx, &instr->dest);
1176
1177 if (ctx->is_blend) {
1178 /* TODO: MRT */
1179 emit_fb_read_blend_scalar(ctx, reg);
1180 } else {
1181 DBG("Unknown output load\n");
1182 assert(0);
1183 }
1184
1185 break;
1186
1187 case nir_intrinsic_load_blend_const_color_rgba: {
1188 assert(ctx->is_blend);
1189 reg = nir_dest_index(ctx, &instr->dest);
1190
1191 /* Blend constants are embedded directly in the shader and
1192 * patched in, so we use some magic routing */
1193
1194 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1195 ins.has_constants = true;
1196 ins.has_blend_constant = true;
1197 emit_mir_instruction(ctx, ins);
1198 break;
1199 }
1200
1201 case nir_intrinsic_store_output:
1202 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1203
1204 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1205
1206 reg = nir_src_index(ctx, &instr->src[0]);
1207
1208 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1209 /* gl_FragColor is not emitted with load/store
1210 * instructions. Instead, it gets plonked into
1211 * r0 at the end of the shader and we do the
1212 * framebuffer writeout dance. TODO: Defer
1213 * writes */
1214
1215 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1216 emit_mir_instruction(ctx, move);
1217
1218 /* Save the index we're writing to for later reference
1219 * in the epilogue */
1220
1221 ctx->fragment_output = reg;
1222 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1223 /* Varyings are written into one of two special
1224 * varying register, r26 or r27. The register itself is selected as the register
1225 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1226 *
1227 * Normally emitting fmov's is frowned upon,
1228 * but due to unique constraints of
1229 * REGISTER_VARYING, fmov emission + a
1230 * dedicated cleanup pass is the only way to
1231 * guarantee correctness when considering some
1232 * (common) edge cases XXX: FIXME */
1233
1234 /* If this varying corresponds to a constant (why?!),
1235 * emit that now since it won't get picked up by
1236 * hoisting (since there is no corresponding move
1237 * emitted otherwise) */
1238
1239 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, reg + 1);
1240
1241 if (constant_value) {
1242 /* Special case: emit the varying write
1243 * directly to r26 (looks funny in asm but it's
1244 * fine) and emit the store _now_. Possibly
1245 * slightly slower, but this is a really stupid
1246 * special case anyway (why on earth would you
1247 * have a constant varying? Your own fault for
1248 * slightly worse perf :P) */
1249
1250 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(26));
1251 attach_constants(ctx, &ins, constant_value, reg + 1);
1252 emit_mir_instruction(ctx, ins);
1253
1254 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset);
1255 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1256 emit_mir_instruction(ctx, st);
1257 } else {
1258 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1259
1260 _mesa_hash_table_u64_insert(ctx->ssa_varyings, reg + 1, (void *) ((uintptr_t) (offset + 1)));
1261 }
1262 } else {
1263 DBG("Unknown store\n");
1264 assert(0);
1265 }
1266
1267 break;
1268
1269 case nir_intrinsic_load_alpha_ref_float:
1270 assert(instr->dest.is_ssa);
1271
1272 float ref_value = ctx->alpha_ref;
1273
1274 float *v = ralloc_array(NULL, float, 4);
1275 memcpy(v, &ref_value, sizeof(float));
1276 _mesa_hash_table_u64_insert(ctx->ssa_constants, instr->dest.ssa.index + 1, v);
1277 break;
1278
1279 case nir_intrinsic_load_viewport_scale:
1280 case nir_intrinsic_load_viewport_offset:
1281 emit_sysval_read(ctx, instr);
1282 break;
1283
1284 default:
1285 printf ("Unhandled intrinsic\n");
1286 assert(0);
1287 break;
1288 }
1289 }
1290
1291 static unsigned
1292 midgard_tex_format(enum glsl_sampler_dim dim)
1293 {
1294 switch (dim) {
1295 case GLSL_SAMPLER_DIM_2D:
1296 case GLSL_SAMPLER_DIM_EXTERNAL:
1297 return TEXTURE_2D;
1298
1299 case GLSL_SAMPLER_DIM_3D:
1300 return TEXTURE_3D;
1301
1302 case GLSL_SAMPLER_DIM_CUBE:
1303 return TEXTURE_CUBE;
1304
1305 default:
1306 DBG("Unknown sampler dim type\n");
1307 assert(0);
1308 return 0;
1309 }
1310 }
1311
1312 static void
1313 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1314 {
1315 /* TODO */
1316 //assert (!instr->sampler);
1317 //assert (!instr->texture_array_size);
1318 assert (instr->op == nir_texop_tex);
1319
1320 /* Allocate registers via a round robin scheme to alternate between the two registers */
1321 int reg = ctx->texture_op_count & 1;
1322 int in_reg = reg, out_reg = reg;
1323
1324 /* Make room for the reg */
1325
1326 if (ctx->texture_index[reg] > -1)
1327 unalias_ssa(ctx, ctx->texture_index[reg]);
1328
1329 int texture_index = instr->texture_index;
1330 int sampler_index = texture_index;
1331
1332 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1333 switch (instr->src[i].src_type) {
1334 case nir_tex_src_coord: {
1335 int index = nir_src_index(ctx, &instr->src[i].src);
1336
1337 midgard_vector_alu_src alu_src = blank_alu_src;
1338
1339 int reg = SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + in_reg);
1340
1341 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1342 /* For cubemaps, we need to load coords into
1343 * special r27, and then use a special ld/st op
1344 * to copy into the texture register */
1345
1346 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X);
1347
1348 midgard_instruction move = v_fmov(index, alu_src, SSA_FIXED_REGISTER(27));
1349 emit_mir_instruction(ctx, move);
1350
1351 midgard_instruction st = m_st_cubemap_coords(reg, 0);
1352 st.load_store.unknown = 0x24; /* XXX: What is this? */
1353 st.load_store.mask = 0x3; /* xy? */
1354 st.load_store.swizzle = alu_src.swizzle;
1355 emit_mir_instruction(ctx, st);
1356
1357 } else {
1358 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X);
1359
1360 midgard_instruction ins = v_fmov(index, alu_src, reg);
1361 emit_mir_instruction(ctx, ins);
1362 }
1363
1364 break;
1365 }
1366
1367 default: {
1368 DBG("Unknown source type\n");
1369 //assert(0);
1370 break;
1371 }
1372 }
1373 }
1374
1375 /* No helper to build texture words -- we do it all here */
1376 midgard_instruction ins = {
1377 .type = TAG_TEXTURE_4,
1378 .texture = {
1379 .op = TEXTURE_OP_NORMAL,
1380 .format = midgard_tex_format(instr->sampler_dim),
1381 .texture_handle = texture_index,
1382 .sampler_handle = sampler_index,
1383
1384 /* TODO: Don't force xyzw */
1385 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
1386 .mask = 0xF,
1387
1388 /* TODO: half */
1389 //.in_reg_full = 1,
1390 .out_full = 1,
1391
1392 .filter = 1,
1393
1394 /* Always 1 */
1395 .unknown7 = 1,
1396
1397 /* Assume we can continue; hint it out later */
1398 .cont = 1,
1399 }
1400 };
1401
1402 /* Set registers to read and write from the same place */
1403 ins.texture.in_reg_select = in_reg;
1404 ins.texture.out_reg_select = out_reg;
1405
1406 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1407 if (instr->sampler_dim == GLSL_SAMPLER_DIM_3D) {
1408 ins.texture.in_reg_swizzle_right = COMPONENT_X;
1409 ins.texture.in_reg_swizzle_left = COMPONENT_Y;
1410 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1411 } else {
1412 ins.texture.in_reg_swizzle_left = COMPONENT_X;
1413 ins.texture.in_reg_swizzle_right = COMPONENT_Y;
1414 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1415 }
1416
1417 emit_mir_instruction(ctx, ins);
1418
1419 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1420
1421 int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest);
1422 alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg));
1423 ctx->texture_index[reg] = o_index;
1424
1425 midgard_instruction ins2 = v_fmov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index);
1426 emit_mir_instruction(ctx, ins2);
1427
1428 /* Used for .cont and .last hinting */
1429 ctx->texture_op_count++;
1430 }
1431
1432 static void
1433 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1434 {
1435 switch (instr->type) {
1436 case nir_jump_break: {
1437 /* Emit a branch out of the loop */
1438 struct midgard_instruction br = v_branch(false, false);
1439 br.branch.target_type = TARGET_BREAK;
1440 br.branch.target_break = ctx->current_loop_depth;
1441 emit_mir_instruction(ctx, br);
1442
1443 DBG("break..\n");
1444 break;
1445 }
1446
1447 default:
1448 DBG("Unknown jump type %d\n", instr->type);
1449 break;
1450 }
1451 }
1452
1453 static void
1454 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1455 {
1456 switch (instr->type) {
1457 case nir_instr_type_load_const:
1458 emit_load_const(ctx, nir_instr_as_load_const(instr));
1459 break;
1460
1461 case nir_instr_type_intrinsic:
1462 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1463 break;
1464
1465 case nir_instr_type_alu:
1466 emit_alu(ctx, nir_instr_as_alu(instr));
1467 break;
1468
1469 case nir_instr_type_tex:
1470 emit_tex(ctx, nir_instr_as_tex(instr));
1471 break;
1472
1473 case nir_instr_type_jump:
1474 emit_jump(ctx, nir_instr_as_jump(instr));
1475 break;
1476
1477 case nir_instr_type_ssa_undef:
1478 /* Spurious */
1479 break;
1480
1481 default:
1482 DBG("Unhandled instruction type\n");
1483 break;
1484 }
1485 }
1486
1487 /* Midgard prefetches instruction types, so during emission we need to
1488 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1489 * if this is the second to last and the last is an ALU, then it's also 1... */
1490
1491 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1492 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1493
1494
1495 /* ALU instructions can inline or embed constants, which decreases register
1496 * pressure and saves space. */
1497
1498 #define CONDITIONAL_ATTACH(src) { \
1499 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1500 \
1501 if (entry) { \
1502 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1503 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1504 } \
1505 }
1506
1507 static void
1508 inline_alu_constants(compiler_context *ctx)
1509 {
1510 mir_foreach_instr(ctx, alu) {
1511 /* Other instructions cannot inline constants */
1512 if (alu->type != TAG_ALU_4) continue;
1513
1514 /* If there is already a constant here, we can do nothing */
1515 if (alu->has_constants) continue;
1516
1517 /* It makes no sense to inline constants on a branch */
1518 if (alu->compact_branch || alu->prepacked_branch) continue;
1519
1520 CONDITIONAL_ATTACH(src0);
1521
1522 if (!alu->has_constants) {
1523 CONDITIONAL_ATTACH(src1)
1524 } else if (!alu->inline_constant) {
1525 /* Corner case: _two_ vec4 constants, for instance with a
1526 * csel. For this case, we can only use a constant
1527 * register for one, we'll have to emit a move for the
1528 * other. Note, if both arguments are constants, then
1529 * necessarily neither argument depends on the value of
1530 * any particular register. As the destination register
1531 * will be wiped, that means we can spill the constant
1532 * to the destination register.
1533 */
1534
1535 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
1536 unsigned scratch = alu->ssa_args.dest;
1537
1538 if (entry) {
1539 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
1540 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
1541
1542 /* Force a break XXX Defer r31 writes */
1543 ins.unit = UNIT_VLUT;
1544
1545 /* Set the source */
1546 alu->ssa_args.src1 = scratch;
1547
1548 /* Inject us -before- the last instruction which set r31 */
1549 mir_insert_instruction_before(mir_prev_op(alu), ins);
1550 }
1551 }
1552 }
1553 }
1554
1555 /* Midgard supports two types of constants, embedded constants (128-bit) and
1556 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1557 * constants can be demoted to inline constants, for space savings and
1558 * sometimes a performance boost */
1559
1560 static void
1561 embedded_to_inline_constant(compiler_context *ctx)
1562 {
1563 mir_foreach_instr(ctx, ins) {
1564 if (!ins->has_constants) continue;
1565
1566 if (ins->ssa_args.inline_constant) continue;
1567
1568 /* Blend constants must not be inlined by definition */
1569 if (ins->has_blend_constant) continue;
1570
1571 /* src1 cannot be an inline constant due to encoding
1572 * restrictions. So, if possible we try to flip the arguments
1573 * in that case */
1574
1575 int op = ins->alu.op;
1576
1577 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1578 switch (op) {
1579 /* These ops require an operational change to flip
1580 * their arguments TODO */
1581 case midgard_alu_op_flt:
1582 case midgard_alu_op_fle:
1583 case midgard_alu_op_ilt:
1584 case midgard_alu_op_ile:
1585 case midgard_alu_op_fcsel:
1586 case midgard_alu_op_icsel:
1587 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
1588 default:
1589 break;
1590 }
1591
1592 if (alu_opcode_props[op].props & OP_COMMUTES) {
1593 /* Flip the SSA numbers */
1594 ins->ssa_args.src0 = ins->ssa_args.src1;
1595 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1596
1597 /* And flip the modifiers */
1598
1599 unsigned src_temp;
1600
1601 src_temp = ins->alu.src2;
1602 ins->alu.src2 = ins->alu.src1;
1603 ins->alu.src1 = src_temp;
1604 }
1605 }
1606
1607 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1608 /* Extract the source information */
1609
1610 midgard_vector_alu_src *src;
1611 int q = ins->alu.src2;
1612 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1613 src = m;
1614
1615 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1616 int component = src->swizzle & 3;
1617
1618 /* Scale constant appropriately, if we can legally */
1619 uint16_t scaled_constant = 0;
1620
1621 if (midgard_is_integer_op(op)) {
1622 unsigned int *iconstants = (unsigned int *) ins->constants;
1623 scaled_constant = (uint16_t) iconstants[component];
1624
1625 /* Constant overflow after resize */
1626 if (scaled_constant != iconstants[component])
1627 continue;
1628 } else {
1629 float original = (float) ins->constants[component];
1630 scaled_constant = _mesa_float_to_half(original);
1631
1632 /* Check for loss of precision. If this is
1633 * mediump, we don't care, but for a highp
1634 * shader, we need to pay attention. NIR
1635 * doesn't yet tell us which mode we're in!
1636 * Practically this prevents most constants
1637 * from being inlined, sadly. */
1638
1639 float fp32 = _mesa_half_to_float(scaled_constant);
1640
1641 if (fp32 != original)
1642 continue;
1643 }
1644
1645 /* We don't know how to handle these with a constant */
1646
1647 if (src->mod || src->half || src->rep_low || src->rep_high) {
1648 DBG("Bailing inline constant...\n");
1649 continue;
1650 }
1651
1652 /* Make sure that the constant is not itself a
1653 * vector by checking if all accessed values
1654 * (by the swizzle) are the same. */
1655
1656 uint32_t *cons = (uint32_t *) ins->constants;
1657 uint32_t value = cons[component];
1658
1659 bool is_vector = false;
1660 unsigned mask = effective_writemask(&ins->alu);
1661
1662 for (int c = 1; c < 4; ++c) {
1663 /* We only care if this component is actually used */
1664 if (!(mask & (1 << c)))
1665 continue;
1666
1667 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
1668
1669 if (test != value) {
1670 is_vector = true;
1671 break;
1672 }
1673 }
1674
1675 if (is_vector)
1676 continue;
1677
1678 /* Get rid of the embedded constant */
1679 ins->has_constants = false;
1680 ins->ssa_args.src1 = SSA_UNUSED_0;
1681 ins->ssa_args.inline_constant = true;
1682 ins->inline_constant = scaled_constant;
1683 }
1684 }
1685 }
1686
1687 /* Map normal SSA sources to other SSA sources / fixed registers (like
1688 * uniforms) */
1689
1690 static void
1691 map_ssa_to_alias(compiler_context *ctx, int *ref)
1692 {
1693 unsigned int alias = (uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_to_alias, *ref + 1);
1694
1695 if (alias) {
1696 /* Remove entry in leftovers to avoid a redunant fmov */
1697
1698 struct set_entry *leftover = _mesa_set_search(ctx->leftover_ssa_to_alias, ((void *) (uintptr_t) (*ref + 1)));
1699
1700 if (leftover)
1701 _mesa_set_remove(ctx->leftover_ssa_to_alias, leftover);
1702
1703 /* Assign the alias map */
1704 *ref = alias - 1;
1705 return;
1706 }
1707 }
1708
1709 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1710 * texture pipeline */
1711
1712 static bool
1713 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
1714 {
1715 bool progress = false;
1716
1717 mir_foreach_instr_in_block_safe(block, ins) {
1718 if (ins->type != TAG_ALU_4) continue;
1719 if (ins->compact_branch) continue;
1720
1721 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
1722 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
1723
1724 mir_remove_instruction(ins);
1725 progress = true;
1726 }
1727
1728 return progress;
1729 }
1730
1731 static bool
1732 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
1733 {
1734 /* abs or neg */
1735 if (!is_int && src.mod) return true;
1736
1737 /* swizzle */
1738 for (unsigned c = 0; c < 4; ++c) {
1739 if (!(mask & (1 << c))) continue;
1740 if (((src.swizzle >> (2*c)) & 3) != c) return true;
1741 }
1742
1743 return false;
1744 }
1745
1746 static bool
1747 midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
1748 {
1749 bool progress = false;
1750
1751 mir_foreach_instr_in_block_safe(block, ins) {
1752 if (ins->type != TAG_ALU_4) continue;
1753 if (!OP_IS_MOVE(ins->alu.op)) continue;
1754
1755 unsigned from = ins->ssa_args.src1;
1756 unsigned to = ins->ssa_args.dest;
1757
1758 /* We only work on pure SSA */
1759
1760 if (to >= SSA_FIXED_MINIMUM) continue;
1761 if (from >= SSA_FIXED_MINIMUM) continue;
1762 if (to >= ctx->func->impl->ssa_alloc) continue;
1763 if (from >= ctx->func->impl->ssa_alloc) continue;
1764
1765 /* Constant propagation is not handled here, either */
1766 if (ins->ssa_args.inline_constant) continue;
1767 if (ins->has_constants) continue;
1768
1769 /* Also, if the move has side effects, we're helpless */
1770
1771 midgard_vector_alu_src src =
1772 vector_alu_from_unsigned(ins->alu.src2);
1773 unsigned mask = squeeze_writemask(ins->alu.mask);
1774 bool is_int = midgard_is_integer_op(ins->alu.op);
1775
1776 if (mir_nontrivial_mod(src, is_int, mask)) continue;
1777 if (ins->alu.outmod != midgard_outmod_none) continue;
1778
1779 mir_foreach_instr_in_block_from(block, v, mir_next_op(ins)) {
1780 if (v->ssa_args.src0 == to) {
1781 v->ssa_args.src0 = from;
1782 progress = true;
1783 }
1784
1785 if (v->ssa_args.src1 == to && !v->ssa_args.inline_constant) {
1786 v->ssa_args.src1 = from;
1787 progress = true;
1788 }
1789 }
1790 }
1791
1792 return progress;
1793 }
1794
1795 static bool
1796 midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
1797 {
1798 bool progress = false;
1799
1800 mir_foreach_instr_in_block_safe(block, ins) {
1801 if (ins->type != TAG_ALU_4) continue;
1802 if (!OP_IS_MOVE(ins->alu.op)) continue;
1803
1804 unsigned from = ins->ssa_args.src1;
1805 unsigned to = ins->ssa_args.dest;
1806
1807 /* Make sure it's simple enough for us to handle */
1808
1809 if (from >= SSA_FIXED_MINIMUM) continue;
1810 if (from >= ctx->func->impl->ssa_alloc) continue;
1811 if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
1812 if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
1813
1814 bool eliminated = false;
1815
1816 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1817 /* The texture registers are not SSA so be careful.
1818 * Conservatively, just stop if we hit a texture op
1819 * (even if it may not write) to where we are */
1820
1821 if (v->type != TAG_ALU_4)
1822 break;
1823
1824 if (v->ssa_args.dest == from) {
1825 /* We don't want to track partial writes ... */
1826 if (v->alu.mask == 0xF) {
1827 v->ssa_args.dest = to;
1828 eliminated = true;
1829 }
1830
1831 break;
1832 }
1833 }
1834
1835 if (eliminated)
1836 mir_remove_instruction(ins);
1837
1838 progress |= eliminated;
1839 }
1840
1841 return progress;
1842 }
1843
1844 /* The following passes reorder MIR instructions to enable better scheduling */
1845
1846 static void
1847 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
1848 {
1849 mir_foreach_instr_in_block_safe(block, ins) {
1850 if (ins->type != TAG_LOAD_STORE_4) continue;
1851
1852 /* We've found a load/store op. Check if next is also load/store. */
1853 midgard_instruction *next_op = mir_next_op(ins);
1854 if (&next_op->link != &block->instructions) {
1855 if (next_op->type == TAG_LOAD_STORE_4) {
1856 /* If so, we're done since we're a pair */
1857 ins = mir_next_op(ins);
1858 continue;
1859 }
1860
1861 /* Maximum search distance to pair, to avoid register pressure disasters */
1862 int search_distance = 8;
1863
1864 /* Otherwise, we have an orphaned load/store -- search for another load */
1865 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
1866 /* Terminate search if necessary */
1867 if (!(search_distance--)) break;
1868
1869 if (c->type != TAG_LOAD_STORE_4) continue;
1870
1871 /* Stores cannot be reordered, since they have
1872 * dependencies. For the same reason, indirect
1873 * loads cannot be reordered as their index is
1874 * loaded in r27.w */
1875
1876 if (OP_IS_STORE(c->load_store.op)) continue;
1877
1878 /* It appears the 0x800 bit is set whenever a
1879 * load is direct, unset when it is indirect.
1880 * Skip indirect loads. */
1881
1882 if (!(c->load_store.unknown & 0x800)) continue;
1883
1884 /* We found one! Move it up to pair and remove it from the old location */
1885
1886 mir_insert_instruction_before(ins, *c);
1887 mir_remove_instruction(c);
1888
1889 break;
1890 }
1891 }
1892 }
1893 }
1894
1895 /* Emit varying stores late */
1896
1897 static void
1898 midgard_emit_store(compiler_context *ctx, midgard_block *block) {
1899 /* Iterate in reverse to get the final write, rather than the first */
1900
1901 mir_foreach_instr_in_block_safe_rev(block, ins) {
1902 /* Check if what we just wrote needs a store */
1903 int idx = ins->ssa_args.dest;
1904 uintptr_t varying = ((uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_varyings, idx + 1));
1905
1906 if (!varying) continue;
1907
1908 varying -= 1;
1909
1910 /* We need to store to the appropriate varying, so emit the
1911 * move/store */
1912
1913 /* TODO: Integrate with special purpose RA (and scheduler?) */
1914 bool high_varying_register = false;
1915
1916 midgard_instruction mov = v_fmov(idx, blank_alu_src, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE + high_varying_register));
1917
1918 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(high_varying_register), varying);
1919 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1920
1921 mir_insert_instruction_before(mir_next_op(ins), st);
1922 mir_insert_instruction_before(mir_next_op(ins), mov);
1923
1924 /* We no longer need to store this varying */
1925 _mesa_hash_table_u64_remove(ctx->ssa_varyings, idx + 1);
1926 }
1927 }
1928
1929 /* If there are leftovers after the below pass, emit actual fmov
1930 * instructions for the slow-but-correct path */
1931
1932 static void
1933 emit_leftover_move(compiler_context *ctx)
1934 {
1935 set_foreach(ctx->leftover_ssa_to_alias, leftover) {
1936 int base = ((uintptr_t) leftover->key) - 1;
1937 int mapped = base;
1938
1939 map_ssa_to_alias(ctx, &mapped);
1940 EMIT(fmov, mapped, blank_alu_src, base);
1941 }
1942 }
1943
1944 static void
1945 actualise_ssa_to_alias(compiler_context *ctx)
1946 {
1947 mir_foreach_instr(ctx, ins) {
1948 map_ssa_to_alias(ctx, &ins->ssa_args.src0);
1949 map_ssa_to_alias(ctx, &ins->ssa_args.src1);
1950 }
1951
1952 emit_leftover_move(ctx);
1953 }
1954
1955 static void
1956 emit_fragment_epilogue(compiler_context *ctx)
1957 {
1958 /* Special case: writing out constants requires us to include the move
1959 * explicitly now, so shove it into r0 */
1960
1961 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, ctx->fragment_output + 1);
1962
1963 if (constant_value) {
1964 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(0));
1965 attach_constants(ctx, &ins, constant_value, ctx->fragment_output + 1);
1966 emit_mir_instruction(ctx, ins);
1967 }
1968
1969 /* Perform the actual fragment writeout. We have two writeout/branch
1970 * instructions, forming a loop until writeout is successful as per the
1971 * docs. TODO: gl_FragDepth */
1972
1973 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
1974 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
1975 }
1976
1977 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
1978 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
1979 * with the int8 analogue to the fragment epilogue */
1980
1981 static void
1982 emit_blend_epilogue(compiler_context *ctx)
1983 {
1984 /* vmul.fmul.none.fulllow hr48, r0, #255 */
1985
1986 midgard_instruction scale = {
1987 .type = TAG_ALU_4,
1988 .unit = UNIT_VMUL,
1989 .inline_constant = _mesa_float_to_half(255.0),
1990 .ssa_args = {
1991 .src0 = SSA_FIXED_REGISTER(0),
1992 .src1 = SSA_UNUSED_0,
1993 .dest = SSA_FIXED_REGISTER(24),
1994 .inline_constant = true
1995 },
1996 .alu = {
1997 .op = midgard_alu_op_fmul,
1998 .reg_mode = midgard_reg_mode_32,
1999 .dest_override = midgard_dest_override_lower,
2000 .mask = 0xFF,
2001 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2002 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2003 }
2004 };
2005
2006 emit_mir_instruction(ctx, scale);
2007
2008 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2009
2010 midgard_vector_alu_src alu_src = blank_alu_src;
2011 alu_src.half = true;
2012
2013 midgard_instruction f2u8 = {
2014 .type = TAG_ALU_4,
2015 .ssa_args = {
2016 .src0 = SSA_FIXED_REGISTER(24),
2017 .src1 = SSA_UNUSED_0,
2018 .dest = SSA_FIXED_REGISTER(0),
2019 .inline_constant = true
2020 },
2021 .alu = {
2022 .op = midgard_alu_op_f2u8,
2023 .reg_mode = midgard_reg_mode_16,
2024 .dest_override = midgard_dest_override_lower,
2025 .outmod = midgard_outmod_pos,
2026 .mask = 0xF,
2027 .src1 = vector_alu_srco_unsigned(alu_src),
2028 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2029 }
2030 };
2031
2032 emit_mir_instruction(ctx, f2u8);
2033
2034 /* vmul.imov.quarter r0, r0, r0 */
2035
2036 midgard_instruction imov_8 = {
2037 .type = TAG_ALU_4,
2038 .ssa_args = {
2039 .src0 = SSA_UNUSED_1,
2040 .src1 = SSA_FIXED_REGISTER(0),
2041 .dest = SSA_FIXED_REGISTER(0),
2042 },
2043 .alu = {
2044 .op = midgard_alu_op_imov,
2045 .reg_mode = midgard_reg_mode_8,
2046 .dest_override = midgard_dest_override_none,
2047 .outmod = midgard_outmod_int,
2048 .mask = 0xFF,
2049 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2050 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2051 }
2052 };
2053
2054 /* Emit branch epilogue with the 8-bit move as the source */
2055
2056 emit_mir_instruction(ctx, imov_8);
2057 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2058
2059 emit_mir_instruction(ctx, imov_8);
2060 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2061 }
2062
2063 static midgard_block *
2064 emit_block(compiler_context *ctx, nir_block *block)
2065 {
2066 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2067 list_addtail(&this_block->link, &ctx->blocks);
2068
2069 this_block->is_scheduled = false;
2070 ++ctx->block_count;
2071
2072 ctx->texture_index[0] = -1;
2073 ctx->texture_index[1] = -1;
2074
2075 /* Add us as a successor to the block we are following */
2076 if (ctx->current_block)
2077 midgard_block_add_successor(ctx->current_block, this_block);
2078
2079 /* Set up current block */
2080 list_inithead(&this_block->instructions);
2081 ctx->current_block = this_block;
2082
2083 nir_foreach_instr(instr, block) {
2084 emit_instr(ctx, instr);
2085 ++ctx->instruction_count;
2086 }
2087
2088 inline_alu_constants(ctx);
2089 embedded_to_inline_constant(ctx);
2090
2091 /* Perform heavylifting for aliasing */
2092 actualise_ssa_to_alias(ctx);
2093
2094 midgard_emit_store(ctx, this_block);
2095 midgard_pair_load_store(ctx, this_block);
2096
2097 /* Append fragment shader epilogue (value writeout) */
2098 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2099 if (block == nir_impl_last_block(ctx->func->impl)) {
2100 if (ctx->is_blend)
2101 emit_blend_epilogue(ctx);
2102 else
2103 emit_fragment_epilogue(ctx);
2104 }
2105 }
2106
2107 if (block == nir_start_block(ctx->func->impl))
2108 ctx->initial_block = this_block;
2109
2110 if (block == nir_impl_last_block(ctx->func->impl))
2111 ctx->final_block = this_block;
2112
2113 /* Allow the next control flow to access us retroactively, for
2114 * branching etc */
2115 ctx->current_block = this_block;
2116
2117 /* Document the fallthrough chain */
2118 ctx->previous_source_block = this_block;
2119
2120 return this_block;
2121 }
2122
2123 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2124
2125 static void
2126 emit_if(struct compiler_context *ctx, nir_if *nif)
2127 {
2128 /* Conditional branches expect the condition in r31.w; emit a move for
2129 * that in the _previous_ block (which is the current block). */
2130 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2131
2132 /* Speculatively emit the branch, but we can't fill it in until later */
2133 EMIT(branch, true, true);
2134 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2135
2136 /* Emit the two subblocks */
2137 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2138
2139 /* Emit a jump from the end of the then block to the end of the else */
2140 EMIT(branch, false, false);
2141 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2142
2143 /* Emit second block, and check if it's empty */
2144
2145 int else_idx = ctx->block_count;
2146 int count_in = ctx->instruction_count;
2147 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2148 int after_else_idx = ctx->block_count;
2149
2150 /* Now that we have the subblocks emitted, fix up the branches */
2151
2152 assert(then_block);
2153 assert(else_block);
2154
2155 if (ctx->instruction_count == count_in) {
2156 /* The else block is empty, so don't emit an exit jump */
2157 mir_remove_instruction(then_exit);
2158 then_branch->branch.target_block = after_else_idx;
2159 } else {
2160 then_branch->branch.target_block = else_idx;
2161 then_exit->branch.target_block = after_else_idx;
2162 }
2163 }
2164
2165 static void
2166 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2167 {
2168 /* Remember where we are */
2169 midgard_block *start_block = ctx->current_block;
2170
2171 /* Allocate a loop number, growing the current inner loop depth */
2172 int loop_idx = ++ctx->current_loop_depth;
2173
2174 /* Get index from before the body so we can loop back later */
2175 int start_idx = ctx->block_count;
2176
2177 /* Emit the body itself */
2178 emit_cf_list(ctx, &nloop->body);
2179
2180 /* Branch back to loop back */
2181 struct midgard_instruction br_back = v_branch(false, false);
2182 br_back.branch.target_block = start_idx;
2183 emit_mir_instruction(ctx, br_back);
2184
2185 /* Mark down that branch in the graph. Note that we're really branching
2186 * to the block *after* we started in. TODO: Why doesn't the branch
2187 * itself have an off-by-one then...? */
2188 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2189
2190 /* Find the index of the block about to follow us (note: we don't add
2191 * one; blocks are 0-indexed so we get a fencepost problem) */
2192 int break_block_idx = ctx->block_count;
2193
2194 /* Fix up the break statements we emitted to point to the right place,
2195 * now that we can allocate a block number for them */
2196
2197 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2198 mir_foreach_instr_in_block(block, ins) {
2199 if (ins->type != TAG_ALU_4) continue;
2200 if (!ins->compact_branch) continue;
2201 if (ins->prepacked_branch) continue;
2202
2203 /* We found a branch -- check the type to see if we need to do anything */
2204 if (ins->branch.target_type != TARGET_BREAK) continue;
2205
2206 /* It's a break! Check if it's our break */
2207 if (ins->branch.target_break != loop_idx) continue;
2208
2209 /* Okay, cool, we're breaking out of this loop.
2210 * Rewrite from a break to a goto */
2211
2212 ins->branch.target_type = TARGET_GOTO;
2213 ins->branch.target_block = break_block_idx;
2214 }
2215 }
2216
2217 /* Now that we've finished emitting the loop, free up the depth again
2218 * so we play nice with recursion amid nested loops */
2219 --ctx->current_loop_depth;
2220 }
2221
2222 static midgard_block *
2223 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2224 {
2225 midgard_block *start_block = NULL;
2226
2227 foreach_list_typed(nir_cf_node, node, node, list) {
2228 switch (node->type) {
2229 case nir_cf_node_block: {
2230 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2231
2232 if (!start_block)
2233 start_block = block;
2234
2235 break;
2236 }
2237
2238 case nir_cf_node_if:
2239 emit_if(ctx, nir_cf_node_as_if(node));
2240 break;
2241
2242 case nir_cf_node_loop:
2243 emit_loop(ctx, nir_cf_node_as_loop(node));
2244 break;
2245
2246 case nir_cf_node_function:
2247 assert(0);
2248 break;
2249 }
2250 }
2251
2252 return start_block;
2253 }
2254
2255 /* Due to lookahead, we need to report the first tag executed in the command
2256 * stream and in branch targets. An initial block might be empty, so iterate
2257 * until we find one that 'works' */
2258
2259 static unsigned
2260 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2261 {
2262 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2263
2264 unsigned first_tag = 0;
2265
2266 do {
2267 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
2268
2269 if (initial_bundle) {
2270 first_tag = initial_bundle->tag;
2271 break;
2272 }
2273
2274 /* Initial block is empty, try the next block */
2275 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
2276 } while(initial_block != NULL);
2277
2278 assert(first_tag);
2279 return first_tag;
2280 }
2281
2282 int
2283 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend)
2284 {
2285 struct util_dynarray *compiled = &program->compiled;
2286
2287 midgard_debug = debug_get_option_midgard_debug();
2288
2289 compiler_context ictx = {
2290 .nir = nir,
2291 .stage = nir->info.stage,
2292
2293 .is_blend = is_blend,
2294 .blend_constant_offset = -1,
2295
2296 .alpha_ref = program->alpha_ref
2297 };
2298
2299 compiler_context *ctx = &ictx;
2300
2301 /* TODO: Decide this at runtime */
2302 ctx->uniform_cutoff = 8;
2303
2304 /* Assign var locations early, so the epilogue can use them if necessary */
2305
2306 nir_assign_var_locations(&nir->outputs, &nir->num_outputs, glsl_type_size);
2307 nir_assign_var_locations(&nir->inputs, &nir->num_inputs, glsl_type_size);
2308 nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms, glsl_type_size);
2309
2310 /* Initialize at a global (not block) level hash tables */
2311
2312 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2313 ctx->ssa_varyings = _mesa_hash_table_u64_create(NULL);
2314 ctx->ssa_to_alias = _mesa_hash_table_u64_create(NULL);
2315 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2316 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2317 ctx->leftover_ssa_to_alias = _mesa_set_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
2318
2319 /* Record the varying mapping for the command stream's bookkeeping */
2320
2321 struct exec_list *varyings =
2322 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2323
2324 nir_foreach_variable(var, varyings) {
2325 unsigned loc = var->data.driver_location;
2326 unsigned sz = glsl_type_size(var->type, FALSE);
2327
2328 for (int c = 0; c < sz; ++c) {
2329 program->varyings[loc + c] = var->data.location;
2330 }
2331 }
2332
2333 /* Lower gl_Position pre-optimisation */
2334
2335 if (ctx->stage == MESA_SHADER_VERTEX)
2336 NIR_PASS_V(nir, nir_lower_viewport_transform);
2337
2338 NIR_PASS_V(nir, nir_lower_var_copies);
2339 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2340 NIR_PASS_V(nir, nir_split_var_copies);
2341 NIR_PASS_V(nir, nir_lower_var_copies);
2342 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2343 NIR_PASS_V(nir, nir_lower_var_copies);
2344 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2345
2346 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2347
2348 /* Optimisation passes */
2349
2350 optimise_nir(nir);
2351
2352 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2353 nir_print_shader(nir, stdout);
2354 }
2355
2356 /* Assign sysvals and counts, now that we're sure
2357 * (post-optimisation) */
2358
2359 midgard_nir_assign_sysvals(ctx, nir);
2360
2361 program->uniform_count = nir->num_uniforms;
2362 program->sysval_count = ctx->sysval_count;
2363 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2364
2365 program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_inputs : 0;
2366 program->varying_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_outputs : ((ctx->stage == MESA_SHADER_FRAGMENT) ? nir->num_inputs : 0);
2367
2368 nir_foreach_function(func, nir) {
2369 if (!func->impl)
2370 continue;
2371
2372 list_inithead(&ctx->blocks);
2373 ctx->block_count = 0;
2374 ctx->func = func;
2375
2376 emit_cf_list(ctx, &func->impl->body);
2377 emit_block(ctx, func->impl->end_block);
2378
2379 break; /* TODO: Multi-function shaders */
2380 }
2381
2382 util_dynarray_init(compiled, NULL);
2383
2384 /* MIR-level optimizations */
2385
2386 bool progress = false;
2387
2388 do {
2389 progress = false;
2390
2391 mir_foreach_block(ctx, block) {
2392 progress |= midgard_opt_copy_prop(ctx, block);
2393 progress |= midgard_opt_copy_prop_tex(ctx, block);
2394 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2395 }
2396 } while (progress);
2397
2398 /* Schedule! */
2399 schedule_program(ctx);
2400
2401 /* Now that all the bundles are scheduled and we can calculate block
2402 * sizes, emit actual branch instructions rather than placeholders */
2403
2404 int br_block_idx = 0;
2405
2406 mir_foreach_block(ctx, block) {
2407 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2408 for (int c = 0; c < bundle->instruction_count; ++c) {
2409 midgard_instruction *ins = bundle->instructions[c];
2410
2411 if (!midgard_is_branch_unit(ins->unit)) continue;
2412
2413 if (ins->prepacked_branch) continue;
2414
2415 /* Parse some basic branch info */
2416 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2417 bool is_conditional = ins->branch.conditional;
2418 bool is_inverted = ins->branch.invert_conditional;
2419 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2420
2421 /* Determine the block we're jumping to */
2422 int target_number = ins->branch.target_block;
2423
2424 /* Report the destination tag */
2425 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2426
2427 /* Count up the number of quadwords we're
2428 * jumping over = number of quadwords until
2429 * (br_block_idx, target_number) */
2430
2431 int quadword_offset = 0;
2432
2433 if (is_discard) {
2434 /* Jump to the end of the shader. We
2435 * need to include not only the
2436 * following blocks, but also the
2437 * contents of our current block (since
2438 * discard can come in the middle of
2439 * the block) */
2440
2441 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
2442
2443 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
2444 quadword_offset += quadword_size(bun->tag);
2445 }
2446
2447 mir_foreach_block_from(ctx, blk, b) {
2448 quadword_offset += b->quadword_count;
2449 }
2450
2451 } else if (target_number > br_block_idx) {
2452 /* Jump forward */
2453
2454 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2455 midgard_block *blk = mir_get_block(ctx, idx);
2456 assert(blk);
2457
2458 quadword_offset += blk->quadword_count;
2459 }
2460 } else {
2461 /* Jump backwards */
2462
2463 for (int idx = br_block_idx; idx >= target_number; --idx) {
2464 midgard_block *blk = mir_get_block(ctx, idx);
2465 assert(blk);
2466
2467 quadword_offset -= blk->quadword_count;
2468 }
2469 }
2470
2471 /* Unconditional extended branches (far jumps)
2472 * have issues, so we always use a conditional
2473 * branch, setting the condition to always for
2474 * unconditional. For compact unconditional
2475 * branches, cond isn't used so it doesn't
2476 * matter what we pick. */
2477
2478 midgard_condition cond =
2479 !is_conditional ? midgard_condition_always :
2480 is_inverted ? midgard_condition_false :
2481 midgard_condition_true;
2482
2483 midgard_jmp_writeout_op op =
2484 is_discard ? midgard_jmp_writeout_op_discard :
2485 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2486 midgard_jmp_writeout_op_branch_cond;
2487
2488 if (!is_compact) {
2489 midgard_branch_extended branch =
2490 midgard_create_branch_extended(
2491 cond, op,
2492 dest_tag,
2493 quadword_offset);
2494
2495 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2496 } else if (is_conditional || is_discard) {
2497 midgard_branch_cond branch = {
2498 .op = op,
2499 .dest_tag = dest_tag,
2500 .offset = quadword_offset,
2501 .cond = cond
2502 };
2503
2504 assert(branch.offset == quadword_offset);
2505
2506 memcpy(&ins->br_compact, &branch, sizeof(branch));
2507 } else {
2508 assert(op == midgard_jmp_writeout_op_branch_uncond);
2509
2510 midgard_branch_uncond branch = {
2511 .op = op,
2512 .dest_tag = dest_tag,
2513 .offset = quadword_offset,
2514 .unknown = 1
2515 };
2516
2517 assert(branch.offset == quadword_offset);
2518
2519 memcpy(&ins->br_compact, &branch, sizeof(branch));
2520 }
2521 }
2522 }
2523
2524 ++br_block_idx;
2525 }
2526
2527 /* Emit flat binary from the instruction arrays. Iterate each block in
2528 * sequence. Save instruction boundaries such that lookahead tags can
2529 * be assigned easily */
2530
2531 /* Cache _all_ bundles in source order for lookahead across failed branches */
2532
2533 int bundle_count = 0;
2534 mir_foreach_block(ctx, block) {
2535 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2536 }
2537 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2538 int bundle_idx = 0;
2539 mir_foreach_block(ctx, block) {
2540 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2541 source_order_bundles[bundle_idx++] = bundle;
2542 }
2543 }
2544
2545 int current_bundle = 0;
2546
2547 mir_foreach_block(ctx, block) {
2548 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2549 int lookahead = 1;
2550
2551 if (current_bundle + 1 < bundle_count) {
2552 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2553
2554 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2555 lookahead = 1;
2556 } else {
2557 lookahead = next;
2558 }
2559 }
2560
2561 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2562 ++current_bundle;
2563 }
2564
2565 /* TODO: Free deeper */
2566 //util_dynarray_fini(&block->instructions);
2567 }
2568
2569 free(source_order_bundles);
2570
2571 /* Report the very first tag executed */
2572 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2573
2574 /* Deal with off-by-one related to the fencepost problem */
2575 program->work_register_count = ctx->work_registers + 1;
2576
2577 program->can_discard = ctx->can_discard;
2578 program->uniform_cutoff = ctx->uniform_cutoff;
2579
2580 program->blend_patch_offset = ctx->blend_constant_offset;
2581
2582 if (midgard_debug & MIDGARD_DBG_SHADERS)
2583 disassemble_midgard(program->compiled.data, program->compiled.size);
2584
2585 return 0;
2586 }