2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
111 midgard_is_branch_unit(unsigned unit
)
113 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
116 /* Generic in-memory data type repesenting a single logical instruction, rather
117 * than a single instruction group. This is the preferred form for code gen.
118 * Multiple midgard_insturctions will later be combined during scheduling,
119 * though this is not represented in this structure. Its format bridges
120 * the low-level binary representation with the higher level semantic meaning.
122 * Notably, it allows registers to be specified as block local SSA, for code
123 * emitted before the register allocation pass.
126 typedef struct midgard_instruction
{
127 /* Must be first for casting */
128 struct list_head link
;
130 unsigned type
; /* ALU, load/store, texture */
132 /* If the register allocator has not run yet... */
135 /* Special fields for an ALU instruction */
136 midgard_reg_info registers
;
138 /* I.e. (1 << alu_bit) */
143 uint16_t inline_constant
;
144 bool has_blend_constant
;
148 bool prepacked_branch
;
151 midgard_load_store_word load_store
;
152 midgard_vector_alu alu
;
153 midgard_texture_word texture
;
154 midgard_branch_extended branch_extended
;
157 /* General branch, rather than packed br_compact. Higher level
158 * than the other components */
159 midgard_branch branch
;
161 } midgard_instruction
;
163 typedef struct midgard_block
{
164 /* Link to next block. Must be first for mir_get_block */
165 struct list_head link
;
167 /* List of midgard_instructions emitted for the current block */
168 struct list_head instructions
;
172 /* List of midgard_bundles emitted (after the scheduler has run) */
173 struct util_dynarray bundles
;
175 /* Number of quadwords _actually_ emitted, as determined after scheduling */
176 unsigned quadword_count
;
178 /* Successors: always one forward (the block after us), maybe
179 * one backwards (for a backward branch). No need for a second
180 * forward, since graph traversal would get there eventually
182 struct midgard_block
*successors
[2];
183 unsigned nr_successors
;
185 /* The successors pointer form a graph, and in the case of
186 * complex control flow, this graph has a cycles. To aid
187 * traversal during liveness analysis, we have a visited?
188 * boolean for passes to use as they see fit, provided they
194 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
196 block
->successors
[block
->nr_successors
++] = successor
;
197 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
200 /* Helpers to generate midgard_instruction's using macro magic, since every
201 * driver seems to do it that way */
203 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
204 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
206 #define M_LOAD_STORE(name, rname, uname) \
207 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
208 midgard_instruction i = { \
209 .type = TAG_LOAD_STORE_4, \
216 .op = midgard_op_##name, \
218 .swizzle = SWIZZLE_XYZW, \
226 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
227 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
229 const midgard_vector_alu_src blank_alu_src
= {
230 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
233 const midgard_vector_alu_src blank_alu_src_xxxx
= {
234 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
237 const midgard_scalar_alu_src blank_scalar_alu_src
= {
241 /* Used for encoding the unused source of 1-op instructions */
242 const midgard_vector_alu_src zero_alu_src
= { 0 };
244 /* Coerce structs to integer */
247 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
250 memcpy(&u
, &src
, sizeof(src
));
254 static midgard_vector_alu_src
255 vector_alu_from_unsigned(unsigned u
)
257 midgard_vector_alu_src s
;
258 memcpy(&s
, &u
, sizeof(s
));
262 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
263 * the corresponding Midgard source */
265 static midgard_vector_alu_src
266 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
268 if (!src
) return blank_alu_src
;
270 midgard_vector_alu_src alu_src
= {
273 .half
= 0, /* TODO */
274 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
278 /* TODO: sign-extend/zero-extend */
279 alu_src
.mod
= midgard_int_normal
;
281 /* These should have been lowered away */
282 assert(!(src
->abs
|| src
->negate
));
284 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
291 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
294 if (!is_int
&& src
.mod
) return true;
297 for (unsigned c
= 0; c
< 4; ++c
) {
298 if (!(mask
& (1 << c
))) continue;
299 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
305 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
307 static midgard_instruction
308 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
310 midgard_instruction ins
= {
313 .src0
= SSA_UNUSED_1
,
318 .op
= midgard_alu_op_fmov
,
319 .reg_mode
= midgard_reg_mode_32
,
320 .dest_override
= midgard_dest_override_none
,
322 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
323 .src2
= vector_alu_srco_unsigned(mod
)
330 /* load/store instructions have both 32-bit and 16-bit variants, depending on
331 * whether we are using vectors composed of highp or mediump. At the moment, we
332 * don't support half-floats -- this requires changes in other parts of the
333 * compiler -- therefore the 16-bit versions are commented out. */
335 //M_LOAD(load_attr_16);
336 M_LOAD(load_attr_32
);
337 //M_LOAD(load_vary_16);
338 M_LOAD(load_vary_32
);
339 //M_LOAD(load_uniform_16);
340 M_LOAD(load_uniform_32
);
341 M_LOAD(load_color_buffer_8
);
342 //M_STORE(store_vary_16);
343 M_STORE(store_vary_32
);
344 M_STORE(store_cubemap_coords
);
346 static midgard_instruction
347 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
349 midgard_branch_cond branch
= {
357 memcpy(&compact
, &branch
, sizeof(branch
));
359 midgard_instruction ins
= {
361 .unit
= ALU_ENAB_BR_COMPACT
,
362 .prepacked_branch
= true,
363 .compact_branch
= true,
364 .br_compact
= compact
367 if (op
== midgard_jmp_writeout_op_writeout
)
373 static midgard_instruction
374 v_branch(bool conditional
, bool invert
)
376 midgard_instruction ins
= {
378 .unit
= ALU_ENAB_BRANCH
,
379 .compact_branch
= true,
381 .conditional
= conditional
,
382 .invert_conditional
= invert
389 static midgard_branch_extended
390 midgard_create_branch_extended( midgard_condition cond
,
391 midgard_jmp_writeout_op op
,
393 signed quadword_offset
)
395 /* For unclear reasons, the condition code is repeated 8 times */
396 uint16_t duplicated_cond
=
406 midgard_branch_extended branch
= {
408 .dest_tag
= dest_tag
,
409 .offset
= quadword_offset
,
410 .cond
= duplicated_cond
416 typedef struct midgard_bundle
{
417 /* Tag for the overall bundle */
420 /* Instructions contained by the bundle */
421 int instruction_count
;
422 midgard_instruction instructions
[5];
424 /* Bundle-wide ALU configuration */
427 bool has_embedded_constants
;
429 bool has_blend_constant
;
431 uint16_t register_words
[8];
432 int register_words_count
;
434 uint64_t body_words
[8];
436 int body_words_count
;
439 typedef struct compiler_context
{
441 gl_shader_stage stage
;
443 /* Is internally a blend shader? Depends on stage == FRAGMENT */
446 /* Tracking for blend constant patching */
447 int blend_constant_number
;
448 int blend_constant_offset
;
450 /* Current NIR function */
453 /* Unordered list of midgard_blocks */
455 struct list_head blocks
;
457 midgard_block
*initial_block
;
458 midgard_block
*previous_source_block
;
459 midgard_block
*final_block
;
461 /* List of midgard_instructions emitted for the current block */
462 midgard_block
*current_block
;
464 /* The current "depth" of the loop, for disambiguating breaks/continues
465 * when using nested loops */
466 int current_loop_depth
;
468 /* Constants which have been loaded, for later inlining */
469 struct hash_table_u64
*ssa_constants
;
471 /* SSA indices to be outputted to corresponding varying offset */
472 struct hash_table_u64
*ssa_varyings
;
474 /* SSA values / registers which have been aliased. Naively, these
475 * demand a fmov output; instead, we alias them in a later pass to
476 * avoid the wasted op.
478 * A note on encoding: to avoid dynamic memory management here, rather
479 * than ampping to a pointer, we map to the source index; the key
480 * itself is just the destination index. */
482 struct hash_table_u64
*ssa_to_alias
;
483 struct set
*leftover_ssa_to_alias
;
485 /* Actual SSA-to-register for RA */
486 struct hash_table_u64
*ssa_to_register
;
488 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
489 struct hash_table_u64
*hash_to_temp
;
493 /* Just the count of the max register used. Higher count => higher
494 * register pressure */
497 /* Used for cont/last hinting. Increase when a tex op is added.
498 * Decrease when a tex op is removed. */
499 int texture_op_count
;
501 /* Mapping of texture register -> SSA index for unaliasing */
502 int texture_index
[2];
504 /* If any path hits a discard instruction */
507 /* The number of uniforms allowable for the fast path */
510 /* Count of instructions emitted from NIR overall, across all blocks */
511 int instruction_count
;
513 /* Alpha ref value passed in */
516 /* The index corresponding to the fragment output */
517 unsigned fragment_output
;
519 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
520 unsigned sysvals
[MAX_SYSVAL_COUNT
];
521 unsigned sysval_count
;
522 struct hash_table_u64
*sysval_to_id
;
525 /* Append instruction to end of current block */
527 static midgard_instruction
*
528 mir_upload_ins(struct midgard_instruction ins
)
530 midgard_instruction
*heap
= malloc(sizeof(ins
));
531 memcpy(heap
, &ins
, sizeof(ins
));
536 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
538 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
542 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
544 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
548 mir_remove_instruction(struct midgard_instruction
*ins
)
550 list_del(&ins
->link
);
553 static midgard_instruction
*
554 mir_prev_op(struct midgard_instruction
*ins
)
556 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
559 static midgard_instruction
*
560 mir_next_op(struct midgard_instruction
*ins
)
562 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
565 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
566 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
568 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
569 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
570 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
571 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
572 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
573 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
574 #define mir_foreach_instr_in_block_from_rev(block, v, from) list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
577 static midgard_instruction
*
578 mir_last_in_block(struct midgard_block
*block
)
580 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
583 static midgard_block
*
584 mir_get_block(compiler_context
*ctx
, int idx
)
586 struct list_head
*lst
= &ctx
->blocks
;
591 return (struct midgard_block
*) lst
;
594 /* Pretty printer for internal Midgard IR */
597 print_mir_source(int source
)
599 if (source
>= SSA_FIXED_MINIMUM
) {
600 /* Specific register */
601 int reg
= SSA_REG_FROM_FIXED(source
);
603 /* TODO: Moving threshold */
604 if (reg
> 16 && reg
< 24)
605 printf("u%d", 23 - reg
);
609 printf("%d", source
);
614 print_mir_instruction(midgard_instruction
*ins
)
620 midgard_alu_op op
= ins
->alu
.op
;
621 const char *name
= alu_opcode_props
[op
].name
;
624 printf("%d.", ins
->unit
);
626 printf("%s", name
? name
: "??");
630 case TAG_LOAD_STORE_4
: {
631 midgard_load_store_op op
= ins
->load_store
.op
;
632 const char *name
= load_store_opcode_names
[op
];
639 case TAG_TEXTURE_4
: {
648 ssa_args
*args
= &ins
->ssa_args
;
650 printf(" %d, ", args
->dest
);
652 print_mir_source(args
->src0
);
655 if (args
->inline_constant
)
656 printf("#%d", ins
->inline_constant
);
658 print_mir_source(args
->src1
);
660 if (ins
->has_constants
)
661 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
667 print_mir_block(midgard_block
*block
)
671 mir_foreach_instr_in_block(block
, ins
) {
672 print_mir_instruction(ins
);
679 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
681 ins
->has_constants
= true;
682 memcpy(&ins
->constants
, constants
, 16);
684 /* If this is the special blend constant, mark this instruction */
686 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
687 ins
->has_blend_constant
= true;
691 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
693 return glsl_count_attribute_slots(type
, false);
696 /* Lower fdot2 to a vector multiplication followed by channel addition */
698 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
700 if (alu
->op
!= nir_op_fdot2
)
703 b
->cursor
= nir_before_instr(&alu
->instr
);
705 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
706 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
708 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
710 nir_ssa_def
*sum
= nir_fadd(b
,
711 nir_channel(b
, product
, 0),
712 nir_channel(b
, product
, 1));
714 /* Replace the fdot2 with this sum */
715 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
719 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
721 switch (instr
->intrinsic
) {
722 case nir_intrinsic_load_viewport_scale
:
723 return PAN_SYSVAL_VIEWPORT_SCALE
;
724 case nir_intrinsic_load_viewport_offset
:
725 return PAN_SYSVAL_VIEWPORT_OFFSET
;
732 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
736 if (instr
->type
== nir_instr_type_intrinsic
) {
737 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
738 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
744 /* We have a sysval load; check if it's already been assigned */
746 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
749 /* It hasn't -- so assign it now! */
751 unsigned id
= ctx
->sysval_count
++;
752 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
753 ctx
->sysvals
[id
] = sysval
;
757 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
759 ctx
->sysval_count
= 0;
761 nir_foreach_function(function
, shader
) {
762 if (!function
->impl
) continue;
764 nir_foreach_block(block
, function
->impl
) {
765 nir_foreach_instr_safe(instr
, block
) {
766 midgard_nir_assign_sysval_body(ctx
, instr
);
773 midgard_nir_lower_fdot2(nir_shader
*shader
)
775 bool progress
= false;
777 nir_foreach_function(function
, shader
) {
778 if (!function
->impl
) continue;
781 nir_builder
*b
= &_b
;
782 nir_builder_init(b
, function
->impl
);
784 nir_foreach_block(block
, function
->impl
) {
785 nir_foreach_instr_safe(instr
, block
) {
786 if (instr
->type
!= nir_instr_type_alu
) continue;
788 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
789 midgard_nir_lower_fdot2_body(b
, alu
);
795 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
803 optimise_nir(nir_shader
*nir
)
807 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
808 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
810 nir_lower_tex_options lower_tex_options
= {
814 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
819 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
820 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
822 NIR_PASS(progress
, nir
, nir_copy_prop
);
823 NIR_PASS(progress
, nir
, nir_opt_dce
);
824 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
825 NIR_PASS(progress
, nir
, nir_opt_cse
);
826 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
827 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
828 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
829 NIR_PASS(progress
, nir
, nir_opt_undef
);
830 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
833 nir_var_function_temp
);
835 /* TODO: Enable vectorize when merged upstream */
836 // NIR_PASS(progress, nir, nir_opt_vectorize);
839 /* Must be run at the end to prevent creation of fsin/fcos ops */
840 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
845 NIR_PASS(progress
, nir
, nir_opt_dce
);
846 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
847 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
848 NIR_PASS(progress
, nir
, nir_copy_prop
);
851 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
852 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
854 /* Lower mods for float ops only. Integer ops don't support modifiers
855 * (saturate doesn't make sense on integers, neg/abs require dedicated
858 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
859 NIR_PASS(progress
, nir
, nir_copy_prop
);
860 NIR_PASS(progress
, nir
, nir_opt_dce
);
862 /* We implement booleans as 32-bit 0/~0 */
863 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
865 /* Take us out of SSA */
866 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
867 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
869 /* We are a vector architecture; write combine where possible */
870 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
871 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
873 NIR_PASS(progress
, nir
, nir_opt_dce
);
876 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
877 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
878 * r0. See the comments in compiler_context */
881 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
883 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
884 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
887 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
890 unalias_ssa(compiler_context
*ctx
, int dest
)
892 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
893 /* TODO: Remove from leftover or no? */
897 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
899 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
903 midgard_is_pinned(compiler_context
*ctx
, int index
)
905 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
908 /* Do not actually emit a load; instead, cache the constant for inlining */
911 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
913 nir_ssa_def def
= instr
->def
;
915 float *v
= ralloc_array(NULL
, float, 4);
916 nir_const_load_to_arr(v
, instr
, f32
);
917 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
920 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
924 expand_writemask(unsigned mask
)
928 for (int i
= 0; i
< 4; ++i
)
936 squeeze_writemask(unsigned mask
)
940 for (int i
= 0; i
< 4; ++i
)
941 if (mask
& (3 << (2 * i
)))
948 /* Determines effective writemask, taking quirks and expansion into account */
950 effective_writemask(midgard_vector_alu
*alu
)
952 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
955 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
].props
);
957 /* If there is a fixed channel count, construct the appropriate mask */
960 return (1 << channel_count
) - 1;
962 /* Otherwise, just squeeze the existing mask */
963 return squeeze_writemask(alu
->mask
);
967 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
969 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
972 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
977 /* If no temp is find, allocate one */
978 temp
= ctx
->temp_count
++;
979 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
981 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
987 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
990 return src
->ssa
->index
;
992 assert(!src
->reg
.indirect
);
993 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
998 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
1001 return dst
->ssa
.index
;
1003 assert(!dst
->reg
.indirect
);
1004 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
1009 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
1011 return nir_src_index(ctx
, &src
->src
);
1014 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
1015 * a conditional test) into that register */
1018 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
1020 int condition
= nir_src_index(ctx
, src
);
1022 /* Source to swizzle the desired component into w */
1024 const midgard_vector_alu_src alu_src
= {
1025 .swizzle
= SWIZZLE(component
, component
, component
, component
),
1028 /* There is no boolean move instruction. Instead, we simulate a move by
1029 * ANDing the condition with itself to get it into r31.w */
1031 midgard_instruction ins
= {
1033 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
1037 .dest
= SSA_FIXED_REGISTER(31),
1040 .op
= midgard_alu_op_iand
,
1041 .reg_mode
= midgard_reg_mode_32
,
1042 .dest_override
= midgard_dest_override_none
,
1043 .mask
= (0x3 << 6), /* w */
1044 .src1
= vector_alu_srco_unsigned(alu_src
),
1045 .src2
= vector_alu_srco_unsigned(alu_src
)
1049 emit_mir_instruction(ctx
, ins
);
1052 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1053 * pinning to eliminate this move in all known cases */
1056 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1058 int offset
= nir_src_index(ctx
, src
);
1060 midgard_instruction ins
= {
1063 .src0
= SSA_UNUSED_1
,
1065 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1068 .op
= midgard_alu_op_imov
,
1069 .reg_mode
= midgard_reg_mode_32
,
1070 .dest_override
= midgard_dest_override_none
,
1071 .mask
= (0x3 << 6), /* w */
1072 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1073 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1077 emit_mir_instruction(ctx
, ins
);
1080 #define ALU_CASE(nir, _op) \
1081 case nir_op_##nir: \
1082 op = midgard_alu_op_##_op; \
1086 nir_is_fzero_constant(nir_src src
)
1088 if (!nir_src_is_const(src
))
1091 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
1092 if (nir_src_comp_as_float(src
, c
) != 0.0)
1100 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1102 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1104 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1105 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1106 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1108 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1109 * supported. A few do not and are commented for now. Also, there are a
1110 * number of NIR ops which Midgard does not support and need to be
1111 * lowered, also TODO. This switch block emits the opcode and calling
1112 * convention of the Midgard instruction; actual packing is done in
1117 switch (instr
->op
) {
1118 ALU_CASE(fadd
, fadd
);
1119 ALU_CASE(fmul
, fmul
);
1120 ALU_CASE(fmin
, fmin
);
1121 ALU_CASE(fmax
, fmax
);
1122 ALU_CASE(imin
, imin
);
1123 ALU_CASE(imax
, imax
);
1124 ALU_CASE(umin
, umin
);
1125 ALU_CASE(umax
, umax
);
1126 ALU_CASE(fmov
, fmov
);
1127 ALU_CASE(ffloor
, ffloor
);
1128 ALU_CASE(fround_even
, froundeven
);
1129 ALU_CASE(ftrunc
, ftrunc
);
1130 ALU_CASE(fceil
, fceil
);
1131 ALU_CASE(fdot3
, fdot3
);
1132 ALU_CASE(fdot4
, fdot4
);
1133 ALU_CASE(iadd
, iadd
);
1134 ALU_CASE(isub
, isub
);
1135 ALU_CASE(imul
, imul
);
1136 ALU_CASE(iabs
, iabs
);
1137 ALU_CASE(imov
, imov
);
1139 ALU_CASE(feq32
, feq
);
1140 ALU_CASE(fne32
, fne
);
1141 ALU_CASE(flt32
, flt
);
1142 ALU_CASE(ieq32
, ieq
);
1143 ALU_CASE(ine32
, ine
);
1144 ALU_CASE(ilt32
, ilt
);
1145 ALU_CASE(ult32
, ult
);
1147 /* We don't have a native b2f32 instruction. Instead, like many
1148 * GPUs, we exploit booleans as 0/~0 for false/true, and
1149 * correspondingly AND
1150 * by 1.0 to do the type conversion. For the moment, prime us
1153 * iand [whatever], #0
1155 * At the end of emit_alu (as MIR), we'll fix-up the constant
1158 ALU_CASE(b2f32
, iand
);
1159 ALU_CASE(b2i32
, iand
);
1161 /* Likewise, we don't have a dedicated f2b32 instruction, but
1162 * we can do a "not equal to 0.0" test. */
1164 ALU_CASE(f2b32
, fne
);
1165 ALU_CASE(i2b32
, ine
);
1167 ALU_CASE(frcp
, frcp
);
1168 ALU_CASE(frsq
, frsqrt
);
1169 ALU_CASE(fsqrt
, fsqrt
);
1170 ALU_CASE(fexp2
, fexp2
);
1171 ALU_CASE(flog2
, flog2
);
1173 ALU_CASE(f2i32
, f2i
);
1174 ALU_CASE(f2u32
, f2u
);
1175 ALU_CASE(i2f32
, i2f
);
1176 ALU_CASE(u2f32
, u2f
);
1178 ALU_CASE(fsin
, fsin
);
1179 ALU_CASE(fcos
, fcos
);
1181 ALU_CASE(iand
, iand
);
1183 ALU_CASE(ixor
, ixor
);
1184 ALU_CASE(inot
, inand
);
1185 ALU_CASE(ishl
, ishl
);
1186 ALU_CASE(ishr
, iasr
);
1187 ALU_CASE(ushr
, ilsr
);
1189 ALU_CASE(b32all_fequal2
, fball_eq
);
1190 ALU_CASE(b32all_fequal3
, fball_eq
);
1191 ALU_CASE(b32all_fequal4
, fball_eq
);
1193 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1194 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1195 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1197 ALU_CASE(b32all_iequal2
, iball_eq
);
1198 ALU_CASE(b32all_iequal3
, iball_eq
);
1199 ALU_CASE(b32all_iequal4
, iball_eq
);
1201 ALU_CASE(b32any_inequal2
, ibany_neq
);
1202 ALU_CASE(b32any_inequal3
, ibany_neq
);
1203 ALU_CASE(b32any_inequal4
, ibany_neq
);
1205 /* For greater-or-equal, we lower to less-or-equal and flip the
1211 case nir_op_uge32
: {
1213 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1214 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1215 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1216 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1219 /* Swap via temporary */
1220 nir_alu_src temp
= instr
->src
[1];
1221 instr
->src
[1] = instr
->src
[0];
1222 instr
->src
[0] = temp
;
1227 /* For a few special csel cases not handled by NIR, we can opt to
1228 * bitwise. Otherwise, we emit the condition and do a real csel */
1230 case nir_op_b32csel
: {
1231 if (nir_is_fzero_constant(instr
->src
[2].src
)) {
1232 /* (b ? v : 0) = (b & v) */
1233 op
= midgard_alu_op_iand
;
1235 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1236 /* (b ? 0 : v) = (!b ? v : 0) = (~b & v) = (v & ~b) */
1237 op
= midgard_alu_op_iandnot
;
1239 instr
->src
[1] = instr
->src
[0];
1240 instr
->src
[0] = instr
->src
[2];
1242 /* Midgard features both fcsel and icsel, depending on
1243 * the type of the arguments/output. However, as long
1244 * as we're careful we can _always_ use icsel and
1245 * _never_ need fcsel, since the latter does additional
1246 * floating-point-specific processing whereas the
1247 * former just moves bits on the wire. It's not obvious
1248 * why these are separate opcodes, save for the ability
1249 * to do things like sat/pos/abs/neg for free */
1251 op
= midgard_alu_op_icsel
;
1253 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1256 /* Figure out which component the condition is in */
1258 unsigned comp
= instr
->src
[0].swizzle
[0];
1260 /* Make sure NIR isn't throwing a mixed condition at us */
1262 for (unsigned c
= 1; c
< nr_components
; ++c
)
1263 assert(instr
->src
[0].swizzle
[c
] == comp
);
1265 /* Emit the condition into r31.w */
1266 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1268 /* The condition is the first argument; move the other
1269 * arguments up one to be a binary instruction for
1272 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1278 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1283 /* Midgard can perform certain modifiers on output ofa n ALU op */
1284 midgard_outmod outmod
=
1285 instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1287 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1289 if (instr
->op
== nir_op_fmax
) {
1290 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1291 op
= midgard_alu_op_fmov
;
1293 outmod
= midgard_outmod_pos
;
1294 instr
->src
[0] = instr
->src
[1];
1295 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1296 op
= midgard_alu_op_fmov
;
1298 outmod
= midgard_outmod_pos
;
1302 /* Fetch unit, quirks, etc information */
1303 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1304 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1306 /* src0 will always exist afaik, but src1 will not for 1-argument
1307 * instructions. The latter can only be fetched if the instruction
1308 * needs it, or else we may segfault. */
1310 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1311 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1313 /* Rather than use the instruction generation helpers, we do it
1314 * ourselves here to avoid the mess */
1316 midgard_instruction ins
= {
1319 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1320 .src1
= quirk_flipped_r24
? src0
: src1
,
1325 nir_alu_src
*nirmods
[2] = { NULL
};
1327 if (nr_inputs
== 2) {
1328 nirmods
[0] = &instr
->src
[0];
1329 nirmods
[1] = &instr
->src
[1];
1330 } else if (nr_inputs
== 1) {
1331 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1336 bool is_int
= midgard_is_integer_op(op
);
1338 midgard_vector_alu alu
= {
1340 .reg_mode
= midgard_reg_mode_32
,
1341 .dest_override
= midgard_dest_override_none
,
1344 /* Writemask only valid for non-SSA NIR */
1345 .mask
= expand_writemask((1 << nr_components
) - 1),
1347 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
1348 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
1351 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1354 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1358 /* Late fixup for emulated instructions */
1360 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1361 /* Presently, our second argument is an inline #0 constant.
1362 * Switch over to an embedded 1.0 constant (that can't fit
1363 * inline, since we're 32-bit, not 16-bit like the inline
1366 ins
.ssa_args
.inline_constant
= false;
1367 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1368 ins
.has_constants
= true;
1370 if (instr
->op
== nir_op_b2f32
) {
1371 ins
.constants
[0] = 1.0f
;
1373 /* Type pun it into place */
1375 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1378 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1379 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1380 ins
.ssa_args
.inline_constant
= false;
1381 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1382 ins
.has_constants
= true;
1383 ins
.constants
[0] = 0.0f
;
1384 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1385 } else if (instr
->op
== nir_op_inot
) {
1386 /* ~b = ~(b & b), so duplicate the source */
1387 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1388 ins
.alu
.src2
= ins
.alu
.src1
;
1391 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1392 /* To avoid duplicating the lookup tables (probably), true LUT
1393 * instructions can only operate as if they were scalars. Lower
1394 * them here by changing the component. */
1396 uint8_t original_swizzle
[4];
1397 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1399 for (int i
= 0; i
< nr_components
; ++i
) {
1400 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1402 for (int j
= 0; j
< 4; ++j
)
1403 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1405 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
1406 emit_mir_instruction(ctx
, ins
);
1409 emit_mir_instruction(ctx
, ins
);
1416 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1418 /* TODO: half-floats */
1420 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1421 /* Fast path: For the first 16 uniforms, direct accesses are
1422 * 0-cycle, since they're just a register fetch in the usual
1423 * case. So, we alias the registers while we're still in
1426 int reg_slot
= 23 - offset
;
1427 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1429 /* Otherwise, read from the 'special' UBO to access
1430 * higher-indexed uniforms, at a performance cost. More
1431 * generally, we're emitting a UBO read instruction. */
1433 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1435 /* TODO: Don't split */
1436 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1437 ins
.load_store
.address
= offset
>> 3;
1439 if (indirect_offset
) {
1440 emit_indirect_offset(ctx
, indirect_offset
);
1441 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1443 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1446 emit_mir_instruction(ctx
, ins
);
1451 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1453 /* First, pull out the destination */
1454 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1456 /* Now, figure out which uniform this is */
1457 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1458 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1460 /* Sysvals are prefix uniforms */
1461 unsigned uniform
= ((uintptr_t) val
) - 1;
1463 /* Emit the read itself -- this is never indirect */
1464 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1468 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1470 unsigned offset
, reg
;
1472 switch (instr
->intrinsic
) {
1473 case nir_intrinsic_discard_if
:
1474 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1478 case nir_intrinsic_discard
: {
1479 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1480 struct midgard_instruction discard
= v_branch(conditional
, false);
1481 discard
.branch
.target_type
= TARGET_DISCARD
;
1482 emit_mir_instruction(ctx
, discard
);
1484 ctx
->can_discard
= true;
1488 case nir_intrinsic_load_uniform
:
1489 case nir_intrinsic_load_input
:
1490 offset
= nir_intrinsic_base(instr
);
1492 bool direct
= nir_src_is_const(instr
->src
[0]);
1495 offset
+= nir_src_as_uint(instr
->src
[0]);
1498 reg
= nir_dest_index(ctx
, &instr
->dest
);
1500 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1501 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1502 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1503 /* XXX: Half-floats? */
1504 /* TODO: swizzle, mask */
1506 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1508 midgard_varying_parameter p
= {
1510 .interpolation
= midgard_interp_default
,
1511 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1515 memcpy(&u
, &p
, sizeof(p
));
1516 ins
.load_store
.varying_parameters
= u
;
1519 /* We have the offset totally ready */
1520 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1522 /* We have it partially ready, but we need to
1523 * add in the dynamic index, moved to r27.w */
1524 emit_indirect_offset(ctx
, &instr
->src
[0]);
1525 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1528 emit_mir_instruction(ctx
, ins
);
1529 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1530 /* Constant encoded as a pinned constant */
1532 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1533 ins
.has_constants
= true;
1534 ins
.has_blend_constant
= true;
1535 emit_mir_instruction(ctx
, ins
);
1536 } else if (ctx
->is_blend
) {
1537 /* For blend shaders, a load might be
1538 * translated various ways depending on what
1539 * we're loading. Figure out how this is used */
1541 nir_variable
*out
= NULL
;
1543 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1544 int drvloc
= var
->data
.driver_location
;
1546 if (nir_intrinsic_base(instr
) == drvloc
) {
1554 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1555 /* Source color preloaded to r0 */
1557 midgard_pin_output(ctx
, reg
, 0);
1558 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1559 /* Destination color must be read from framebuffer */
1561 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1562 ins
.load_store
.swizzle
= 0; /* xxxx */
1564 /* Read each component sequentially */
1566 for (int c
= 0; c
< 4; ++c
) {
1567 ins
.load_store
.mask
= (1 << c
);
1568 ins
.load_store
.unknown
= c
;
1569 emit_mir_instruction(ctx
, ins
);
1572 /* vadd.u2f hr2, zext(hr2), #0 */
1574 midgard_vector_alu_src alu_src
= blank_alu_src
;
1575 alu_src
.mod
= midgard_int_zero_extend
;
1576 alu_src
.half
= true;
1578 midgard_instruction u2f
= {
1582 .src1
= SSA_UNUSED_0
,
1584 .inline_constant
= true
1587 .op
= midgard_alu_op_u2f
,
1588 .reg_mode
= midgard_reg_mode_16
,
1589 .dest_override
= midgard_dest_override_none
,
1591 .src1
= vector_alu_srco_unsigned(alu_src
),
1592 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1596 emit_mir_instruction(ctx
, u2f
);
1598 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1602 midgard_instruction fmul
= {
1604 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1608 .src1
= SSA_UNUSED_0
,
1609 .inline_constant
= true
1612 .op
= midgard_alu_op_fmul
,
1613 .reg_mode
= midgard_reg_mode_32
,
1614 .dest_override
= midgard_dest_override_none
,
1615 .outmod
= midgard_outmod_sat
,
1617 .src1
= vector_alu_srco_unsigned(alu_src
),
1618 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1622 emit_mir_instruction(ctx
, fmul
);
1624 DBG("Unknown input in blend shader\n");
1627 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1628 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1629 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1630 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1631 emit_mir_instruction(ctx
, ins
);
1633 DBG("Unknown load\n");
1639 case nir_intrinsic_store_output
:
1640 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1642 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1644 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1646 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1647 /* gl_FragColor is not emitted with load/store
1648 * instructions. Instead, it gets plonked into
1649 * r0 at the end of the shader and we do the
1650 * framebuffer writeout dance. TODO: Defer
1653 midgard_pin_output(ctx
, reg
, 0);
1655 /* Save the index we're writing to for later reference
1656 * in the epilogue */
1658 ctx
->fragment_output
= reg
;
1659 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1660 /* Varyings are written into one of two special
1661 * varying register, r26 or r27. The register itself is selected as the register
1662 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1664 * Normally emitting fmov's is frowned upon,
1665 * but due to unique constraints of
1666 * REGISTER_VARYING, fmov emission + a
1667 * dedicated cleanup pass is the only way to
1668 * guarantee correctness when considering some
1669 * (common) edge cases XXX: FIXME */
1671 /* If this varying corresponds to a constant (why?!),
1672 * emit that now since it won't get picked up by
1673 * hoisting (since there is no corresponding move
1674 * emitted otherwise) */
1676 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1678 if (constant_value
) {
1679 /* Special case: emit the varying write
1680 * directly to r26 (looks funny in asm but it's
1681 * fine) and emit the store _now_. Possibly
1682 * slightly slower, but this is a really stupid
1683 * special case anyway (why on earth would you
1684 * have a constant varying? Your own fault for
1685 * slightly worse perf :P) */
1687 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1688 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1689 emit_mir_instruction(ctx
, ins
);
1691 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1692 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1693 emit_mir_instruction(ctx
, st
);
1695 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1697 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1700 DBG("Unknown store\n");
1706 case nir_intrinsic_load_alpha_ref_float
:
1707 assert(instr
->dest
.is_ssa
);
1709 float ref_value
= ctx
->alpha_ref
;
1711 float *v
= ralloc_array(NULL
, float, 4);
1712 memcpy(v
, &ref_value
, sizeof(float));
1713 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1716 case nir_intrinsic_load_viewport_scale
:
1717 case nir_intrinsic_load_viewport_offset
:
1718 emit_sysval_read(ctx
, instr
);
1722 printf ("Unhandled intrinsic\n");
1729 midgard_tex_format(enum glsl_sampler_dim dim
)
1732 case GLSL_SAMPLER_DIM_2D
:
1733 case GLSL_SAMPLER_DIM_EXTERNAL
:
1736 case GLSL_SAMPLER_DIM_3D
:
1739 case GLSL_SAMPLER_DIM_CUBE
:
1740 return TEXTURE_CUBE
;
1743 DBG("Unknown sampler dim type\n");
1750 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1753 //assert (!instr->sampler);
1754 //assert (!instr->texture_array_size);
1755 assert (instr
->op
== nir_texop_tex
);
1757 /* Allocate registers via a round robin scheme to alternate between the two registers */
1758 int reg
= ctx
->texture_op_count
& 1;
1759 int in_reg
= reg
, out_reg
= reg
;
1761 /* Make room for the reg */
1763 if (ctx
->texture_index
[reg
] > -1)
1764 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1766 int texture_index
= instr
->texture_index
;
1767 int sampler_index
= texture_index
;
1769 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1770 switch (instr
->src
[i
].src_type
) {
1771 case nir_tex_src_coord
: {
1772 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1774 midgard_vector_alu_src alu_src
= blank_alu_src
;
1776 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1778 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1779 /* For cubemaps, we need to load coords into
1780 * special r27, and then use a special ld/st op
1781 * to copy into the texture register */
1783 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1785 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1786 emit_mir_instruction(ctx
, move
);
1788 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1789 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1790 st
.load_store
.mask
= 0x3; /* xy? */
1791 st
.load_store
.swizzle
= alu_src
.swizzle
;
1792 emit_mir_instruction(ctx
, st
);
1795 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1797 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1798 emit_mir_instruction(ctx
, ins
);
1805 DBG("Unknown source type\n");
1812 /* No helper to build texture words -- we do it all here */
1813 midgard_instruction ins
= {
1814 .type
= TAG_TEXTURE_4
,
1816 .op
= TEXTURE_OP_NORMAL
,
1817 .format
= midgard_tex_format(instr
->sampler_dim
),
1818 .texture_handle
= texture_index
,
1819 .sampler_handle
= sampler_index
,
1821 /* TODO: Don't force xyzw */
1822 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1834 /* Assume we can continue; hint it out later */
1839 /* Set registers to read and write from the same place */
1840 ins
.texture
.in_reg_select
= in_reg
;
1841 ins
.texture
.out_reg_select
= out_reg
;
1843 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1844 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1845 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1846 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1847 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1849 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1850 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1851 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1854 emit_mir_instruction(ctx
, ins
);
1856 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1858 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1859 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1860 ctx
->texture_index
[reg
] = o_index
;
1862 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1863 emit_mir_instruction(ctx
, ins2
);
1865 /* Used for .cont and .last hinting */
1866 ctx
->texture_op_count
++;
1870 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1872 switch (instr
->type
) {
1873 case nir_jump_break
: {
1874 /* Emit a branch out of the loop */
1875 struct midgard_instruction br
= v_branch(false, false);
1876 br
.branch
.target_type
= TARGET_BREAK
;
1877 br
.branch
.target_break
= ctx
->current_loop_depth
;
1878 emit_mir_instruction(ctx
, br
);
1885 DBG("Unknown jump type %d\n", instr
->type
);
1891 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1893 switch (instr
->type
) {
1894 case nir_instr_type_load_const
:
1895 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1898 case nir_instr_type_intrinsic
:
1899 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1902 case nir_instr_type_alu
:
1903 emit_alu(ctx
, nir_instr_as_alu(instr
));
1906 case nir_instr_type_tex
:
1907 emit_tex(ctx
, nir_instr_as_tex(instr
));
1910 case nir_instr_type_jump
:
1911 emit_jump(ctx
, nir_instr_as_jump(instr
));
1914 case nir_instr_type_ssa_undef
:
1919 DBG("Unhandled instruction type\n");
1924 /* Determine the actual hardware from the index based on the RA results or special values */
1927 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1929 if (reg
>= SSA_FIXED_MINIMUM
)
1930 return SSA_REG_FROM_FIXED(reg
);
1933 assert(reg
< maxreg
);
1934 int r
= ra_get_node_reg(g
, reg
);
1935 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1940 /* fmov style unused */
1942 return REGISTER_UNUSED
;
1944 /* lut style unused */
1946 return REGISTER_UNUSED
;
1949 DBG("Unknown SSA register alias %d\n", reg
);
1956 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1958 /* Choose the first available register to minimise reported register pressure */
1960 for (int i
= 0; i
< 16; ++i
) {
1961 if (BITSET_TEST(regs
, i
)) {
1971 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1973 if (ins
->ssa_args
.src0
== src
) return true;
1974 if (ins
->ssa_args
.src1
== src
) return true;
1979 /* Determine if a variable is live in the successors of a block */
1981 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
1983 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
1984 midgard_block
*succ
= bl
->successors
[i
];
1986 /* If we already visited, the value we're seeking
1987 * isn't down this path (or we would have short
1990 if (succ
->visited
) continue;
1992 /* Otherwise (it's visited *now*), check the block */
1994 succ
->visited
= true;
1996 mir_foreach_instr_in_block(succ
, ins
) {
1997 if (midgard_is_live_in_instr(ins
, src
))
2001 /* ...and also, check *its* successors */
2002 if (is_live_after_successors(ctx
, succ
, src
))
2007 /* Welp. We're really not live. */
2013 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
2015 /* Check the rest of the block for liveness */
2017 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
2018 if (midgard_is_live_in_instr(ins
, src
))
2022 /* Check the rest of the blocks for liveness recursively */
2024 bool succ
= is_live_after_successors(ctx
, block
, src
);
2026 mir_foreach_block(ctx
, block
) {
2027 block
->visited
= false;
2034 allocate_registers(compiler_context
*ctx
)
2036 /* First, initialize the RA */
2037 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
2039 /* Create a primary (general purpose) class, as well as special purpose
2040 * pipeline register classes */
2042 int primary_class
= ra_alloc_reg_class(regs
);
2043 int varying_class
= ra_alloc_reg_class(regs
);
2045 /* Add the full set of work registers */
2046 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
2047 for (int i
= 0; i
< work_count
; ++i
)
2048 ra_class_add_reg(regs
, primary_class
, i
);
2050 /* Add special registers */
2051 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
2052 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
2054 /* We're done setting up */
2055 ra_set_finalize(regs
, NULL
);
2057 /* Transform the MIR into squeezed index form */
2058 mir_foreach_block(ctx
, block
) {
2059 mir_foreach_instr_in_block(block
, ins
) {
2060 if (ins
->compact_branch
) continue;
2062 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
2063 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
2064 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
2066 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2067 print_mir_block(block
);
2070 if (!ctx
->temp_count
)
2073 /* Let's actually do register allocation */
2074 int nodes
= ctx
->temp_count
;
2075 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
2077 /* Set everything to the work register class, unless it has somewhere
2080 mir_foreach_block(ctx
, block
) {
2081 mir_foreach_instr_in_block(block
, ins
) {
2082 if (ins
->compact_branch
) continue;
2084 if (ins
->ssa_args
.dest
< 0) continue;
2086 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2088 int class = primary_class
;
2090 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2094 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2095 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2098 unsigned reg
= temp
- 1;
2099 int t
= find_or_allocate_temp(ctx
, index
);
2100 ra_set_node_reg(g
, t
, reg
);
2104 /* Determine liveness */
2106 int *live_start
= malloc(nodes
* sizeof(int));
2107 int *live_end
= malloc(nodes
* sizeof(int));
2109 /* Initialize as non-existent */
2111 for (int i
= 0; i
< nodes
; ++i
) {
2112 live_start
[i
] = live_end
[i
] = -1;
2117 mir_foreach_block(ctx
, block
) {
2118 mir_foreach_instr_in_block(block
, ins
) {
2119 if (ins
->compact_branch
) continue;
2121 /* Dest is < 0 for store_vary instructions, which break
2122 * the usual SSA conventions. Liveness analysis doesn't
2123 * make sense on these instructions, so skip them to
2124 * avoid memory corruption */
2126 if (ins
->ssa_args
.dest
< 0) continue;
2128 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2129 /* If this destination is not yet live, it is now since we just wrote it */
2131 int dest
= ins
->ssa_args
.dest
;
2133 if (live_start
[dest
] == -1)
2134 live_start
[dest
] = d
;
2137 /* Since we just used a source, the source might be
2138 * dead now. Scan the rest of the block for
2139 * invocations, and if there are none, the source dies
2142 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2144 for (int src
= 0; src
< 2; ++src
) {
2145 int s
= sources
[src
];
2147 if (s
< 0) continue;
2149 if (s
>= SSA_FIXED_MINIMUM
) continue;
2151 if (!is_live_after(ctx
, block
, ins
, s
)) {
2160 /* If a node still hasn't been killed, kill it now */
2162 for (int i
= 0; i
< nodes
; ++i
) {
2163 /* live_start == -1 most likely indicates a pinned output */
2165 if (live_end
[i
] == -1)
2169 /* Setup interference between nodes that are live at the same time */
2171 for (int i
= 0; i
< nodes
; ++i
) {
2172 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2173 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2174 ra_add_node_interference(g
, i
, j
);
2178 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2180 if (!ra_allocate(g
)) {
2181 DBG("Error allocating registers\n");
2189 mir_foreach_block(ctx
, block
) {
2190 mir_foreach_instr_in_block(block
, ins
) {
2191 if (ins
->compact_branch
) continue;
2193 ssa_args args
= ins
->ssa_args
;
2195 switch (ins
->type
) {
2197 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2199 ins
->registers
.src2_imm
= args
.inline_constant
;
2201 if (args
.inline_constant
) {
2202 /* Encode inline 16-bit constant as a vector by default */
2204 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2206 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2208 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2209 ins
->alu
.src2
= imm
<< 2;
2211 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2214 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2218 case TAG_LOAD_STORE_4
: {
2219 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2220 /* TODO: use ssa_args for store_vary */
2221 ins
->load_store
.reg
= 0;
2223 bool has_dest
= args
.dest
>= 0;
2224 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2226 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2239 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2240 * use scalar ALU instructions, for functional or performance reasons. To do
2241 * this, we just demote vector ALU payloads to scalar. */
2244 component_from_mask(unsigned mask
)
2246 for (int c
= 0; c
< 4; ++c
) {
2247 if (mask
& (3 << (2 * c
)))
2256 is_single_component_mask(unsigned mask
)
2260 for (int c
= 0; c
< 4; ++c
)
2261 if (mask
& (3 << (2 * c
)))
2264 return components
== 1;
2267 /* Create a mask of accessed components from a swizzle to figure out vector
2271 swizzle_to_access_mask(unsigned swizzle
)
2273 unsigned component_mask
= 0;
2275 for (int i
= 0; i
< 4; ++i
) {
2276 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2277 component_mask
|= (1 << c
);
2280 return component_mask
;
2284 vector_to_scalar_source(unsigned u
, bool is_int
)
2286 midgard_vector_alu_src v
;
2287 memcpy(&v
, &u
, sizeof(v
));
2289 /* TODO: Integers */
2291 midgard_scalar_alu_src s
= {
2293 .component
= (v
.swizzle
& 3) << 1
2299 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
2300 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
2304 memcpy(&o
, &s
, sizeof(s
));
2306 return o
& ((1 << 6) - 1);
2309 static midgard_scalar_alu
2310 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2312 bool is_int
= midgard_is_integer_op(v
.op
);
2314 /* The output component is from the mask */
2315 midgard_scalar_alu s
= {
2317 .src1
= vector_to_scalar_source(v
.src1
, is_int
),
2318 .src2
= vector_to_scalar_source(v
.src2
, is_int
),
2321 .output_full
= 1, /* TODO: Half */
2322 .output_component
= component_from_mask(v
.mask
) << 1,
2325 /* Inline constant is passed along rather than trying to extract it
2328 if (ins
->ssa_args
.inline_constant
) {
2330 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2331 imm
|= (lower_11
>> 9) & 3;
2332 imm
|= (lower_11
>> 6) & 4;
2333 imm
|= (lower_11
>> 2) & 0x38;
2334 imm
|= (lower_11
& 63) << 6;
2342 /* Midgard prefetches instruction types, so during emission we need to
2343 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2344 * if this is the second to last and the last is an ALU, then it's also 1... */
2346 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2347 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2349 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2350 bytes_emitted += sizeof(type)
2353 emit_binary_vector_instruction(midgard_instruction
*ains
,
2354 uint16_t *register_words
, int *register_words_count
,
2355 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2356 size_t *bytes_emitted
)
2358 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2359 *bytes_emitted
+= sizeof(midgard_reg_info
);
2361 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2362 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2363 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2366 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2367 * mind that we are a vector architecture and we can write to different
2368 * components simultaneously */
2371 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2373 /* Each instruction reads some registers and writes to a register. See
2374 * where the first writes */
2376 /* Figure out where exactly we wrote to */
2377 int source
= first
->ssa_args
.dest
;
2378 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2380 /* As long as the second doesn't read from the first, we're okay */
2381 if (second
->ssa_args
.src0
== source
) {
2382 if (first
->type
== TAG_ALU_4
) {
2383 /* Figure out which components we just read from */
2385 int q
= second
->alu
.src1
;
2386 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2388 /* Check if there are components in common, and fail if so */
2389 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2396 if (second
->ssa_args
.src1
== source
)
2399 /* Otherwise, it's safe in that regard. Another data hazard is both
2400 * writing to the same place, of course */
2402 if (second
->ssa_args
.dest
== source
) {
2403 /* ...but only if the components overlap */
2404 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2406 if (dest_mask
& source_mask
)
2416 midgard_instruction
**segment
, unsigned segment_size
,
2417 midgard_instruction
*ains
)
2419 for (int s
= 0; s
< segment_size
; ++s
)
2420 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2428 /* Schedules, but does not emit, a single basic block. After scheduling, the
2429 * final tag and size of the block are known, which are necessary for branching
2432 static midgard_bundle
2433 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2435 int instructions_emitted
= 0, instructions_consumed
= -1;
2436 midgard_bundle bundle
= { 0 };
2438 uint8_t tag
= ins
->type
;
2440 /* Default to the instruction's tag */
2443 switch (ins
->type
) {
2445 uint32_t control
= 0;
2446 size_t bytes_emitted
= sizeof(control
);
2448 /* TODO: Constant combining */
2449 int index
= 0, last_unit
= 0;
2451 /* Previous instructions, for the purpose of parallelism */
2452 midgard_instruction
*segment
[4] = {0};
2453 int segment_size
= 0;
2455 instructions_emitted
= -1;
2456 midgard_instruction
*pins
= ins
;
2459 midgard_instruction
*ains
= pins
;
2461 /* Advance instruction pointer */
2463 ains
= mir_next_op(pins
);
2467 /* Out-of-work condition */
2468 if ((struct list_head
*) ains
== &block
->instructions
)
2471 /* Ensure that the chain can continue */
2472 if (ains
->type
!= TAG_ALU_4
) break;
2474 /* According to the presentation "The ARM
2475 * Mali-T880 Mobile GPU" from HotChips 27,
2476 * there are two pipeline stages. Branching
2477 * position determined experimentally. Lines
2478 * are executed in parallel:
2481 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2483 * Verify that there are no ordering dependencies here.
2485 * TODO: Allow for parallelism!!!
2488 /* Pick a unit for it if it doesn't force a particular unit */
2490 int unit
= ains
->unit
;
2493 int op
= ains
->alu
.op
;
2494 int units
= alu_opcode_props
[op
].props
;
2496 /* TODO: Promotion of scalars to vectors */
2497 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2500 assert(units
& UNITS_SCALAR
);
2503 if (last_unit
>= UNIT_VADD
) {
2504 if (units
& UNIT_VLUT
)
2509 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2511 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2513 else if (units
& UNIT_VLUT
)
2519 if (last_unit
>= UNIT_VADD
) {
2520 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2522 else if (units
& UNIT_VLUT
)
2527 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2529 else if (units
& UNIT_SMUL
)
2530 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2531 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2538 assert(unit
& units
);
2541 /* Late unit check, this time for encoding (not parallelism) */
2542 if (unit
<= last_unit
) break;
2544 /* Clear the segment */
2545 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2548 if (midgard_has_hazard(segment
, segment_size
, ains
))
2551 /* We're good to go -- emit the instruction */
2554 segment
[segment_size
++] = ains
;
2556 /* Only one set of embedded constants per
2557 * bundle possible; if we have more, we must
2558 * break the chain early, unfortunately */
2560 if (ains
->has_constants
) {
2561 if (bundle
.has_embedded_constants
) {
2562 /* ...but if there are already
2563 * constants but these are the
2564 * *same* constants, we let it
2567 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2570 bundle
.has_embedded_constants
= true;
2571 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2573 /* If this is a blend shader special constant, track it for patching */
2574 if (ains
->has_blend_constant
)
2575 bundle
.has_blend_constant
= true;
2579 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2580 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2581 &bundle
.register_words_count
, bundle
.body_words
,
2582 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2583 } else if (ains
->compact_branch
) {
2584 /* All of r0 has to be written out
2585 * along with the branch writeout.
2588 if (ains
->writeout
) {
2590 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2591 ins
.unit
= UNIT_VMUL
;
2593 control
|= ins
.unit
;
2595 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2596 &bundle
.register_words_count
, bundle
.body_words
,
2597 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2599 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2600 bool written_late
= false;
2601 bool components
[4] = { 0 };
2602 uint16_t register_dep_mask
= 0;
2603 uint16_t written_mask
= 0;
2605 midgard_instruction
*qins
= ins
;
2606 for (int t
= 0; t
< index
; ++t
) {
2607 if (qins
->registers
.out_reg
!= 0) {
2608 /* Mark down writes */
2610 written_mask
|= (1 << qins
->registers
.out_reg
);
2612 /* Mark down the register dependencies for errata check */
2614 if (qins
->registers
.src1_reg
< 16)
2615 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2617 if (qins
->registers
.src2_reg
< 16)
2618 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2620 int mask
= qins
->alu
.mask
;
2622 for (int c
= 0; c
< 4; ++c
)
2623 if (mask
& (0x3 << (2 * c
)))
2624 components
[c
] = true;
2626 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2628 if (qins
->unit
== UNIT_VLUT
)
2629 written_late
= true;
2632 /* Advance instruction pointer */
2633 qins
= mir_next_op(qins
);
2637 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2638 if (register_dep_mask
& written_mask
) {
2639 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2646 /* If even a single component is not written, break it up (conservative check). */
2647 bool breakup
= false;
2649 for (int c
= 0; c
< 4; ++c
)
2656 /* Otherwise, we're free to proceed */
2660 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2661 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2662 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2663 bytes_emitted
+= sizeof(midgard_branch_extended
);
2665 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2666 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2667 bytes_emitted
+= sizeof(ains
->br_compact
);
2670 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2671 bytes_emitted
+= sizeof(midgard_reg_info
);
2673 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2674 bundle
.body_words_count
++;
2675 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2678 /* Defer marking until after writing to allow for break */
2679 control
|= ains
->unit
;
2680 last_unit
= ains
->unit
;
2681 ++instructions_emitted
;
2685 /* Bubble up the number of instructions for skipping */
2686 instructions_consumed
= index
- 1;
2690 /* Pad ALU op to nearest word */
2692 if (bytes_emitted
& 15) {
2693 padding
= 16 - (bytes_emitted
& 15);
2694 bytes_emitted
+= padding
;
2697 /* Constants must always be quadwords */
2698 if (bundle
.has_embedded_constants
)
2699 bytes_emitted
+= 16;
2701 /* Size ALU instruction for tag */
2702 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2703 bundle
.padding
= padding
;
2704 bundle
.control
= bundle
.tag
| control
;
2709 case TAG_LOAD_STORE_4
: {
2710 /* Load store instructions have two words at once. If
2711 * we only have one queued up, we need to NOP pad.
2712 * Otherwise, we store both in succession to save space
2713 * and cycles -- letting them go in parallel -- skip
2714 * the next. The usefulness of this optimisation is
2715 * greatly dependent on the quality of the instruction
2719 midgard_instruction
*next_op
= mir_next_op(ins
);
2721 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2722 /* As the two operate concurrently, make sure
2723 * they are not dependent */
2725 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2726 /* Skip ahead, since it's redundant with the pair */
2727 instructions_consumed
= 1 + (instructions_emitted
++);
2735 /* Texture ops default to single-op-per-bundle scheduling */
2739 /* Copy the instructions into the bundle */
2740 bundle
.instruction_count
= instructions_emitted
+ 1;
2744 midgard_instruction
*uins
= ins
;
2745 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2746 bundle
.instructions
[used_idx
++] = *uins
;
2747 uins
= mir_next_op(uins
);
2750 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2756 quadword_size(int tag
)
2771 case TAG_LOAD_STORE_4
:
2783 /* Schedule a single block by iterating its instruction to create bundles.
2784 * While we go, tally about the bundle sizes to compute the block size. */
2787 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2789 util_dynarray_init(&block
->bundles
, NULL
);
2791 block
->quadword_count
= 0;
2793 mir_foreach_instr_in_block(block
, ins
) {
2795 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2796 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2798 if (bundle
.has_blend_constant
) {
2799 /* TODO: Multiblock? */
2800 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2801 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2805 ins
= mir_next_op(ins
);
2807 block
->quadword_count
+= quadword_size(bundle
.tag
);
2810 block
->is_scheduled
= true;
2814 schedule_program(compiler_context
*ctx
)
2816 allocate_registers(ctx
);
2818 mir_foreach_block(ctx
, block
) {
2819 schedule_block(ctx
, block
);
2823 /* After everything is scheduled, emit whole bundles at a time */
2826 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2828 int lookahead
= next_tag
<< 4;
2830 switch (bundle
->tag
) {
2835 /* Actually emit each component */
2836 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2838 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2839 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2841 /* Emit body words based on the instructions bundled */
2842 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2843 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2845 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2846 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2847 } else if (ins
->compact_branch
) {
2848 /* Dummy move, XXX DRY */
2849 if ((i
== 0) && ins
->writeout
) {
2850 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2851 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2854 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2855 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2857 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2861 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2862 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2866 /* Emit padding (all zero) */
2867 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2869 /* Tack on constants */
2871 if (bundle
->has_embedded_constants
) {
2872 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2873 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2874 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2875 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2881 case TAG_LOAD_STORE_4
: {
2882 /* One or two composing instructions */
2884 uint64_t current64
, next64
= LDST_NOP
;
2886 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2888 if (bundle
->instruction_count
== 2)
2889 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2891 midgard_load_store instruction
= {
2892 .type
= bundle
->tag
,
2893 .next_type
= next_tag
,
2898 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2903 case TAG_TEXTURE_4
: {
2904 /* Texture instructions are easy, since there is no
2905 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2907 midgard_instruction
*ins
= &bundle
->instructions
[0];
2909 ins
->texture
.type
= TAG_TEXTURE_4
;
2910 ins
->texture
.next_type
= next_tag
;
2912 ctx
->texture_op_count
--;
2914 if (!ctx
->texture_op_count
) {
2915 ins
->texture
.cont
= 0;
2916 ins
->texture
.last
= 1;
2919 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2924 DBG("Unknown midgard instruction type\n");
2931 /* ALU instructions can inline or embed constants, which decreases register
2932 * pressure and saves space. */
2934 #define CONDITIONAL_ATTACH(src) { \
2935 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2938 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2939 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2944 inline_alu_constants(compiler_context
*ctx
)
2946 mir_foreach_instr(ctx
, alu
) {
2947 /* Other instructions cannot inline constants */
2948 if (alu
->type
!= TAG_ALU_4
) continue;
2950 /* If there is already a constant here, we can do nothing */
2951 if (alu
->has_constants
) continue;
2953 /* It makes no sense to inline constants on a branch */
2954 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2956 CONDITIONAL_ATTACH(src0
);
2958 if (!alu
->has_constants
) {
2959 CONDITIONAL_ATTACH(src1
)
2960 } else if (!alu
->inline_constant
) {
2961 /* Corner case: _two_ vec4 constants, for instance with a
2962 * csel. For this case, we can only use a constant
2963 * register for one, we'll have to emit a move for the
2964 * other. Note, if both arguments are constants, then
2965 * necessarily neither argument depends on the value of
2966 * any particular register. As the destination register
2967 * will be wiped, that means we can spill the constant
2968 * to the destination register.
2971 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2972 unsigned scratch
= alu
->ssa_args
.dest
;
2975 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2976 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2978 /* Force a break XXX Defer r31 writes */
2979 ins
.unit
= UNIT_VLUT
;
2981 /* Set the source */
2982 alu
->ssa_args
.src1
= scratch
;
2984 /* Inject us -before- the last instruction which set r31 */
2985 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2991 /* Midgard supports two types of constants, embedded constants (128-bit) and
2992 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2993 * constants can be demoted to inline constants, for space savings and
2994 * sometimes a performance boost */
2997 embedded_to_inline_constant(compiler_context
*ctx
)
2999 mir_foreach_instr(ctx
, ins
) {
3000 if (!ins
->has_constants
) continue;
3002 if (ins
->ssa_args
.inline_constant
) continue;
3004 /* Blend constants must not be inlined by definition */
3005 if (ins
->has_blend_constant
) continue;
3007 /* src1 cannot be an inline constant due to encoding
3008 * restrictions. So, if possible we try to flip the arguments
3011 int op
= ins
->alu
.op
;
3013 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3015 /* These ops require an operational change to flip
3016 * their arguments TODO */
3017 case midgard_alu_op_flt
:
3018 case midgard_alu_op_fle
:
3019 case midgard_alu_op_ilt
:
3020 case midgard_alu_op_ile
:
3021 case midgard_alu_op_fcsel
:
3022 case midgard_alu_op_icsel
:
3023 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
3028 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
3029 /* Flip the SSA numbers */
3030 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
3031 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
3033 /* And flip the modifiers */
3037 src_temp
= ins
->alu
.src2
;
3038 ins
->alu
.src2
= ins
->alu
.src1
;
3039 ins
->alu
.src1
= src_temp
;
3043 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3044 /* Extract the source information */
3046 midgard_vector_alu_src
*src
;
3047 int q
= ins
->alu
.src2
;
3048 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
3051 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
3052 int component
= src
->swizzle
& 3;
3054 /* Scale constant appropriately, if we can legally */
3055 uint16_t scaled_constant
= 0;
3057 /* XXX: Check legality */
3058 if (midgard_is_integer_op(op
)) {
3059 /* TODO: Inline integer */
3062 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
3063 scaled_constant
= (uint16_t) iconstants
[component
];
3065 /* Constant overflow after resize */
3066 if (scaled_constant
!= iconstants
[component
])
3069 float original
= (float) ins
->constants
[component
];
3070 scaled_constant
= _mesa_float_to_half(original
);
3072 /* Check for loss of precision. If this is
3073 * mediump, we don't care, but for a highp
3074 * shader, we need to pay attention. NIR
3075 * doesn't yet tell us which mode we're in!
3076 * Practically this prevents most constants
3077 * from being inlined, sadly. */
3079 float fp32
= _mesa_half_to_float(scaled_constant
);
3081 if (fp32
!= original
)
3085 /* We don't know how to handle these with a constant */
3087 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
3088 DBG("Bailing inline constant...\n");
3092 /* Make sure that the constant is not itself a
3093 * vector by checking if all accessed values
3094 * (by the swizzle) are the same. */
3096 uint32_t *cons
= (uint32_t *) ins
->constants
;
3097 uint32_t value
= cons
[component
];
3099 bool is_vector
= false;
3100 unsigned mask
= effective_writemask(&ins
->alu
);
3102 for (int c
= 1; c
< 4; ++c
) {
3103 /* We only care if this component is actually used */
3104 if (!(mask
& (1 << c
)))
3107 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3109 if (test
!= value
) {
3118 /* Get rid of the embedded constant */
3119 ins
->has_constants
= false;
3120 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3121 ins
->ssa_args
.inline_constant
= true;
3122 ins
->inline_constant
= scaled_constant
;
3127 /* Map normal SSA sources to other SSA sources / fixed registers (like
3131 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3133 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3136 /* Remove entry in leftovers to avoid a redunant fmov */
3138 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3141 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3143 /* Assign the alias map */
3149 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3150 * texture pipeline */
3153 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3155 bool progress
= false;
3157 mir_foreach_instr_in_block_safe(block
, ins
) {
3158 if (ins
->type
!= TAG_ALU_4
) continue;
3159 if (ins
->compact_branch
) continue;
3161 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3162 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3163 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3165 mir_remove_instruction(ins
);
3173 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
3175 bool progress
= false;
3177 mir_foreach_instr_in_block_safe(block
, ins
) {
3178 if (ins
->type
!= TAG_ALU_4
) continue;
3179 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3181 unsigned from
= ins
->ssa_args
.src1
;
3182 unsigned to
= ins
->ssa_args
.dest
;
3184 /* We only work on pure SSA */
3186 if (to
>= SSA_FIXED_MINIMUM
) continue;
3187 if (from
>= SSA_FIXED_MINIMUM
) continue;
3188 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
3189 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
3191 /* Also, if the move has side effects, we're helpless */
3193 midgard_vector_alu_src src
=
3194 vector_alu_from_unsigned(ins
->alu
.src2
);
3195 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
3196 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
3198 if (mir_nontrivial_mod(src
, is_int
, mask
)) continue;
3199 if (ins
->alu
.outmod
!= midgard_outmod_none
) continue;
3201 mir_foreach_instr_in_block_from(block
, v
, mir_next_op(ins
)) {
3202 if (v
->ssa_args
.src0
== to
) {
3203 v
->ssa_args
.src0
= from
;
3207 if (v
->ssa_args
.src1
== to
&& !v
->ssa_args
.inline_constant
) {
3208 v
->ssa_args
.src1
= from
;
3218 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
3220 bool progress
= false;
3222 mir_foreach_instr_in_block_safe(block
, ins
) {
3223 if (ins
->type
!= TAG_ALU_4
) continue;
3224 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3226 unsigned from
= ins
->ssa_args
.src1
;
3227 unsigned to
= ins
->ssa_args
.dest
;
3229 /* Make sure it's simple enough for us to handle */
3231 if (from
>= SSA_FIXED_MINIMUM
) continue;
3232 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
3233 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
3234 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
3236 bool eliminated
= false;
3238 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
3239 /* The texture registers are not SSA so be careful.
3240 * Conservatively, just stop if we hit a texture op
3241 * (even if it may not write) to where we are */
3243 if (v
->type
!= TAG_ALU_4
)
3246 if (v
->ssa_args
.dest
== from
) {
3247 /* We don't want to track partial writes ... */
3248 if (v
->alu
.mask
== 0xF) {
3249 v
->ssa_args
.dest
= to
;
3258 mir_remove_instruction(ins
);
3260 progress
|= eliminated
;
3266 /* We don't really understand the imov/fmov split, so always use fmov (but let
3267 * it be imov in the IR so we don't do unsafe floating point "optimizations"
3268 * and break things */
3271 midgard_imov_workaround(compiler_context
*ctx
, midgard_block
*block
)
3273 mir_foreach_instr_in_block_safe(block
, ins
) {
3274 if (ins
->type
!= TAG_ALU_4
) continue;
3275 if (ins
->alu
.op
!= midgard_alu_op_imov
) continue;
3277 ins
->alu
.op
= midgard_alu_op_fmov
;
3278 ins
->alu
.outmod
= midgard_outmod_none
;
3280 /* Remove flags that don't make sense */
3282 midgard_vector_alu_src s
=
3283 vector_alu_from_unsigned(ins
->alu
.src2
);
3287 ins
->alu
.src2
= vector_alu_srco_unsigned(s
);
3291 /* The following passes reorder MIR instructions to enable better scheduling */
3294 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3296 mir_foreach_instr_in_block_safe(block
, ins
) {
3297 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3299 /* We've found a load/store op. Check if next is also load/store. */
3300 midgard_instruction
*next_op
= mir_next_op(ins
);
3301 if (&next_op
->link
!= &block
->instructions
) {
3302 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3303 /* If so, we're done since we're a pair */
3304 ins
= mir_next_op(ins
);
3308 /* Maximum search distance to pair, to avoid register pressure disasters */
3309 int search_distance
= 8;
3311 /* Otherwise, we have an orphaned load/store -- search for another load */
3312 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3313 /* Terminate search if necessary */
3314 if (!(search_distance
--)) break;
3316 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3318 /* Stores cannot be reordered, since they have
3319 * dependencies. For the same reason, indirect
3320 * loads cannot be reordered as their index is
3321 * loaded in r27.w */
3323 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3325 /* It appears the 0x800 bit is set whenever a
3326 * load is direct, unset when it is indirect.
3327 * Skip indirect loads. */
3329 if (!(c
->load_store
.unknown
& 0x800)) continue;
3331 /* We found one! Move it up to pair and remove it from the old location */
3333 mir_insert_instruction_before(ins
, *c
);
3334 mir_remove_instruction(c
);
3342 /* Emit varying stores late */
3345 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3346 /* Iterate in reverse to get the final write, rather than the first */
3348 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3349 /* Check if what we just wrote needs a store */
3350 int idx
= ins
->ssa_args
.dest
;
3351 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3353 if (!varying
) continue;
3357 /* We need to store to the appropriate varying, so emit the
3360 /* TODO: Integrate with special purpose RA (and scheduler?) */
3361 bool high_varying_register
= false;
3363 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3365 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3366 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3368 mir_insert_instruction_before(mir_next_op(ins
), st
);
3369 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3371 /* We no longer need to store this varying */
3372 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3376 /* If there are leftovers after the below pass, emit actual fmov
3377 * instructions for the slow-but-correct path */
3380 emit_leftover_move(compiler_context
*ctx
)
3382 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3383 int base
= ((uintptr_t) leftover
->key
) - 1;
3386 map_ssa_to_alias(ctx
, &mapped
);
3387 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3392 actualise_ssa_to_alias(compiler_context
*ctx
)
3394 mir_foreach_instr(ctx
, ins
) {
3395 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3396 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3399 emit_leftover_move(ctx
);
3403 emit_fragment_epilogue(compiler_context
*ctx
)
3405 /* Special case: writing out constants requires us to include the move
3406 * explicitly now, so shove it into r0 */
3408 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3410 if (constant_value
) {
3411 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3412 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3413 emit_mir_instruction(ctx
, ins
);
3416 /* Perform the actual fragment writeout. We have two writeout/branch
3417 * instructions, forming a loop until writeout is successful as per the
3418 * docs. TODO: gl_FragDepth */
3420 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3421 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3424 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3425 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3426 * with the int8 analogue to the fragment epilogue */
3429 emit_blend_epilogue(compiler_context
*ctx
)
3431 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3433 midgard_instruction scale
= {
3436 .inline_constant
= _mesa_float_to_half(255.0),
3438 .src0
= SSA_FIXED_REGISTER(0),
3439 .src1
= SSA_UNUSED_0
,
3440 .dest
= SSA_FIXED_REGISTER(24),
3441 .inline_constant
= true
3444 .op
= midgard_alu_op_fmul
,
3445 .reg_mode
= midgard_reg_mode_32
,
3446 .dest_override
= midgard_dest_override_lower
,
3448 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3449 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3453 emit_mir_instruction(ctx
, scale
);
3455 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3457 midgard_vector_alu_src alu_src
= blank_alu_src
;
3458 alu_src
.half
= true;
3460 midgard_instruction f2u8
= {
3463 .src0
= SSA_FIXED_REGISTER(24),
3464 .src1
= SSA_UNUSED_0
,
3465 .dest
= SSA_FIXED_REGISTER(0),
3466 .inline_constant
= true
3469 .op
= midgard_alu_op_f2u8
,
3470 .reg_mode
= midgard_reg_mode_16
,
3471 .dest_override
= midgard_dest_override_lower
,
3472 .outmod
= midgard_outmod_pos
,
3474 .src1
= vector_alu_srco_unsigned(alu_src
),
3475 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3479 emit_mir_instruction(ctx
, f2u8
);
3481 /* vmul.imov.quarter r0, r0, r0 */
3483 midgard_instruction imov_8
= {
3486 .src0
= SSA_UNUSED_1
,
3487 .src1
= SSA_FIXED_REGISTER(0),
3488 .dest
= SSA_FIXED_REGISTER(0),
3491 .op
= midgard_alu_op_imov
,
3492 .reg_mode
= midgard_reg_mode_8
,
3493 .dest_override
= midgard_dest_override_none
,
3495 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3496 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3500 /* Emit branch epilogue with the 8-bit move as the source */
3502 emit_mir_instruction(ctx
, imov_8
);
3503 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3505 emit_mir_instruction(ctx
, imov_8
);
3506 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3509 static midgard_block
*
3510 emit_block(compiler_context
*ctx
, nir_block
*block
)
3512 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3513 list_addtail(&this_block
->link
, &ctx
->blocks
);
3515 this_block
->is_scheduled
= false;
3518 ctx
->texture_index
[0] = -1;
3519 ctx
->texture_index
[1] = -1;
3521 /* Add us as a successor to the block we are following */
3522 if (ctx
->current_block
)
3523 midgard_block_add_successor(ctx
->current_block
, this_block
);
3525 /* Set up current block */
3526 list_inithead(&this_block
->instructions
);
3527 ctx
->current_block
= this_block
;
3529 nir_foreach_instr(instr
, block
) {
3530 emit_instr(ctx
, instr
);
3531 ++ctx
->instruction_count
;
3534 inline_alu_constants(ctx
);
3535 embedded_to_inline_constant(ctx
);
3537 /* Perform heavylifting for aliasing */
3538 actualise_ssa_to_alias(ctx
);
3540 midgard_emit_store(ctx
, this_block
);
3541 midgard_pair_load_store(ctx
, this_block
);
3542 midgard_imov_workaround(ctx
, this_block
);
3544 /* Append fragment shader epilogue (value writeout) */
3545 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3546 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3548 emit_blend_epilogue(ctx
);
3550 emit_fragment_epilogue(ctx
);
3554 if (block
== nir_start_block(ctx
->func
->impl
))
3555 ctx
->initial_block
= this_block
;
3557 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3558 ctx
->final_block
= this_block
;
3560 /* Allow the next control flow to access us retroactively, for
3562 ctx
->current_block
= this_block
;
3564 /* Document the fallthrough chain */
3565 ctx
->previous_source_block
= this_block
;
3570 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3573 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3575 /* Conditional branches expect the condition in r31.w; emit a move for
3576 * that in the _previous_ block (which is the current block). */
3577 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3579 /* Speculatively emit the branch, but we can't fill it in until later */
3580 EMIT(branch
, true, true);
3581 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3583 /* Emit the two subblocks */
3584 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3586 /* Emit a jump from the end of the then block to the end of the else */
3587 EMIT(branch
, false, false);
3588 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3590 /* Emit second block, and check if it's empty */
3592 int else_idx
= ctx
->block_count
;
3593 int count_in
= ctx
->instruction_count
;
3594 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3595 int after_else_idx
= ctx
->block_count
;
3597 /* Now that we have the subblocks emitted, fix up the branches */
3602 if (ctx
->instruction_count
== count_in
) {
3603 /* The else block is empty, so don't emit an exit jump */
3604 mir_remove_instruction(then_exit
);
3605 then_branch
->branch
.target_block
= after_else_idx
;
3607 then_branch
->branch
.target_block
= else_idx
;
3608 then_exit
->branch
.target_block
= after_else_idx
;
3613 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3615 /* Remember where we are */
3616 midgard_block
*start_block
= ctx
->current_block
;
3618 /* Allocate a loop number, growing the current inner loop depth */
3619 int loop_idx
= ++ctx
->current_loop_depth
;
3621 /* Get index from before the body so we can loop back later */
3622 int start_idx
= ctx
->block_count
;
3624 /* Emit the body itself */
3625 emit_cf_list(ctx
, &nloop
->body
);
3627 /* Branch back to loop back */
3628 struct midgard_instruction br_back
= v_branch(false, false);
3629 br_back
.branch
.target_block
= start_idx
;
3630 emit_mir_instruction(ctx
, br_back
);
3632 /* Mark down that branch in the graph. Note that we're really branching
3633 * to the block *after* we started in. TODO: Why doesn't the branch
3634 * itself have an off-by-one then...? */
3635 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
3637 /* Find the index of the block about to follow us (note: we don't add
3638 * one; blocks are 0-indexed so we get a fencepost problem) */
3639 int break_block_idx
= ctx
->block_count
;
3641 /* Fix up the break statements we emitted to point to the right place,
3642 * now that we can allocate a block number for them */
3644 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3645 mir_foreach_instr_in_block(block
, ins
) {
3646 if (ins
->type
!= TAG_ALU_4
) continue;
3647 if (!ins
->compact_branch
) continue;
3648 if (ins
->prepacked_branch
) continue;
3650 /* We found a branch -- check the type to see if we need to do anything */
3651 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3653 /* It's a break! Check if it's our break */
3654 if (ins
->branch
.target_break
!= loop_idx
) continue;
3656 /* Okay, cool, we're breaking out of this loop.
3657 * Rewrite from a break to a goto */
3659 ins
->branch
.target_type
= TARGET_GOTO
;
3660 ins
->branch
.target_block
= break_block_idx
;
3664 /* Now that we've finished emitting the loop, free up the depth again
3665 * so we play nice with recursion amid nested loops */
3666 --ctx
->current_loop_depth
;
3669 static midgard_block
*
3670 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3672 midgard_block
*start_block
= NULL
;
3674 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3675 switch (node
->type
) {
3676 case nir_cf_node_block
: {
3677 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3680 start_block
= block
;
3685 case nir_cf_node_if
:
3686 emit_if(ctx
, nir_cf_node_as_if(node
));
3689 case nir_cf_node_loop
:
3690 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3693 case nir_cf_node_function
:
3702 /* Due to lookahead, we need to report the first tag executed in the command
3703 * stream and in branch targets. An initial block might be empty, so iterate
3704 * until we find one that 'works' */
3707 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3709 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3711 unsigned first_tag
= 0;
3714 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3716 if (initial_bundle
) {
3717 first_tag
= initial_bundle
->tag
;
3721 /* Initial block is empty, try the next block */
3722 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3723 } while(initial_block
!= NULL
);
3730 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3732 struct util_dynarray
*compiled
= &program
->compiled
;
3734 midgard_debug
= debug_get_option_midgard_debug();
3736 compiler_context ictx
= {
3738 .stage
= nir
->info
.stage
,
3740 .is_blend
= is_blend
,
3741 .blend_constant_offset
= -1,
3743 .alpha_ref
= program
->alpha_ref
3746 compiler_context
*ctx
= &ictx
;
3748 /* TODO: Decide this at runtime */
3749 ctx
->uniform_cutoff
= 8;
3751 /* Assign var locations early, so the epilogue can use them if necessary */
3753 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3754 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3755 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3757 /* Initialize at a global (not block) level hash tables */
3759 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3760 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3761 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3762 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3763 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3764 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3765 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3767 /* Record the varying mapping for the command stream's bookkeeping */
3769 struct exec_list
*varyings
=
3770 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3772 nir_foreach_variable(var
, varyings
) {
3773 unsigned loc
= var
->data
.driver_location
;
3774 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3776 for (int c
= 0; c
< sz
; ++c
) {
3777 program
->varyings
[loc
+ c
] = var
->data
.location
;
3781 /* Lower gl_Position pre-optimisation */
3783 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3784 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3786 NIR_PASS_V(nir
, nir_lower_var_copies
);
3787 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3788 NIR_PASS_V(nir
, nir_split_var_copies
);
3789 NIR_PASS_V(nir
, nir_lower_var_copies
);
3790 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3791 NIR_PASS_V(nir
, nir_lower_var_copies
);
3792 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3794 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3796 /* Optimisation passes */
3800 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3801 nir_print_shader(nir
, stdout
);
3804 /* Assign sysvals and counts, now that we're sure
3805 * (post-optimisation) */
3807 midgard_nir_assign_sysvals(ctx
, nir
);
3809 program
->uniform_count
= nir
->num_uniforms
;
3810 program
->sysval_count
= ctx
->sysval_count
;
3811 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3813 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3814 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3816 nir_foreach_function(func
, nir
) {
3820 list_inithead(&ctx
->blocks
);
3821 ctx
->block_count
= 0;
3824 emit_cf_list(ctx
, &func
->impl
->body
);
3825 emit_block(ctx
, func
->impl
->end_block
);
3827 break; /* TODO: Multi-function shaders */
3830 util_dynarray_init(compiled
, NULL
);
3832 /* MIR-level optimizations */
3834 bool progress
= false;
3839 mir_foreach_block(ctx
, block
) {
3840 progress
|= midgard_opt_copy_prop(ctx
, block
);
3841 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
3842 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
3847 schedule_program(ctx
);
3849 /* Now that all the bundles are scheduled and we can calculate block
3850 * sizes, emit actual branch instructions rather than placeholders */
3852 int br_block_idx
= 0;
3854 mir_foreach_block(ctx
, block
) {
3855 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3856 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3857 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3859 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3861 if (ins
->prepacked_branch
) continue;
3863 /* Parse some basic branch info */
3864 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3865 bool is_conditional
= ins
->branch
.conditional
;
3866 bool is_inverted
= ins
->branch
.invert_conditional
;
3867 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3869 /* Determine the block we're jumping to */
3870 int target_number
= ins
->branch
.target_block
;
3872 /* Report the destination tag. Discards don't need this */
3873 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3875 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3876 int quadword_offset
= 0;
3879 /* Jump to the end of the shader. We
3880 * need to include not only the
3881 * following blocks, but also the
3882 * contents of our current block (since
3883 * discard can come in the middle of
3886 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3888 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3889 quadword_offset
+= quadword_size(bun
->tag
);
3892 mir_foreach_block_from(ctx
, blk
, b
) {
3893 quadword_offset
+= b
->quadword_count
;
3896 } else if (target_number
> br_block_idx
) {
3899 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3900 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3903 quadword_offset
+= blk
->quadword_count
;
3906 /* Jump backwards */
3908 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3909 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3912 quadword_offset
-= blk
->quadword_count
;
3916 /* Unconditional extended branches (far jumps)
3917 * have issues, so we always use a conditional
3918 * branch, setting the condition to always for
3919 * unconditional. For compact unconditional
3920 * branches, cond isn't used so it doesn't
3921 * matter what we pick. */
3923 midgard_condition cond
=
3924 !is_conditional
? midgard_condition_always
:
3925 is_inverted
? midgard_condition_false
:
3926 midgard_condition_true
;
3928 midgard_jmp_writeout_op op
=
3929 is_discard
? midgard_jmp_writeout_op_discard
:
3930 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3931 midgard_jmp_writeout_op_branch_cond
;
3934 midgard_branch_extended branch
=
3935 midgard_create_branch_extended(
3940 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3941 } else if (is_conditional
|| is_discard
) {
3942 midgard_branch_cond branch
= {
3944 .dest_tag
= dest_tag
,
3945 .offset
= quadword_offset
,
3949 assert(branch
.offset
== quadword_offset
);
3951 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3953 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3955 midgard_branch_uncond branch
= {
3957 .dest_tag
= dest_tag
,
3958 .offset
= quadword_offset
,
3962 assert(branch
.offset
== quadword_offset
);
3964 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3972 /* Emit flat binary from the instruction arrays. Iterate each block in
3973 * sequence. Save instruction boundaries such that lookahead tags can
3974 * be assigned easily */
3976 /* Cache _all_ bundles in source order for lookahead across failed branches */
3978 int bundle_count
= 0;
3979 mir_foreach_block(ctx
, block
) {
3980 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3982 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3984 mir_foreach_block(ctx
, block
) {
3985 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3986 source_order_bundles
[bundle_idx
++] = bundle
;
3990 int current_bundle
= 0;
3992 mir_foreach_block(ctx
, block
) {
3993 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3996 if (current_bundle
+ 1 < bundle_count
) {
3997 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3999 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
4006 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
4010 /* TODO: Free deeper */
4011 //util_dynarray_fini(&block->instructions);
4014 free(source_order_bundles
);
4016 /* Report the very first tag executed */
4017 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
4019 /* Deal with off-by-one related to the fencepost problem */
4020 program
->work_register_count
= ctx
->work_registers
+ 1;
4022 program
->can_discard
= ctx
->can_discard
;
4023 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
4025 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
4027 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
4028 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);