2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
51 #include "disassemble.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
61 int midgard_debug
= 0;
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
69 midgard_is_branch_unit(unsigned unit
)
71 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
75 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
77 block
->successors
[block
->nr_successors
++] = successor
;
78 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
97 .op = midgard_op_##name, \
99 .swizzle = SWIZZLE_XYZW, \
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
116 if (!src
) return blank_alu_src
;
118 midgard_vector_alu_src alu_src
= {
121 .half
= 0, /* TODO */
122 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
126 /* TODO: sign-extend/zero-extend */
127 alu_src
.mod
= midgard_int_normal
;
129 /* These should have been lowered away */
130 assert(!(src
->abs
|| src
->negate
));
132 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
138 /* load/store instructions have both 32-bit and 16-bit variants, depending on
139 * whether we are using vectors composed of highp or mediump. At the moment, we
140 * don't support half-floats -- this requires changes in other parts of the
141 * compiler -- therefore the 16-bit versions are commented out. */
143 //M_LOAD(ld_attr_16);
145 //M_LOAD(ld_vary_16);
147 //M_LOAD(ld_uniform_16);
148 M_LOAD(ld_uniform_32
);
149 M_LOAD(ld_color_buffer_8
);
150 //M_STORE(st_vary_16);
152 M_STORE(st_cubemap_coords
);
154 static midgard_instruction
155 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
157 midgard_branch_cond branch
= {
165 memcpy(&compact
, &branch
, sizeof(branch
));
167 midgard_instruction ins
= {
169 .unit
= ALU_ENAB_BR_COMPACT
,
170 .prepacked_branch
= true,
171 .compact_branch
= true,
172 .br_compact
= compact
175 if (op
== midgard_jmp_writeout_op_writeout
)
181 static midgard_instruction
182 v_branch(bool conditional
, bool invert
)
184 midgard_instruction ins
= {
186 .unit
= ALU_ENAB_BRANCH
,
187 .compact_branch
= true,
189 .conditional
= conditional
,
190 .invert_conditional
= invert
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond
,
199 midgard_jmp_writeout_op op
,
201 signed quadword_offset
)
203 /* For unclear reasons, the condition code is repeated 8 times */
204 uint16_t duplicated_cond
=
214 midgard_branch_extended branch
= {
216 .dest_tag
= dest_tag
,
217 .offset
= quadword_offset
,
218 .cond
= duplicated_cond
225 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
227 ins
->has_constants
= true;
228 memcpy(&ins
->constants
, constants
, 16);
232 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
234 return glsl_count_attribute_slots(type
, false);
237 /* Lower fdot2 to a vector multiplication followed by channel addition */
239 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
241 if (alu
->op
!= nir_op_fdot2
)
244 b
->cursor
= nir_before_instr(&alu
->instr
);
246 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
247 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
249 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
251 nir_ssa_def
*sum
= nir_fadd(b
,
252 nir_channel(b
, product
, 0),
253 nir_channel(b
, product
, 1));
255 /* Replace the fdot2 with this sum */
256 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
260 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
262 switch (instr
->intrinsic
) {
263 case nir_intrinsic_load_viewport_scale
:
264 return PAN_SYSVAL_VIEWPORT_SCALE
;
265 case nir_intrinsic_load_viewport_offset
:
266 return PAN_SYSVAL_VIEWPORT_OFFSET
;
273 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
277 if (instr
->type
== nir_instr_type_intrinsic
) {
278 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
279 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
285 /* We have a sysval load; check if it's already been assigned */
287 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
290 /* It hasn't -- so assign it now! */
292 unsigned id
= ctx
->sysval_count
++;
293 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
294 ctx
->sysvals
[id
] = sysval
;
298 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
300 ctx
->sysval_count
= 0;
302 nir_foreach_function(function
, shader
) {
303 if (!function
->impl
) continue;
305 nir_foreach_block(block
, function
->impl
) {
306 nir_foreach_instr_safe(instr
, block
) {
307 midgard_nir_assign_sysval_body(ctx
, instr
);
314 midgard_nir_lower_fdot2(nir_shader
*shader
)
316 bool progress
= false;
318 nir_foreach_function(function
, shader
) {
319 if (!function
->impl
) continue;
322 nir_builder
*b
= &_b
;
323 nir_builder_init(b
, function
->impl
);
325 nir_foreach_block(block
, function
->impl
) {
326 nir_foreach_instr_safe(instr
, block
) {
327 if (instr
->type
!= nir_instr_type_alu
) continue;
329 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
330 midgard_nir_lower_fdot2_body(b
, alu
);
336 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
344 optimise_nir(nir_shader
*nir
)
347 unsigned lower_flrp
=
348 (nir
->options
->lower_flrp16
? 16 : 0) |
349 (nir
->options
->lower_flrp32
? 32 : 0) |
350 (nir
->options
->lower_flrp64
? 64 : 0);
352 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
353 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
354 NIR_PASS(progress
, nir
, nir_lower_idiv
);
356 nir_lower_tex_options lower_tex_options
= {
360 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
365 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
366 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
368 NIR_PASS(progress
, nir
, nir_copy_prop
);
369 NIR_PASS(progress
, nir
, nir_opt_dce
);
370 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
371 NIR_PASS(progress
, nir
, nir_opt_cse
);
372 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
373 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
374 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
376 if (lower_flrp
!= 0) {
377 bool lower_flrp_progress
= false;
378 NIR_PASS(lower_flrp_progress
,
382 false /* always_precise */,
383 nir
->options
->lower_ffma
);
384 if (lower_flrp_progress
) {
385 NIR_PASS(progress
, nir
,
386 nir_opt_constant_folding
);
390 /* Nothing should rematerialize any flrps, so we only
391 * need to do this lowering once.
396 NIR_PASS(progress
, nir
, nir_opt_undef
);
397 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
400 nir_var_function_temp
);
402 /* TODO: Enable vectorize when merged upstream */
403 // NIR_PASS(progress, nir, nir_opt_vectorize);
406 /* Must be run at the end to prevent creation of fsin/fcos ops */
407 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
412 NIR_PASS(progress
, nir
, nir_opt_dce
);
413 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
414 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
415 NIR_PASS(progress
, nir
, nir_copy_prop
);
418 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
420 /* We implement booleans as 32-bit 0/~0 */
421 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
423 /* Now that booleans are lowered, we can run out late opts */
424 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
426 /* Lower mods for float ops only. Integer ops don't support modifiers
427 * (saturate doesn't make sense on integers, neg/abs require dedicated
430 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
431 NIR_PASS(progress
, nir
, nir_copy_prop
);
432 NIR_PASS(progress
, nir
, nir_opt_dce
);
434 /* Take us out of SSA */
435 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
436 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
438 /* We are a vector architecture; write combine where possible */
439 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
440 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
442 NIR_PASS(progress
, nir
, nir_opt_dce
);
445 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
446 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
447 * r0. See the comments in compiler_context */
450 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
452 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
453 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
456 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
459 unalias_ssa(compiler_context
*ctx
, int dest
)
461 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
462 /* TODO: Remove from leftover or no? */
465 /* Do not actually emit a load; instead, cache the constant for inlining */
468 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
470 nir_ssa_def def
= instr
->def
;
472 float *v
= rzalloc_array(NULL
, float, 4);
473 nir_const_load_to_arr(v
, instr
, f32
);
474 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
478 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
481 return src
->ssa
->index
;
483 assert(!src
->reg
.indirect
);
484 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
489 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
492 return dst
->ssa
.index
;
494 assert(!dst
->reg
.indirect
);
495 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
500 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
502 return nir_src_index(ctx
, &src
->src
);
506 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
508 unsigned comp
= src
->swizzle
[0];
510 for (unsigned c
= 1; c
< nr_components
; ++c
) {
511 if (src
->swizzle
[c
] != comp
)
518 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
519 * output of a conditional test) into that register */
522 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
524 int condition
= nir_src_index(ctx
, src
);
526 /* Source to swizzle the desired component into w */
528 const midgard_vector_alu_src alu_src
= {
529 .swizzle
= SWIZZLE(component
, component
, component
, component
),
532 /* There is no boolean move instruction. Instead, we simulate a move by
533 * ANDing the condition with itself to get it into r31.w */
535 midgard_instruction ins
= {
538 /* We need to set the conditional as close as possible */
539 .precede_break
= true,
540 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
546 .dest
= SSA_FIXED_REGISTER(31),
549 .op
= midgard_alu_op_iand
,
550 .outmod
= midgard_outmod_int
,
551 .reg_mode
= midgard_reg_mode_32
,
552 .dest_override
= midgard_dest_override_none
,
553 .mask
= (0x3 << 6), /* w */
554 .src1
= vector_alu_srco_unsigned(alu_src
),
555 .src2
= vector_alu_srco_unsigned(alu_src
)
559 emit_mir_instruction(ctx
, ins
);
562 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
566 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
568 int condition
= nir_src_index(ctx
, &src
->src
);
570 /* Source to swizzle the desired component into w */
572 const midgard_vector_alu_src alu_src
= {
573 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
576 /* There is no boolean move instruction. Instead, we simulate a move by
577 * ANDing the condition with itself to get it into r31.w */
579 midgard_instruction ins
= {
581 .precede_break
= true,
585 .dest
= SSA_FIXED_REGISTER(31),
588 .op
= midgard_alu_op_iand
,
589 .outmod
= midgard_outmod_int
,
590 .reg_mode
= midgard_reg_mode_32
,
591 .dest_override
= midgard_dest_override_none
,
592 .mask
= expand_writemask((1 << nr_comp
) - 1),
593 .src1
= vector_alu_srco_unsigned(alu_src
),
594 .src2
= vector_alu_srco_unsigned(alu_src
)
598 emit_mir_instruction(ctx
, ins
);
603 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
604 * pinning to eliminate this move in all known cases */
607 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
609 int offset
= nir_src_index(ctx
, src
);
611 midgard_instruction ins
= {
614 .src0
= SSA_UNUSED_1
,
616 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
619 .op
= midgard_alu_op_imov
,
620 .outmod
= midgard_outmod_int
,
621 .reg_mode
= midgard_reg_mode_32
,
622 .dest_override
= midgard_dest_override_none
,
623 .mask
= (0x3 << 6), /* w */
624 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
625 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
629 emit_mir_instruction(ctx
, ins
);
632 #define ALU_CASE(nir, _op) \
634 op = midgard_alu_op_##_op; \
637 nir_is_fzero_constant(nir_src src
)
639 if (!nir_src_is_const(src
))
642 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
643 if (nir_src_comp_as_float(src
, c
) != 0.0)
651 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
653 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
655 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
656 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
657 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
659 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
660 * supported. A few do not and are commented for now. Also, there are a
661 * number of NIR ops which Midgard does not support and need to be
662 * lowered, also TODO. This switch block emits the opcode and calling
663 * convention of the Midgard instruction; actual packing is done in
669 ALU_CASE(fadd
, fadd
);
670 ALU_CASE(fmul
, fmul
);
671 ALU_CASE(fmin
, fmin
);
672 ALU_CASE(fmax
, fmax
);
673 ALU_CASE(imin
, imin
);
674 ALU_CASE(imax
, imax
);
675 ALU_CASE(umin
, umin
);
676 ALU_CASE(umax
, umax
);
677 ALU_CASE(ffloor
, ffloor
);
678 ALU_CASE(fround_even
, froundeven
);
679 ALU_CASE(ftrunc
, ftrunc
);
680 ALU_CASE(fceil
, fceil
);
681 ALU_CASE(fdot3
, fdot3
);
682 ALU_CASE(fdot4
, fdot4
);
683 ALU_CASE(iadd
, iadd
);
684 ALU_CASE(isub
, isub
);
685 ALU_CASE(imul
, imul
);
687 /* Zero shoved as second-arg */
688 ALU_CASE(iabs
, iabsdiff
);
692 ALU_CASE(feq32
, feq
);
693 ALU_CASE(fne32
, fne
);
694 ALU_CASE(flt32
, flt
);
695 ALU_CASE(ieq32
, ieq
);
696 ALU_CASE(ine32
, ine
);
697 ALU_CASE(ilt32
, ilt
);
698 ALU_CASE(ult32
, ult
);
700 /* We don't have a native b2f32 instruction. Instead, like many
701 * GPUs, we exploit booleans as 0/~0 for false/true, and
702 * correspondingly AND
703 * by 1.0 to do the type conversion. For the moment, prime us
706 * iand [whatever], #0
708 * At the end of emit_alu (as MIR), we'll fix-up the constant
711 ALU_CASE(b2f32
, iand
);
712 ALU_CASE(b2i32
, iand
);
714 /* Likewise, we don't have a dedicated f2b32 instruction, but
715 * we can do a "not equal to 0.0" test. */
717 ALU_CASE(f2b32
, fne
);
718 ALU_CASE(i2b32
, ine
);
720 ALU_CASE(frcp
, frcp
);
721 ALU_CASE(frsq
, frsqrt
);
722 ALU_CASE(fsqrt
, fsqrt
);
723 ALU_CASE(fexp2
, fexp2
);
724 ALU_CASE(flog2
, flog2
);
726 ALU_CASE(f2i32
, f2i
);
727 ALU_CASE(f2u32
, f2u
);
728 ALU_CASE(i2f32
, i2f
);
729 ALU_CASE(u2f32
, u2f
);
731 ALU_CASE(fsin
, fsin
);
732 ALU_CASE(fcos
, fcos
);
734 ALU_CASE(iand
, iand
);
736 ALU_CASE(ixor
, ixor
);
737 ALU_CASE(inot
, inand
);
738 ALU_CASE(ishl
, ishl
);
739 ALU_CASE(ishr
, iasr
);
740 ALU_CASE(ushr
, ilsr
);
742 ALU_CASE(b32all_fequal2
, fball_eq
);
743 ALU_CASE(b32all_fequal3
, fball_eq
);
744 ALU_CASE(b32all_fequal4
, fball_eq
);
746 ALU_CASE(b32any_fnequal2
, fbany_neq
);
747 ALU_CASE(b32any_fnequal3
, fbany_neq
);
748 ALU_CASE(b32any_fnequal4
, fbany_neq
);
750 ALU_CASE(b32all_iequal2
, iball_eq
);
751 ALU_CASE(b32all_iequal3
, iball_eq
);
752 ALU_CASE(b32all_iequal4
, iball_eq
);
754 ALU_CASE(b32any_inequal2
, ibany_neq
);
755 ALU_CASE(b32any_inequal3
, ibany_neq
);
756 ALU_CASE(b32any_inequal4
, ibany_neq
);
758 /* Source mods will be shoved in later */
759 ALU_CASE(fabs
, fmov
);
760 ALU_CASE(fneg
, fmov
);
761 ALU_CASE(fsat
, fmov
);
763 /* For greater-or-equal, we lower to less-or-equal and flip the
771 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
772 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
773 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
774 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
777 /* Swap via temporary */
778 nir_alu_src temp
= instr
->src
[1];
779 instr
->src
[1] = instr
->src
[0];
780 instr
->src
[0] = temp
;
785 case nir_op_b32csel
: {
786 /* Midgard features both fcsel and icsel, depending on
787 * the type of the arguments/output. However, as long
788 * as we're careful we can _always_ use icsel and
789 * _never_ need fcsel, since the latter does additional
790 * floating-point-specific processing whereas the
791 * former just moves bits on the wire. It's not obvious
792 * why these are separate opcodes, save for the ability
793 * to do things like sat/pos/abs/neg for free */
795 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
796 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
798 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
801 /* Emit the condition into r31 */
804 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
806 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
808 /* The condition is the first argument; move the other
809 * arguments up one to be a binary instruction for
812 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
817 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
822 /* Midgard can perform certain modifiers on output of an ALU op */
823 midgard_outmod outmod
=
824 midgard_is_integer_out_op(op
) ? midgard_outmod_int
:
825 instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
827 if (instr
->op
== nir_op_fsat
)
828 outmod
= midgard_outmod_sat
;
830 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
832 if (instr
->op
== nir_op_fmax
) {
833 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
834 op
= midgard_alu_op_fmov
;
836 outmod
= midgard_outmod_pos
;
837 instr
->src
[0] = instr
->src
[1];
838 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
839 op
= midgard_alu_op_fmov
;
841 outmod
= midgard_outmod_pos
;
845 /* Fetch unit, quirks, etc information */
846 unsigned opcode_props
= alu_opcode_props
[op
].props
;
847 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
849 /* src0 will always exist afaik, but src1 will not for 1-argument
850 * instructions. The latter can only be fetched if the instruction
851 * needs it, or else we may segfault. */
853 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
854 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
856 /* Rather than use the instruction generation helpers, we do it
857 * ourselves here to avoid the mess */
859 midgard_instruction ins
= {
862 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
863 .src1
= quirk_flipped_r24
? src0
: src1
,
868 nir_alu_src
*nirmods
[2] = { NULL
};
870 if (nr_inputs
== 2) {
871 nirmods
[0] = &instr
->src
[0];
872 nirmods
[1] = &instr
->src
[1];
873 } else if (nr_inputs
== 1) {
874 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
879 /* These were lowered to a move, so apply the corresponding mod */
881 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
882 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
884 if (instr
->op
== nir_op_fneg
)
885 s
->negate
= !s
->negate
;
887 if (instr
->op
== nir_op_fabs
)
891 bool is_int
= midgard_is_integer_op(op
);
893 midgard_vector_alu alu
= {
895 .reg_mode
= midgard_reg_mode_32
,
896 .dest_override
= midgard_dest_override_none
,
899 /* Writemask only valid for non-SSA NIR */
900 .mask
= expand_writemask((1 << nr_components
) - 1),
902 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
903 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
906 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
909 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
913 /* Late fixup for emulated instructions */
915 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
916 /* Presently, our second argument is an inline #0 constant.
917 * Switch over to an embedded 1.0 constant (that can't fit
918 * inline, since we're 32-bit, not 16-bit like the inline
921 ins
.ssa_args
.inline_constant
= false;
922 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
923 ins
.has_constants
= true;
925 if (instr
->op
== nir_op_b2f32
) {
926 ins
.constants
[0] = 1.0f
;
928 /* Type pun it into place */
930 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
933 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
934 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
935 /* Lots of instructions need a 0 plonked in */
936 ins
.ssa_args
.inline_constant
= false;
937 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
938 ins
.has_constants
= true;
939 ins
.constants
[0] = 0.0f
;
940 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
941 } else if (instr
->op
== nir_op_inot
) {
942 /* ~b = ~(b & b), so duplicate the source */
943 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
944 ins
.alu
.src2
= ins
.alu
.src1
;
947 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
948 /* To avoid duplicating the lookup tables (probably), true LUT
949 * instructions can only operate as if they were scalars. Lower
950 * them here by changing the component. */
952 uint8_t original_swizzle
[4];
953 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
955 for (int i
= 0; i
< nr_components
; ++i
) {
956 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
958 for (int j
= 0; j
< 4; ++j
)
959 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
961 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
962 emit_mir_instruction(ctx
, ins
);
965 emit_mir_instruction(ctx
, ins
);
972 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
974 /* TODO: half-floats */
976 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
977 /* Fast path: For the first 16 uniforms, direct accesses are
978 * 0-cycle, since they're just a register fetch in the usual
979 * case. So, we alias the registers while we're still in
982 int reg_slot
= 23 - offset
;
983 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
985 /* Otherwise, read from the 'special' UBO to access
986 * higher-indexed uniforms, at a performance cost. More
987 * generally, we're emitting a UBO read instruction. */
989 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
991 /* TODO: Don't split */
992 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
993 ins
.load_store
.address
= offset
>> 3;
995 if (indirect_offset
) {
996 emit_indirect_offset(ctx
, indirect_offset
);
997 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
999 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1002 emit_mir_instruction(ctx
, ins
);
1007 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1009 /* First, pull out the destination */
1010 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1012 /* Now, figure out which uniform this is */
1013 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1014 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1016 /* Sysvals are prefix uniforms */
1017 unsigned uniform
= ((uintptr_t) val
) - 1;
1019 /* Emit the read itself -- this is never indirect */
1020 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1023 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1024 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1025 * generations have faster vectorized reads. This operation is for blend
1026 * shaders in particular; reading the tilebuffer from the fragment shader
1027 * remains an open problem. */
1030 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1032 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1033 ins
.load_store
.swizzle
= 0; /* xxxx */
1035 /* Read each component sequentially */
1037 for (unsigned c
= 0; c
< 4; ++c
) {
1038 ins
.load_store
.mask
= (1 << c
);
1039 ins
.load_store
.unknown
= c
;
1040 emit_mir_instruction(ctx
, ins
);
1043 /* vadd.u2f hr2, zext(hr2), #0 */
1045 midgard_vector_alu_src alu_src
= blank_alu_src
;
1046 alu_src
.mod
= midgard_int_zero_extend
;
1047 alu_src
.half
= true;
1049 midgard_instruction u2f
= {
1053 .src1
= SSA_UNUSED_0
,
1055 .inline_constant
= true
1058 .op
= midgard_alu_op_u2f
,
1059 .reg_mode
= midgard_reg_mode_16
,
1060 .dest_override
= midgard_dest_override_none
,
1062 .src1
= vector_alu_srco_unsigned(alu_src
),
1063 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1067 emit_mir_instruction(ctx
, u2f
);
1069 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1073 midgard_instruction fmul
= {
1075 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1079 .src1
= SSA_UNUSED_0
,
1080 .inline_constant
= true
1083 .op
= midgard_alu_op_fmul
,
1084 .reg_mode
= midgard_reg_mode_32
,
1085 .dest_override
= midgard_dest_override_none
,
1086 .outmod
= midgard_outmod_sat
,
1088 .src1
= vector_alu_srco_unsigned(alu_src
),
1089 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1093 emit_mir_instruction(ctx
, fmul
);
1097 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1099 unsigned offset
, reg
;
1101 switch (instr
->intrinsic
) {
1102 case nir_intrinsic_discard_if
:
1103 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1107 case nir_intrinsic_discard
: {
1108 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1109 struct midgard_instruction discard
= v_branch(conditional
, false);
1110 discard
.branch
.target_type
= TARGET_DISCARD
;
1111 emit_mir_instruction(ctx
, discard
);
1113 ctx
->can_discard
= true;
1117 case nir_intrinsic_load_uniform
:
1118 case nir_intrinsic_load_input
:
1119 offset
= nir_intrinsic_base(instr
);
1121 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1122 bool direct
= nir_src_is_const(instr
->src
[0]);
1125 offset
+= nir_src_as_uint(instr
->src
[0]);
1128 /* We may need to apply a fractional offset */
1129 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1130 nir_intrinsic_component(instr
) : 0;
1131 reg
= nir_dest_index(ctx
, &instr
->dest
);
1133 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1134 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1135 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1136 /* XXX: Half-floats? */
1137 /* TODO: swizzle, mask */
1139 midgard_instruction ins
= m_ld_vary_32(reg
, offset
);
1140 ins
.load_store
.mask
= (1 << nr_comp
) - 1;
1141 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1143 midgard_varying_parameter p
= {
1145 .interpolation
= midgard_interp_default
,
1146 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1150 memcpy(&u
, &p
, sizeof(p
));
1151 ins
.load_store
.varying_parameters
= u
;
1154 /* We have the offset totally ready */
1155 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1157 /* We have it partially ready, but we need to
1158 * add in the dynamic index, moved to r27.w */
1159 emit_indirect_offset(ctx
, &instr
->src
[0]);
1160 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1163 emit_mir_instruction(ctx
, ins
);
1164 } else if (ctx
->is_blend
) {
1165 /* For blend shaders, load the input color, which is
1166 * preloaded to r0 */
1168 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1169 emit_mir_instruction(ctx
, move
);
1170 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1171 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1172 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1173 ins
.load_store
.mask
= (1 << nr_comp
) - 1;
1174 emit_mir_instruction(ctx
, ins
);
1176 DBG("Unknown load\n");
1182 case nir_intrinsic_load_output
:
1183 assert(nir_src_is_const(instr
->src
[0]));
1184 reg
= nir_dest_index(ctx
, &instr
->dest
);
1186 if (ctx
->is_blend
) {
1188 emit_fb_read_blend_scalar(ctx
, reg
);
1190 DBG("Unknown output load\n");
1196 case nir_intrinsic_load_blend_const_color_rgba
: {
1197 assert(ctx
->is_blend
);
1198 reg
= nir_dest_index(ctx
, &instr
->dest
);
1200 /* Blend constants are embedded directly in the shader and
1201 * patched in, so we use some magic routing */
1203 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1204 ins
.has_constants
= true;
1205 ins
.has_blend_constant
= true;
1206 emit_mir_instruction(ctx
, ins
);
1210 case nir_intrinsic_store_output
:
1211 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1213 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1215 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1217 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1218 /* gl_FragColor is not emitted with load/store
1219 * instructions. Instead, it gets plonked into
1220 * r0 at the end of the shader and we do the
1221 * framebuffer writeout dance. TODO: Defer
1224 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1225 emit_mir_instruction(ctx
, move
);
1227 /* Save the index we're writing to for later reference
1228 * in the epilogue */
1230 ctx
->fragment_output
= reg
;
1231 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1232 /* Varyings are written into one of two special
1233 * varying register, r26 or r27. The register itself is
1234 * selected as the register in the st_vary instruction,
1235 * minus the base of 26. E.g. write into r27 and then
1236 * call st_vary(1) */
1238 midgard_instruction ins
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1239 emit_mir_instruction(ctx
, ins
);
1241 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1242 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1243 emit_mir_instruction(ctx
, st
);
1245 DBG("Unknown store\n");
1251 case nir_intrinsic_load_alpha_ref_float
:
1252 assert(instr
->dest
.is_ssa
);
1254 float ref_value
= ctx
->alpha_ref
;
1256 float *v
= ralloc_array(NULL
, float, 4);
1257 memcpy(v
, &ref_value
, sizeof(float));
1258 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1261 case nir_intrinsic_load_viewport_scale
:
1262 case nir_intrinsic_load_viewport_offset
:
1263 emit_sysval_read(ctx
, instr
);
1267 printf ("Unhandled intrinsic\n");
1274 midgard_tex_format(enum glsl_sampler_dim dim
)
1277 case GLSL_SAMPLER_DIM_2D
:
1278 case GLSL_SAMPLER_DIM_EXTERNAL
:
1281 case GLSL_SAMPLER_DIM_3D
:
1284 case GLSL_SAMPLER_DIM_CUBE
:
1285 return TEXTURE_CUBE
;
1288 DBG("Unknown sampler dim type\n");
1295 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1298 //assert (!instr->sampler);
1299 //assert (!instr->texture_array_size);
1300 assert (instr
->op
== nir_texop_tex
);
1302 /* Allocate registers via a round robin scheme to alternate between the two registers */
1303 int reg
= ctx
->texture_op_count
& 1;
1304 int in_reg
= reg
, out_reg
= reg
;
1306 /* Make room for the reg */
1308 if (ctx
->texture_index
[reg
] > -1)
1309 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1311 int texture_index
= instr
->texture_index
;
1312 int sampler_index
= texture_index
;
1314 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1315 switch (instr
->src
[i
].src_type
) {
1316 case nir_tex_src_coord
: {
1317 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1319 midgard_vector_alu_src alu_src
= blank_alu_src
;
1321 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1323 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1324 /* For cubemaps, we need to load coords into
1325 * special r27, and then use a special ld/st op
1326 * to copy into the texture register */
1328 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1330 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1331 emit_mir_instruction(ctx
, move
);
1333 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1334 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1335 st
.load_store
.mask
= 0x3; /* xy? */
1336 st
.load_store
.swizzle
= alu_src
.swizzle
;
1337 emit_mir_instruction(ctx
, st
);
1340 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1342 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1343 emit_mir_instruction(ctx
, ins
);
1350 DBG("Unknown source type\n");
1357 /* No helper to build texture words -- we do it all here */
1358 midgard_instruction ins
= {
1359 .type
= TAG_TEXTURE_4
,
1361 .op
= TEXTURE_OP_NORMAL
,
1362 .format
= midgard_tex_format(instr
->sampler_dim
),
1363 .texture_handle
= texture_index
,
1364 .sampler_handle
= sampler_index
,
1366 /* TODO: Don't force xyzw */
1367 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1379 /* Assume we can continue; hint it out later */
1384 /* Set registers to read and write from the same place */
1385 ins
.texture
.in_reg_select
= in_reg
;
1386 ins
.texture
.out_reg_select
= out_reg
;
1388 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1389 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1390 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1391 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1392 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1394 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1395 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1396 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1399 emit_mir_instruction(ctx
, ins
);
1401 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1403 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1404 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1405 ctx
->texture_index
[reg
] = o_index
;
1407 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1408 emit_mir_instruction(ctx
, ins2
);
1410 /* Used for .cont and .last hinting */
1411 ctx
->texture_op_count
++;
1415 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1417 switch (instr
->type
) {
1418 case nir_jump_break
: {
1419 /* Emit a branch out of the loop */
1420 struct midgard_instruction br
= v_branch(false, false);
1421 br
.branch
.target_type
= TARGET_BREAK
;
1422 br
.branch
.target_break
= ctx
->current_loop_depth
;
1423 emit_mir_instruction(ctx
, br
);
1430 DBG("Unknown jump type %d\n", instr
->type
);
1436 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1438 switch (instr
->type
) {
1439 case nir_instr_type_load_const
:
1440 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1443 case nir_instr_type_intrinsic
:
1444 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1447 case nir_instr_type_alu
:
1448 emit_alu(ctx
, nir_instr_as_alu(instr
));
1451 case nir_instr_type_tex
:
1452 emit_tex(ctx
, nir_instr_as_tex(instr
));
1455 case nir_instr_type_jump
:
1456 emit_jump(ctx
, nir_instr_as_jump(instr
));
1459 case nir_instr_type_ssa_undef
:
1464 DBG("Unhandled instruction type\n");
1470 /* ALU instructions can inline or embed constants, which decreases register
1471 * pressure and saves space. */
1473 #define CONDITIONAL_ATTACH(src) { \
1474 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1477 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1478 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1483 inline_alu_constants(compiler_context
*ctx
)
1485 mir_foreach_instr(ctx
, alu
) {
1486 /* Other instructions cannot inline constants */
1487 if (alu
->type
!= TAG_ALU_4
) continue;
1489 /* If there is already a constant here, we can do nothing */
1490 if (alu
->has_constants
) continue;
1492 /* It makes no sense to inline constants on a branch */
1493 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1495 CONDITIONAL_ATTACH(src0
);
1497 if (!alu
->has_constants
) {
1498 CONDITIONAL_ATTACH(src1
)
1499 } else if (!alu
->inline_constant
) {
1500 /* Corner case: _two_ vec4 constants, for instance with a
1501 * csel. For this case, we can only use a constant
1502 * register for one, we'll have to emit a move for the
1503 * other. Note, if both arguments are constants, then
1504 * necessarily neither argument depends on the value of
1505 * any particular register. As the destination register
1506 * will be wiped, that means we can spill the constant
1507 * to the destination register.
1510 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1511 unsigned scratch
= alu
->ssa_args
.dest
;
1514 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1515 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1517 /* Force a break XXX Defer r31 writes */
1518 ins
.unit
= UNIT_VLUT
;
1520 /* Set the source */
1521 alu
->ssa_args
.src1
= scratch
;
1523 /* Inject us -before- the last instruction which set r31 */
1524 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1530 /* Midgard supports two types of constants, embedded constants (128-bit) and
1531 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1532 * constants can be demoted to inline constants, for space savings and
1533 * sometimes a performance boost */
1536 embedded_to_inline_constant(compiler_context
*ctx
)
1538 mir_foreach_instr(ctx
, ins
) {
1539 if (!ins
->has_constants
) continue;
1541 if (ins
->ssa_args
.inline_constant
) continue;
1543 /* Blend constants must not be inlined by definition */
1544 if (ins
->has_blend_constant
) continue;
1546 /* src1 cannot be an inline constant due to encoding
1547 * restrictions. So, if possible we try to flip the arguments
1550 int op
= ins
->alu
.op
;
1552 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1554 /* These ops require an operational change to flip
1555 * their arguments TODO */
1556 case midgard_alu_op_flt
:
1557 case midgard_alu_op_fle
:
1558 case midgard_alu_op_ilt
:
1559 case midgard_alu_op_ile
:
1560 case midgard_alu_op_fcsel
:
1561 case midgard_alu_op_icsel
:
1562 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1567 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1568 /* Flip the SSA numbers */
1569 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1570 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1572 /* And flip the modifiers */
1576 src_temp
= ins
->alu
.src2
;
1577 ins
->alu
.src2
= ins
->alu
.src1
;
1578 ins
->alu
.src1
= src_temp
;
1582 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1583 /* Extract the source information */
1585 midgard_vector_alu_src
*src
;
1586 int q
= ins
->alu
.src2
;
1587 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1590 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1591 int component
= src
->swizzle
& 3;
1593 /* Scale constant appropriately, if we can legally */
1594 uint16_t scaled_constant
= 0;
1596 if (midgard_is_integer_op(op
)) {
1597 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1598 scaled_constant
= (uint16_t) iconstants
[component
];
1600 /* Constant overflow after resize */
1601 if (scaled_constant
!= iconstants
[component
])
1604 float original
= (float) ins
->constants
[component
];
1605 scaled_constant
= _mesa_float_to_half(original
);
1607 /* Check for loss of precision. If this is
1608 * mediump, we don't care, but for a highp
1609 * shader, we need to pay attention. NIR
1610 * doesn't yet tell us which mode we're in!
1611 * Practically this prevents most constants
1612 * from being inlined, sadly. */
1614 float fp32
= _mesa_half_to_float(scaled_constant
);
1616 if (fp32
!= original
)
1620 /* We don't know how to handle these with a constant */
1622 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1623 DBG("Bailing inline constant...\n");
1627 /* Make sure that the constant is not itself a
1628 * vector by checking if all accessed values
1629 * (by the swizzle) are the same. */
1631 uint32_t *cons
= (uint32_t *) ins
->constants
;
1632 uint32_t value
= cons
[component
];
1634 bool is_vector
= false;
1635 unsigned mask
= effective_writemask(&ins
->alu
);
1637 for (int c
= 1; c
< 4; ++c
) {
1638 /* We only care if this component is actually used */
1639 if (!(mask
& (1 << c
)))
1642 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1644 if (test
!= value
) {
1653 /* Get rid of the embedded constant */
1654 ins
->has_constants
= false;
1655 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1656 ins
->ssa_args
.inline_constant
= true;
1657 ins
->inline_constant
= scaled_constant
;
1662 /* Map normal SSA sources to other SSA sources / fixed registers (like
1666 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
1668 /* Sign is used quite deliberately for unused */
1672 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
1675 /* Remove entry in leftovers to avoid a redunant fmov */
1677 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
1680 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
1682 /* Assign the alias map */
1688 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1689 * texture pipeline */
1692 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
1694 bool progress
= false;
1696 mir_foreach_instr_in_block_safe(block
, ins
) {
1697 if (ins
->type
!= TAG_ALU_4
) continue;
1698 if (ins
->compact_branch
) continue;
1700 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1701 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
1703 mir_remove_instruction(ins
);
1711 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
1714 if (!is_int
&& src
.mod
) return true;
1717 for (unsigned c
= 0; c
< 4; ++c
) {
1718 if (!(mask
& (1 << c
))) continue;
1719 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
1726 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
1728 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
1729 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
1731 midgard_vector_alu_src src2
=
1732 vector_alu_from_unsigned(ins
->alu
.src2
);
1734 return mir_nontrivial_mod(src2
, is_int
, mask
);
1738 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
1740 bool progress
= false;
1742 mir_foreach_instr_in_block_safe(block
, ins
) {
1743 if (ins
->type
!= TAG_ALU_4
) continue;
1744 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
1746 unsigned from
= ins
->ssa_args
.src1
;
1747 unsigned to
= ins
->ssa_args
.dest
;
1749 /* We only work on pure SSA */
1751 if (to
>= SSA_FIXED_MINIMUM
) continue;
1752 if (from
>= SSA_FIXED_MINIMUM
) continue;
1753 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
1754 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
1756 /* Constant propagation is not handled here, either */
1757 if (ins
->ssa_args
.inline_constant
) continue;
1758 if (ins
->has_constants
) continue;
1760 if (mir_nontrivial_source2_mod(ins
)) continue;
1761 if (ins
->alu
.outmod
!= midgard_outmod_none
) continue;
1763 /* We're clear -- rewrite */
1764 mir_rewrite_index_src(ctx
, to
, from
);
1765 mir_remove_instruction(ins
);
1772 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1773 * the move can be propagated away entirely */
1776 mir_compose_outmod(midgard_outmod
*outmod
, midgard_outmod comp
)
1779 if (comp
== midgard_outmod_none
)
1782 if (*outmod
== midgard_outmod_none
) {
1787 /* TODO: Compose rules */
1792 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
1794 bool progress
= false;
1796 mir_foreach_instr_in_block_safe(block
, ins
) {
1797 if (ins
->type
!= TAG_ALU_4
) continue;
1798 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
1799 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
1801 /* TODO: Registers? */
1802 unsigned src
= ins
->ssa_args
.src1
;
1803 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
1805 /* There might be a source modifier, too */
1806 if (mir_nontrivial_source2_mod(ins
)) continue;
1808 /* Backpropagate the modifier */
1809 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1810 if (v
->type
!= TAG_ALU_4
) continue;
1811 if (v
->ssa_args
.dest
!= src
) continue;
1813 midgard_outmod temp
= v
->alu
.outmod
;
1814 progress
|= mir_compose_outmod(&temp
, ins
->alu
.outmod
);
1816 /* Throw in the towel.. */
1817 if (!progress
) break;
1819 /* Otherwise, transfer the modifier */
1820 v
->alu
.outmod
= temp
;
1821 ins
->alu
.outmod
= midgard_outmod_none
;
1831 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
1833 bool progress
= false;
1835 mir_foreach_instr_in_block_safe(block
, ins
) {
1836 if (ins
->type
!= TAG_ALU_4
) continue;
1837 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
1839 unsigned from
= ins
->ssa_args
.src1
;
1840 unsigned to
= ins
->ssa_args
.dest
;
1842 /* Make sure it's simple enough for us to handle */
1844 if (from
>= SSA_FIXED_MINIMUM
) continue;
1845 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
1846 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
1847 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
1849 bool eliminated
= false;
1851 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1852 /* The texture registers are not SSA so be careful.
1853 * Conservatively, just stop if we hit a texture op
1854 * (even if it may not write) to where we are */
1856 if (v
->type
!= TAG_ALU_4
)
1859 if (v
->ssa_args
.dest
== from
) {
1860 /* We don't want to track partial writes ... */
1861 if (v
->alu
.mask
== 0xF) {
1862 v
->ssa_args
.dest
= to
;
1871 mir_remove_instruction(ins
);
1873 progress
|= eliminated
;
1879 /* The following passes reorder MIR instructions to enable better scheduling */
1882 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
1884 mir_foreach_instr_in_block_safe(block
, ins
) {
1885 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
1887 /* We've found a load/store op. Check if next is also load/store. */
1888 midgard_instruction
*next_op
= mir_next_op(ins
);
1889 if (&next_op
->link
!= &block
->instructions
) {
1890 if (next_op
->type
== TAG_LOAD_STORE_4
) {
1891 /* If so, we're done since we're a pair */
1892 ins
= mir_next_op(ins
);
1896 /* Maximum search distance to pair, to avoid register pressure disasters */
1897 int search_distance
= 8;
1899 /* Otherwise, we have an orphaned load/store -- search for another load */
1900 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
1901 /* Terminate search if necessary */
1902 if (!(search_distance
--)) break;
1904 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
1906 /* Stores cannot be reordered, since they have
1907 * dependencies. For the same reason, indirect
1908 * loads cannot be reordered as their index is
1909 * loaded in r27.w */
1911 if (OP_IS_STORE(c
->load_store
.op
)) continue;
1913 /* It appears the 0x800 bit is set whenever a
1914 * load is direct, unset when it is indirect.
1915 * Skip indirect loads. */
1917 if (!(c
->load_store
.unknown
& 0x800)) continue;
1919 /* We found one! Move it up to pair and remove it from the old location */
1921 mir_insert_instruction_before(ins
, *c
);
1922 mir_remove_instruction(c
);
1930 /* If there are leftovers after the below pass, emit actual fmov
1931 * instructions for the slow-but-correct path */
1934 emit_leftover_move(compiler_context
*ctx
)
1936 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
1937 int base
= ((uintptr_t) leftover
->key
) - 1;
1940 map_ssa_to_alias(ctx
, &mapped
);
1941 EMIT(fmov
, mapped
, blank_alu_src
, base
);
1946 actualise_ssa_to_alias(compiler_context
*ctx
)
1948 mir_foreach_instr(ctx
, ins
) {
1949 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
1950 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
1953 emit_leftover_move(ctx
);
1957 emit_fragment_epilogue(compiler_context
*ctx
)
1959 /* Special case: writing out constants requires us to include the move
1960 * explicitly now, so shove it into r0 */
1962 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
1964 if (constant_value
) {
1965 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
1966 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
1967 emit_mir_instruction(ctx
, ins
);
1970 /* Perform the actual fragment writeout. We have two writeout/branch
1971 * instructions, forming a loop until writeout is successful as per the
1972 * docs. TODO: gl_FragDepth */
1974 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
1975 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
1978 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
1979 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
1980 * with the int8 analogue to the fragment epilogue */
1983 emit_blend_epilogue(compiler_context
*ctx
)
1985 /* vmul.fmul.none.fulllow hr48, r0, #255 */
1987 midgard_instruction scale
= {
1990 .inline_constant
= _mesa_float_to_half(255.0),
1992 .src0
= SSA_FIXED_REGISTER(0),
1993 .src1
= SSA_UNUSED_0
,
1994 .dest
= SSA_FIXED_REGISTER(24),
1995 .inline_constant
= true
1998 .op
= midgard_alu_op_fmul
,
1999 .reg_mode
= midgard_reg_mode_32
,
2000 .dest_override
= midgard_dest_override_lower
,
2002 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2003 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2007 emit_mir_instruction(ctx
, scale
);
2009 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2011 midgard_vector_alu_src alu_src
= blank_alu_src
;
2012 alu_src
.half
= true;
2014 midgard_instruction f2u8
= {
2017 .src0
= SSA_FIXED_REGISTER(24),
2018 .src1
= SSA_UNUSED_0
,
2019 .dest
= SSA_FIXED_REGISTER(0),
2020 .inline_constant
= true
2023 .op
= midgard_alu_op_f2u8
,
2024 .reg_mode
= midgard_reg_mode_16
,
2025 .dest_override
= midgard_dest_override_lower
,
2026 .outmod
= midgard_outmod_pos
,
2028 .src1
= vector_alu_srco_unsigned(alu_src
),
2029 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2033 emit_mir_instruction(ctx
, f2u8
);
2035 /* vmul.imov.quarter r0, r0, r0 */
2037 midgard_instruction imov_8
= {
2040 .src0
= SSA_UNUSED_1
,
2041 .src1
= SSA_FIXED_REGISTER(0),
2042 .dest
= SSA_FIXED_REGISTER(0),
2045 .op
= midgard_alu_op_imov
,
2046 .reg_mode
= midgard_reg_mode_8
,
2047 .dest_override
= midgard_dest_override_none
,
2048 .outmod
= midgard_outmod_int
,
2050 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2051 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2055 /* Emit branch epilogue with the 8-bit move as the source */
2057 emit_mir_instruction(ctx
, imov_8
);
2058 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2060 emit_mir_instruction(ctx
, imov_8
);
2061 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2064 static midgard_block
*
2065 emit_block(compiler_context
*ctx
, nir_block
*block
)
2067 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2068 list_addtail(&this_block
->link
, &ctx
->blocks
);
2070 this_block
->is_scheduled
= false;
2073 ctx
->texture_index
[0] = -1;
2074 ctx
->texture_index
[1] = -1;
2076 /* Add us as a successor to the block we are following */
2077 if (ctx
->current_block
)
2078 midgard_block_add_successor(ctx
->current_block
, this_block
);
2080 /* Set up current block */
2081 list_inithead(&this_block
->instructions
);
2082 ctx
->current_block
= this_block
;
2084 nir_foreach_instr(instr
, block
) {
2085 emit_instr(ctx
, instr
);
2086 ++ctx
->instruction_count
;
2089 inline_alu_constants(ctx
);
2090 embedded_to_inline_constant(ctx
);
2092 /* Perform heavylifting for aliasing */
2093 actualise_ssa_to_alias(ctx
);
2095 midgard_pair_load_store(ctx
, this_block
);
2097 /* Append fragment shader epilogue (value writeout) */
2098 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2099 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2101 emit_blend_epilogue(ctx
);
2103 emit_fragment_epilogue(ctx
);
2107 if (block
== nir_start_block(ctx
->func
->impl
))
2108 ctx
->initial_block
= this_block
;
2110 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2111 ctx
->final_block
= this_block
;
2113 /* Allow the next control flow to access us retroactively, for
2115 ctx
->current_block
= this_block
;
2117 /* Document the fallthrough chain */
2118 ctx
->previous_source_block
= this_block
;
2123 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2126 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2128 /* Conditional branches expect the condition in r31.w; emit a move for
2129 * that in the _previous_ block (which is the current block). */
2130 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2132 /* Speculatively emit the branch, but we can't fill it in until later */
2133 EMIT(branch
, true, true);
2134 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2136 /* Emit the two subblocks */
2137 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2139 /* Emit a jump from the end of the then block to the end of the else */
2140 EMIT(branch
, false, false);
2141 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2143 /* Emit second block, and check if it's empty */
2145 int else_idx
= ctx
->block_count
;
2146 int count_in
= ctx
->instruction_count
;
2147 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2148 int after_else_idx
= ctx
->block_count
;
2150 /* Now that we have the subblocks emitted, fix up the branches */
2155 if (ctx
->instruction_count
== count_in
) {
2156 /* The else block is empty, so don't emit an exit jump */
2157 mir_remove_instruction(then_exit
);
2158 then_branch
->branch
.target_block
= after_else_idx
;
2160 then_branch
->branch
.target_block
= else_idx
;
2161 then_exit
->branch
.target_block
= after_else_idx
;
2166 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2168 /* Remember where we are */
2169 midgard_block
*start_block
= ctx
->current_block
;
2171 /* Allocate a loop number, growing the current inner loop depth */
2172 int loop_idx
= ++ctx
->current_loop_depth
;
2174 /* Get index from before the body so we can loop back later */
2175 int start_idx
= ctx
->block_count
;
2177 /* Emit the body itself */
2178 emit_cf_list(ctx
, &nloop
->body
);
2180 /* Branch back to loop back */
2181 struct midgard_instruction br_back
= v_branch(false, false);
2182 br_back
.branch
.target_block
= start_idx
;
2183 emit_mir_instruction(ctx
, br_back
);
2185 /* Mark down that branch in the graph. Note that we're really branching
2186 * to the block *after* we started in. TODO: Why doesn't the branch
2187 * itself have an off-by-one then...? */
2188 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2190 /* Find the index of the block about to follow us (note: we don't add
2191 * one; blocks are 0-indexed so we get a fencepost problem) */
2192 int break_block_idx
= ctx
->block_count
;
2194 /* Fix up the break statements we emitted to point to the right place,
2195 * now that we can allocate a block number for them */
2197 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2198 mir_foreach_instr_in_block(block
, ins
) {
2199 if (ins
->type
!= TAG_ALU_4
) continue;
2200 if (!ins
->compact_branch
) continue;
2201 if (ins
->prepacked_branch
) continue;
2203 /* We found a branch -- check the type to see if we need to do anything */
2204 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2206 /* It's a break! Check if it's our break */
2207 if (ins
->branch
.target_break
!= loop_idx
) continue;
2209 /* Okay, cool, we're breaking out of this loop.
2210 * Rewrite from a break to a goto */
2212 ins
->branch
.target_type
= TARGET_GOTO
;
2213 ins
->branch
.target_block
= break_block_idx
;
2217 /* Now that we've finished emitting the loop, free up the depth again
2218 * so we play nice with recursion amid nested loops */
2219 --ctx
->current_loop_depth
;
2222 static midgard_block
*
2223 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2225 midgard_block
*start_block
= NULL
;
2227 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2228 switch (node
->type
) {
2229 case nir_cf_node_block
: {
2230 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2233 start_block
= block
;
2238 case nir_cf_node_if
:
2239 emit_if(ctx
, nir_cf_node_as_if(node
));
2242 case nir_cf_node_loop
:
2243 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2246 case nir_cf_node_function
:
2255 /* Due to lookahead, we need to report the first tag executed in the command
2256 * stream and in branch targets. An initial block might be empty, so iterate
2257 * until we find one that 'works' */
2260 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2262 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2264 unsigned first_tag
= 0;
2267 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2269 if (initial_bundle
) {
2270 first_tag
= initial_bundle
->tag
;
2274 /* Initial block is empty, try the next block */
2275 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2276 } while(initial_block
!= NULL
);
2283 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2285 struct util_dynarray
*compiled
= &program
->compiled
;
2287 midgard_debug
= debug_get_option_midgard_debug();
2289 compiler_context ictx
= {
2291 .stage
= nir
->info
.stage
,
2293 .is_blend
= is_blend
,
2294 .blend_constant_offset
= -1,
2296 .alpha_ref
= program
->alpha_ref
2299 compiler_context
*ctx
= &ictx
;
2301 /* TODO: Decide this at runtime */
2302 ctx
->uniform_cutoff
= 8;
2304 /* Initialize at a global (not block) level hash tables */
2306 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2307 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2308 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2309 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2310 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2312 /* Record the varying mapping for the command stream's bookkeeping */
2314 struct exec_list
*varyings
=
2315 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2317 nir_foreach_variable(var
, varyings
) {
2318 unsigned loc
= var
->data
.driver_location
;
2319 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2321 for (int c
= 0; c
< sz
; ++c
) {
2322 program
->varyings
[loc
+ c
] = var
->data
.location
;
2326 /* Lower gl_Position pre-optimisation */
2328 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2329 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2331 NIR_PASS_V(nir
, nir_lower_var_copies
);
2332 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2333 NIR_PASS_V(nir
, nir_split_var_copies
);
2334 NIR_PASS_V(nir
, nir_lower_var_copies
);
2335 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2336 NIR_PASS_V(nir
, nir_lower_var_copies
);
2337 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2339 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2341 /* Optimisation passes */
2345 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2346 nir_print_shader(nir
, stdout
);
2349 /* Assign sysvals and counts, now that we're sure
2350 * (post-optimisation) */
2352 midgard_nir_assign_sysvals(ctx
, nir
);
2354 program
->uniform_count
= nir
->num_uniforms
;
2355 program
->sysval_count
= ctx
->sysval_count
;
2356 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2358 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2359 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
2361 nir_foreach_function(func
, nir
) {
2365 list_inithead(&ctx
->blocks
);
2366 ctx
->block_count
= 0;
2369 emit_cf_list(ctx
, &func
->impl
->body
);
2370 emit_block(ctx
, func
->impl
->end_block
);
2372 break; /* TODO: Multi-function shaders */
2375 util_dynarray_init(compiled
, NULL
);
2377 /* MIR-level optimizations */
2379 bool progress
= false;
2384 mir_foreach_block(ctx
, block
) {
2385 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2386 progress
|= midgard_opt_copy_prop(ctx
, block
);
2387 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
2388 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2393 schedule_program(ctx
);
2395 /* Now that all the bundles are scheduled and we can calculate block
2396 * sizes, emit actual branch instructions rather than placeholders */
2398 int br_block_idx
= 0;
2400 mir_foreach_block(ctx
, block
) {
2401 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2402 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2403 midgard_instruction
*ins
= bundle
->instructions
[c
];
2405 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2407 if (ins
->prepacked_branch
) continue;
2409 /* Parse some basic branch info */
2410 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2411 bool is_conditional
= ins
->branch
.conditional
;
2412 bool is_inverted
= ins
->branch
.invert_conditional
;
2413 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2415 /* Determine the block we're jumping to */
2416 int target_number
= ins
->branch
.target_block
;
2418 /* Report the destination tag */
2419 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2421 /* Count up the number of quadwords we're
2422 * jumping over = number of quadwords until
2423 * (br_block_idx, target_number) */
2425 int quadword_offset
= 0;
2428 /* Jump to the end of the shader. We
2429 * need to include not only the
2430 * following blocks, but also the
2431 * contents of our current block (since
2432 * discard can come in the middle of
2435 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2437 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2438 quadword_offset
+= quadword_size(bun
->tag
);
2441 mir_foreach_block_from(ctx
, blk
, b
) {
2442 quadword_offset
+= b
->quadword_count
;
2445 } else if (target_number
> br_block_idx
) {
2448 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2449 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2452 quadword_offset
+= blk
->quadword_count
;
2455 /* Jump backwards */
2457 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2458 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2461 quadword_offset
-= blk
->quadword_count
;
2465 /* Unconditional extended branches (far jumps)
2466 * have issues, so we always use a conditional
2467 * branch, setting the condition to always for
2468 * unconditional. For compact unconditional
2469 * branches, cond isn't used so it doesn't
2470 * matter what we pick. */
2472 midgard_condition cond
=
2473 !is_conditional
? midgard_condition_always
:
2474 is_inverted
? midgard_condition_false
:
2475 midgard_condition_true
;
2477 midgard_jmp_writeout_op op
=
2478 is_discard
? midgard_jmp_writeout_op_discard
:
2479 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2480 midgard_jmp_writeout_op_branch_cond
;
2483 midgard_branch_extended branch
=
2484 midgard_create_branch_extended(
2489 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2490 } else if (is_conditional
|| is_discard
) {
2491 midgard_branch_cond branch
= {
2493 .dest_tag
= dest_tag
,
2494 .offset
= quadword_offset
,
2498 assert(branch
.offset
== quadword_offset
);
2500 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2502 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2504 midgard_branch_uncond branch
= {
2506 .dest_tag
= dest_tag
,
2507 .offset
= quadword_offset
,
2511 assert(branch
.offset
== quadword_offset
);
2513 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2521 /* Emit flat binary from the instruction arrays. Iterate each block in
2522 * sequence. Save instruction boundaries such that lookahead tags can
2523 * be assigned easily */
2525 /* Cache _all_ bundles in source order for lookahead across failed branches */
2527 int bundle_count
= 0;
2528 mir_foreach_block(ctx
, block
) {
2529 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2531 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2533 mir_foreach_block(ctx
, block
) {
2534 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2535 source_order_bundles
[bundle_idx
++] = bundle
;
2539 int current_bundle
= 0;
2541 /* Midgard prefetches instruction types, so during emission we
2542 * need to lookahead. Unless this is the last instruction, in
2543 * which we return 1. Or if this is the second to last and the
2544 * last is an ALU, then it's also 1... */
2546 mir_foreach_block(ctx
, block
) {
2547 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2550 if (current_bundle
+ 1 < bundle_count
) {
2551 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2553 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2560 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2564 /* TODO: Free deeper */
2565 //util_dynarray_fini(&block->instructions);
2568 free(source_order_bundles
);
2570 /* Report the very first tag executed */
2571 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2573 /* Deal with off-by-one related to the fencepost problem */
2574 program
->work_register_count
= ctx
->work_registers
+ 1;
2576 program
->can_discard
= ctx
->can_discard
;
2577 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2579 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2581 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2582 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);