2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 /* Successors: always one forward (the block after us), maybe
173 * one backwards (for a backward branch). No need for a second
174 * forward, since graph traversal would get there eventually
176 struct midgard_block
*successors
[2];
177 unsigned nr_successors
;
179 /* The successors pointer form a graph, and in the case of
180 * complex control flow, this graph has a cycles. To aid
181 * traversal during liveness analysis, we have a visited?
182 * boolean for passes to use as they see fit, provided they
188 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
190 block
->successors
[block
->nr_successors
++] = successor
;
191 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
194 /* Helpers to generate midgard_instruction's using macro magic, since every
195 * driver seems to do it that way */
197 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
198 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
200 #define M_LOAD_STORE(name, rname, uname) \
201 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
202 midgard_instruction i = { \
203 .type = TAG_LOAD_STORE_4, \
210 .op = midgard_op_##name, \
212 .swizzle = SWIZZLE_XYZW, \
220 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
221 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
223 const midgard_vector_alu_src blank_alu_src
= {
224 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
227 const midgard_vector_alu_src blank_alu_src_xxxx
= {
228 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
231 const midgard_scalar_alu_src blank_scalar_alu_src
= {
235 /* Used for encoding the unused source of 1-op instructions */
236 const midgard_vector_alu_src zero_alu_src
= { 0 };
238 /* Coerce structs to integer */
241 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
244 memcpy(&u
, &src
, sizeof(src
));
248 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
249 * the corresponding Midgard source */
251 static midgard_vector_alu_src
252 vector_alu_modifiers(nir_alu_src
*src
)
254 if (!src
) return blank_alu_src
;
256 midgard_vector_alu_src alu_src
= {
258 .negate
= src
->negate
,
261 .half
= 0, /* TODO */
262 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
268 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
270 static midgard_instruction
271 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
273 midgard_instruction ins
= {
276 .src0
= SSA_UNUSED_1
,
281 .op
= midgard_alu_op_fmov
,
282 .reg_mode
= midgard_reg_mode_full
,
283 .dest_override
= midgard_dest_override_none
,
285 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
286 .src2
= vector_alu_srco_unsigned(mod
)
293 /* load/store instructions have both 32-bit and 16-bit variants, depending on
294 * whether we are using vectors composed of highp or mediump. At the moment, we
295 * don't support half-floats -- this requires changes in other parts of the
296 * compiler -- therefore the 16-bit versions are commented out. */
298 //M_LOAD(load_attr_16);
299 M_LOAD(load_attr_32
);
300 //M_LOAD(load_vary_16);
301 M_LOAD(load_vary_32
);
302 //M_LOAD(load_uniform_16);
303 M_LOAD(load_uniform_32
);
304 M_LOAD(load_color_buffer_8
);
305 //M_STORE(store_vary_16);
306 M_STORE(store_vary_32
);
307 M_STORE(store_cubemap_coords
);
309 static midgard_instruction
310 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
312 midgard_branch_cond branch
= {
320 memcpy(&compact
, &branch
, sizeof(branch
));
322 midgard_instruction ins
= {
324 .unit
= ALU_ENAB_BR_COMPACT
,
325 .prepacked_branch
= true,
326 .compact_branch
= true,
327 .br_compact
= compact
330 if (op
== midgard_jmp_writeout_op_writeout
)
336 static midgard_instruction
337 v_branch(bool conditional
, bool invert
)
339 midgard_instruction ins
= {
341 .unit
= ALU_ENAB_BRANCH
,
342 .compact_branch
= true,
344 .conditional
= conditional
,
345 .invert_conditional
= invert
352 static midgard_branch_extended
353 midgard_create_branch_extended( midgard_condition cond
,
354 midgard_jmp_writeout_op op
,
356 signed quadword_offset
)
358 /* For unclear reasons, the condition code is repeated 8 times */
359 uint16_t duplicated_cond
=
369 midgard_branch_extended branch
= {
371 .dest_tag
= dest_tag
,
372 .offset
= quadword_offset
,
373 .cond
= duplicated_cond
379 typedef struct midgard_bundle
{
380 /* Tag for the overall bundle */
383 /* Instructions contained by the bundle */
384 int instruction_count
;
385 midgard_instruction instructions
[5];
387 /* Bundle-wide ALU configuration */
390 bool has_embedded_constants
;
392 bool has_blend_constant
;
394 uint16_t register_words
[8];
395 int register_words_count
;
397 uint64_t body_words
[8];
399 int body_words_count
;
402 typedef struct compiler_context
{
404 gl_shader_stage stage
;
406 /* Is internally a blend shader? Depends on stage == FRAGMENT */
409 /* Tracking for blend constant patching */
410 int blend_constant_number
;
411 int blend_constant_offset
;
413 /* Current NIR function */
416 /* Unordered list of midgard_blocks */
418 struct list_head blocks
;
420 midgard_block
*initial_block
;
421 midgard_block
*previous_source_block
;
422 midgard_block
*final_block
;
424 /* List of midgard_instructions emitted for the current block */
425 midgard_block
*current_block
;
427 /* The current "depth" of the loop, for disambiguating breaks/continues
428 * when using nested loops */
429 int current_loop_depth
;
431 /* Constants which have been loaded, for later inlining */
432 struct hash_table_u64
*ssa_constants
;
434 /* SSA indices to be outputted to corresponding varying offset */
435 struct hash_table_u64
*ssa_varyings
;
437 /* SSA values / registers which have been aliased. Naively, these
438 * demand a fmov output; instead, we alias them in a later pass to
439 * avoid the wasted op.
441 * A note on encoding: to avoid dynamic memory management here, rather
442 * than ampping to a pointer, we map to the source index; the key
443 * itself is just the destination index. */
445 struct hash_table_u64
*ssa_to_alias
;
446 struct set
*leftover_ssa_to_alias
;
448 /* Actual SSA-to-register for RA */
449 struct hash_table_u64
*ssa_to_register
;
451 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
452 struct hash_table_u64
*hash_to_temp
;
456 /* Just the count of the max register used. Higher count => higher
457 * register pressure */
460 /* Used for cont/last hinting. Increase when a tex op is added.
461 * Decrease when a tex op is removed. */
462 int texture_op_count
;
464 /* Mapping of texture register -> SSA index for unaliasing */
465 int texture_index
[2];
467 /* If any path hits a discard instruction */
470 /* The number of uniforms allowable for the fast path */
473 /* Count of instructions emitted from NIR overall, across all blocks */
474 int instruction_count
;
476 /* Alpha ref value passed in */
479 /* The index corresponding to the fragment output */
480 unsigned fragment_output
;
482 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
483 unsigned sysvals
[MAX_SYSVAL_COUNT
];
484 unsigned sysval_count
;
485 struct hash_table_u64
*sysval_to_id
;
488 /* Append instruction to end of current block */
490 static midgard_instruction
*
491 mir_upload_ins(struct midgard_instruction ins
)
493 midgard_instruction
*heap
= malloc(sizeof(ins
));
494 memcpy(heap
, &ins
, sizeof(ins
));
499 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
501 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
505 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
507 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
511 mir_remove_instruction(struct midgard_instruction
*ins
)
513 list_del(&ins
->link
);
516 static midgard_instruction
*
517 mir_prev_op(struct midgard_instruction
*ins
)
519 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
522 static midgard_instruction
*
523 mir_next_op(struct midgard_instruction
*ins
)
525 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
528 static midgard_block
*
529 mir_next_block(struct midgard_block
*blk
)
531 return list_first_entry(&(blk
->link
), midgard_block
, link
);
535 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
536 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
538 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
539 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
540 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
541 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
542 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
543 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
546 static midgard_instruction
*
547 mir_last_in_block(struct midgard_block
*block
)
549 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
552 static midgard_block
*
553 mir_get_block(compiler_context
*ctx
, int idx
)
555 struct list_head
*lst
= &ctx
->blocks
;
560 return (struct midgard_block
*) lst
;
563 /* Pretty printer for internal Midgard IR */
566 print_mir_source(int source
)
568 if (source
>= SSA_FIXED_MINIMUM
) {
569 /* Specific register */
570 int reg
= SSA_REG_FROM_FIXED(source
);
572 /* TODO: Moving threshold */
573 if (reg
> 16 && reg
< 24)
574 printf("u%d", 23 - reg
);
578 printf("%d", source
);
583 print_mir_instruction(midgard_instruction
*ins
)
589 midgard_alu_op op
= ins
->alu
.op
;
590 const char *name
= alu_opcode_names
[op
];
593 printf("%d.", ins
->unit
);
595 printf("%s", name
? name
: "??");
599 case TAG_LOAD_STORE_4
: {
600 midgard_load_store_op op
= ins
->load_store
.op
;
601 const char *name
= load_store_opcode_names
[op
];
608 case TAG_TEXTURE_4
: {
617 ssa_args
*args
= &ins
->ssa_args
;
619 printf(" %d, ", args
->dest
);
621 print_mir_source(args
->src0
);
624 if (args
->inline_constant
)
625 printf("#%d", ins
->inline_constant
);
627 print_mir_source(args
->src1
);
629 if (ins
->has_constants
)
630 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
636 print_mir_block(midgard_block
*block
)
640 mir_foreach_instr_in_block(block
, ins
) {
641 print_mir_instruction(ins
);
648 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
650 ins
->has_constants
= true;
651 memcpy(&ins
->constants
, constants
, 16);
653 /* If this is the special blend constant, mark this instruction */
655 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
656 ins
->has_blend_constant
= true;
660 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
662 return glsl_count_attribute_slots(type
, false);
665 /* Lower fdot2 to a vector multiplication followed by channel addition */
667 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
669 if (alu
->op
!= nir_op_fdot2
)
672 b
->cursor
= nir_before_instr(&alu
->instr
);
674 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
675 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
677 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
679 nir_ssa_def
*sum
= nir_fadd(b
,
680 nir_channel(b
, product
, 0),
681 nir_channel(b
, product
, 1));
683 /* Replace the fdot2 with this sum */
684 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
688 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
690 switch (instr
->intrinsic
) {
691 case nir_intrinsic_load_viewport_scale
:
692 return PAN_SYSVAL_VIEWPORT_SCALE
;
693 case nir_intrinsic_load_viewport_offset
:
694 return PAN_SYSVAL_VIEWPORT_OFFSET
;
701 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
705 if (instr
->type
== nir_instr_type_intrinsic
) {
706 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
707 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
713 /* We have a sysval load; check if it's already been assigned */
715 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
718 /* It hasn't -- so assign it now! */
720 unsigned id
= ctx
->sysval_count
++;
721 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
722 ctx
->sysvals
[id
] = sysval
;
726 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
728 ctx
->sysval_count
= 0;
730 nir_foreach_function(function
, shader
) {
731 if (!function
->impl
) continue;
733 nir_foreach_block(block
, function
->impl
) {
734 nir_foreach_instr_safe(instr
, block
) {
735 midgard_nir_assign_sysval_body(ctx
, instr
);
742 midgard_nir_lower_fdot2(nir_shader
*shader
)
744 bool progress
= false;
746 nir_foreach_function(function
, shader
) {
747 if (!function
->impl
) continue;
750 nir_builder
*b
= &_b
;
751 nir_builder_init(b
, function
->impl
);
753 nir_foreach_block(block
, function
->impl
) {
754 nir_foreach_instr_safe(instr
, block
) {
755 if (instr
->type
!= nir_instr_type_alu
) continue;
757 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
758 midgard_nir_lower_fdot2_body(b
, alu
);
764 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
772 optimise_nir(nir_shader
*nir
)
776 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
777 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
779 nir_lower_tex_options lower_tex_options
= {
783 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
788 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
789 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
791 NIR_PASS(progress
, nir
, nir_copy_prop
);
792 NIR_PASS(progress
, nir
, nir_opt_dce
);
793 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
794 NIR_PASS(progress
, nir
, nir_opt_cse
);
795 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
796 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
797 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
798 NIR_PASS(progress
, nir
, nir_opt_undef
);
799 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
802 nir_var_function_temp
);
804 /* TODO: Enable vectorize when merged upstream */
805 // NIR_PASS(progress, nir, nir_opt_vectorize);
808 /* Must be run at the end to prevent creation of fsin/fcos ops */
809 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
814 NIR_PASS(progress
, nir
, nir_opt_dce
);
815 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
816 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
817 NIR_PASS(progress
, nir
, nir_copy_prop
);
820 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
821 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
823 /* Lower mods for float ops only. Integer ops don't support modifiers
824 * (saturate doesn't make sense on integers, neg/abs require dedicated
827 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
828 NIR_PASS(progress
, nir
, nir_copy_prop
);
829 NIR_PASS(progress
, nir
, nir_opt_dce
);
831 /* We implement booleans as 32-bit 0/~0 */
832 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
834 /* Take us out of SSA */
835 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
836 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
838 /* We are a vector architecture; write combine where possible */
839 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
840 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
842 NIR_PASS(progress
, nir
, nir_opt_dce
);
845 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
846 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
847 * r0. See the comments in compiler_context */
850 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
852 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
853 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
856 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
859 unalias_ssa(compiler_context
*ctx
, int dest
)
861 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
862 /* TODO: Remove from leftover or no? */
866 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
868 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
872 midgard_is_pinned(compiler_context
*ctx
, int index
)
874 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
877 /* Do not actually emit a load; instead, cache the constant for inlining */
880 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
882 nir_ssa_def def
= instr
->def
;
884 float *v
= ralloc_array(NULL
, float, 4);
885 nir_const_load_to_arr(v
, instr
, f32
);
886 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
889 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
893 expand_writemask(unsigned mask
)
897 for (int i
= 0; i
< 4; ++i
)
905 squeeze_writemask(unsigned mask
)
909 for (int i
= 0; i
< 4; ++i
)
910 if (mask
& (3 << (2 * i
)))
917 /* Determines effective writemask, taking quirks and expansion into account */
919 effective_writemask(midgard_vector_alu
*alu
)
921 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
924 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
926 /* If there is a fixed channel count, construct the appropriate mask */
929 return (1 << channel_count
) - 1;
931 /* Otherwise, just squeeze the existing mask */
932 return squeeze_writemask(alu
->mask
);
936 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
938 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
941 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
946 /* If no temp is find, allocate one */
947 temp
= ctx
->temp_count
++;
948 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
950 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
956 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
959 return src
->ssa
->index
;
961 assert(!src
->reg
.indirect
);
962 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
967 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
970 return dst
->ssa
.index
;
972 assert(!dst
->reg
.indirect
);
973 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
978 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
980 return nir_src_index(ctx
, &src
->src
);
983 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
984 * a conditional test) into that register */
987 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
989 int condition
= nir_src_index(ctx
, src
);
991 /* Source to swizzle the desired component into w */
993 const midgard_vector_alu_src alu_src
= {
994 .swizzle
= SWIZZLE(component
, component
, component
, component
),
997 /* There is no boolean move instruction. Instead, we simulate a move by
998 * ANDing the condition with itself to get it into r31.w */
1000 midgard_instruction ins
= {
1002 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
1006 .dest
= SSA_FIXED_REGISTER(31),
1009 .op
= midgard_alu_op_iand
,
1010 .reg_mode
= midgard_reg_mode_full
,
1011 .dest_override
= midgard_dest_override_none
,
1012 .mask
= (0x3 << 6), /* w */
1013 .src1
= vector_alu_srco_unsigned(alu_src
),
1014 .src2
= vector_alu_srco_unsigned(alu_src
)
1018 emit_mir_instruction(ctx
, ins
);
1021 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1022 * pinning to eliminate this move in all known cases */
1025 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1027 int offset
= nir_src_index(ctx
, src
);
1029 midgard_instruction ins
= {
1032 .src0
= SSA_UNUSED_1
,
1034 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1037 .op
= midgard_alu_op_imov
,
1038 .reg_mode
= midgard_reg_mode_full
,
1039 .dest_override
= midgard_dest_override_none
,
1040 .mask
= (0x3 << 6), /* w */
1041 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1042 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1046 emit_mir_instruction(ctx
, ins
);
1049 #define ALU_CASE(nir, _op) \
1050 case nir_op_##nir: \
1051 op = midgard_alu_op_##_op; \
1055 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1057 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1059 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1060 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1061 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1063 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1064 * supported. A few do not and are commented for now. Also, there are a
1065 * number of NIR ops which Midgard does not support and need to be
1066 * lowered, also TODO. This switch block emits the opcode and calling
1067 * convention of the Midgard instruction; actual packing is done in
1072 switch (instr
->op
) {
1073 ALU_CASE(fadd
, fadd
);
1074 ALU_CASE(fmul
, fmul
);
1075 ALU_CASE(fmin
, fmin
);
1076 ALU_CASE(fmax
, fmax
);
1077 ALU_CASE(imin
, imin
);
1078 ALU_CASE(imax
, imax
);
1079 ALU_CASE(umin
, umin
);
1080 ALU_CASE(umax
, umax
);
1081 ALU_CASE(fmov
, fmov
);
1082 ALU_CASE(ffloor
, ffloor
);
1083 ALU_CASE(fround_even
, froundeven
);
1084 ALU_CASE(ftrunc
, ftrunc
);
1085 ALU_CASE(fceil
, fceil
);
1086 ALU_CASE(fdot3
, fdot3
);
1087 ALU_CASE(fdot4
, fdot4
);
1088 ALU_CASE(iadd
, iadd
);
1089 ALU_CASE(isub
, isub
);
1090 ALU_CASE(imul
, imul
);
1091 ALU_CASE(iabs
, iabs
);
1093 /* XXX: Use fmov, not imov, since imov was causing major
1094 * issues with texture precision? XXX research */
1095 ALU_CASE(imov
, imov
);
1097 ALU_CASE(feq32
, feq
);
1098 ALU_CASE(fne32
, fne
);
1099 ALU_CASE(flt32
, flt
);
1100 ALU_CASE(ieq32
, ieq
);
1101 ALU_CASE(ine32
, ine
);
1102 ALU_CASE(ilt32
, ilt
);
1103 ALU_CASE(ult32
, ult
);
1105 /* We don't have a native b2f32 instruction. Instead, like many
1106 * GPUs, we exploit booleans as 0/~0 for false/true, and
1107 * correspondingly AND
1108 * by 1.0 to do the type conversion. For the moment, prime us
1111 * iand [whatever], #0
1113 * At the end of emit_alu (as MIR), we'll fix-up the constant
1116 ALU_CASE(b2f32
, iand
);
1117 ALU_CASE(b2i32
, iand
);
1119 /* Likewise, we don't have a dedicated f2b32 instruction, but
1120 * we can do a "not equal to 0.0" test. */
1122 ALU_CASE(f2b32
, fne
);
1123 ALU_CASE(i2b32
, ine
);
1125 ALU_CASE(frcp
, frcp
);
1126 ALU_CASE(frsq
, frsqrt
);
1127 ALU_CASE(fsqrt
, fsqrt
);
1128 ALU_CASE(fexp2
, fexp2
);
1129 ALU_CASE(flog2
, flog2
);
1131 ALU_CASE(f2i32
, f2i
);
1132 ALU_CASE(f2u32
, f2u
);
1133 ALU_CASE(i2f32
, i2f
);
1134 ALU_CASE(u2f32
, u2f
);
1136 ALU_CASE(fsin
, fsin
);
1137 ALU_CASE(fcos
, fcos
);
1139 ALU_CASE(iand
, iand
);
1141 ALU_CASE(ixor
, ixor
);
1142 ALU_CASE(inot
, inot
);
1143 ALU_CASE(ishl
, ishl
);
1144 ALU_CASE(ishr
, iasr
);
1145 ALU_CASE(ushr
, ilsr
);
1147 ALU_CASE(b32all_fequal2
, fball_eq
);
1148 ALU_CASE(b32all_fequal3
, fball_eq
);
1149 ALU_CASE(b32all_fequal4
, fball_eq
);
1151 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1152 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1153 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1155 ALU_CASE(b32all_iequal2
, iball_eq
);
1156 ALU_CASE(b32all_iequal3
, iball_eq
);
1157 ALU_CASE(b32all_iequal4
, iball_eq
);
1159 ALU_CASE(b32any_inequal2
, ibany_neq
);
1160 ALU_CASE(b32any_inequal3
, ibany_neq
);
1161 ALU_CASE(b32any_inequal4
, ibany_neq
);
1163 /* For greater-or-equal, we lower to less-or-equal and flip the
1169 case nir_op_uge32
: {
1171 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1172 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1173 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1174 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1177 /* Swap via temporary */
1178 nir_alu_src temp
= instr
->src
[1];
1179 instr
->src
[1] = instr
->src
[0];
1180 instr
->src
[0] = temp
;
1185 case nir_op_b32csel
: {
1186 op
= midgard_alu_op_fcsel
;
1188 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1191 /* Figure out which component the condition is in */
1193 unsigned comp
= instr
->src
[0].swizzle
[0];
1195 /* Make sure NIR isn't throwing a mixed condition at us */
1197 for (unsigned c
= 1; c
< nr_components
; ++c
)
1198 assert(instr
->src
[0].swizzle
[c
] == comp
);
1200 /* Emit the condition into r31.w */
1201 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1203 /* The condition is the first argument; move the other
1204 * arguments up one to be a binary instruction for
1207 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1212 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1217 /* Fetch unit, quirks, etc information */
1218 unsigned opcode_props
= alu_opcode_props
[op
];
1219 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1221 /* Initialise fields common between scalar/vector instructions */
1222 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1224 /* src0 will always exist afaik, but src1 will not for 1-argument
1225 * instructions. The latter can only be fetched if the instruction
1226 * needs it, or else we may segfault. */
1228 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1229 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1231 /* Rather than use the instruction generation helpers, we do it
1232 * ourselves here to avoid the mess */
1234 midgard_instruction ins
= {
1237 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1238 .src1
= quirk_flipped_r24
? src0
: src1
,
1243 nir_alu_src
*nirmods
[2] = { NULL
};
1245 if (nr_inputs
== 2) {
1246 nirmods
[0] = &instr
->src
[0];
1247 nirmods
[1] = &instr
->src
[1];
1248 } else if (nr_inputs
== 1) {
1249 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1254 midgard_vector_alu alu
= {
1256 .reg_mode
= midgard_reg_mode_full
,
1257 .dest_override
= midgard_dest_override_none
,
1260 /* Writemask only valid for non-SSA NIR */
1261 .mask
= expand_writemask((1 << nr_components
) - 1),
1263 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1264 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1267 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1270 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1274 /* Late fixup for emulated instructions */
1276 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1277 /* Presently, our second argument is an inline #0 constant.
1278 * Switch over to an embedded 1.0 constant (that can't fit
1279 * inline, since we're 32-bit, not 16-bit like the inline
1282 ins
.ssa_args
.inline_constant
= false;
1283 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1284 ins
.has_constants
= true;
1286 if (instr
->op
== nir_op_b2f32
) {
1287 ins
.constants
[0] = 1.0f
;
1289 /* Type pun it into place */
1291 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1294 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1295 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1296 ins
.ssa_args
.inline_constant
= false;
1297 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1298 ins
.has_constants
= true;
1299 ins
.constants
[0] = 0.0f
;
1300 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1303 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1304 /* To avoid duplicating the lookup tables (probably), true LUT
1305 * instructions can only operate as if they were scalars. Lower
1306 * them here by changing the component. */
1308 uint8_t original_swizzle
[4];
1309 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1311 for (int i
= 0; i
< nr_components
; ++i
) {
1312 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1314 for (int j
= 0; j
< 4; ++j
)
1315 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1317 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1318 emit_mir_instruction(ctx
, ins
);
1321 emit_mir_instruction(ctx
, ins
);
1328 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1330 /* TODO: half-floats */
1332 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1333 /* Fast path: For the first 16 uniforms, direct accesses are
1334 * 0-cycle, since they're just a register fetch in the usual
1335 * case. So, we alias the registers while we're still in
1338 int reg_slot
= 23 - offset
;
1339 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1341 /* Otherwise, read from the 'special' UBO to access
1342 * higher-indexed uniforms, at a performance cost. More
1343 * generally, we're emitting a UBO read instruction. */
1345 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1347 /* TODO: Don't split */
1348 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1349 ins
.load_store
.address
= offset
>> 3;
1351 if (indirect_offset
) {
1352 emit_indirect_offset(ctx
, indirect_offset
);
1353 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1355 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1358 emit_mir_instruction(ctx
, ins
);
1363 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1365 /* First, pull out the destination */
1366 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1368 /* Now, figure out which uniform this is */
1369 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1370 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1372 /* Sysvals are prefix uniforms */
1373 unsigned uniform
= ((uintptr_t) val
) - 1;
1375 /* Emit the read itself -- this is never indirect */
1376 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1380 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1382 unsigned offset
, reg
;
1384 switch (instr
->intrinsic
) {
1385 case nir_intrinsic_discard_if
:
1386 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1390 case nir_intrinsic_discard
: {
1391 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1392 struct midgard_instruction discard
= v_branch(conditional
, false);
1393 discard
.branch
.target_type
= TARGET_DISCARD
;
1394 emit_mir_instruction(ctx
, discard
);
1396 ctx
->can_discard
= true;
1400 case nir_intrinsic_load_uniform
:
1401 case nir_intrinsic_load_input
:
1402 offset
= nir_intrinsic_base(instr
);
1404 bool direct
= nir_src_is_const(instr
->src
[0]);
1407 offset
+= nir_src_as_uint(instr
->src
[0]);
1410 reg
= nir_dest_index(ctx
, &instr
->dest
);
1412 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1413 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1414 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1415 /* XXX: Half-floats? */
1416 /* TODO: swizzle, mask */
1418 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1420 midgard_varying_parameter p
= {
1422 .interpolation
= midgard_interp_default
,
1423 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1427 memcpy(&u
, &p
, sizeof(p
));
1428 ins
.load_store
.varying_parameters
= u
;
1431 /* We have the offset totally ready */
1432 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1434 /* We have it partially ready, but we need to
1435 * add in the dynamic index, moved to r27.w */
1436 emit_indirect_offset(ctx
, &instr
->src
[0]);
1437 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1440 emit_mir_instruction(ctx
, ins
);
1441 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1442 /* Constant encoded as a pinned constant */
1444 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1445 ins
.has_constants
= true;
1446 ins
.has_blend_constant
= true;
1447 emit_mir_instruction(ctx
, ins
);
1448 } else if (ctx
->is_blend
) {
1449 /* For blend shaders, a load might be
1450 * translated various ways depending on what
1451 * we're loading. Figure out how this is used */
1453 nir_variable
*out
= NULL
;
1455 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1456 int drvloc
= var
->data
.driver_location
;
1458 if (nir_intrinsic_base(instr
) == drvloc
) {
1466 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1467 /* Source color preloaded to r0 */
1469 midgard_pin_output(ctx
, reg
, 0);
1470 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1471 /* Destination color must be read from framebuffer */
1473 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1474 ins
.load_store
.swizzle
= 0; /* xxxx */
1476 /* Read each component sequentially */
1478 for (int c
= 0; c
< 4; ++c
) {
1479 ins
.load_store
.mask
= (1 << c
);
1480 ins
.load_store
.unknown
= c
;
1481 emit_mir_instruction(ctx
, ins
);
1484 /* vadd.u2f hr2, abs(hr2), #0 */
1486 midgard_vector_alu_src alu_src
= blank_alu_src
;
1488 alu_src
.half
= true;
1490 midgard_instruction u2f
= {
1494 .src1
= SSA_UNUSED_0
,
1496 .inline_constant
= true
1499 .op
= midgard_alu_op_u2f
,
1500 .reg_mode
= midgard_reg_mode_half
,
1501 .dest_override
= midgard_dest_override_none
,
1503 .src1
= vector_alu_srco_unsigned(alu_src
),
1504 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1508 emit_mir_instruction(ctx
, u2f
);
1510 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1512 alu_src
.abs
= false;
1514 midgard_instruction fmul
= {
1516 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1520 .src1
= SSA_UNUSED_0
,
1521 .inline_constant
= true
1524 .op
= midgard_alu_op_fmul
,
1525 .reg_mode
= midgard_reg_mode_full
,
1526 .dest_override
= midgard_dest_override_none
,
1527 .outmod
= midgard_outmod_sat
,
1529 .src1
= vector_alu_srco_unsigned(alu_src
),
1530 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1534 emit_mir_instruction(ctx
, fmul
);
1536 DBG("Unknown input in blend shader\n");
1539 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1540 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1541 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1542 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1543 emit_mir_instruction(ctx
, ins
);
1545 DBG("Unknown load\n");
1551 case nir_intrinsic_store_output
:
1552 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1554 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1556 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1558 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1559 /* gl_FragColor is not emitted with load/store
1560 * instructions. Instead, it gets plonked into
1561 * r0 at the end of the shader and we do the
1562 * framebuffer writeout dance. TODO: Defer
1565 midgard_pin_output(ctx
, reg
, 0);
1567 /* Save the index we're writing to for later reference
1568 * in the epilogue */
1570 ctx
->fragment_output
= reg
;
1571 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1572 /* Varyings are written into one of two special
1573 * varying register, r26 or r27. The register itself is selected as the register
1574 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1576 * Normally emitting fmov's is frowned upon,
1577 * but due to unique constraints of
1578 * REGISTER_VARYING, fmov emission + a
1579 * dedicated cleanup pass is the only way to
1580 * guarantee correctness when considering some
1581 * (common) edge cases XXX: FIXME */
1583 /* If this varying corresponds to a constant (why?!),
1584 * emit that now since it won't get picked up by
1585 * hoisting (since there is no corresponding move
1586 * emitted otherwise) */
1588 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1590 if (constant_value
) {
1591 /* Special case: emit the varying write
1592 * directly to r26 (looks funny in asm but it's
1593 * fine) and emit the store _now_. Possibly
1594 * slightly slower, but this is a really stupid
1595 * special case anyway (why on earth would you
1596 * have a constant varying? Your own fault for
1597 * slightly worse perf :P) */
1599 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1600 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1601 emit_mir_instruction(ctx
, ins
);
1603 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1604 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1605 emit_mir_instruction(ctx
, st
);
1607 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1609 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1612 DBG("Unknown store\n");
1618 case nir_intrinsic_load_alpha_ref_float
:
1619 assert(instr
->dest
.is_ssa
);
1621 float ref_value
= ctx
->alpha_ref
;
1623 float *v
= ralloc_array(NULL
, float, 4);
1624 memcpy(v
, &ref_value
, sizeof(float));
1625 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1628 case nir_intrinsic_load_viewport_scale
:
1629 case nir_intrinsic_load_viewport_offset
:
1630 emit_sysval_read(ctx
, instr
);
1634 printf ("Unhandled intrinsic\n");
1641 midgard_tex_format(enum glsl_sampler_dim dim
)
1644 case GLSL_SAMPLER_DIM_2D
:
1645 case GLSL_SAMPLER_DIM_EXTERNAL
:
1648 case GLSL_SAMPLER_DIM_3D
:
1651 case GLSL_SAMPLER_DIM_CUBE
:
1652 return TEXTURE_CUBE
;
1655 DBG("Unknown sampler dim type\n");
1662 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1665 //assert (!instr->sampler);
1666 //assert (!instr->texture_array_size);
1667 assert (instr
->op
== nir_texop_tex
);
1669 /* Allocate registers via a round robin scheme to alternate between the two registers */
1670 int reg
= ctx
->texture_op_count
& 1;
1671 int in_reg
= reg
, out_reg
= reg
;
1673 /* Make room for the reg */
1675 if (ctx
->texture_index
[reg
] > -1)
1676 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1678 int texture_index
= instr
->texture_index
;
1679 int sampler_index
= texture_index
;
1681 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1682 switch (instr
->src
[i
].src_type
) {
1683 case nir_tex_src_coord
: {
1684 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1686 midgard_vector_alu_src alu_src
= blank_alu_src
;
1688 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1690 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1691 /* For cubemaps, we need to load coords into
1692 * special r27, and then use a special ld/st op
1693 * to copy into the texture register */
1695 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1697 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1698 emit_mir_instruction(ctx
, move
);
1700 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1701 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1702 st
.load_store
.mask
= 0x3; /* xy? */
1703 st
.load_store
.swizzle
= alu_src
.swizzle
;
1704 emit_mir_instruction(ctx
, st
);
1707 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1709 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1710 emit_mir_instruction(ctx
, ins
);
1713 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1719 DBG("Unknown source type\n");
1726 /* No helper to build texture words -- we do it all here */
1727 midgard_instruction ins
= {
1728 .type
= TAG_TEXTURE_4
,
1730 .op
= TEXTURE_OP_NORMAL
,
1731 .format
= midgard_tex_format(instr
->sampler_dim
),
1732 .texture_handle
= texture_index
,
1733 .sampler_handle
= sampler_index
,
1735 /* TODO: Don't force xyzw */
1736 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1748 /* Assume we can continue; hint it out later */
1753 /* Set registers to read and write from the same place */
1754 ins
.texture
.in_reg_select
= in_reg
;
1755 ins
.texture
.out_reg_select
= out_reg
;
1757 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1758 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1759 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1760 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1761 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1763 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1764 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1765 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1768 emit_mir_instruction(ctx
, ins
);
1770 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1772 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1773 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1774 ctx
->texture_index
[reg
] = o_index
;
1776 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1777 emit_mir_instruction(ctx
, ins2
);
1779 /* Used for .cont and .last hinting */
1780 ctx
->texture_op_count
++;
1784 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1786 switch (instr
->type
) {
1787 case nir_jump_break
: {
1788 /* Emit a branch out of the loop */
1789 struct midgard_instruction br
= v_branch(false, false);
1790 br
.branch
.target_type
= TARGET_BREAK
;
1791 br
.branch
.target_break
= ctx
->current_loop_depth
;
1792 emit_mir_instruction(ctx
, br
);
1799 DBG("Unknown jump type %d\n", instr
->type
);
1805 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1807 switch (instr
->type
) {
1808 case nir_instr_type_load_const
:
1809 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1812 case nir_instr_type_intrinsic
:
1813 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1816 case nir_instr_type_alu
:
1817 emit_alu(ctx
, nir_instr_as_alu(instr
));
1820 case nir_instr_type_tex
:
1821 emit_tex(ctx
, nir_instr_as_tex(instr
));
1824 case nir_instr_type_jump
:
1825 emit_jump(ctx
, nir_instr_as_jump(instr
));
1828 case nir_instr_type_ssa_undef
:
1833 DBG("Unhandled instruction type\n");
1838 /* Determine the actual hardware from the index based on the RA results or special values */
1841 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1843 if (reg
>= SSA_FIXED_MINIMUM
)
1844 return SSA_REG_FROM_FIXED(reg
);
1847 assert(reg
< maxreg
);
1848 int r
= ra_get_node_reg(g
, reg
);
1849 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1854 /* fmov style unused */
1856 return REGISTER_UNUSED
;
1858 /* lut style unused */
1860 return REGISTER_UNUSED
;
1863 DBG("Unknown SSA register alias %d\n", reg
);
1870 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1872 /* Choose the first available register to minimise reported register pressure */
1874 for (int i
= 0; i
< 16; ++i
) {
1875 if (BITSET_TEST(regs
, i
)) {
1885 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1887 if (ins
->ssa_args
.src0
== src
) return true;
1888 if (ins
->ssa_args
.src1
== src
) return true;
1893 /* Determine if a variable is live in the successors of a block */
1895 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
1897 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
1898 midgard_block
*succ
= bl
->successors
[i
];
1900 /* If we already visited, the value we're seeking
1901 * isn't down this path (or we would have short
1904 if (succ
->visited
) continue;
1906 /* Otherwise (it's visited *now*), check the block */
1908 succ
->visited
= true;
1910 mir_foreach_instr_in_block(succ
, ins
) {
1911 if (midgard_is_live_in_instr(ins
, src
))
1915 /* ...and also, check *its* successors */
1916 if (is_live_after_successors(ctx
, succ
, src
))
1921 /* Welp. We're really not live. */
1927 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1929 /* Check the rest of the block for liveness */
1931 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1932 if (midgard_is_live_in_instr(ins
, src
))
1936 /* Check the rest of the blocks for liveness recursively */
1938 bool succ
= is_live_after_successors(ctx
, block
, src
);
1940 mir_foreach_block(ctx
, block
) {
1941 block
->visited
= false;
1948 allocate_registers(compiler_context
*ctx
)
1950 /* First, initialize the RA */
1951 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1953 /* Create a primary (general purpose) class, as well as special purpose
1954 * pipeline register classes */
1956 int primary_class
= ra_alloc_reg_class(regs
);
1957 int varying_class
= ra_alloc_reg_class(regs
);
1959 /* Add the full set of work registers */
1960 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1961 for (int i
= 0; i
< work_count
; ++i
)
1962 ra_class_add_reg(regs
, primary_class
, i
);
1964 /* Add special registers */
1965 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1966 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1968 /* We're done setting up */
1969 ra_set_finalize(regs
, NULL
);
1971 /* Transform the MIR into squeezed index form */
1972 mir_foreach_block(ctx
, block
) {
1973 mir_foreach_instr_in_block(block
, ins
) {
1974 if (ins
->compact_branch
) continue;
1976 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1977 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1978 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1980 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1981 print_mir_block(block
);
1984 /* Let's actually do register allocation */
1985 int nodes
= ctx
->temp_count
;
1986 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1988 /* Set everything to the work register class, unless it has somewhere
1991 mir_foreach_block(ctx
, block
) {
1992 mir_foreach_instr_in_block(block
, ins
) {
1993 if (ins
->compact_branch
) continue;
1995 if (ins
->ssa_args
.dest
< 0) continue;
1997 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1999 int class = primary_class
;
2001 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2005 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2006 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2009 unsigned reg
= temp
- 1;
2010 int t
= find_or_allocate_temp(ctx
, index
);
2011 ra_set_node_reg(g
, t
, reg
);
2015 /* Determine liveness */
2017 int *live_start
= malloc(nodes
* sizeof(int));
2018 int *live_end
= malloc(nodes
* sizeof(int));
2020 /* Initialize as non-existent */
2022 for (int i
= 0; i
< nodes
; ++i
) {
2023 live_start
[i
] = live_end
[i
] = -1;
2028 mir_foreach_block(ctx
, block
) {
2029 mir_foreach_instr_in_block(block
, ins
) {
2030 if (ins
->compact_branch
) continue;
2032 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2033 /* If this destination is not yet live, it is now since we just wrote it */
2035 int dest
= ins
->ssa_args
.dest
;
2037 if (live_start
[dest
] == -1)
2038 live_start
[dest
] = d
;
2041 /* Since we just used a source, the source might be
2042 * dead now. Scan the rest of the block for
2043 * invocations, and if there are none, the source dies
2046 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2048 for (int src
= 0; src
< 2; ++src
) {
2049 int s
= sources
[src
];
2051 if (s
< 0) continue;
2053 if (s
>= SSA_FIXED_MINIMUM
) continue;
2055 if (!is_live_after(ctx
, block
, ins
, s
)) {
2064 /* If a node still hasn't been killed, kill it now */
2066 for (int i
= 0; i
< nodes
; ++i
) {
2067 /* live_start == -1 most likely indicates a pinned output */
2069 if (live_end
[i
] == -1)
2073 /* Setup interference between nodes that are live at the same time */
2075 for (int i
= 0; i
< nodes
; ++i
) {
2076 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2077 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2078 ra_add_node_interference(g
, i
, j
);
2082 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2084 if (!ra_allocate(g
)) {
2085 DBG("Error allocating registers\n");
2093 mir_foreach_block(ctx
, block
) {
2094 mir_foreach_instr_in_block(block
, ins
) {
2095 if (ins
->compact_branch
) continue;
2097 ssa_args args
= ins
->ssa_args
;
2099 switch (ins
->type
) {
2101 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2103 ins
->registers
.src2_imm
= args
.inline_constant
;
2105 if (args
.inline_constant
) {
2106 /* Encode inline 16-bit constant as a vector by default */
2108 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2110 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2112 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2113 ins
->alu
.src2
= imm
<< 2;
2115 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2118 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2122 case TAG_LOAD_STORE_4
: {
2123 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2124 /* TODO: use ssa_args for store_vary */
2125 ins
->load_store
.reg
= 0;
2127 bool has_dest
= args
.dest
>= 0;
2128 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2130 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2143 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2144 * use scalar ALU instructions, for functional or performance reasons. To do
2145 * this, we just demote vector ALU payloads to scalar. */
2148 component_from_mask(unsigned mask
)
2150 for (int c
= 0; c
< 4; ++c
) {
2151 if (mask
& (3 << (2 * c
)))
2160 is_single_component_mask(unsigned mask
)
2164 for (int c
= 0; c
< 4; ++c
)
2165 if (mask
& (3 << (2 * c
)))
2168 return components
== 1;
2171 /* Create a mask of accessed components from a swizzle to figure out vector
2175 swizzle_to_access_mask(unsigned swizzle
)
2177 unsigned component_mask
= 0;
2179 for (int i
= 0; i
< 4; ++i
) {
2180 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2181 component_mask
|= (1 << c
);
2184 return component_mask
;
2188 vector_to_scalar_source(unsigned u
)
2190 midgard_vector_alu_src v
;
2191 memcpy(&v
, &u
, sizeof(v
));
2193 midgard_scalar_alu_src s
= {
2197 .component
= (v
.swizzle
& 3) << 1
2201 memcpy(&o
, &s
, sizeof(s
));
2203 return o
& ((1 << 6) - 1);
2206 static midgard_scalar_alu
2207 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2209 /* The output component is from the mask */
2210 midgard_scalar_alu s
= {
2212 .src1
= vector_to_scalar_source(v
.src1
),
2213 .src2
= vector_to_scalar_source(v
.src2
),
2216 .output_full
= 1, /* TODO: Half */
2217 .output_component
= component_from_mask(v
.mask
) << 1,
2220 /* Inline constant is passed along rather than trying to extract it
2223 if (ins
->ssa_args
.inline_constant
) {
2225 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2226 imm
|= (lower_11
>> 9) & 3;
2227 imm
|= (lower_11
>> 6) & 4;
2228 imm
|= (lower_11
>> 2) & 0x38;
2229 imm
|= (lower_11
& 63) << 6;
2237 /* Midgard prefetches instruction types, so during emission we need to
2238 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2239 * if this is the second to last and the last is an ALU, then it's also 1... */
2241 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2242 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2244 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2245 bytes_emitted += sizeof(type)
2248 emit_binary_vector_instruction(midgard_instruction
*ains
,
2249 uint16_t *register_words
, int *register_words_count
,
2250 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2251 size_t *bytes_emitted
)
2253 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2254 *bytes_emitted
+= sizeof(midgard_reg_info
);
2256 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2257 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2258 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2261 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2262 * mind that we are a vector architecture and we can write to different
2263 * components simultaneously */
2266 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2268 /* Each instruction reads some registers and writes to a register. See
2269 * where the first writes */
2271 /* Figure out where exactly we wrote to */
2272 int source
= first
->ssa_args
.dest
;
2273 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2275 /* As long as the second doesn't read from the first, we're okay */
2276 if (second
->ssa_args
.src0
== source
) {
2277 if (first
->type
== TAG_ALU_4
) {
2278 /* Figure out which components we just read from */
2280 int q
= second
->alu
.src1
;
2281 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2283 /* Check if there are components in common, and fail if so */
2284 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2291 if (second
->ssa_args
.src1
== source
)
2294 /* Otherwise, it's safe in that regard. Another data hazard is both
2295 * writing to the same place, of course */
2297 if (second
->ssa_args
.dest
== source
) {
2298 /* ...but only if the components overlap */
2299 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2301 if (dest_mask
& source_mask
)
2311 midgard_instruction
**segment
, unsigned segment_size
,
2312 midgard_instruction
*ains
)
2314 for (int s
= 0; s
< segment_size
; ++s
)
2315 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2323 /* Schedules, but does not emit, a single basic block. After scheduling, the
2324 * final tag and size of the block are known, which are necessary for branching
2327 static midgard_bundle
2328 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2330 int instructions_emitted
= 0, instructions_consumed
= -1;
2331 midgard_bundle bundle
= { 0 };
2333 uint8_t tag
= ins
->type
;
2335 /* Default to the instruction's tag */
2338 switch (ins
->type
) {
2340 uint32_t control
= 0;
2341 size_t bytes_emitted
= sizeof(control
);
2343 /* TODO: Constant combining */
2344 int index
= 0, last_unit
= 0;
2346 /* Previous instructions, for the purpose of parallelism */
2347 midgard_instruction
*segment
[4] = {0};
2348 int segment_size
= 0;
2350 instructions_emitted
= -1;
2351 midgard_instruction
*pins
= ins
;
2354 midgard_instruction
*ains
= pins
;
2356 /* Advance instruction pointer */
2358 ains
= mir_next_op(pins
);
2362 /* Out-of-work condition */
2363 if ((struct list_head
*) ains
== &block
->instructions
)
2366 /* Ensure that the chain can continue */
2367 if (ains
->type
!= TAG_ALU_4
) break;
2369 /* According to the presentation "The ARM
2370 * Mali-T880 Mobile GPU" from HotChips 27,
2371 * there are two pipeline stages. Branching
2372 * position determined experimentally. Lines
2373 * are executed in parallel:
2376 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2378 * Verify that there are no ordering dependencies here.
2380 * TODO: Allow for parallelism!!!
2383 /* Pick a unit for it if it doesn't force a particular unit */
2385 int unit
= ains
->unit
;
2388 int op
= ains
->alu
.op
;
2389 int units
= alu_opcode_props
[op
];
2391 /* TODO: Promotion of scalars to vectors */
2392 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2395 assert(units
& UNITS_SCALAR
);
2398 if (last_unit
>= UNIT_VADD
) {
2399 if (units
& UNIT_VLUT
)
2404 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2406 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2408 else if (units
& UNIT_VLUT
)
2414 if (last_unit
>= UNIT_VADD
) {
2415 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2417 else if (units
& UNIT_VLUT
)
2422 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2424 else if (units
& UNIT_SMUL
)
2425 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2426 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2433 assert(unit
& units
);
2436 /* Late unit check, this time for encoding (not parallelism) */
2437 if (unit
<= last_unit
) break;
2439 /* Clear the segment */
2440 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2443 if (midgard_has_hazard(segment
, segment_size
, ains
))
2446 /* We're good to go -- emit the instruction */
2449 segment
[segment_size
++] = ains
;
2451 /* Only one set of embedded constants per
2452 * bundle possible; if we have more, we must
2453 * break the chain early, unfortunately */
2455 if (ains
->has_constants
) {
2456 if (bundle
.has_embedded_constants
) {
2457 /* ...but if there are already
2458 * constants but these are the
2459 * *same* constants, we let it
2462 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2465 bundle
.has_embedded_constants
= true;
2466 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2468 /* If this is a blend shader special constant, track it for patching */
2469 if (ains
->has_blend_constant
)
2470 bundle
.has_blend_constant
= true;
2474 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2475 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2476 &bundle
.register_words_count
, bundle
.body_words
,
2477 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2478 } else if (ains
->compact_branch
) {
2479 /* All of r0 has to be written out
2480 * along with the branch writeout.
2483 if (ains
->writeout
) {
2485 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2486 ins
.unit
= UNIT_VMUL
;
2488 control
|= ins
.unit
;
2490 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2491 &bundle
.register_words_count
, bundle
.body_words
,
2492 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2494 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2495 bool written_late
= false;
2496 bool components
[4] = { 0 };
2497 uint16_t register_dep_mask
= 0;
2498 uint16_t written_mask
= 0;
2500 midgard_instruction
*qins
= ins
;
2501 for (int t
= 0; t
< index
; ++t
) {
2502 if (qins
->registers
.out_reg
!= 0) {
2503 /* Mark down writes */
2505 written_mask
|= (1 << qins
->registers
.out_reg
);
2507 /* Mark down the register dependencies for errata check */
2509 if (qins
->registers
.src1_reg
< 16)
2510 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2512 if (qins
->registers
.src2_reg
< 16)
2513 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2515 int mask
= qins
->alu
.mask
;
2517 for (int c
= 0; c
< 4; ++c
)
2518 if (mask
& (0x3 << (2 * c
)))
2519 components
[c
] = true;
2521 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2523 if (qins
->unit
== UNIT_VLUT
)
2524 written_late
= true;
2527 /* Advance instruction pointer */
2528 qins
= mir_next_op(qins
);
2532 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2533 if (register_dep_mask
& written_mask
) {
2534 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2541 /* If even a single component is not written, break it up (conservative check). */
2542 bool breakup
= false;
2544 for (int c
= 0; c
< 4; ++c
)
2551 /* Otherwise, we're free to proceed */
2555 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2556 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2557 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2558 bytes_emitted
+= sizeof(midgard_branch_extended
);
2560 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2561 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2562 bytes_emitted
+= sizeof(ains
->br_compact
);
2565 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2566 bytes_emitted
+= sizeof(midgard_reg_info
);
2568 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2569 bundle
.body_words_count
++;
2570 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2573 /* Defer marking until after writing to allow for break */
2574 control
|= ains
->unit
;
2575 last_unit
= ains
->unit
;
2576 ++instructions_emitted
;
2580 /* Bubble up the number of instructions for skipping */
2581 instructions_consumed
= index
- 1;
2585 /* Pad ALU op to nearest word */
2587 if (bytes_emitted
& 15) {
2588 padding
= 16 - (bytes_emitted
& 15);
2589 bytes_emitted
+= padding
;
2592 /* Constants must always be quadwords */
2593 if (bundle
.has_embedded_constants
)
2594 bytes_emitted
+= 16;
2596 /* Size ALU instruction for tag */
2597 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2598 bundle
.padding
= padding
;
2599 bundle
.control
= bundle
.tag
| control
;
2604 case TAG_LOAD_STORE_4
: {
2605 /* Load store instructions have two words at once. If
2606 * we only have one queued up, we need to NOP pad.
2607 * Otherwise, we store both in succession to save space
2608 * and cycles -- letting them go in parallel -- skip
2609 * the next. The usefulness of this optimisation is
2610 * greatly dependent on the quality of the instruction
2614 midgard_instruction
*next_op
= mir_next_op(ins
);
2616 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2617 /* As the two operate concurrently, make sure
2618 * they are not dependent */
2620 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2621 /* Skip ahead, since it's redundant with the pair */
2622 instructions_consumed
= 1 + (instructions_emitted
++);
2630 /* Texture ops default to single-op-per-bundle scheduling */
2634 /* Copy the instructions into the bundle */
2635 bundle
.instruction_count
= instructions_emitted
+ 1;
2639 midgard_instruction
*uins
= ins
;
2640 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2641 bundle
.instructions
[used_idx
++] = *uins
;
2642 uins
= mir_next_op(uins
);
2645 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2651 quadword_size(int tag
)
2666 case TAG_LOAD_STORE_4
:
2678 /* Schedule a single block by iterating its instruction to create bundles.
2679 * While we go, tally about the bundle sizes to compute the block size. */
2682 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2684 util_dynarray_init(&block
->bundles
, NULL
);
2686 block
->quadword_count
= 0;
2688 mir_foreach_instr_in_block(block
, ins
) {
2690 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2691 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2693 if (bundle
.has_blend_constant
) {
2694 /* TODO: Multiblock? */
2695 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2696 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2700 ins
= mir_next_op(ins
);
2702 block
->quadword_count
+= quadword_size(bundle
.tag
);
2705 block
->is_scheduled
= true;
2709 schedule_program(compiler_context
*ctx
)
2711 allocate_registers(ctx
);
2713 mir_foreach_block(ctx
, block
) {
2714 schedule_block(ctx
, block
);
2718 /* After everything is scheduled, emit whole bundles at a time */
2721 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2723 int lookahead
= next_tag
<< 4;
2725 switch (bundle
->tag
) {
2730 /* Actually emit each component */
2731 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2733 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2734 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2736 /* Emit body words based on the instructions bundled */
2737 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2738 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2740 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2741 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2742 } else if (ins
->compact_branch
) {
2743 /* Dummy move, XXX DRY */
2744 if ((i
== 0) && ins
->writeout
) {
2745 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2746 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2749 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2750 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2752 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2756 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2757 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2761 /* Emit padding (all zero) */
2762 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2764 /* Tack on constants */
2766 if (bundle
->has_embedded_constants
) {
2767 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2768 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2769 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2770 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2776 case TAG_LOAD_STORE_4
: {
2777 /* One or two composing instructions */
2779 uint64_t current64
, next64
= LDST_NOP
;
2781 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2783 if (bundle
->instruction_count
== 2)
2784 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2786 midgard_load_store instruction
= {
2787 .type
= bundle
->tag
,
2788 .next_type
= next_tag
,
2793 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2798 case TAG_TEXTURE_4
: {
2799 /* Texture instructions are easy, since there is no
2800 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2802 midgard_instruction
*ins
= &bundle
->instructions
[0];
2804 ins
->texture
.type
= TAG_TEXTURE_4
;
2805 ins
->texture
.next_type
= next_tag
;
2807 ctx
->texture_op_count
--;
2809 if (!ctx
->texture_op_count
) {
2810 ins
->texture
.cont
= 0;
2811 ins
->texture
.last
= 1;
2814 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2819 DBG("Unknown midgard instruction type\n");
2826 /* ALU instructions can inline or embed constants, which decreases register
2827 * pressure and saves space. */
2829 #define CONDITIONAL_ATTACH(src) { \
2830 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2833 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2834 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2839 inline_alu_constants(compiler_context
*ctx
)
2841 mir_foreach_instr(ctx
, alu
) {
2842 /* Other instructions cannot inline constants */
2843 if (alu
->type
!= TAG_ALU_4
) continue;
2845 /* If there is already a constant here, we can do nothing */
2846 if (alu
->has_constants
) continue;
2848 /* It makes no sense to inline constants on a branch */
2849 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2851 CONDITIONAL_ATTACH(src0
);
2853 if (!alu
->has_constants
) {
2854 CONDITIONAL_ATTACH(src1
)
2855 } else if (!alu
->inline_constant
) {
2856 /* Corner case: _two_ vec4 constants, for instance with a
2857 * csel. For this case, we can only use a constant
2858 * register for one, we'll have to emit a move for the
2859 * other. Note, if both arguments are constants, then
2860 * necessarily neither argument depends on the value of
2861 * any particular register. As the destination register
2862 * will be wiped, that means we can spill the constant
2863 * to the destination register.
2866 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2867 unsigned scratch
= alu
->ssa_args
.dest
;
2870 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2871 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2873 /* Force a break XXX Defer r31 writes */
2874 ins
.unit
= UNIT_VLUT
;
2876 /* Set the source */
2877 alu
->ssa_args
.src1
= scratch
;
2879 /* Inject us -before- the last instruction which set r31 */
2880 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2886 /* Midgard supports two types of constants, embedded constants (128-bit) and
2887 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2888 * constants can be demoted to inline constants, for space savings and
2889 * sometimes a performance boost */
2892 embedded_to_inline_constant(compiler_context
*ctx
)
2894 mir_foreach_instr(ctx
, ins
) {
2895 if (!ins
->has_constants
) continue;
2897 if (ins
->ssa_args
.inline_constant
) continue;
2899 /* Blend constants must not be inlined by definition */
2900 if (ins
->has_blend_constant
) continue;
2902 /* src1 cannot be an inline constant due to encoding
2903 * restrictions. So, if possible we try to flip the arguments
2906 int op
= ins
->alu
.op
;
2908 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2909 /* Flip based on op. Fallthrough intentional */
2912 /* These ops require an operational change to flip their arguments TODO */
2913 case midgard_alu_op_flt
:
2914 case midgard_alu_op_fle
:
2915 case midgard_alu_op_ilt
:
2916 case midgard_alu_op_ile
:
2917 case midgard_alu_op_fcsel
:
2918 case midgard_alu_op_icsel
:
2919 case midgard_alu_op_isub
:
2920 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2923 /* These ops are commutative and Just Flip */
2924 case midgard_alu_op_fne
:
2925 case midgard_alu_op_fadd
:
2926 case midgard_alu_op_fmul
:
2927 case midgard_alu_op_fmin
:
2928 case midgard_alu_op_fmax
:
2929 case midgard_alu_op_iadd
:
2930 case midgard_alu_op_imul
:
2931 case midgard_alu_op_feq
:
2932 case midgard_alu_op_ieq
:
2933 case midgard_alu_op_ine
:
2934 case midgard_alu_op_iand
:
2935 case midgard_alu_op_ior
:
2936 case midgard_alu_op_ixor
:
2937 /* Flip the SSA numbers */
2938 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2939 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2941 /* And flip the modifiers */
2945 src_temp
= ins
->alu
.src2
;
2946 ins
->alu
.src2
= ins
->alu
.src1
;
2947 ins
->alu
.src1
= src_temp
;
2954 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2955 /* Extract the source information */
2957 midgard_vector_alu_src
*src
;
2958 int q
= ins
->alu
.src2
;
2959 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2962 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2963 int component
= src
->swizzle
& 3;
2965 /* Scale constant appropriately, if we can legally */
2966 uint16_t scaled_constant
= 0;
2968 /* XXX: Check legality */
2969 if (midgard_is_integer_op(op
)) {
2970 /* TODO: Inline integer */
2973 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2974 scaled_constant
= (uint16_t) iconstants
[component
];
2976 /* Constant overflow after resize */
2977 if (scaled_constant
!= iconstants
[component
])
2980 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2983 /* We don't know how to handle these with a constant */
2985 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2986 DBG("Bailing inline constant...\n");
2990 /* Make sure that the constant is not itself a
2991 * vector by checking if all accessed values
2992 * (by the swizzle) are the same. */
2994 uint32_t *cons
= (uint32_t *) ins
->constants
;
2995 uint32_t value
= cons
[component
];
2997 bool is_vector
= false;
2998 unsigned mask
= effective_writemask(&ins
->alu
);
3000 for (int c
= 1; c
< 4; ++c
) {
3001 /* We only care if this component is actually used */
3002 if (!(mask
& (1 << c
)))
3005 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3007 if (test
!= value
) {
3016 /* Get rid of the embedded constant */
3017 ins
->has_constants
= false;
3018 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3019 ins
->ssa_args
.inline_constant
= true;
3020 ins
->inline_constant
= scaled_constant
;
3025 /* Map normal SSA sources to other SSA sources / fixed registers (like
3029 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3031 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3034 /* Remove entry in leftovers to avoid a redunant fmov */
3036 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3039 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3041 /* Assign the alias map */
3047 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3048 * texture pipeline */
3051 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3053 mir_foreach_instr_in_block_safe(block
, ins
) {
3054 if (ins
->type
!= TAG_ALU_4
) continue;
3055 if (ins
->compact_branch
) continue;
3057 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3058 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3059 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3061 mir_remove_instruction(ins
);
3065 /* The following passes reorder MIR instructions to enable better scheduling */
3068 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3070 mir_foreach_instr_in_block_safe(block
, ins
) {
3071 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3073 /* We've found a load/store op. Check if next is also load/store. */
3074 midgard_instruction
*next_op
= mir_next_op(ins
);
3075 if (&next_op
->link
!= &block
->instructions
) {
3076 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3077 /* If so, we're done since we're a pair */
3078 ins
= mir_next_op(ins
);
3082 /* Maximum search distance to pair, to avoid register pressure disasters */
3083 int search_distance
= 8;
3085 /* Otherwise, we have an orphaned load/store -- search for another load */
3086 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3087 /* Terminate search if necessary */
3088 if (!(search_distance
--)) break;
3090 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3092 /* Stores cannot be reordered, since they have
3093 * dependencies. For the same reason, indirect
3094 * loads cannot be reordered as their index is
3095 * loaded in r27.w */
3097 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3099 /* It appears the 0x800 bit is set whenever a
3100 * load is direct, unset when it is indirect.
3101 * Skip indirect loads. */
3103 if (!(c
->load_store
.unknown
& 0x800)) continue;
3105 /* We found one! Move it up to pair and remove it from the old location */
3107 mir_insert_instruction_before(ins
, *c
);
3108 mir_remove_instruction(c
);
3116 /* Emit varying stores late */
3119 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3120 /* Iterate in reverse to get the final write, rather than the first */
3122 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3123 /* Check if what we just wrote needs a store */
3124 int idx
= ins
->ssa_args
.dest
;
3125 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3127 if (!varying
) continue;
3131 /* We need to store to the appropriate varying, so emit the
3134 /* TODO: Integrate with special purpose RA (and scheduler?) */
3135 bool high_varying_register
= false;
3137 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3139 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3140 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3142 mir_insert_instruction_before(mir_next_op(ins
), st
);
3143 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3145 /* We no longer need to store this varying */
3146 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3150 /* If there are leftovers after the below pass, emit actual fmov
3151 * instructions for the slow-but-correct path */
3154 emit_leftover_move(compiler_context
*ctx
)
3156 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3157 int base
= ((uintptr_t) leftover
->key
) - 1;
3160 map_ssa_to_alias(ctx
, &mapped
);
3161 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3166 actualise_ssa_to_alias(compiler_context
*ctx
)
3168 mir_foreach_instr(ctx
, ins
) {
3169 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3170 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3173 emit_leftover_move(ctx
);
3177 emit_fragment_epilogue(compiler_context
*ctx
)
3179 /* Special case: writing out constants requires us to include the move
3180 * explicitly now, so shove it into r0 */
3182 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3184 if (constant_value
) {
3185 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3186 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3187 emit_mir_instruction(ctx
, ins
);
3190 /* Perform the actual fragment writeout. We have two writeout/branch
3191 * instructions, forming a loop until writeout is successful as per the
3192 * docs. TODO: gl_FragDepth */
3194 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3195 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3198 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3199 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3200 * with the int8 analogue to the fragment epilogue */
3203 emit_blend_epilogue(compiler_context
*ctx
)
3205 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3207 midgard_instruction scale
= {
3210 .inline_constant
= _mesa_float_to_half(255.0),
3212 .src0
= SSA_FIXED_REGISTER(0),
3213 .src1
= SSA_UNUSED_0
,
3214 .dest
= SSA_FIXED_REGISTER(24),
3215 .inline_constant
= true
3218 .op
= midgard_alu_op_fmul
,
3219 .reg_mode
= midgard_reg_mode_full
,
3220 .dest_override
= midgard_dest_override_lower
,
3222 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3223 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3227 emit_mir_instruction(ctx
, scale
);
3229 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3231 midgard_vector_alu_src alu_src
= blank_alu_src
;
3232 alu_src
.half
= true;
3234 midgard_instruction f2u8
= {
3237 .src0
= SSA_FIXED_REGISTER(24),
3238 .src1
= SSA_UNUSED_0
,
3239 .dest
= SSA_FIXED_REGISTER(0),
3240 .inline_constant
= true
3243 .op
= midgard_alu_op_f2u8
,
3244 .reg_mode
= midgard_reg_mode_half
,
3245 .dest_override
= midgard_dest_override_lower
,
3246 .outmod
= midgard_outmod_pos
,
3248 .src1
= vector_alu_srco_unsigned(alu_src
),
3249 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3253 emit_mir_instruction(ctx
, f2u8
);
3255 /* vmul.imov.quarter r0, r0, r0 */
3257 midgard_instruction imov_8
= {
3260 .src0
= SSA_UNUSED_1
,
3261 .src1
= SSA_FIXED_REGISTER(0),
3262 .dest
= SSA_FIXED_REGISTER(0),
3265 .op
= midgard_alu_op_imov
,
3266 .reg_mode
= midgard_reg_mode_quarter
,
3267 .dest_override
= midgard_dest_override_none
,
3269 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3270 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3274 /* Emit branch epilogue with the 8-bit move as the source */
3276 emit_mir_instruction(ctx
, imov_8
);
3277 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3279 emit_mir_instruction(ctx
, imov_8
);
3280 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3283 static midgard_block
*
3284 emit_block(compiler_context
*ctx
, nir_block
*block
)
3286 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3287 list_addtail(&this_block
->link
, &ctx
->blocks
);
3289 this_block
->is_scheduled
= false;
3292 ctx
->texture_index
[0] = -1;
3293 ctx
->texture_index
[1] = -1;
3295 /* Add us as a successor to the block we are following */
3296 if (ctx
->current_block
)
3297 midgard_block_add_successor(ctx
->current_block
, this_block
);
3299 /* Set up current block */
3300 list_inithead(&this_block
->instructions
);
3301 ctx
->current_block
= this_block
;
3303 nir_foreach_instr(instr
, block
) {
3304 emit_instr(ctx
, instr
);
3305 ++ctx
->instruction_count
;
3308 inline_alu_constants(ctx
);
3309 embedded_to_inline_constant(ctx
);
3311 /* Perform heavylifting for aliasing */
3312 actualise_ssa_to_alias(ctx
);
3314 midgard_emit_store(ctx
, this_block
);
3315 midgard_pair_load_store(ctx
, this_block
);
3317 /* Append fragment shader epilogue (value writeout) */
3318 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3319 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3321 emit_blend_epilogue(ctx
);
3323 emit_fragment_epilogue(ctx
);
3327 if (block
== nir_start_block(ctx
->func
->impl
))
3328 ctx
->initial_block
= this_block
;
3330 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3331 ctx
->final_block
= this_block
;
3333 /* Allow the next control flow to access us retroactively, for
3335 ctx
->current_block
= this_block
;
3337 /* Document the fallthrough chain */
3338 ctx
->previous_source_block
= this_block
;
3343 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3346 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3348 /* Conditional branches expect the condition in r31.w; emit a move for
3349 * that in the _previous_ block (which is the current block). */
3350 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3352 /* Speculatively emit the branch, but we can't fill it in until later */
3353 EMIT(branch
, true, true);
3354 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3356 /* Emit the two subblocks */
3357 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3359 /* Emit a jump from the end of the then block to the end of the else */
3360 EMIT(branch
, false, false);
3361 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3363 /* Emit second block, and check if it's empty */
3365 int else_idx
= ctx
->block_count
;
3366 int count_in
= ctx
->instruction_count
;
3367 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3368 int after_else_idx
= ctx
->block_count
;
3370 /* Now that we have the subblocks emitted, fix up the branches */
3375 if (ctx
->instruction_count
== count_in
) {
3376 /* The else block is empty, so don't emit an exit jump */
3377 mir_remove_instruction(then_exit
);
3378 then_branch
->branch
.target_block
= after_else_idx
;
3380 then_branch
->branch
.target_block
= else_idx
;
3381 then_exit
->branch
.target_block
= after_else_idx
;
3386 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3388 /* Remember where we are */
3389 midgard_block
*start_block
= ctx
->current_block
;
3391 /* Allocate a loop number, growing the current inner loop depth */
3392 int loop_idx
= ++ctx
->current_loop_depth
;
3394 /* Get index from before the body so we can loop back later */
3395 int start_idx
= ctx
->block_count
;
3397 /* Emit the body itself */
3398 emit_cf_list(ctx
, &nloop
->body
);
3400 /* Branch back to loop back */
3401 struct midgard_instruction br_back
= v_branch(false, false);
3402 br_back
.branch
.target_block
= start_idx
;
3403 emit_mir_instruction(ctx
, br_back
);
3405 /* Mark down that branch in the graph */
3406 midgard_block_add_successor(ctx
->current_block
, start_block
);
3408 /* Find the index of the block about to follow us (note: we don't add
3409 * one; blocks are 0-indexed so we get a fencepost problem) */
3410 int break_block_idx
= ctx
->block_count
;
3412 /* Fix up the break statements we emitted to point to the right place,
3413 * now that we can allocate a block number for them */
3415 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3416 mir_foreach_instr_in_block(block
, ins
) {
3417 if (ins
->type
!= TAG_ALU_4
) continue;
3418 if (!ins
->compact_branch
) continue;
3419 if (ins
->prepacked_branch
) continue;
3421 /* We found a branch -- check the type to see if we need to do anything */
3422 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3424 /* It's a break! Check if it's our break */
3425 if (ins
->branch
.target_break
!= loop_idx
) continue;
3427 /* Okay, cool, we're breaking out of this loop.
3428 * Rewrite from a break to a goto */
3430 ins
->branch
.target_type
= TARGET_GOTO
;
3431 ins
->branch
.target_block
= break_block_idx
;
3435 /* Now that we've finished emitting the loop, free up the depth again
3436 * so we play nice with recursion amid nested loops */
3437 --ctx
->current_loop_depth
;
3440 static midgard_block
*
3441 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3443 midgard_block
*start_block
= NULL
;
3445 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3446 switch (node
->type
) {
3447 case nir_cf_node_block
: {
3448 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3451 start_block
= block
;
3456 case nir_cf_node_if
:
3457 emit_if(ctx
, nir_cf_node_as_if(node
));
3460 case nir_cf_node_loop
:
3461 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3464 case nir_cf_node_function
:
3473 /* Due to lookahead, we need to report the first tag executed in the command
3474 * stream and in branch targets. An initial block might be empty, so iterate
3475 * until we find one that 'works' */
3478 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3480 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3482 unsigned first_tag
= 0;
3485 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3487 if (initial_bundle
) {
3488 first_tag
= initial_bundle
->tag
;
3492 /* Initial block is empty, try the next block */
3493 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3494 } while(initial_block
!= NULL
);
3501 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3503 struct util_dynarray
*compiled
= &program
->compiled
;
3505 midgard_debug
= debug_get_option_midgard_debug();
3507 compiler_context ictx
= {
3509 .stage
= nir
->info
.stage
,
3511 .is_blend
= is_blend
,
3512 .blend_constant_offset
= -1,
3514 .alpha_ref
= program
->alpha_ref
3517 compiler_context
*ctx
= &ictx
;
3519 /* TODO: Decide this at runtime */
3520 ctx
->uniform_cutoff
= 8;
3522 /* Assign var locations early, so the epilogue can use them if necessary */
3524 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3525 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3526 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3528 /* Initialize at a global (not block) level hash tables */
3530 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3531 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3532 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3533 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3534 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3535 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3536 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3538 /* Record the varying mapping for the command stream's bookkeeping */
3540 struct exec_list
*varyings
=
3541 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3543 nir_foreach_variable(var
, varyings
) {
3544 unsigned loc
= var
->data
.driver_location
;
3545 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3547 for (int c
= 0; c
< sz
; ++c
) {
3548 program
->varyings
[loc
+ c
] = var
->data
.location
;
3552 /* Lower gl_Position pre-optimisation */
3554 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3555 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3557 NIR_PASS_V(nir
, nir_lower_var_copies
);
3558 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3559 NIR_PASS_V(nir
, nir_split_var_copies
);
3560 NIR_PASS_V(nir
, nir_lower_var_copies
);
3561 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3562 NIR_PASS_V(nir
, nir_lower_var_copies
);
3563 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3565 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3567 /* Optimisation passes */
3571 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3572 nir_print_shader(nir
, stdout
);
3575 /* Assign sysvals and counts, now that we're sure
3576 * (post-optimisation) */
3578 midgard_nir_assign_sysvals(ctx
, nir
);
3580 program
->uniform_count
= nir
->num_uniforms
;
3581 program
->sysval_count
= ctx
->sysval_count
;
3582 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3584 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3585 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3587 nir_foreach_function(func
, nir
) {
3591 list_inithead(&ctx
->blocks
);
3592 ctx
->block_count
= 0;
3595 emit_cf_list(ctx
, &func
->impl
->body
);
3596 emit_block(ctx
, func
->impl
->end_block
);
3598 break; /* TODO: Multi-function shaders */
3601 util_dynarray_init(compiled
, NULL
);
3603 /* Peephole optimizations */
3605 mir_foreach_block(ctx
, block
) {
3606 midgard_opt_dead_code_eliminate(ctx
, block
);
3610 schedule_program(ctx
);
3612 /* Now that all the bundles are scheduled and we can calculate block
3613 * sizes, emit actual branch instructions rather than placeholders */
3615 int br_block_idx
= 0;
3617 mir_foreach_block(ctx
, block
) {
3618 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3619 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3620 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3622 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3624 if (ins
->prepacked_branch
) continue;
3626 /* Parse some basic branch info */
3627 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3628 bool is_conditional
= ins
->branch
.conditional
;
3629 bool is_inverted
= ins
->branch
.invert_conditional
;
3630 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3632 /* Determine the block we're jumping to */
3633 int target_number
= ins
->branch
.target_block
;
3635 /* Report the destination tag. Discards don't need this */
3636 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3638 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3639 int quadword_offset
= 0;
3642 /* Jump to the end of the shader. We
3643 * need to include not only the
3644 * following blocks, but also the
3645 * contents of our current block (since
3646 * discard can come in the middle of
3649 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3651 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3652 quadword_offset
+= quadword_size(bun
->tag
);
3655 mir_foreach_block_from(ctx
, blk
, b
) {
3656 quadword_offset
+= b
->quadword_count
;
3659 } else if (target_number
> br_block_idx
) {
3662 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3663 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3666 quadword_offset
+= blk
->quadword_count
;
3669 /* Jump backwards */
3671 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3672 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3675 quadword_offset
-= blk
->quadword_count
;
3679 /* Unconditional extended branches (far jumps)
3680 * have issues, so we always use a conditional
3681 * branch, setting the condition to always for
3682 * unconditional. For compact unconditional
3683 * branches, cond isn't used so it doesn't
3684 * matter what we pick. */
3686 midgard_condition cond
=
3687 !is_conditional
? midgard_condition_always
:
3688 is_inverted
? midgard_condition_false
:
3689 midgard_condition_true
;
3691 midgard_jmp_writeout_op op
=
3692 is_discard
? midgard_jmp_writeout_op_discard
:
3693 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3694 midgard_jmp_writeout_op_branch_cond
;
3697 midgard_branch_extended branch
=
3698 midgard_create_branch_extended(
3703 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3704 } else if (is_conditional
|| is_discard
) {
3705 midgard_branch_cond branch
= {
3707 .dest_tag
= dest_tag
,
3708 .offset
= quadword_offset
,
3712 assert(branch
.offset
== quadword_offset
);
3714 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3716 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3718 midgard_branch_uncond branch
= {
3720 .dest_tag
= dest_tag
,
3721 .offset
= quadword_offset
,
3725 assert(branch
.offset
== quadword_offset
);
3727 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3735 /* Emit flat binary from the instruction arrays. Iterate each block in
3736 * sequence. Save instruction boundaries such that lookahead tags can
3737 * be assigned easily */
3739 /* Cache _all_ bundles in source order for lookahead across failed branches */
3741 int bundle_count
= 0;
3742 mir_foreach_block(ctx
, block
) {
3743 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3745 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3747 mir_foreach_block(ctx
, block
) {
3748 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3749 source_order_bundles
[bundle_idx
++] = bundle
;
3753 int current_bundle
= 0;
3755 mir_foreach_block(ctx
, block
) {
3756 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3759 if (current_bundle
+ 1 < bundle_count
) {
3760 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3762 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3769 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3773 /* TODO: Free deeper */
3774 //util_dynarray_fini(&block->instructions);
3777 free(source_order_bundles
);
3779 /* Report the very first tag executed */
3780 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3782 /* Deal with off-by-one related to the fencepost problem */
3783 program
->work_register_count
= ctx
->work_registers
+ 1;
3785 program
->can_discard
= ctx
->can_discard
;
3786 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3788 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3790 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3791 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);