2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 struct midgard_block
*next_fallthrough
;
175 /* Helpers to generate midgard_instruction's using macro magic, since every
176 * driver seems to do it that way */
178 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
180 #define M_LOAD_STORE(name, rname, uname) \
181 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
182 midgard_instruction i = { \
183 .type = TAG_LOAD_STORE_4, \
190 .op = midgard_op_##name, \
192 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
200 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
201 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
203 const midgard_vector_alu_src blank_alu_src
= {
204 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
207 const midgard_vector_alu_src blank_alu_src_xxxx
= {
208 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
211 const midgard_scalar_alu_src blank_scalar_alu_src
= {
215 /* Used for encoding the unused source of 1-op instructions */
216 const midgard_vector_alu_src zero_alu_src
= { 0 };
218 /* Coerce structs to integer */
221 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
224 memcpy(&u
, &src
, sizeof(src
));
228 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
229 * the corresponding Midgard source */
231 static midgard_vector_alu_src
232 vector_alu_modifiers(nir_alu_src
*src
)
234 if (!src
) return blank_alu_src
;
236 midgard_vector_alu_src alu_src
= {
238 .negate
= src
->negate
,
241 .half
= 0, /* TODO */
242 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
248 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
250 static midgard_instruction
251 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
253 midgard_instruction ins
= {
256 .src0
= SSA_UNUSED_1
,
261 .op
= midgard_alu_op_fmov
,
262 .reg_mode
= midgard_reg_mode_full
,
263 .dest_override
= midgard_dest_override_none
,
265 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
266 .src2
= vector_alu_srco_unsigned(mod
)
273 /* load/store instructions have both 32-bit and 16-bit variants, depending on
274 * whether we are using vectors composed of highp or mediump. At the moment, we
275 * don't support half-floats -- this requires changes in other parts of the
276 * compiler -- therefore the 16-bit versions are commented out. */
278 //M_LOAD(load_attr_16);
279 M_LOAD(load_attr_32
);
280 //M_LOAD(load_vary_16);
281 M_LOAD(load_vary_32
);
282 //M_LOAD(load_uniform_16);
283 M_LOAD(load_uniform_32
);
284 M_LOAD(load_color_buffer_8
);
285 //M_STORE(store_vary_16);
286 M_STORE(store_vary_32
);
288 static midgard_instruction
289 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
291 midgard_branch_cond branch
= {
299 memcpy(&compact
, &branch
, sizeof(branch
));
301 midgard_instruction ins
= {
303 .unit
= ALU_ENAB_BR_COMPACT
,
304 .prepacked_branch
= true,
305 .compact_branch
= true,
306 .br_compact
= compact
309 if (op
== midgard_jmp_writeout_op_writeout
)
315 static midgard_instruction
316 v_branch(bool conditional
, bool invert
)
318 midgard_instruction ins
= {
320 .unit
= ALU_ENAB_BRANCH
,
321 .compact_branch
= true,
323 .conditional
= conditional
,
324 .invert_conditional
= invert
331 static midgard_branch_extended
332 midgard_create_branch_extended( midgard_condition cond
,
333 midgard_jmp_writeout_op op
,
335 signed quadword_offset
)
337 /* For unclear reasons, the condition code is repeated 8 times */
338 uint16_t duplicated_cond
=
348 midgard_branch_extended branch
= {
350 .dest_tag
= dest_tag
,
351 .offset
= quadword_offset
,
352 .cond
= duplicated_cond
358 typedef struct midgard_bundle
{
359 /* Tag for the overall bundle */
362 /* Instructions contained by the bundle */
363 int instruction_count
;
364 midgard_instruction instructions
[5];
366 /* Bundle-wide ALU configuration */
369 bool has_embedded_constants
;
371 bool has_blend_constant
;
373 uint16_t register_words
[8];
374 int register_words_count
;
376 uint64_t body_words
[8];
378 int body_words_count
;
381 typedef struct compiler_context
{
383 gl_shader_stage stage
;
385 /* Is internally a blend shader? Depends on stage == FRAGMENT */
388 /* Tracking for blend constant patching */
389 int blend_constant_number
;
390 int blend_constant_offset
;
392 /* Current NIR function */
395 /* Unordered list of midgard_blocks */
397 struct list_head blocks
;
399 midgard_block
*initial_block
;
400 midgard_block
*previous_source_block
;
401 midgard_block
*final_block
;
403 /* List of midgard_instructions emitted for the current block */
404 midgard_block
*current_block
;
406 /* The index corresponding to the current loop, e.g. for breaks/contineus */
409 /* Constants which have been loaded, for later inlining */
410 struct hash_table_u64
*ssa_constants
;
412 /* SSA indices to be outputted to corresponding varying offset */
413 struct hash_table_u64
*ssa_varyings
;
415 /* SSA values / registers which have been aliased. Naively, these
416 * demand a fmov output; instead, we alias them in a later pass to
417 * avoid the wasted op.
419 * A note on encoding: to avoid dynamic memory management here, rather
420 * than ampping to a pointer, we map to the source index; the key
421 * itself is just the destination index. */
423 struct hash_table_u64
*ssa_to_alias
;
424 struct set
*leftover_ssa_to_alias
;
426 /* Actual SSA-to-register for RA */
427 struct hash_table_u64
*ssa_to_register
;
429 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
430 struct hash_table_u64
*hash_to_temp
;
434 /* Uniform IDs for mdg */
435 struct hash_table_u64
*uniform_nir_to_mdg
;
438 /* Just the count of the max register used. Higher count => higher
439 * register pressure */
442 /* Used for cont/last hinting. Increase when a tex op is added.
443 * Decrease when a tex op is removed. */
444 int texture_op_count
;
446 /* Mapping of texture register -> SSA index for unaliasing */
447 int texture_index
[2];
449 /* Count of special uniforms (viewport, etc) in vec4 units */
450 int special_uniforms
;
452 /* If any path hits a discard instruction */
455 /* The number of uniforms allowable for the fast path */
458 /* Count of instructions emitted from NIR overall, across all blocks */
459 int instruction_count
;
461 /* Alpha ref value passed in */
464 /* The index corresponding to the fragment output */
465 unsigned fragment_output
;
468 /* Append instruction to end of current block */
470 static midgard_instruction
*
471 mir_upload_ins(struct midgard_instruction ins
)
473 midgard_instruction
*heap
= malloc(sizeof(ins
));
474 memcpy(heap
, &ins
, sizeof(ins
));
479 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
481 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
485 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
487 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
491 mir_remove_instruction(struct midgard_instruction
*ins
)
493 list_del(&ins
->link
);
496 static midgard_instruction
*
497 mir_prev_op(struct midgard_instruction
*ins
)
499 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
502 static midgard_instruction
*
503 mir_next_op(struct midgard_instruction
*ins
)
505 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
508 static midgard_block
*
509 mir_next_block(struct midgard_block
*blk
)
511 return list_first_entry(&(blk
->link
), midgard_block
, link
);
515 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
516 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
518 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
519 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
520 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
521 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
522 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
523 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
526 static midgard_instruction
*
527 mir_last_in_block(struct midgard_block
*block
)
529 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
532 static midgard_block
*
533 mir_get_block(compiler_context
*ctx
, int idx
)
535 struct list_head
*lst
= &ctx
->blocks
;
540 return (struct midgard_block
*) lst
;
543 /* Pretty printer for internal Midgard IR */
546 print_mir_source(int source
)
548 if (source
>= SSA_FIXED_MINIMUM
) {
549 /* Specific register */
550 int reg
= SSA_REG_FROM_FIXED(source
);
552 /* TODO: Moving threshold */
553 if (reg
> 16 && reg
< 24)
554 printf("u%d", 23 - reg
);
558 printf("%d", source
);
563 print_mir_instruction(midgard_instruction
*ins
)
569 midgard_alu_op op
= ins
->alu
.op
;
570 const char *name
= alu_opcode_names
[op
];
573 printf("%d.", ins
->unit
);
575 printf("%s", name
? name
: "??");
579 case TAG_LOAD_STORE_4
: {
580 midgard_load_store_op op
= ins
->load_store
.op
;
581 const char *name
= load_store_opcode_names
[op
];
588 case TAG_TEXTURE_4
: {
597 ssa_args
*args
= &ins
->ssa_args
;
599 printf(" %d, ", args
->dest
);
601 print_mir_source(args
->src0
);
604 if (args
->inline_constant
)
605 printf("#%d", ins
->inline_constant
);
607 print_mir_source(args
->src1
);
609 if (ins
->has_constants
)
610 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
616 print_mir_block(midgard_block
*block
)
620 mir_foreach_instr_in_block(block
, ins
) {
621 print_mir_instruction(ins
);
630 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
632 ins
->has_constants
= true;
633 memcpy(&ins
->constants
, constants
, 16);
635 /* If this is the special blend constant, mark this instruction */
637 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
638 ins
->has_blend_constant
= true;
642 glsl_type_size(const struct glsl_type
*type
)
644 return glsl_count_attribute_slots(type
, false);
647 /* Lower fdot2 to a vector multiplication followed by channel addition */
649 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
651 if (alu
->op
!= nir_op_fdot2
)
654 b
->cursor
= nir_before_instr(&alu
->instr
);
656 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
657 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
659 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
661 nir_ssa_def
*sum
= nir_fadd(b
,
662 nir_channel(b
, product
, 0),
663 nir_channel(b
, product
, 1));
665 /* Replace the fdot2 with this sum */
666 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
670 midgard_nir_lower_fdot2(nir_shader
*shader
)
672 bool progress
= false;
674 nir_foreach_function(function
, shader
) {
675 if (!function
->impl
) continue;
678 nir_builder
*b
= &_b
;
679 nir_builder_init(b
, function
->impl
);
681 nir_foreach_block(block
, function
->impl
) {
682 nir_foreach_instr_safe(instr
, block
) {
683 if (instr
->type
!= nir_instr_type_alu
) continue;
685 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
686 midgard_nir_lower_fdot2_body(b
, alu
);
692 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
700 optimise_nir(nir_shader
*nir
)
704 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
705 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
707 nir_lower_tex_options lower_tex_options
= {
711 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
716 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
717 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
718 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
719 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
721 NIR_PASS(progress
, nir
, nir_copy_prop
);
722 NIR_PASS(progress
, nir
, nir_opt_dce
);
723 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
724 NIR_PASS(progress
, nir
, nir_opt_cse
);
725 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
726 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
727 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
728 NIR_PASS(progress
, nir
, nir_opt_undef
);
729 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
732 nir_var_function_temp
);
734 /* TODO: Enable vectorize when merged upstream */
735 // NIR_PASS(progress, nir, nir_opt_vectorize);
738 /* Must be run at the end to prevent creation of fsin/fcos ops */
739 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
744 NIR_PASS(progress
, nir
, nir_opt_dce
);
745 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
746 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
747 NIR_PASS(progress
, nir
, nir_copy_prop
);
750 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
753 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_all_source_mods
);
754 NIR_PASS(progress
, nir
, nir_copy_prop
);
755 NIR_PASS(progress
, nir
, nir_opt_dce
);
757 /* Take us out of SSA */
758 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
759 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
761 /* We are a vector architecture; write combine where possible */
762 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
763 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
765 NIR_PASS(progress
, nir
, nir_opt_dce
);
768 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
769 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
770 * r0. See the comments in compiler_context */
773 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
775 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
776 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
779 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
782 unalias_ssa(compiler_context
*ctx
, int dest
)
784 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
785 /* TODO: Remove from leftover or no? */
789 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
791 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
795 midgard_is_pinned(compiler_context
*ctx
, int index
)
797 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
800 /* Do not actually emit a load; instead, cache the constant for inlining */
803 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
805 nir_ssa_def def
= instr
->def
;
807 float *v
= ralloc_array(NULL
, float, 4);
808 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
809 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
812 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
816 expand_writemask(unsigned mask
)
820 for (int i
= 0; i
< 4; ++i
)
828 squeeze_writemask(unsigned mask
)
832 for (int i
= 0; i
< 4; ++i
)
833 if (mask
& (3 << (2 * i
)))
840 /* Determines effective writemask, taking quirks and expansion into account */
842 effective_writemask(midgard_vector_alu
*alu
)
844 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
847 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
849 /* If there is a fixed channel count, construct the appropriate mask */
852 return (1 << channel_count
) - 1;
854 /* Otherwise, just squeeze the existing mask */
855 return squeeze_writemask(alu
->mask
);
859 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
861 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
864 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
869 /* If no temp is find, allocate one */
870 temp
= ctx
->temp_count
++;
871 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
873 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
879 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
882 return src
->ssa
->index
;
884 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
888 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
891 return dst
->ssa
.index
;
893 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
897 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
899 return nir_src_index(ctx
, &src
->src
);
902 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
903 * a conditional test) into that register */
906 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
908 /* XXX: Force component correct */
909 int condition
= nir_src_index(ctx
, src
);
911 /* There is no boolean move instruction. Instead, we simulate a move by
912 * ANDing the condition with itself to get it into r31.w */
914 midgard_instruction ins
= {
916 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
920 .dest
= SSA_FIXED_REGISTER(31),
923 .op
= midgard_alu_op_iand
,
924 .reg_mode
= midgard_reg_mode_full
,
925 .dest_override
= midgard_dest_override_none
,
926 .mask
= (0x3 << 6), /* w */
927 .src1
= vector_alu_srco_unsigned(blank_alu_src_xxxx
),
928 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
932 emit_mir_instruction(ctx
, ins
);
935 #define ALU_CASE(nir, _op) \
937 op = midgard_alu_op_##_op; \
941 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
943 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
945 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
946 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
947 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
949 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
950 * supported. A few do not and are commented for now. Also, there are a
951 * number of NIR ops which Midgard does not support and need to be
952 * lowered, also TODO. This switch block emits the opcode and calling
953 * convention of the Midgard instruction; actual packing is done in
959 ALU_CASE(fadd
, fadd
);
960 ALU_CASE(fmul
, fmul
);
961 ALU_CASE(fmin
, fmin
);
962 ALU_CASE(fmax
, fmax
);
963 ALU_CASE(imin
, imin
);
964 ALU_CASE(imax
, imax
);
965 ALU_CASE(fmov
, fmov
);
966 ALU_CASE(ffloor
, ffloor
);
967 ALU_CASE(fround_even
, froundeven
);
968 ALU_CASE(ftrunc
, ftrunc
);
969 ALU_CASE(fceil
, fceil
);
970 ALU_CASE(fdot3
, fdot3
);
971 ALU_CASE(fdot4
, fdot4
);
972 ALU_CASE(iadd
, iadd
);
973 ALU_CASE(isub
, isub
);
974 ALU_CASE(imul
, imul
);
976 /* XXX: Use fmov, not imov, since imov was causing major
977 * issues with texture precision? XXX research */
978 ALU_CASE(imov
, fmov
);
987 ALU_CASE(frcp
, frcp
);
988 ALU_CASE(frsq
, frsqrt
);
989 ALU_CASE(fsqrt
, fsqrt
);
990 ALU_CASE(fpow
, fpow
);
991 ALU_CASE(fexp2
, fexp2
);
992 ALU_CASE(flog2
, flog2
);
994 ALU_CASE(f2i32
, f2i
);
995 ALU_CASE(f2u32
, f2u
);
996 ALU_CASE(i2f32
, i2f
);
997 ALU_CASE(u2f32
, u2f
);
999 ALU_CASE(fsin
, fsin
);
1000 ALU_CASE(fcos
, fcos
);
1002 ALU_CASE(iand
, iand
);
1004 ALU_CASE(ixor
, ixor
);
1005 ALU_CASE(inot
, inot
);
1006 ALU_CASE(ishl
, ishl
);
1007 ALU_CASE(ishr
, iasr
);
1008 ALU_CASE(ushr
, ilsr
);
1010 ALU_CASE(ball_fequal2
, fball_eq
);
1011 ALU_CASE(ball_fequal3
, fball_eq
);
1012 ALU_CASE(ball_fequal4
, fball_eq
);
1014 ALU_CASE(bany_fnequal2
, fbany_neq
);
1015 ALU_CASE(bany_fnequal3
, fbany_neq
);
1016 ALU_CASE(bany_fnequal4
, fbany_neq
);
1018 ALU_CASE(ball_iequal2
, iball_eq
);
1019 ALU_CASE(ball_iequal3
, iball_eq
);
1020 ALU_CASE(ball_iequal4
, iball_eq
);
1022 ALU_CASE(bany_inequal2
, ibany_neq
);
1023 ALU_CASE(bany_inequal3
, ibany_neq
);
1024 ALU_CASE(bany_inequal4
, ibany_neq
);
1026 /* For greater-or-equal, we use less-or-equal and flip the
1030 op
= midgard_alu_op_ile
;
1032 /* Swap via temporary */
1033 nir_alu_src temp
= instr
->src
[1];
1034 instr
->src
[1] = instr
->src
[0];
1035 instr
->src
[0] = temp
;
1040 case nir_op_bcsel
: {
1041 op
= midgard_alu_op_fcsel
;
1043 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1046 emit_condition(ctx
, &instr
->src
[0].src
, false);
1048 /* The condition is the first argument; move the other
1049 * arguments up one to be a binary instruction for
1052 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1056 /* We don't have a native b2f32 instruction. Instead, like many GPUs,
1057 * we exploit booleans as 0/~0 for false/true, and correspondingly AND
1058 * by 1.0 to do the type conversion. For the moment, prime us to emit:
1060 * iand [whatever], #0
1062 * At the end of emit_alu (as MIR), we'll fix-up the constant */
1064 case nir_op_b2f32
: {
1065 op
= midgard_alu_op_iand
;
1070 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1075 /* Fetch unit, quirks, etc information */
1076 unsigned opcode_props
= alu_opcode_props
[op
];
1077 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1079 /* Initialise fields common between scalar/vector instructions */
1080 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1082 /* src0 will always exist afaik, but src1 will not for 1-argument
1083 * instructions. The latter can only be fetched if the instruction
1084 * needs it, or else we may segfault. */
1086 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1087 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1089 /* Rather than use the instruction generation helpers, we do it
1090 * ourselves here to avoid the mess */
1092 midgard_instruction ins
= {
1095 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1096 .src1
= quirk_flipped_r24
? src0
: src1
,
1101 nir_alu_src
*nirmods
[2] = { NULL
};
1103 if (nr_inputs
== 2) {
1104 nirmods
[0] = &instr
->src
[0];
1105 nirmods
[1] = &instr
->src
[1];
1106 } else if (nr_inputs
== 1) {
1107 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1112 midgard_vector_alu alu
= {
1114 .reg_mode
= midgard_reg_mode_full
,
1115 .dest_override
= midgard_dest_override_none
,
1118 /* Writemask only valid for non-SSA NIR */
1119 .mask
= expand_writemask((1 << nr_components
) - 1),
1121 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1122 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1125 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1128 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1132 /* Late fixup for emulated instructions */
1134 if (instr
->op
== nir_op_b2f32
) {
1135 /* Presently, our second argument is an inline #0 constant.
1136 * Switch over to an embedded 1.0 constant (that can't fit
1137 * inline, since we're 32-bit, not 16-bit like the inline
1140 ins
.ssa_args
.inline_constant
= false;
1141 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1142 ins
.has_constants
= true;
1143 ins
.constants
[0] = 1.0;
1145 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1148 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1149 /* To avoid duplicating the lookup tables (probably), true LUT
1150 * instructions can only operate as if they were scalars. Lower
1151 * them here by changing the component. */
1153 uint8_t original_swizzle
[4];
1154 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1156 for (int i
= 0; i
< nr_components
; ++i
) {
1157 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1159 for (int j
= 0; j
< 4; ++j
)
1160 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1162 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1163 emit_mir_instruction(ctx
, ins
);
1166 emit_mir_instruction(ctx
, ins
);
1173 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1175 nir_const_value
*const_offset
;
1176 unsigned offset
, reg
;
1178 switch (instr
->intrinsic
) {
1179 case nir_intrinsic_discard_if
:
1180 emit_condition(ctx
, &instr
->src
[0], true);
1184 case nir_intrinsic_discard
: {
1185 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1186 struct midgard_instruction discard
= v_branch(conditional
, false);
1187 discard
.branch
.target_type
= TARGET_DISCARD
;
1188 emit_mir_instruction(ctx
, discard
);
1190 ctx
->can_discard
= true;
1194 case nir_intrinsic_load_uniform
:
1195 case nir_intrinsic_load_input
:
1196 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1197 assert (const_offset
&& "no indirect inputs");
1199 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1201 reg
= nir_dest_index(ctx
, &instr
->dest
);
1203 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1204 /* TODO: half-floats */
1206 int uniform_offset
= 0;
1208 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1209 /* XXX: Resolve which uniform */
1212 /* Offset away from the special
1215 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1219 DBG("WARNING: Unknown uniform %d\n", offset
);
1223 uniform_offset
= (uintptr_t) (entry
) - 1;
1224 uniform_offset
+= ctx
->special_uniforms
;
1227 if (uniform_offset
< ctx
->uniform_cutoff
) {
1228 /* Fast path: For the first 16 uniform,
1229 * accesses are 0-cycle, since they're
1230 * just a register fetch in the usual
1231 * case. So, we alias the registers
1232 * while we're still in SSA-space */
1234 int reg_slot
= 23 - uniform_offset
;
1235 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1237 /* Otherwise, read from the 'special'
1238 * UBO to access higher-indexed
1239 * uniforms, at a performance cost */
1241 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1243 /* TODO: Don't split */
1244 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1245 ins
.load_store
.address
= uniform_offset
>> 3;
1247 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1248 emit_mir_instruction(ctx
, ins
);
1250 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1251 /* XXX: Half-floats? */
1252 /* TODO: swizzle, mask */
1254 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1256 midgard_varying_parameter p
= {
1258 .interpolation
= midgard_interp_default
,
1259 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1263 memcpy(&u
, &p
, sizeof(p
));
1264 ins
.load_store
.varying_parameters
= u
;
1266 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1267 emit_mir_instruction(ctx
, ins
);
1268 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1269 /* Constant encoded as a pinned constant */
1271 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1272 ins
.has_constants
= true;
1273 ins
.has_blend_constant
= true;
1274 emit_mir_instruction(ctx
, ins
);
1275 } else if (ctx
->is_blend
) {
1276 /* For blend shaders, a load might be
1277 * translated various ways depending on what
1278 * we're loading. Figure out how this is used */
1280 nir_variable
*out
= NULL
;
1282 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1283 int drvloc
= var
->data
.driver_location
;
1285 if (nir_intrinsic_base(instr
) == drvloc
) {
1293 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1294 /* Source color preloaded to r0 */
1296 midgard_pin_output(ctx
, reg
, 0);
1297 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1298 /* Destination color must be read from framebuffer */
1300 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1301 ins
.load_store
.swizzle
= 0; /* xxxx */
1303 /* Read each component sequentially */
1305 for (int c
= 0; c
< 4; ++c
) {
1306 ins
.load_store
.mask
= (1 << c
);
1307 ins
.load_store
.unknown
= c
;
1308 emit_mir_instruction(ctx
, ins
);
1311 /* vadd.u2f hr2, abs(hr2), #0 */
1313 midgard_vector_alu_src alu_src
= blank_alu_src
;
1315 alu_src
.half
= true;
1317 midgard_instruction u2f
= {
1321 .src1
= SSA_UNUSED_0
,
1323 .inline_constant
= true
1326 .op
= midgard_alu_op_u2f
,
1327 .reg_mode
= midgard_reg_mode_half
,
1328 .dest_override
= midgard_dest_override_none
,
1330 .src1
= vector_alu_srco_unsigned(alu_src
),
1331 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1335 emit_mir_instruction(ctx
, u2f
);
1337 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1339 alu_src
.abs
= false;
1341 midgard_instruction fmul
= {
1343 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1347 .src1
= SSA_UNUSED_0
,
1348 .inline_constant
= true
1351 .op
= midgard_alu_op_fmul
,
1352 .reg_mode
= midgard_reg_mode_full
,
1353 .dest_override
= midgard_dest_override_none
,
1354 .outmod
= midgard_outmod_sat
,
1356 .src1
= vector_alu_srco_unsigned(alu_src
),
1357 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1361 emit_mir_instruction(ctx
, fmul
);
1363 DBG("Unknown input in blend shader\n");
1366 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1367 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1368 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1369 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1370 emit_mir_instruction(ctx
, ins
);
1372 DBG("Unknown load\n");
1378 case nir_intrinsic_store_output
:
1379 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1380 assert(const_offset
&& "no indirect outputs");
1382 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1384 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1386 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1387 /* gl_FragColor is not emitted with load/store
1388 * instructions. Instead, it gets plonked into
1389 * r0 at the end of the shader and we do the
1390 * framebuffer writeout dance. TODO: Defer
1393 midgard_pin_output(ctx
, reg
, 0);
1395 /* Save the index we're writing to for later reference
1396 * in the epilogue */
1398 ctx
->fragment_output
= reg
;
1399 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1400 /* Varyings are written into one of two special
1401 * varying register, r26 or r27. The register itself is selected as the register
1402 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1404 * Normally emitting fmov's is frowned upon,
1405 * but due to unique constraints of
1406 * REGISTER_VARYING, fmov emission + a
1407 * dedicated cleanup pass is the only way to
1408 * guarantee correctness when considering some
1409 * (common) edge cases XXX: FIXME */
1411 /* If this varying corresponds to a constant (why?!),
1412 * emit that now since it won't get picked up by
1413 * hoisting (since there is no corresponding move
1414 * emitted otherwise) */
1416 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1418 if (constant_value
) {
1419 /* Special case: emit the varying write
1420 * directly to r26 (looks funny in asm but it's
1421 * fine) and emit the store _now_. Possibly
1422 * slightly slower, but this is a really stupid
1423 * special case anyway (why on earth would you
1424 * have a constant varying? Your own fault for
1425 * slightly worse perf :P) */
1427 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1428 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1429 emit_mir_instruction(ctx
, ins
);
1431 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1432 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1433 emit_mir_instruction(ctx
, st
);
1435 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1437 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1440 DBG("Unknown store\n");
1446 case nir_intrinsic_load_alpha_ref_float
:
1447 assert(instr
->dest
.is_ssa
);
1449 float ref_value
= ctx
->alpha_ref
;
1451 float *v
= ralloc_array(NULL
, float, 4);
1452 memcpy(v
, &ref_value
, sizeof(float));
1453 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1458 printf ("Unhandled intrinsic\n");
1465 midgard_tex_format(enum glsl_sampler_dim dim
)
1468 case GLSL_SAMPLER_DIM_2D
:
1469 case GLSL_SAMPLER_DIM_EXTERNAL
:
1472 case GLSL_SAMPLER_DIM_3D
:
1475 case GLSL_SAMPLER_DIM_CUBE
:
1476 return TEXTURE_CUBE
;
1479 DBG("Unknown sampler dim type\n");
1486 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1489 //assert (!instr->sampler);
1490 //assert (!instr->texture_array_size);
1491 assert (instr
->op
== nir_texop_tex
);
1493 /* Allocate registers via a round robin scheme to alternate between the two registers */
1494 int reg
= ctx
->texture_op_count
& 1;
1495 int in_reg
= reg
, out_reg
= reg
;
1497 /* Make room for the reg */
1499 if (ctx
->texture_index
[reg
] > -1)
1500 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1502 int texture_index
= instr
->texture_index
;
1503 int sampler_index
= texture_index
;
1505 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1506 switch (instr
->src
[i
].src_type
) {
1507 case nir_tex_src_coord
: {
1508 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1510 midgard_vector_alu_src alu_src
= blank_alu_src
;
1511 alu_src
.swizzle
= (COMPONENT_Y
<< 2);
1513 midgard_instruction ins
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
));
1514 emit_mir_instruction(ctx
, ins
);
1516 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1522 DBG("Unknown source type\n");
1529 /* No helper to build texture words -- we do it all here */
1530 midgard_instruction ins
= {
1531 .type
= TAG_TEXTURE_4
,
1533 .op
= TEXTURE_OP_NORMAL
,
1534 .format
= midgard_tex_format(instr
->sampler_dim
),
1535 .texture_handle
= texture_index
,
1536 .sampler_handle
= sampler_index
,
1538 /* TODO: Don't force xyzw */
1539 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1551 /* Assume we can continue; hint it out later */
1556 /* Set registers to read and write from the same place */
1557 ins
.texture
.in_reg_select
= in_reg
;
1558 ins
.texture
.out_reg_select
= out_reg
;
1560 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1561 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1562 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1563 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1564 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1566 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1567 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1568 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1571 emit_mir_instruction(ctx
, ins
);
1573 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1575 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1576 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1577 ctx
->texture_index
[reg
] = o_index
;
1579 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1580 emit_mir_instruction(ctx
, ins2
);
1582 /* Used for .cont and .last hinting */
1583 ctx
->texture_op_count
++;
1587 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1589 switch (instr
->type
) {
1590 case nir_jump_break
: {
1591 /* Emit a branch out of the loop */
1592 struct midgard_instruction br
= v_branch(false, false);
1593 br
.branch
.target_type
= TARGET_BREAK
;
1594 br
.branch
.target_break
= ctx
->current_loop
;
1595 emit_mir_instruction(ctx
, br
);
1602 DBG("Unknown jump type %d\n", instr
->type
);
1608 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1610 switch (instr
->type
) {
1611 case nir_instr_type_load_const
:
1612 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1615 case nir_instr_type_intrinsic
:
1616 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1619 case nir_instr_type_alu
:
1620 emit_alu(ctx
, nir_instr_as_alu(instr
));
1623 case nir_instr_type_tex
:
1624 emit_tex(ctx
, nir_instr_as_tex(instr
));
1627 case nir_instr_type_jump
:
1628 emit_jump(ctx
, nir_instr_as_jump(instr
));
1631 case nir_instr_type_ssa_undef
:
1636 DBG("Unhandled instruction type\n");
1641 /* Determine the actual hardware from the index based on the RA results or special values */
1644 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1646 if (reg
>= SSA_FIXED_MINIMUM
)
1647 return SSA_REG_FROM_FIXED(reg
);
1650 assert(reg
< maxreg
);
1651 int r
= ra_get_node_reg(g
, reg
);
1652 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1657 /* fmov style unused */
1659 return REGISTER_UNUSED
;
1661 /* lut style unused */
1663 return REGISTER_UNUSED
;
1666 DBG("Unknown SSA register alias %d\n", reg
);
1673 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1675 /* Choose the first available register to minimise reported register pressure */
1677 for (int i
= 0; i
< 16; ++i
) {
1678 if (BITSET_TEST(regs
, i
)) {
1688 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1690 if (ins
->ssa_args
.src0
== src
) return true;
1691 if (ins
->ssa_args
.src1
== src
) return true;
1697 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1699 /* Check the rest of the block for liveness */
1700 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1701 if (midgard_is_live_in_instr(ins
, src
))
1705 /* Check the rest of the blocks for liveness */
1706 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1707 mir_foreach_instr_in_block(b
, ins
) {
1708 if (midgard_is_live_in_instr(ins
, src
))
1713 /* TODO: How does control flow interact in complex shaders? */
1719 allocate_registers(compiler_context
*ctx
)
1721 /* First, initialize the RA */
1722 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1724 /* Create a primary (general purpose) class, as well as special purpose
1725 * pipeline register classes */
1727 int primary_class
= ra_alloc_reg_class(regs
);
1728 int varying_class
= ra_alloc_reg_class(regs
);
1730 /* Add the full set of work registers */
1731 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1732 for (int i
= 0; i
< work_count
; ++i
)
1733 ra_class_add_reg(regs
, primary_class
, i
);
1735 /* Add special registers */
1736 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1737 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1739 /* We're done setting up */
1740 ra_set_finalize(regs
, NULL
);
1742 /* Transform the MIR into squeezed index form */
1743 mir_foreach_block(ctx
, block
) {
1744 mir_foreach_instr_in_block(block
, ins
) {
1745 if (ins
->compact_branch
) continue;
1747 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1748 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1749 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1751 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1752 print_mir_block(block
);
1755 /* Let's actually do register allocation */
1756 int nodes
= ctx
->temp_count
;
1757 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1759 /* Set everything to the work register class, unless it has somewhere
1762 mir_foreach_block(ctx
, block
) {
1763 mir_foreach_instr_in_block(block
, ins
) {
1764 if (ins
->compact_branch
) continue;
1766 if (ins
->ssa_args
.dest
< 0) continue;
1768 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1770 int class = primary_class
;
1772 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1776 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1777 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1780 unsigned reg
= temp
- 1;
1781 int t
= find_or_allocate_temp(ctx
, index
);
1782 ra_set_node_reg(g
, t
, reg
);
1786 /* Determine liveness */
1788 int *live_start
= malloc(nodes
* sizeof(int));
1789 int *live_end
= malloc(nodes
* sizeof(int));
1791 /* Initialize as non-existent */
1793 for (int i
= 0; i
< nodes
; ++i
) {
1794 live_start
[i
] = live_end
[i
] = -1;
1799 mir_foreach_block(ctx
, block
) {
1800 mir_foreach_instr_in_block(block
, ins
) {
1801 if (ins
->compact_branch
) continue;
1803 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1804 /* If this destination is not yet live, it is now since we just wrote it */
1806 int dest
= ins
->ssa_args
.dest
;
1808 if (live_start
[dest
] == -1)
1809 live_start
[dest
] = d
;
1812 /* Since we just used a source, the source might be
1813 * dead now. Scan the rest of the block for
1814 * invocations, and if there are none, the source dies
1817 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1819 for (int src
= 0; src
< 2; ++src
) {
1820 int s
= sources
[src
];
1822 if (s
< 0) continue;
1824 if (s
>= SSA_FIXED_MINIMUM
) continue;
1826 if (!is_live_after(ctx
, block
, ins
, s
)) {
1835 /* If a node still hasn't been killed, kill it now */
1837 for (int i
= 0; i
< nodes
; ++i
) {
1838 /* live_start == -1 most likely indicates a pinned output */
1840 if (live_end
[i
] == -1)
1844 /* Setup interference between nodes that are live at the same time */
1846 for (int i
= 0; i
< nodes
; ++i
) {
1847 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1848 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1849 ra_add_node_interference(g
, i
, j
);
1853 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1855 if (!ra_allocate(g
)) {
1856 DBG("Error allocating registers\n");
1864 mir_foreach_block(ctx
, block
) {
1865 mir_foreach_instr_in_block(block
, ins
) {
1866 if (ins
->compact_branch
) continue;
1868 ssa_args args
= ins
->ssa_args
;
1870 switch (ins
->type
) {
1872 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1874 ins
->registers
.src2_imm
= args
.inline_constant
;
1876 if (args
.inline_constant
) {
1877 /* Encode inline 16-bit constant as a vector by default */
1879 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1881 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1883 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1884 ins
->alu
.src2
= imm
<< 2;
1886 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1889 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1893 case TAG_LOAD_STORE_4
: {
1894 if (OP_IS_STORE(ins
->load_store
.op
)) {
1895 /* TODO: use ssa_args for store_vary */
1896 ins
->load_store
.reg
= 0;
1898 bool has_dest
= args
.dest
>= 0;
1899 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1901 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1914 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1915 * use scalar ALU instructions, for functional or performance reasons. To do
1916 * this, we just demote vector ALU payloads to scalar. */
1919 component_from_mask(unsigned mask
)
1921 for (int c
= 0; c
< 4; ++c
) {
1922 if (mask
& (3 << (2 * c
)))
1931 is_single_component_mask(unsigned mask
)
1935 for (int c
= 0; c
< 4; ++c
)
1936 if (mask
& (3 << (2 * c
)))
1939 return components
== 1;
1942 /* Create a mask of accessed components from a swizzle to figure out vector
1946 swizzle_to_access_mask(unsigned swizzle
)
1948 unsigned component_mask
= 0;
1950 for (int i
= 0; i
< 4; ++i
) {
1951 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1952 component_mask
|= (1 << c
);
1955 return component_mask
;
1959 vector_to_scalar_source(unsigned u
)
1961 midgard_vector_alu_src v
;
1962 memcpy(&v
, &u
, sizeof(v
));
1964 midgard_scalar_alu_src s
= {
1968 .component
= (v
.swizzle
& 3) << 1
1972 memcpy(&o
, &s
, sizeof(s
));
1974 return o
& ((1 << 6) - 1);
1977 static midgard_scalar_alu
1978 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1980 /* The output component is from the mask */
1981 midgard_scalar_alu s
= {
1983 .src1
= vector_to_scalar_source(v
.src1
),
1984 .src2
= vector_to_scalar_source(v
.src2
),
1987 .output_full
= 1, /* TODO: Half */
1988 .output_component
= component_from_mask(v
.mask
) << 1,
1991 /* Inline constant is passed along rather than trying to extract it
1994 if (ins
->ssa_args
.inline_constant
) {
1996 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1997 imm
|= (lower_11
>> 9) & 3;
1998 imm
|= (lower_11
>> 6) & 4;
1999 imm
|= (lower_11
>> 2) & 0x38;
2000 imm
|= (lower_11
& 63) << 6;
2008 /* Midgard prefetches instruction types, so during emission we need to
2009 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2010 * if this is the second to last and the last is an ALU, then it's also 1... */
2012 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2013 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2015 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2016 bytes_emitted += sizeof(type)
2019 emit_binary_vector_instruction(midgard_instruction
*ains
,
2020 uint16_t *register_words
, int *register_words_count
,
2021 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2022 size_t *bytes_emitted
)
2024 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2025 *bytes_emitted
+= sizeof(midgard_reg_info
);
2027 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2028 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2029 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2032 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2033 * mind that we are a vector architecture and we can write to different
2034 * components simultaneously */
2037 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2039 /* Each instruction reads some registers and writes to a register. See
2040 * where the first writes */
2042 /* Figure out where exactly we wrote to */
2043 int source
= first
->ssa_args
.dest
;
2044 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2046 /* As long as the second doesn't read from the first, we're okay */
2047 if (second
->ssa_args
.src0
== source
) {
2048 if (first
->type
== TAG_ALU_4
) {
2049 /* Figure out which components we just read from */
2051 int q
= second
->alu
.src1
;
2052 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2054 /* Check if there are components in common, and fail if so */
2055 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2062 if (second
->ssa_args
.src1
== source
)
2065 /* Otherwise, it's safe in that regard. Another data hazard is both
2066 * writing to the same place, of course */
2068 if (second
->ssa_args
.dest
== source
) {
2069 /* ...but only if the components overlap */
2070 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2072 if (dest_mask
& source_mask
)
2082 midgard_instruction
**segment
, unsigned segment_size
,
2083 midgard_instruction
*ains
)
2085 for (int s
= 0; s
< segment_size
; ++s
)
2086 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2094 /* Schedules, but does not emit, a single basic block. After scheduling, the
2095 * final tag and size of the block are known, which are necessary for branching
2098 static midgard_bundle
2099 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2101 int instructions_emitted
= 0, instructions_consumed
= -1;
2102 midgard_bundle bundle
= { 0 };
2104 uint8_t tag
= ins
->type
;
2106 /* Default to the instruction's tag */
2109 switch (ins
->type
) {
2111 uint32_t control
= 0;
2112 size_t bytes_emitted
= sizeof(control
);
2114 /* TODO: Constant combining */
2115 int index
= 0, last_unit
= 0;
2117 /* Previous instructions, for the purpose of parallelism */
2118 midgard_instruction
*segment
[4] = {0};
2119 int segment_size
= 0;
2121 instructions_emitted
= -1;
2122 midgard_instruction
*pins
= ins
;
2125 midgard_instruction
*ains
= pins
;
2127 /* Advance instruction pointer */
2129 ains
= mir_next_op(pins
);
2133 /* Out-of-work condition */
2134 if ((struct list_head
*) ains
== &block
->instructions
)
2137 /* Ensure that the chain can continue */
2138 if (ains
->type
!= TAG_ALU_4
) break;
2140 /* According to the presentation "The ARM
2141 * Mali-T880 Mobile GPU" from HotChips 27,
2142 * there are two pipeline stages. Branching
2143 * position determined experimentally. Lines
2144 * are executed in parallel:
2147 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2149 * Verify that there are no ordering dependencies here.
2151 * TODO: Allow for parallelism!!!
2154 /* Pick a unit for it if it doesn't force a particular unit */
2156 int unit
= ains
->unit
;
2159 int op
= ains
->alu
.op
;
2160 int units
= alu_opcode_props
[op
];
2162 /* TODO: Promotion of scalars to vectors */
2163 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2166 assert(units
& UNITS_SCALAR
);
2169 if (last_unit
>= UNIT_VADD
) {
2170 if (units
& UNIT_VLUT
)
2175 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2177 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2179 else if (units
& UNIT_VLUT
)
2185 if (last_unit
>= UNIT_VADD
) {
2186 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2188 else if (units
& UNIT_VLUT
)
2193 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2195 else if (units
& UNIT_SMUL
)
2196 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2197 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2204 assert(unit
& units
);
2207 /* Late unit check, this time for encoding (not parallelism) */
2208 if (unit
<= last_unit
) break;
2210 /* Clear the segment */
2211 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2214 if (midgard_has_hazard(segment
, segment_size
, ains
))
2217 /* We're good to go -- emit the instruction */
2220 segment
[segment_size
++] = ains
;
2222 /* Only one set of embedded constants per
2223 * bundle possible; if we have more, we must
2224 * break the chain early, unfortunately */
2226 if (ains
->has_constants
) {
2227 if (bundle
.has_embedded_constants
) {
2228 /* ...but if there are already
2229 * constants but these are the
2230 * *same* constants, we let it
2233 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2236 bundle
.has_embedded_constants
= true;
2237 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2239 /* If this is a blend shader special constant, track it for patching */
2240 if (ains
->has_blend_constant
)
2241 bundle
.has_blend_constant
= true;
2245 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2246 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2247 &bundle
.register_words_count
, bundle
.body_words
,
2248 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2249 } else if (ains
->compact_branch
) {
2250 /* All of r0 has to be written out
2251 * along with the branch writeout.
2254 if (ains
->writeout
) {
2256 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2257 ins
.unit
= UNIT_VMUL
;
2259 control
|= ins
.unit
;
2261 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2262 &bundle
.register_words_count
, bundle
.body_words
,
2263 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2265 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2266 bool written_late
= false;
2267 bool components
[4] = { 0 };
2268 uint16_t register_dep_mask
= 0;
2269 uint16_t written_mask
= 0;
2271 midgard_instruction
*qins
= ins
;
2272 for (int t
= 0; t
< index
; ++t
) {
2273 if (qins
->registers
.out_reg
!= 0) {
2274 /* Mark down writes */
2276 written_mask
|= (1 << qins
->registers
.out_reg
);
2278 /* Mark down the register dependencies for errata check */
2280 if (qins
->registers
.src1_reg
< 16)
2281 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2283 if (qins
->registers
.src2_reg
< 16)
2284 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2286 int mask
= qins
->alu
.mask
;
2288 for (int c
= 0; c
< 4; ++c
)
2289 if (mask
& (0x3 << (2 * c
)))
2290 components
[c
] = true;
2292 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2294 if (qins
->unit
== UNIT_VLUT
)
2295 written_late
= true;
2298 /* Advance instruction pointer */
2299 qins
= mir_next_op(qins
);
2303 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2304 if (register_dep_mask
& written_mask
) {
2305 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2312 /* If even a single component is not written, break it up (conservative check). */
2313 bool breakup
= false;
2315 for (int c
= 0; c
< 4; ++c
)
2322 /* Otherwise, we're free to proceed */
2326 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2327 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2328 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2329 bytes_emitted
+= sizeof(midgard_branch_extended
);
2331 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2332 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2333 bytes_emitted
+= sizeof(ains
->br_compact
);
2336 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2337 bytes_emitted
+= sizeof(midgard_reg_info
);
2339 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2340 bundle
.body_words_count
++;
2341 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2344 /* Defer marking until after writing to allow for break */
2345 control
|= ains
->unit
;
2346 last_unit
= ains
->unit
;
2347 ++instructions_emitted
;
2351 /* Bubble up the number of instructions for skipping */
2352 instructions_consumed
= index
- 1;
2356 /* Pad ALU op to nearest word */
2358 if (bytes_emitted
& 15) {
2359 padding
= 16 - (bytes_emitted
& 15);
2360 bytes_emitted
+= padding
;
2363 /* Constants must always be quadwords */
2364 if (bundle
.has_embedded_constants
)
2365 bytes_emitted
+= 16;
2367 /* Size ALU instruction for tag */
2368 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2369 bundle
.padding
= padding
;
2370 bundle
.control
= bundle
.tag
| control
;
2375 case TAG_LOAD_STORE_4
: {
2376 /* Load store instructions have two words at once. If
2377 * we only have one queued up, we need to NOP pad.
2378 * Otherwise, we store both in succession to save space
2379 * and cycles -- letting them go in parallel -- skip
2380 * the next. The usefulness of this optimisation is
2381 * greatly dependent on the quality of the instruction
2385 midgard_instruction
*next_op
= mir_next_op(ins
);
2387 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2388 /* As the two operate concurrently, make sure
2389 * they are not dependent */
2391 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2392 /* Skip ahead, since it's redundant with the pair */
2393 instructions_consumed
= 1 + (instructions_emitted
++);
2401 /* Texture ops default to single-op-per-bundle scheduling */
2405 /* Copy the instructions into the bundle */
2406 bundle
.instruction_count
= instructions_emitted
+ 1;
2410 midgard_instruction
*uins
= ins
;
2411 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2412 bundle
.instructions
[used_idx
++] = *uins
;
2413 uins
= mir_next_op(uins
);
2416 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2422 quadword_size(int tag
)
2437 case TAG_LOAD_STORE_4
:
2449 /* Schedule a single block by iterating its instruction to create bundles.
2450 * While we go, tally about the bundle sizes to compute the block size. */
2453 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2455 util_dynarray_init(&block
->bundles
, NULL
);
2457 block
->quadword_count
= 0;
2459 mir_foreach_instr_in_block(block
, ins
) {
2461 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2462 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2464 if (bundle
.has_blend_constant
) {
2465 /* TODO: Multiblock? */
2466 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2467 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2471 ins
= mir_next_op(ins
);
2473 block
->quadword_count
+= quadword_size(bundle
.tag
);
2476 block
->is_scheduled
= true;
2480 schedule_program(compiler_context
*ctx
)
2482 allocate_registers(ctx
);
2484 mir_foreach_block(ctx
, block
) {
2485 schedule_block(ctx
, block
);
2489 /* After everything is scheduled, emit whole bundles at a time */
2492 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2494 int lookahead
= next_tag
<< 4;
2496 switch (bundle
->tag
) {
2501 /* Actually emit each component */
2502 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2504 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2505 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2507 /* Emit body words based on the instructions bundled */
2508 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2509 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2511 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2512 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2513 } else if (ins
->compact_branch
) {
2514 /* Dummy move, XXX DRY */
2515 if ((i
== 0) && ins
->writeout
) {
2516 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2517 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2520 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2521 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2523 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2527 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2528 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2532 /* Emit padding (all zero) */
2533 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2535 /* Tack on constants */
2537 if (bundle
->has_embedded_constants
) {
2538 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2539 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2540 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2541 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2547 case TAG_LOAD_STORE_4
: {
2548 /* One or two composing instructions */
2550 uint64_t current64
, next64
= LDST_NOP
;
2552 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2554 if (bundle
->instruction_count
== 2)
2555 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2557 midgard_load_store instruction
= {
2558 .type
= bundle
->tag
,
2559 .next_type
= next_tag
,
2564 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2569 case TAG_TEXTURE_4
: {
2570 /* Texture instructions are easy, since there is no
2571 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2573 midgard_instruction
*ins
= &bundle
->instructions
[0];
2575 ins
->texture
.type
= TAG_TEXTURE_4
;
2576 ins
->texture
.next_type
= next_tag
;
2578 ctx
->texture_op_count
--;
2580 if (!ctx
->texture_op_count
) {
2581 ins
->texture
.cont
= 0;
2582 ins
->texture
.last
= 1;
2585 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2590 DBG("Unknown midgard instruction type\n");
2597 /* ALU instructions can inline or embed constants, which decreases register
2598 * pressure and saves space. */
2600 #define CONDITIONAL_ATTACH(src) { \
2601 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2604 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2605 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2610 inline_alu_constants(compiler_context
*ctx
)
2612 mir_foreach_instr(ctx
, alu
) {
2613 /* Other instructions cannot inline constants */
2614 if (alu
->type
!= TAG_ALU_4
) continue;
2616 /* If there is already a constant here, we can do nothing */
2617 if (alu
->has_constants
) continue;
2619 CONDITIONAL_ATTACH(src0
);
2621 if (!alu
->has_constants
) {
2622 CONDITIONAL_ATTACH(src1
)
2623 } else if (!alu
->inline_constant
) {
2624 /* Corner case: _two_ vec4 constants, for instance with a
2625 * csel. For this case, we can only use a constant
2626 * register for one, we'll have to emit a move for the
2627 * other. Note, if both arguments are constants, then
2628 * necessarily neither argument depends on the value of
2629 * any particular register. As the destination register
2630 * will be wiped, that means we can spill the constant
2631 * to the destination register.
2634 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2635 unsigned scratch
= alu
->ssa_args
.dest
;
2638 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2639 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2641 /* Force a break XXX Defer r31 writes */
2642 ins
.unit
= UNIT_VLUT
;
2644 /* Set the source */
2645 alu
->ssa_args
.src1
= scratch
;
2647 /* Inject us -before- the last instruction which set r31 */
2648 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2654 /* Midgard supports two types of constants, embedded constants (128-bit) and
2655 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2656 * constants can be demoted to inline constants, for space savings and
2657 * sometimes a performance boost */
2660 embedded_to_inline_constant(compiler_context
*ctx
)
2662 mir_foreach_instr(ctx
, ins
) {
2663 if (!ins
->has_constants
) continue;
2665 if (ins
->ssa_args
.inline_constant
) continue;
2667 /* Blend constants must not be inlined by definition */
2668 if (ins
->has_blend_constant
) continue;
2670 /* src1 cannot be an inline constant due to encoding
2671 * restrictions. So, if possible we try to flip the arguments
2674 int op
= ins
->alu
.op
;
2676 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2677 /* Flip based on op. Fallthrough intentional */
2680 /* These ops require an operational change to flip their arguments TODO */
2681 case midgard_alu_op_flt
:
2682 case midgard_alu_op_fle
:
2683 case midgard_alu_op_ilt
:
2684 case midgard_alu_op_ile
:
2685 case midgard_alu_op_fcsel
:
2686 case midgard_alu_op_icsel
:
2687 case midgard_alu_op_isub
:
2688 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2691 /* These ops are commutative and Just Flip */
2692 case midgard_alu_op_fne
:
2693 case midgard_alu_op_fadd
:
2694 case midgard_alu_op_fmul
:
2695 case midgard_alu_op_fmin
:
2696 case midgard_alu_op_fmax
:
2697 case midgard_alu_op_iadd
:
2698 case midgard_alu_op_imul
:
2699 case midgard_alu_op_feq
:
2700 case midgard_alu_op_ieq
:
2701 case midgard_alu_op_ine
:
2702 case midgard_alu_op_iand
:
2703 case midgard_alu_op_ior
:
2704 case midgard_alu_op_ixor
:
2705 /* Flip the SSA numbers */
2706 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2707 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2709 /* And flip the modifiers */
2713 src_temp
= ins
->alu
.src2
;
2714 ins
->alu
.src2
= ins
->alu
.src1
;
2715 ins
->alu
.src1
= src_temp
;
2722 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2723 /* Extract the source information */
2725 midgard_vector_alu_src
*src
;
2726 int q
= ins
->alu
.src2
;
2727 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2730 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2731 int component
= src
->swizzle
& 3;
2733 /* Scale constant appropriately, if we can legally */
2734 uint16_t scaled_constant
= 0;
2736 /* XXX: Check legality */
2737 if (midgard_is_integer_op(op
)) {
2738 /* TODO: Inline integer */
2741 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2742 scaled_constant
= (uint16_t) iconstants
[component
];
2744 /* Constant overflow after resize */
2745 if (scaled_constant
!= iconstants
[component
])
2748 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2751 /* We don't know how to handle these with a constant */
2753 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2754 DBG("Bailing inline constant...\n");
2758 /* Make sure that the constant is not itself a
2759 * vector by checking if all accessed values
2760 * (by the swizzle) are the same. */
2762 uint32_t *cons
= (uint32_t *) ins
->constants
;
2763 uint32_t value
= cons
[component
];
2765 bool is_vector
= false;
2766 unsigned mask
= effective_writemask(&ins
->alu
);
2768 for (int c
= 1; c
< 4; ++c
) {
2769 /* We only care if this component is actually used */
2770 if (!(mask
& (1 << c
)))
2773 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2775 if (test
!= value
) {
2784 /* Get rid of the embedded constant */
2785 ins
->has_constants
= false;
2786 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2787 ins
->ssa_args
.inline_constant
= true;
2788 ins
->inline_constant
= scaled_constant
;
2793 /* Map normal SSA sources to other SSA sources / fixed registers (like
2797 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2799 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2802 /* Remove entry in leftovers to avoid a redunant fmov */
2804 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2807 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2809 /* Assign the alias map */
2815 #define AS_SRC(to, u) \
2816 int q##to = ins->alu.src2; \
2817 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2819 /* Removing unused moves is necessary to clean up the texture pipeline results.
2821 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2824 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2826 mir_foreach_instr_in_block_safe(block
, ins
) {
2827 if (ins
->type
!= TAG_ALU_4
) continue;
2829 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2831 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2833 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2835 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2837 mir_remove_instruction(ins
);
2841 /* The following passes reorder MIR instructions to enable better scheduling */
2844 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2846 mir_foreach_instr_in_block_safe(block
, ins
) {
2847 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2849 /* We've found a load/store op. Check if next is also load/store. */
2850 midgard_instruction
*next_op
= mir_next_op(ins
);
2851 if (&next_op
->link
!= &block
->instructions
) {
2852 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2853 /* If so, we're done since we're a pair */
2854 ins
= mir_next_op(ins
);
2858 /* Maximum search distance to pair, to avoid register pressure disasters */
2859 int search_distance
= 8;
2861 /* Otherwise, we have an orphaned load/store -- search for another load */
2862 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2863 /* Terminate search if necessary */
2864 if (!(search_distance
--)) break;
2866 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2868 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2870 /* We found one! Move it up to pair and remove it from the old location */
2872 mir_insert_instruction_before(ins
, *c
);
2873 mir_remove_instruction(c
);
2881 /* Emit varying stores late */
2884 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2885 /* Iterate in reverse to get the final write, rather than the first */
2887 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2888 /* Check if what we just wrote needs a store */
2889 int idx
= ins
->ssa_args
.dest
;
2890 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2892 if (!varying
) continue;
2896 /* We need to store to the appropriate varying, so emit the
2899 /* TODO: Integrate with special purpose RA (and scheduler?) */
2900 bool high_varying_register
= false;
2902 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2904 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2905 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2907 mir_insert_instruction_before(mir_next_op(ins
), st
);
2908 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2910 /* We no longer need to store this varying */
2911 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2915 /* If there are leftovers after the below pass, emit actual fmov
2916 * instructions for the slow-but-correct path */
2919 emit_leftover_move(compiler_context
*ctx
)
2921 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2922 int base
= ((uintptr_t) leftover
->key
) - 1;
2925 map_ssa_to_alias(ctx
, &mapped
);
2926 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2931 actualise_ssa_to_alias(compiler_context
*ctx
)
2933 mir_foreach_instr(ctx
, ins
) {
2934 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2935 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2938 emit_leftover_move(ctx
);
2941 /* Vertex shaders do not write gl_Position as is; instead, they write a
2942 * transformed screen space position as a varying. See section 12.5 "Coordinate
2943 * Transformation" of the ES 3.2 full specification for details.
2945 * This transformation occurs early on, as NIR and prior to optimisation, in
2946 * order to take advantage of NIR optimisation passes of the transform itself.
2950 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
2952 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
2954 /* Get viewport from the uniforms */
2955 nir_intrinsic_instr
*load
;
2956 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
2957 load
->num_components
= 4;
2958 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
2959 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
2960 nir_builder_instr_insert(b
, &load
->instr
);
2962 /* Formatted as <width, height, centerx, centery> */
2963 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
2964 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
2965 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
2966 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
2968 /* XXX: From uniforms? */
2969 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
2970 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
2972 /* World space to normalised device coordinates */
2974 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
2975 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
2977 /* Normalised device coordinates to screen space */
2979 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
2980 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
2982 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2983 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2984 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
2986 /* gl_Position will be written out in screenspace xyz, with w set to
2987 * the reciprocal we computed earlier. The transformed w component is
2988 * then used for perspective-correct varying interpolation. The
2989 * transformed w component must preserve its original sign; this is
2990 * used in depth clipping computations */
2992 nir_ssa_def
*screen_space
= nir_vec4(b
,
2993 nir_channel(b
, viewport_xy
, 0),
2994 nir_channel(b
, viewport_xy
, 1),
2998 /* Finally, write out the transformed values to the varying */
3000 nir_intrinsic_instr
*store
;
3001 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
3002 store
->num_components
= 4;
3003 nir_intrinsic_set_base(store
, 0);
3004 nir_intrinsic_set_write_mask(store
, 0xf);
3005 store
->src
[0].ssa
= screen_space
;
3006 store
->src
[0].is_ssa
= true;
3007 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
3008 nir_builder_instr_insert(b
, &store
->instr
);
3012 transform_position_writes(nir_shader
*shader
)
3014 nir_foreach_function(func
, shader
) {
3015 nir_foreach_block(block
, func
->impl
) {
3016 nir_foreach_instr_safe(instr
, block
) {
3017 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
3019 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
3020 nir_variable
*out
= NULL
;
3022 switch (intr
->intrinsic
) {
3023 case nir_intrinsic_store_output
:
3024 /* already had i/o lowered.. lookup the matching output var: */
3025 nir_foreach_variable(var
, &shader
->outputs
) {
3026 int drvloc
= var
->data
.driver_location
;
3028 if (nir_intrinsic_base(intr
) == drvloc
) {
3042 if (out
->data
.mode
!= nir_var_shader_out
)
3045 if (out
->data
.location
!= VARYING_SLOT_POS
)
3049 nir_builder_init(&b
, func
->impl
);
3050 b
.cursor
= nir_before_instr(instr
);
3052 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
3053 nir_instr_remove(instr
);
3060 emit_fragment_epilogue(compiler_context
*ctx
)
3062 /* Special case: writing out constants requires us to include the move
3063 * explicitly now, so shove it into r0 */
3065 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3067 if (constant_value
) {
3068 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3069 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3070 emit_mir_instruction(ctx
, ins
);
3073 /* Perform the actual fragment writeout. We have two writeout/branch
3074 * instructions, forming a loop until writeout is successful as per the
3075 * docs. TODO: gl_FragDepth */
3077 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3078 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3081 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3082 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3083 * with the int8 analogue to the fragment epilogue */
3086 emit_blend_epilogue(compiler_context
*ctx
)
3088 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3090 midgard_instruction scale
= {
3093 .inline_constant
= _mesa_float_to_half(255.0),
3095 .src0
= SSA_FIXED_REGISTER(0),
3096 .src1
= SSA_UNUSED_0
,
3097 .dest
= SSA_FIXED_REGISTER(24),
3098 .inline_constant
= true
3101 .op
= midgard_alu_op_fmul
,
3102 .reg_mode
= midgard_reg_mode_full
,
3103 .dest_override
= midgard_dest_override_lower
,
3105 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3106 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3110 emit_mir_instruction(ctx
, scale
);
3112 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3114 midgard_vector_alu_src alu_src
= blank_alu_src
;
3115 alu_src
.half
= true;
3117 midgard_instruction f2u8
= {
3120 .src0
= SSA_FIXED_REGISTER(24),
3121 .src1
= SSA_UNUSED_0
,
3122 .dest
= SSA_FIXED_REGISTER(0),
3123 .inline_constant
= true
3126 .op
= midgard_alu_op_f2u8
,
3127 .reg_mode
= midgard_reg_mode_half
,
3128 .dest_override
= midgard_dest_override_lower
,
3129 .outmod
= midgard_outmod_pos
,
3131 .src1
= vector_alu_srco_unsigned(alu_src
),
3132 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3136 emit_mir_instruction(ctx
, f2u8
);
3138 /* vmul.imov.quarter r0, r0, r0 */
3140 midgard_instruction imov_8
= {
3143 .src0
= SSA_UNUSED_1
,
3144 .src1
= SSA_FIXED_REGISTER(0),
3145 .dest
= SSA_FIXED_REGISTER(0),
3148 .op
= midgard_alu_op_imov
,
3149 .reg_mode
= midgard_reg_mode_quarter
,
3150 .dest_override
= midgard_dest_override_none
,
3152 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3153 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3157 /* Emit branch epilogue with the 8-bit move as the source */
3159 emit_mir_instruction(ctx
, imov_8
);
3160 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3162 emit_mir_instruction(ctx
, imov_8
);
3163 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3166 static midgard_block
*
3167 emit_block(compiler_context
*ctx
, nir_block
*block
)
3169 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3170 list_addtail(&this_block
->link
, &ctx
->blocks
);
3172 this_block
->is_scheduled
= false;
3175 ctx
->texture_index
[0] = -1;
3176 ctx
->texture_index
[1] = -1;
3178 /* Set up current block */
3179 list_inithead(&this_block
->instructions
);
3180 ctx
->current_block
= this_block
;
3182 nir_foreach_instr(instr
, block
) {
3183 emit_instr(ctx
, instr
);
3184 ++ctx
->instruction_count
;
3187 inline_alu_constants(ctx
);
3188 embedded_to_inline_constant(ctx
);
3190 /* Perform heavylifting for aliasing */
3191 actualise_ssa_to_alias(ctx
);
3193 midgard_emit_store(ctx
, this_block
);
3194 midgard_eliminate_orphan_moves(ctx
, this_block
);
3195 midgard_pair_load_store(ctx
, this_block
);
3197 /* Append fragment shader epilogue (value writeout) */
3198 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3199 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3201 emit_blend_epilogue(ctx
);
3203 emit_fragment_epilogue(ctx
);
3207 /* Fallthrough save */
3208 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3210 if (block
== nir_start_block(ctx
->func
->impl
))
3211 ctx
->initial_block
= this_block
;
3213 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3214 ctx
->final_block
= this_block
;
3216 /* Allow the next control flow to access us retroactively, for
3218 ctx
->current_block
= this_block
;
3220 /* Document the fallthrough chain */
3221 ctx
->previous_source_block
= this_block
;
3226 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3229 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3231 /* Conditional branches expect the condition in r31.w; emit a move for
3232 * that in the _previous_ block (which is the current block). */
3233 emit_condition(ctx
, &nif
->condition
, true);
3235 /* Speculatively emit the branch, but we can't fill it in until later */
3236 EMIT(branch
, true, true);
3237 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3239 /* Emit the two subblocks */
3240 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3242 /* Emit a jump from the end of the then block to the end of the else */
3243 EMIT(branch
, false, false);
3244 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3246 /* Emit second block, and check if it's empty */
3248 int else_idx
= ctx
->block_count
;
3249 int count_in
= ctx
->instruction_count
;
3250 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3251 int after_else_idx
= ctx
->block_count
;
3253 /* Now that we have the subblocks emitted, fix up the branches */
3258 if (ctx
->instruction_count
== count_in
) {
3259 /* The else block is empty, so don't emit an exit jump */
3260 mir_remove_instruction(then_exit
);
3261 then_branch
->branch
.target_block
= after_else_idx
;
3263 then_branch
->branch
.target_block
= else_idx
;
3264 then_exit
->branch
.target_block
= after_else_idx
;
3269 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3271 /* Remember where we are */
3272 midgard_block
*start_block
= ctx
->current_block
;
3274 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3275 * single current_loop variable, maybe we need a stack */
3277 int loop_idx
= ++ctx
->current_loop
;
3279 /* Get index from before the body so we can loop back later */
3280 int start_idx
= ctx
->block_count
;
3282 /* Emit the body itself */
3283 emit_cf_list(ctx
, &nloop
->body
);
3285 /* Branch back to loop back */
3286 struct midgard_instruction br_back
= v_branch(false, false);
3287 br_back
.branch
.target_block
= start_idx
;
3288 emit_mir_instruction(ctx
, br_back
);
3290 /* Find the index of the block about to follow us (note: we don't add
3291 * one; blocks are 0-indexed so we get a fencepost problem) */
3292 int break_block_idx
= ctx
->block_count
;
3294 /* Fix up the break statements we emitted to point to the right place,
3295 * now that we can allocate a block number for them */
3297 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3298 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3299 print_mir_block(block
);
3300 mir_foreach_instr_in_block(block
, ins
) {
3301 if (ins
->type
!= TAG_ALU_4
) continue;
3302 if (!ins
->compact_branch
) continue;
3303 if (ins
->prepacked_branch
) continue;
3305 /* We found a branch -- check the type to see if we need to do anything */
3306 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3308 /* It's a break! Check if it's our break */
3309 if (ins
->branch
.target_break
!= loop_idx
) continue;
3311 /* Okay, cool, we're breaking out of this loop.
3312 * Rewrite from a break to a goto */
3314 ins
->branch
.target_type
= TARGET_GOTO
;
3315 ins
->branch
.target_block
= break_block_idx
;
3320 static midgard_block
*
3321 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3323 midgard_block
*start_block
= NULL
;
3325 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3326 switch (node
->type
) {
3327 case nir_cf_node_block
: {
3328 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3331 start_block
= block
;
3336 case nir_cf_node_if
:
3337 emit_if(ctx
, nir_cf_node_as_if(node
));
3340 case nir_cf_node_loop
:
3341 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3344 case nir_cf_node_function
:
3353 /* Due to lookahead, we need to report the first tag executed in the command
3354 * stream and in branch targets. An initial block might be empty, so iterate
3355 * until we find one that 'works' */
3358 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3360 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3362 unsigned first_tag
= 0;
3365 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3367 if (initial_bundle
) {
3368 first_tag
= initial_bundle
->tag
;
3372 /* Initial block is empty, try the next block */
3373 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3374 } while(initial_block
!= NULL
);
3381 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3383 struct util_dynarray
*compiled
= &program
->compiled
;
3385 midgard_debug
= debug_get_option_midgard_debug();
3387 compiler_context ictx
= {
3389 .stage
= nir
->info
.stage
,
3391 .is_blend
= is_blend
,
3392 .blend_constant_offset
= -1,
3394 .alpha_ref
= program
->alpha_ref
3397 compiler_context
*ctx
= &ictx
;
3399 /* TODO: Decide this at runtime */
3400 ctx
->uniform_cutoff
= 8;
3402 switch (ctx
->stage
) {
3403 case MESA_SHADER_VERTEX
:
3404 ctx
->special_uniforms
= 1;
3408 ctx
->special_uniforms
= 0;
3412 /* Append epilogue uniforms if necessary. The cmdstream depends on
3413 * these being at the -end-; see assign_var_locations. */
3415 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3416 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3419 /* Assign var locations early, so the epilogue can use them if necessary */
3421 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3422 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3423 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3425 /* Initialize at a global (not block) level hash tables */
3427 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3428 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3429 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3430 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3431 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3432 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3434 /* Assign actual uniform location, skipping over samplers */
3436 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3438 nir_foreach_variable(var
, &nir
->uniforms
) {
3439 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3441 unsigned length
= glsl_get_aoa_size(var
->type
);
3444 length
= glsl_get_length(var
->type
);
3448 length
= glsl_get_matrix_columns(var
->type
);
3451 for (int col
= 0; col
< length
; ++col
) {
3452 int id
= ctx
->uniform_count
++;
3453 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3457 /* Record the varying mapping for the command stream's bookkeeping */
3459 struct exec_list
*varyings
=
3460 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3462 nir_foreach_variable(var
, varyings
) {
3463 unsigned loc
= var
->data
.driver_location
;
3464 program
->varyings
[loc
] = var
->data
.location
;
3467 /* Lower vars -- not I/O -- before epilogue */
3469 NIR_PASS_V(nir
, nir_lower_var_copies
);
3470 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3471 NIR_PASS_V(nir
, nir_split_var_copies
);
3472 NIR_PASS_V(nir
, nir_lower_var_copies
);
3473 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3474 NIR_PASS_V(nir
, nir_lower_var_copies
);
3475 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3476 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3478 /* Append vertex epilogue before optimisation, so the epilogue itself
3481 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3482 transform_position_writes(nir
);
3484 /* Optimisation passes */
3488 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3489 nir_print_shader(nir
, stdout
);
3492 /* Assign counts, now that we're sure (post-optimisation) */
3493 program
->uniform_count
= nir
->num_uniforms
;
3495 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3496 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3499 nir_foreach_function(func
, nir
) {
3503 list_inithead(&ctx
->blocks
);
3504 ctx
->block_count
= 0;
3507 emit_cf_list(ctx
, &func
->impl
->body
);
3508 emit_block(ctx
, func
->impl
->end_block
);
3510 break; /* TODO: Multi-function shaders */
3513 util_dynarray_init(compiled
, NULL
);
3516 schedule_program(ctx
);
3518 /* Now that all the bundles are scheduled and we can calculate block
3519 * sizes, emit actual branch instructions rather than placeholders */
3521 int br_block_idx
= 0;
3523 mir_foreach_block(ctx
, block
) {
3524 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3525 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3526 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3528 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3530 if (ins
->prepacked_branch
) continue;
3532 /* Parse some basic branch info */
3533 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3534 bool is_conditional
= ins
->branch
.conditional
;
3535 bool is_inverted
= ins
->branch
.invert_conditional
;
3536 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3538 /* Determine the block we're jumping to */
3539 int target_number
= ins
->branch
.target_block
;
3541 /* Report the destination tag. Discards don't need this */
3542 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3544 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3545 int quadword_offset
= 0;
3548 /* Jump to the end of the shader. We
3549 * need to include not only the
3550 * following blocks, but also the
3551 * contents of our current block (since
3552 * discard can come in the middle of
3555 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3557 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3558 quadword_offset
+= quadword_size(bun
->tag
);
3561 mir_foreach_block_from(ctx
, blk
, b
) {
3562 quadword_offset
+= b
->quadword_count
;
3565 } else if (target_number
> br_block_idx
) {
3568 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3569 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3572 quadword_offset
+= blk
->quadword_count
;
3575 /* Jump backwards */
3577 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3578 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3581 quadword_offset
-= blk
->quadword_count
;
3585 /* Unconditional extended branches (far jumps)
3586 * have issues, so we always use a conditional
3587 * branch, setting the condition to always for
3588 * unconditional. For compact unconditional
3589 * branches, cond isn't used so it doesn't
3590 * matter what we pick. */
3592 midgard_condition cond
=
3593 !is_conditional
? midgard_condition_always
:
3594 is_inverted
? midgard_condition_false
:
3595 midgard_condition_true
;
3597 midgard_jmp_writeout_op op
=
3598 is_discard
? midgard_jmp_writeout_op_discard
:
3599 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3600 midgard_jmp_writeout_op_branch_cond
;
3603 midgard_branch_extended branch
=
3604 midgard_create_branch_extended(
3609 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3610 } else if (is_conditional
|| is_discard
) {
3611 midgard_branch_cond branch
= {
3613 .dest_tag
= dest_tag
,
3614 .offset
= quadword_offset
,
3618 assert(branch
.offset
== quadword_offset
);
3620 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3622 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3624 midgard_branch_uncond branch
= {
3626 .dest_tag
= dest_tag
,
3627 .offset
= quadword_offset
,
3631 assert(branch
.offset
== quadword_offset
);
3633 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3641 /* Emit flat binary from the instruction arrays. Iterate each block in
3642 * sequence. Save instruction boundaries such that lookahead tags can
3643 * be assigned easily */
3645 /* Cache _all_ bundles in source order for lookahead across failed branches */
3647 int bundle_count
= 0;
3648 mir_foreach_block(ctx
, block
) {
3649 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3651 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3653 mir_foreach_block(ctx
, block
) {
3654 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3655 source_order_bundles
[bundle_idx
++] = bundle
;
3659 int current_bundle
= 0;
3661 mir_foreach_block(ctx
, block
) {
3662 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3665 if (current_bundle
+ 1 < bundle_count
) {
3666 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3668 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3675 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3679 /* TODO: Free deeper */
3680 //util_dynarray_fini(&block->instructions);
3683 free(source_order_bundles
);
3685 /* Report the very first tag executed */
3686 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3688 /* Deal with off-by-one related to the fencepost problem */
3689 program
->work_register_count
= ctx
->work_registers
+ 1;
3691 program
->can_discard
= ctx
->can_discard
;
3692 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3694 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3696 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3697 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);