2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
111 midgard_is_branch_unit(unsigned unit
)
113 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
116 /* Generic in-memory data type repesenting a single logical instruction, rather
117 * than a single instruction group. This is the preferred form for code gen.
118 * Multiple midgard_insturctions will later be combined during scheduling,
119 * though this is not represented in this structure. Its format bridges
120 * the low-level binary representation with the higher level semantic meaning.
122 * Notably, it allows registers to be specified as block local SSA, for code
123 * emitted before the register allocation pass.
126 typedef struct midgard_instruction
{
127 /* Must be first for casting */
128 struct list_head link
;
130 unsigned type
; /* ALU, load/store, texture */
132 /* If the register allocator has not run yet... */
135 /* Special fields for an ALU instruction */
136 midgard_reg_info registers
;
138 /* I.e. (1 << alu_bit) */
143 uint16_t inline_constant
;
144 bool has_blend_constant
;
148 bool prepacked_branch
;
151 midgard_load_store_word load_store
;
152 midgard_vector_alu alu
;
153 midgard_texture_word texture
;
154 midgard_branch_extended branch_extended
;
157 /* General branch, rather than packed br_compact. Higher level
158 * than the other components */
159 midgard_branch branch
;
161 } midgard_instruction
;
163 typedef struct midgard_block
{
164 /* Link to next block. Must be first for mir_get_block */
165 struct list_head link
;
167 /* List of midgard_instructions emitted for the current block */
168 struct list_head instructions
;
172 /* List of midgard_bundles emitted (after the scheduler has run) */
173 struct util_dynarray bundles
;
175 /* Number of quadwords _actually_ emitted, as determined after scheduling */
176 unsigned quadword_count
;
178 /* Successors: always one forward (the block after us), maybe
179 * one backwards (for a backward branch). No need for a second
180 * forward, since graph traversal would get there eventually
182 struct midgard_block
*successors
[2];
183 unsigned nr_successors
;
185 /* The successors pointer form a graph, and in the case of
186 * complex control flow, this graph has a cycles. To aid
187 * traversal during liveness analysis, we have a visited?
188 * boolean for passes to use as they see fit, provided they
194 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
196 block
->successors
[block
->nr_successors
++] = successor
;
197 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
200 /* Helpers to generate midgard_instruction's using macro magic, since every
201 * driver seems to do it that way */
203 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
204 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
206 #define M_LOAD_STORE(name, rname, uname) \
207 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
208 midgard_instruction i = { \
209 .type = TAG_LOAD_STORE_4, \
216 .op = midgard_op_##name, \
218 .swizzle = SWIZZLE_XYZW, \
226 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
227 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
229 const midgard_vector_alu_src blank_alu_src
= {
230 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
233 const midgard_vector_alu_src blank_alu_src_xxxx
= {
234 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
237 const midgard_scalar_alu_src blank_scalar_alu_src
= {
241 /* Used for encoding the unused source of 1-op instructions */
242 const midgard_vector_alu_src zero_alu_src
= { 0 };
244 /* Coerce structs to integer */
247 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
250 memcpy(&u
, &src
, sizeof(src
));
254 static midgard_vector_alu_src
255 vector_alu_from_unsigned(unsigned u
)
257 midgard_vector_alu_src s
;
258 memcpy(&s
, &u
, sizeof(s
));
262 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
263 * the corresponding Midgard source */
265 static midgard_vector_alu_src
266 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
268 if (!src
) return blank_alu_src
;
270 midgard_vector_alu_src alu_src
= {
273 .half
= 0, /* TODO */
274 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
278 /* TODO: sign-extend/zero-extend */
279 alu_src
.mod
= midgard_int_normal
;
281 /* These should have been lowered away */
282 assert(!(src
->abs
|| src
->negate
));
284 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
291 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
294 if (!is_int
&& src
.mod
) return true;
297 for (unsigned c
= 0; c
< 4; ++c
) {
298 if (!(mask
& (1 << c
))) continue;
299 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
305 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
307 static midgard_instruction
308 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
310 midgard_instruction ins
= {
313 .src0
= SSA_UNUSED_1
,
318 .op
= midgard_alu_op_fmov
,
319 .reg_mode
= midgard_reg_mode_32
,
320 .dest_override
= midgard_dest_override_none
,
322 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
323 .src2
= vector_alu_srco_unsigned(mod
)
330 /* load/store instructions have both 32-bit and 16-bit variants, depending on
331 * whether we are using vectors composed of highp or mediump. At the moment, we
332 * don't support half-floats -- this requires changes in other parts of the
333 * compiler -- therefore the 16-bit versions are commented out. */
335 //M_LOAD(load_attr_16);
336 M_LOAD(load_attr_32
);
337 //M_LOAD(load_vary_16);
338 M_LOAD(load_vary_32
);
339 //M_LOAD(load_uniform_16);
340 M_LOAD(load_uniform_32
);
341 M_LOAD(load_color_buffer_8
);
342 //M_STORE(store_vary_16);
343 M_STORE(store_vary_32
);
344 M_STORE(store_cubemap_coords
);
346 static midgard_instruction
347 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
349 midgard_branch_cond branch
= {
357 memcpy(&compact
, &branch
, sizeof(branch
));
359 midgard_instruction ins
= {
361 .unit
= ALU_ENAB_BR_COMPACT
,
362 .prepacked_branch
= true,
363 .compact_branch
= true,
364 .br_compact
= compact
367 if (op
== midgard_jmp_writeout_op_writeout
)
373 static midgard_instruction
374 v_branch(bool conditional
, bool invert
)
376 midgard_instruction ins
= {
378 .unit
= ALU_ENAB_BRANCH
,
379 .compact_branch
= true,
381 .conditional
= conditional
,
382 .invert_conditional
= invert
389 static midgard_branch_extended
390 midgard_create_branch_extended( midgard_condition cond
,
391 midgard_jmp_writeout_op op
,
393 signed quadword_offset
)
395 /* For unclear reasons, the condition code is repeated 8 times */
396 uint16_t duplicated_cond
=
406 midgard_branch_extended branch
= {
408 .dest_tag
= dest_tag
,
409 .offset
= quadword_offset
,
410 .cond
= duplicated_cond
416 typedef struct midgard_bundle
{
417 /* Tag for the overall bundle */
420 /* Instructions contained by the bundle */
421 int instruction_count
;
422 midgard_instruction instructions
[5];
424 /* Bundle-wide ALU configuration */
427 bool has_embedded_constants
;
429 bool has_blend_constant
;
431 uint16_t register_words
[8];
432 int register_words_count
;
434 uint64_t body_words
[8];
436 int body_words_count
;
439 typedef struct compiler_context
{
441 gl_shader_stage stage
;
443 /* Is internally a blend shader? Depends on stage == FRAGMENT */
446 /* Tracking for blend constant patching */
447 int blend_constant_number
;
448 int blend_constant_offset
;
450 /* Current NIR function */
453 /* Unordered list of midgard_blocks */
455 struct list_head blocks
;
457 midgard_block
*initial_block
;
458 midgard_block
*previous_source_block
;
459 midgard_block
*final_block
;
461 /* List of midgard_instructions emitted for the current block */
462 midgard_block
*current_block
;
464 /* The current "depth" of the loop, for disambiguating breaks/continues
465 * when using nested loops */
466 int current_loop_depth
;
468 /* Constants which have been loaded, for later inlining */
469 struct hash_table_u64
*ssa_constants
;
471 /* SSA indices to be outputted to corresponding varying offset */
472 struct hash_table_u64
*ssa_varyings
;
474 /* SSA values / registers which have been aliased. Naively, these
475 * demand a fmov output; instead, we alias them in a later pass to
476 * avoid the wasted op.
478 * A note on encoding: to avoid dynamic memory management here, rather
479 * than ampping to a pointer, we map to the source index; the key
480 * itself is just the destination index. */
482 struct hash_table_u64
*ssa_to_alias
;
483 struct set
*leftover_ssa_to_alias
;
485 /* Actual SSA-to-register for RA */
486 struct hash_table_u64
*ssa_to_register
;
488 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
489 struct hash_table_u64
*hash_to_temp
;
493 /* Just the count of the max register used. Higher count => higher
494 * register pressure */
497 /* Used for cont/last hinting. Increase when a tex op is added.
498 * Decrease when a tex op is removed. */
499 int texture_op_count
;
501 /* Mapping of texture register -> SSA index for unaliasing */
502 int texture_index
[2];
504 /* If any path hits a discard instruction */
507 /* The number of uniforms allowable for the fast path */
510 /* Count of instructions emitted from NIR overall, across all blocks */
511 int instruction_count
;
513 /* Alpha ref value passed in */
516 /* The index corresponding to the fragment output */
517 unsigned fragment_output
;
519 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
520 unsigned sysvals
[MAX_SYSVAL_COUNT
];
521 unsigned sysval_count
;
522 struct hash_table_u64
*sysval_to_id
;
525 /* Append instruction to end of current block */
527 static midgard_instruction
*
528 mir_upload_ins(struct midgard_instruction ins
)
530 midgard_instruction
*heap
= malloc(sizeof(ins
));
531 memcpy(heap
, &ins
, sizeof(ins
));
536 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
538 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
542 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
544 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
548 mir_remove_instruction(struct midgard_instruction
*ins
)
550 list_del(&ins
->link
);
553 static midgard_instruction
*
554 mir_prev_op(struct midgard_instruction
*ins
)
556 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
559 static midgard_instruction
*
560 mir_next_op(struct midgard_instruction
*ins
)
562 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
565 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
566 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
568 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
569 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
570 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
571 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
572 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
573 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
574 #define mir_foreach_instr_in_block_from_rev(block, v, from) list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
577 static midgard_instruction
*
578 mir_last_in_block(struct midgard_block
*block
)
580 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
583 static midgard_block
*
584 mir_get_block(compiler_context
*ctx
, int idx
)
586 struct list_head
*lst
= &ctx
->blocks
;
591 return (struct midgard_block
*) lst
;
594 /* Pretty printer for internal Midgard IR */
597 print_mir_source(int source
)
599 if (source
>= SSA_FIXED_MINIMUM
) {
600 /* Specific register */
601 int reg
= SSA_REG_FROM_FIXED(source
);
603 /* TODO: Moving threshold */
604 if (reg
> 16 && reg
< 24)
605 printf("u%d", 23 - reg
);
609 printf("%d", source
);
614 print_mir_instruction(midgard_instruction
*ins
)
620 midgard_alu_op op
= ins
->alu
.op
;
621 const char *name
= alu_opcode_props
[op
].name
;
624 printf("%d.", ins
->unit
);
626 printf("%s", name
? name
: "??");
630 case TAG_LOAD_STORE_4
: {
631 midgard_load_store_op op
= ins
->load_store
.op
;
632 const char *name
= load_store_opcode_names
[op
];
639 case TAG_TEXTURE_4
: {
648 ssa_args
*args
= &ins
->ssa_args
;
650 printf(" %d, ", args
->dest
);
652 print_mir_source(args
->src0
);
655 if (args
->inline_constant
)
656 printf("#%d", ins
->inline_constant
);
658 print_mir_source(args
->src1
);
660 if (ins
->has_constants
)
661 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
667 print_mir_block(midgard_block
*block
)
671 mir_foreach_instr_in_block(block
, ins
) {
672 print_mir_instruction(ins
);
679 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
681 ins
->has_constants
= true;
682 memcpy(&ins
->constants
, constants
, 16);
684 /* If this is the special blend constant, mark this instruction */
686 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
687 ins
->has_blend_constant
= true;
691 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
693 return glsl_count_attribute_slots(type
, false);
696 /* Lower fdot2 to a vector multiplication followed by channel addition */
698 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
700 if (alu
->op
!= nir_op_fdot2
)
703 b
->cursor
= nir_before_instr(&alu
->instr
);
705 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
706 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
708 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
710 nir_ssa_def
*sum
= nir_fadd(b
,
711 nir_channel(b
, product
, 0),
712 nir_channel(b
, product
, 1));
714 /* Replace the fdot2 with this sum */
715 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
718 /* Lower csel with mixed condition channels to mulitple csel instructions. For
719 * context, the csel ops on Midgard are vector in *outputs*, but not in
720 * *conditions*. So, if the condition is e.g. yyyy, a single op can select a
721 * vec4. But if the condition is e.g. xyzw, four ops are needed as the ISA
722 * can't cope with the divergent channels.*/
725 midgard_nir_lower_mixed_csel_body(nir_builder
*b
, nir_alu_instr
*alu
)
727 if (alu
->op
!= nir_op_bcsel
)
730 b
->cursor
= nir_before_instr(&alu
->instr
);
732 /* Must be run before registering */
733 assert(alu
->dest
.dest
.is_ssa
);
735 /* Check for mixed condition */
737 unsigned comp
= alu
->src
[0].swizzle
[0];
738 unsigned nr_components
= alu
->dest
.dest
.ssa
.num_components
;
742 for (unsigned c
= 1; c
< nr_components
; ++c
)
743 mixed
|= (alu
->src
[0].swizzle
[c
] != comp
);
748 /* We're mixed, so lower */
750 assert(nr_components
<= 4);
751 nir_ssa_def
*results
[4];
753 nir_ssa_def
*cond
= nir_ssa_for_alu_src(b
, alu
, 0);
754 nir_ssa_def
*choice0
= nir_ssa_for_alu_src(b
, alu
, 1);
755 nir_ssa_def
*choice1
= nir_ssa_for_alu_src(b
, alu
, 2);
757 for (unsigned c
= 0; c
< nr_components
; ++c
) {
758 results
[c
] = nir_bcsel(b
,
759 nir_channel(b
, cond
, c
),
760 nir_channel(b
, choice0
, c
),
761 nir_channel(b
, choice1
, c
));
764 /* Replace with our scalarized version */
766 nir_ssa_def
*result
= nir_vec(b
, results
, nr_components
);
767 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(result
));
771 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
773 switch (instr
->intrinsic
) {
774 case nir_intrinsic_load_viewport_scale
:
775 return PAN_SYSVAL_VIEWPORT_SCALE
;
776 case nir_intrinsic_load_viewport_offset
:
777 return PAN_SYSVAL_VIEWPORT_OFFSET
;
784 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
788 if (instr
->type
== nir_instr_type_intrinsic
) {
789 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
790 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
796 /* We have a sysval load; check if it's already been assigned */
798 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
801 /* It hasn't -- so assign it now! */
803 unsigned id
= ctx
->sysval_count
++;
804 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
805 ctx
->sysvals
[id
] = sysval
;
809 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
811 ctx
->sysval_count
= 0;
813 nir_foreach_function(function
, shader
) {
814 if (!function
->impl
) continue;
816 nir_foreach_block(block
, function
->impl
) {
817 nir_foreach_instr_safe(instr
, block
) {
818 midgard_nir_assign_sysval_body(ctx
, instr
);
825 midgard_nir_lower_fdot2(nir_shader
*shader
)
827 bool progress
= false;
829 nir_foreach_function(function
, shader
) {
830 if (!function
->impl
) continue;
833 nir_builder
*b
= &_b
;
834 nir_builder_init(b
, function
->impl
);
836 nir_foreach_block(block
, function
->impl
) {
837 nir_foreach_instr_safe(instr
, block
) {
838 if (instr
->type
!= nir_instr_type_alu
) continue;
840 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
841 midgard_nir_lower_fdot2_body(b
, alu
);
847 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
855 midgard_nir_lower_mixed_csel(nir_shader
*shader
)
857 bool progress
= false;
859 nir_foreach_function(function
, shader
) {
860 if (!function
->impl
) continue;
863 nir_builder
*b
= &_b
;
864 nir_builder_init(b
, function
->impl
);
866 nir_foreach_block(block
, function
->impl
) {
867 nir_foreach_instr_safe(instr
, block
) {
868 if (instr
->type
!= nir_instr_type_alu
) continue;
870 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
871 midgard_nir_lower_mixed_csel_body(b
, alu
);
877 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
885 optimise_nir(nir_shader
*nir
)
888 unsigned lower_flrp
=
889 (nir
->options
->lower_flrp16
? 16 : 0) |
890 (nir
->options
->lower_flrp32
? 32 : 0) |
891 (nir
->options
->lower_flrp64
? 64 : 0);
893 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
894 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
895 NIR_PASS(progress
, nir
, midgard_nir_lower_mixed_csel
);
897 nir_lower_tex_options lower_tex_options
= {
901 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
906 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
907 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
909 NIR_PASS(progress
, nir
, nir_copy_prop
);
910 NIR_PASS(progress
, nir
, nir_opt_dce
);
911 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
912 NIR_PASS(progress
, nir
, nir_opt_cse
);
913 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
914 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
915 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
917 if (lower_flrp
!= 0) {
918 bool lower_flrp_progress
= false;
919 NIR_PASS(lower_flrp_progress
,
923 false /* always_precise */,
924 nir
->options
->lower_ffma
);
925 if (lower_flrp_progress
) {
926 NIR_PASS(progress
, nir
,
927 nir_opt_constant_folding
);
931 /* Nothing should rematerialize any flrps, so we only
932 * need to do this lowering once.
937 NIR_PASS(progress
, nir
, nir_opt_undef
);
938 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
941 nir_var_function_temp
);
943 /* TODO: Enable vectorize when merged upstream */
944 // NIR_PASS(progress, nir, nir_opt_vectorize);
947 /* Must be run at the end to prevent creation of fsin/fcos ops */
948 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
953 NIR_PASS(progress
, nir
, nir_opt_dce
);
954 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
955 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
956 NIR_PASS(progress
, nir
, nir_copy_prop
);
959 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
960 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
962 /* Lower mods for float ops only. Integer ops don't support modifiers
963 * (saturate doesn't make sense on integers, neg/abs require dedicated
966 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
967 NIR_PASS(progress
, nir
, nir_copy_prop
);
968 NIR_PASS(progress
, nir
, nir_opt_dce
);
970 /* We implement booleans as 32-bit 0/~0 */
971 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
973 /* Take us out of SSA */
974 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
975 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
977 /* We are a vector architecture; write combine where possible */
978 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
979 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
981 NIR_PASS(progress
, nir
, nir_opt_dce
);
984 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
985 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
986 * r0. See the comments in compiler_context */
989 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
991 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
992 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
995 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
998 unalias_ssa(compiler_context
*ctx
, int dest
)
1000 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
1001 /* TODO: Remove from leftover or no? */
1005 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
1007 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
1011 midgard_is_pinned(compiler_context
*ctx
, int index
)
1013 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
1016 /* Do not actually emit a load; instead, cache the constant for inlining */
1019 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
1021 nir_ssa_def def
= instr
->def
;
1023 float *v
= rzalloc_array(NULL
, float, 4);
1024 nir_const_load_to_arr(v
, instr
, f32
);
1025 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
1028 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
1029 * do the inverse) */
1032 expand_writemask(unsigned mask
)
1036 for (int i
= 0; i
< 4; ++i
)
1037 if (mask
& (1 << i
))
1038 o
|= (3 << (2 * i
));
1044 squeeze_writemask(unsigned mask
)
1048 for (int i
= 0; i
< 4; ++i
)
1049 if (mask
& (3 << (2 * i
)))
1056 /* Determines effective writemask, taking quirks and expansion into account */
1058 effective_writemask(midgard_vector_alu
*alu
)
1060 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
1063 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
].props
);
1065 /* If there is a fixed channel count, construct the appropriate mask */
1068 return (1 << channel_count
) - 1;
1070 /* Otherwise, just squeeze the existing mask */
1071 return squeeze_writemask(alu
->mask
);
1075 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
1077 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
1080 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
1085 /* If no temp is find, allocate one */
1086 temp
= ctx
->temp_count
++;
1087 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
1089 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
1095 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
1098 return src
->ssa
->index
;
1100 assert(!src
->reg
.indirect
);
1101 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
1106 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
1109 return dst
->ssa
.index
;
1111 assert(!dst
->reg
.indirect
);
1112 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
1117 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
1119 return nir_src_index(ctx
, &src
->src
);
1122 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
1123 * a conditional test) into that register */
1126 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
1128 int condition
= nir_src_index(ctx
, src
);
1130 /* Source to swizzle the desired component into w */
1132 const midgard_vector_alu_src alu_src
= {
1133 .swizzle
= SWIZZLE(component
, component
, component
, component
),
1136 /* There is no boolean move instruction. Instead, we simulate a move by
1137 * ANDing the condition with itself to get it into r31.w */
1139 midgard_instruction ins
= {
1141 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
1145 .dest
= SSA_FIXED_REGISTER(31),
1148 .op
= midgard_alu_op_iand
,
1149 .reg_mode
= midgard_reg_mode_32
,
1150 .dest_override
= midgard_dest_override_none
,
1151 .mask
= (0x3 << 6), /* w */
1152 .src1
= vector_alu_srco_unsigned(alu_src
),
1153 .src2
= vector_alu_srco_unsigned(alu_src
)
1157 emit_mir_instruction(ctx
, ins
);
1160 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1161 * pinning to eliminate this move in all known cases */
1164 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1166 int offset
= nir_src_index(ctx
, src
);
1168 midgard_instruction ins
= {
1171 .src0
= SSA_UNUSED_1
,
1173 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1176 .op
= midgard_alu_op_imov
,
1177 .reg_mode
= midgard_reg_mode_32
,
1178 .dest_override
= midgard_dest_override_none
,
1179 .mask
= (0x3 << 6), /* w */
1180 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1181 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1185 emit_mir_instruction(ctx
, ins
);
1188 #define ALU_CASE(nir, _op) \
1189 case nir_op_##nir: \
1190 op = midgard_alu_op_##_op; \
1194 nir_is_fzero_constant(nir_src src
)
1196 if (!nir_src_is_const(src
))
1199 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
1200 if (nir_src_comp_as_float(src
, c
) != 0.0)
1208 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1210 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1212 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1213 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1214 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1216 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1217 * supported. A few do not and are commented for now. Also, there are a
1218 * number of NIR ops which Midgard does not support and need to be
1219 * lowered, also TODO. This switch block emits the opcode and calling
1220 * convention of the Midgard instruction; actual packing is done in
1225 switch (instr
->op
) {
1226 ALU_CASE(fadd
, fadd
);
1227 ALU_CASE(fmul
, fmul
);
1228 ALU_CASE(fmin
, fmin
);
1229 ALU_CASE(fmax
, fmax
);
1230 ALU_CASE(imin
, imin
);
1231 ALU_CASE(imax
, imax
);
1232 ALU_CASE(umin
, umin
);
1233 ALU_CASE(umax
, umax
);
1234 ALU_CASE(fmov
, fmov
);
1235 ALU_CASE(ffloor
, ffloor
);
1236 ALU_CASE(fround_even
, froundeven
);
1237 ALU_CASE(ftrunc
, ftrunc
);
1238 ALU_CASE(fceil
, fceil
);
1239 ALU_CASE(fdot3
, fdot3
);
1240 ALU_CASE(fdot4
, fdot4
);
1241 ALU_CASE(iadd
, iadd
);
1242 ALU_CASE(isub
, isub
);
1243 ALU_CASE(imul
, imul
);
1244 ALU_CASE(iabs
, iabs
);
1245 ALU_CASE(imov
, imov
);
1247 ALU_CASE(feq32
, feq
);
1248 ALU_CASE(fne32
, fne
);
1249 ALU_CASE(flt32
, flt
);
1250 ALU_CASE(ieq32
, ieq
);
1251 ALU_CASE(ine32
, ine
);
1252 ALU_CASE(ilt32
, ilt
);
1253 ALU_CASE(ult32
, ult
);
1255 /* We don't have a native b2f32 instruction. Instead, like many
1256 * GPUs, we exploit booleans as 0/~0 for false/true, and
1257 * correspondingly AND
1258 * by 1.0 to do the type conversion. For the moment, prime us
1261 * iand [whatever], #0
1263 * At the end of emit_alu (as MIR), we'll fix-up the constant
1266 ALU_CASE(b2f32
, iand
);
1267 ALU_CASE(b2i32
, iand
);
1269 /* Likewise, we don't have a dedicated f2b32 instruction, but
1270 * we can do a "not equal to 0.0" test. */
1272 ALU_CASE(f2b32
, fne
);
1273 ALU_CASE(i2b32
, ine
);
1275 ALU_CASE(frcp
, frcp
);
1276 ALU_CASE(frsq
, frsqrt
);
1277 ALU_CASE(fsqrt
, fsqrt
);
1278 ALU_CASE(fexp2
, fexp2
);
1279 ALU_CASE(flog2
, flog2
);
1281 ALU_CASE(f2i32
, f2i
);
1282 ALU_CASE(f2u32
, f2u
);
1283 ALU_CASE(i2f32
, i2f
);
1284 ALU_CASE(u2f32
, u2f
);
1286 ALU_CASE(fsin
, fsin
);
1287 ALU_CASE(fcos
, fcos
);
1289 ALU_CASE(iand
, iand
);
1291 ALU_CASE(ixor
, ixor
);
1292 ALU_CASE(inot
, inand
);
1293 ALU_CASE(ishl
, ishl
);
1294 ALU_CASE(ishr
, iasr
);
1295 ALU_CASE(ushr
, ilsr
);
1297 ALU_CASE(b32all_fequal2
, fball_eq
);
1298 ALU_CASE(b32all_fequal3
, fball_eq
);
1299 ALU_CASE(b32all_fequal4
, fball_eq
);
1301 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1302 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1303 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1305 ALU_CASE(b32all_iequal2
, iball_eq
);
1306 ALU_CASE(b32all_iequal3
, iball_eq
);
1307 ALU_CASE(b32all_iequal4
, iball_eq
);
1309 ALU_CASE(b32any_inequal2
, ibany_neq
);
1310 ALU_CASE(b32any_inequal3
, ibany_neq
);
1311 ALU_CASE(b32any_inequal4
, ibany_neq
);
1313 /* For greater-or-equal, we lower to less-or-equal and flip the
1319 case nir_op_uge32
: {
1321 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1322 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1323 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1324 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1327 /* Swap via temporary */
1328 nir_alu_src temp
= instr
->src
[1];
1329 instr
->src
[1] = instr
->src
[0];
1330 instr
->src
[0] = temp
;
1335 /* For a few special csel cases not handled by NIR, we can opt to
1336 * bitwise. Otherwise, we emit the condition and do a real csel */
1338 case nir_op_b32csel
: {
1339 if (nir_is_fzero_constant(instr
->src
[2].src
)) {
1340 /* (b ? v : 0) = (b & v) */
1341 op
= midgard_alu_op_iand
;
1343 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1344 /* (b ? 0 : v) = (!b ? v : 0) = (~b & v) = (v & ~b) */
1345 op
= midgard_alu_op_iandnot
;
1347 instr
->src
[1] = instr
->src
[0];
1348 instr
->src
[0] = instr
->src
[2];
1350 /* Midgard features both fcsel and icsel, depending on
1351 * the type of the arguments/output. However, as long
1352 * as we're careful we can _always_ use icsel and
1353 * _never_ need fcsel, since the latter does additional
1354 * floating-point-specific processing whereas the
1355 * former just moves bits on the wire. It's not obvious
1356 * why these are separate opcodes, save for the ability
1357 * to do things like sat/pos/abs/neg for free */
1359 op
= midgard_alu_op_icsel
;
1361 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1364 /* Figure out which component the condition is in */
1366 unsigned comp
= instr
->src
[0].swizzle
[0];
1368 /* Make sure NIR isn't throwing a mixed condition at us */
1370 for (unsigned c
= 1; c
< nr_components
; ++c
)
1371 assert(instr
->src
[0].swizzle
[c
] == comp
);
1373 /* Emit the condition into r31.w */
1374 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1376 /* The condition is the first argument; move the other
1377 * arguments up one to be a binary instruction for
1380 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1386 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1391 /* Midgard can perform certain modifiers on output ofa n ALU op */
1392 midgard_outmod outmod
=
1393 instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1395 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1397 if (instr
->op
== nir_op_fmax
) {
1398 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1399 op
= midgard_alu_op_fmov
;
1401 outmod
= midgard_outmod_pos
;
1402 instr
->src
[0] = instr
->src
[1];
1403 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1404 op
= midgard_alu_op_fmov
;
1406 outmod
= midgard_outmod_pos
;
1410 /* Fetch unit, quirks, etc information */
1411 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1412 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1414 /* src0 will always exist afaik, but src1 will not for 1-argument
1415 * instructions. The latter can only be fetched if the instruction
1416 * needs it, or else we may segfault. */
1418 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1419 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1421 /* Rather than use the instruction generation helpers, we do it
1422 * ourselves here to avoid the mess */
1424 midgard_instruction ins
= {
1427 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1428 .src1
= quirk_flipped_r24
? src0
: src1
,
1433 nir_alu_src
*nirmods
[2] = { NULL
};
1435 if (nr_inputs
== 2) {
1436 nirmods
[0] = &instr
->src
[0];
1437 nirmods
[1] = &instr
->src
[1];
1438 } else if (nr_inputs
== 1) {
1439 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1444 bool is_int
= midgard_is_integer_op(op
);
1446 midgard_vector_alu alu
= {
1448 .reg_mode
= midgard_reg_mode_32
,
1449 .dest_override
= midgard_dest_override_none
,
1452 /* Writemask only valid for non-SSA NIR */
1453 .mask
= expand_writemask((1 << nr_components
) - 1),
1455 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
1456 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
1459 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1462 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1466 /* Late fixup for emulated instructions */
1468 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1469 /* Presently, our second argument is an inline #0 constant.
1470 * Switch over to an embedded 1.0 constant (that can't fit
1471 * inline, since we're 32-bit, not 16-bit like the inline
1474 ins
.ssa_args
.inline_constant
= false;
1475 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1476 ins
.has_constants
= true;
1478 if (instr
->op
== nir_op_b2f32
) {
1479 ins
.constants
[0] = 1.0f
;
1481 /* Type pun it into place */
1483 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1486 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1487 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1488 ins
.ssa_args
.inline_constant
= false;
1489 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1490 ins
.has_constants
= true;
1491 ins
.constants
[0] = 0.0f
;
1492 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1493 } else if (instr
->op
== nir_op_inot
) {
1494 /* ~b = ~(b & b), so duplicate the source */
1495 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1496 ins
.alu
.src2
= ins
.alu
.src1
;
1499 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1500 /* To avoid duplicating the lookup tables (probably), true LUT
1501 * instructions can only operate as if they were scalars. Lower
1502 * them here by changing the component. */
1504 uint8_t original_swizzle
[4];
1505 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1507 for (int i
= 0; i
< nr_components
; ++i
) {
1508 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1510 for (int j
= 0; j
< 4; ++j
)
1511 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1513 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
1514 emit_mir_instruction(ctx
, ins
);
1517 emit_mir_instruction(ctx
, ins
);
1524 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1526 /* TODO: half-floats */
1528 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1529 /* Fast path: For the first 16 uniforms, direct accesses are
1530 * 0-cycle, since they're just a register fetch in the usual
1531 * case. So, we alias the registers while we're still in
1534 int reg_slot
= 23 - offset
;
1535 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1537 /* Otherwise, read from the 'special' UBO to access
1538 * higher-indexed uniforms, at a performance cost. More
1539 * generally, we're emitting a UBO read instruction. */
1541 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1543 /* TODO: Don't split */
1544 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1545 ins
.load_store
.address
= offset
>> 3;
1547 if (indirect_offset
) {
1548 emit_indirect_offset(ctx
, indirect_offset
);
1549 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1551 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1554 emit_mir_instruction(ctx
, ins
);
1559 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1561 /* First, pull out the destination */
1562 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1564 /* Now, figure out which uniform this is */
1565 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1566 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1568 /* Sysvals are prefix uniforms */
1569 unsigned uniform
= ((uintptr_t) val
) - 1;
1571 /* Emit the read itself -- this is never indirect */
1572 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1576 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1578 unsigned offset
, reg
;
1580 switch (instr
->intrinsic
) {
1581 case nir_intrinsic_discard_if
:
1582 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1586 case nir_intrinsic_discard
: {
1587 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1588 struct midgard_instruction discard
= v_branch(conditional
, false);
1589 discard
.branch
.target_type
= TARGET_DISCARD
;
1590 emit_mir_instruction(ctx
, discard
);
1592 ctx
->can_discard
= true;
1596 case nir_intrinsic_load_uniform
:
1597 case nir_intrinsic_load_input
:
1598 offset
= nir_intrinsic_base(instr
);
1600 bool direct
= nir_src_is_const(instr
->src
[0]);
1603 offset
+= nir_src_as_uint(instr
->src
[0]);
1606 reg
= nir_dest_index(ctx
, &instr
->dest
);
1608 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1609 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1610 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1611 /* XXX: Half-floats? */
1612 /* TODO: swizzle, mask */
1614 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1616 midgard_varying_parameter p
= {
1618 .interpolation
= midgard_interp_default
,
1619 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1623 memcpy(&u
, &p
, sizeof(p
));
1624 ins
.load_store
.varying_parameters
= u
;
1627 /* We have the offset totally ready */
1628 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1630 /* We have it partially ready, but we need to
1631 * add in the dynamic index, moved to r27.w */
1632 emit_indirect_offset(ctx
, &instr
->src
[0]);
1633 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1636 emit_mir_instruction(ctx
, ins
);
1637 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1638 /* Constant encoded as a pinned constant */
1640 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1641 ins
.has_constants
= true;
1642 ins
.has_blend_constant
= true;
1643 emit_mir_instruction(ctx
, ins
);
1644 } else if (ctx
->is_blend
) {
1645 /* For blend shaders, a load might be
1646 * translated various ways depending on what
1647 * we're loading. Figure out how this is used */
1649 nir_variable
*out
= NULL
;
1651 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1652 int drvloc
= var
->data
.driver_location
;
1654 if (nir_intrinsic_base(instr
) == drvloc
) {
1662 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1663 /* Source color preloaded to r0 */
1665 midgard_pin_output(ctx
, reg
, 0);
1666 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1667 /* Destination color must be read from framebuffer */
1669 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1670 ins
.load_store
.swizzle
= 0; /* xxxx */
1672 /* Read each component sequentially */
1674 for (int c
= 0; c
< 4; ++c
) {
1675 ins
.load_store
.mask
= (1 << c
);
1676 ins
.load_store
.unknown
= c
;
1677 emit_mir_instruction(ctx
, ins
);
1680 /* vadd.u2f hr2, zext(hr2), #0 */
1682 midgard_vector_alu_src alu_src
= blank_alu_src
;
1683 alu_src
.mod
= midgard_int_zero_extend
;
1684 alu_src
.half
= true;
1686 midgard_instruction u2f
= {
1690 .src1
= SSA_UNUSED_0
,
1692 .inline_constant
= true
1695 .op
= midgard_alu_op_u2f
,
1696 .reg_mode
= midgard_reg_mode_16
,
1697 .dest_override
= midgard_dest_override_none
,
1699 .src1
= vector_alu_srco_unsigned(alu_src
),
1700 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1704 emit_mir_instruction(ctx
, u2f
);
1706 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1710 midgard_instruction fmul
= {
1712 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1716 .src1
= SSA_UNUSED_0
,
1717 .inline_constant
= true
1720 .op
= midgard_alu_op_fmul
,
1721 .reg_mode
= midgard_reg_mode_32
,
1722 .dest_override
= midgard_dest_override_none
,
1723 .outmod
= midgard_outmod_sat
,
1725 .src1
= vector_alu_srco_unsigned(alu_src
),
1726 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1730 emit_mir_instruction(ctx
, fmul
);
1732 DBG("Unknown input in blend shader\n");
1735 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1736 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1737 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1738 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1739 emit_mir_instruction(ctx
, ins
);
1741 DBG("Unknown load\n");
1747 case nir_intrinsic_store_output
:
1748 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1750 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1752 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1754 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1755 /* gl_FragColor is not emitted with load/store
1756 * instructions. Instead, it gets plonked into
1757 * r0 at the end of the shader and we do the
1758 * framebuffer writeout dance. TODO: Defer
1761 midgard_pin_output(ctx
, reg
, 0);
1763 /* Save the index we're writing to for later reference
1764 * in the epilogue */
1766 ctx
->fragment_output
= reg
;
1767 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1768 /* Varyings are written into one of two special
1769 * varying register, r26 or r27. The register itself is selected as the register
1770 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1772 * Normally emitting fmov's is frowned upon,
1773 * but due to unique constraints of
1774 * REGISTER_VARYING, fmov emission + a
1775 * dedicated cleanup pass is the only way to
1776 * guarantee correctness when considering some
1777 * (common) edge cases XXX: FIXME */
1779 /* If this varying corresponds to a constant (why?!),
1780 * emit that now since it won't get picked up by
1781 * hoisting (since there is no corresponding move
1782 * emitted otherwise) */
1784 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1786 if (constant_value
) {
1787 /* Special case: emit the varying write
1788 * directly to r26 (looks funny in asm but it's
1789 * fine) and emit the store _now_. Possibly
1790 * slightly slower, but this is a really stupid
1791 * special case anyway (why on earth would you
1792 * have a constant varying? Your own fault for
1793 * slightly worse perf :P) */
1795 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1796 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1797 emit_mir_instruction(ctx
, ins
);
1799 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1800 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1801 emit_mir_instruction(ctx
, st
);
1803 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1805 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1808 DBG("Unknown store\n");
1814 case nir_intrinsic_load_alpha_ref_float
:
1815 assert(instr
->dest
.is_ssa
);
1817 float ref_value
= ctx
->alpha_ref
;
1819 float *v
= ralloc_array(NULL
, float, 4);
1820 memcpy(v
, &ref_value
, sizeof(float));
1821 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1824 case nir_intrinsic_load_viewport_scale
:
1825 case nir_intrinsic_load_viewport_offset
:
1826 emit_sysval_read(ctx
, instr
);
1830 printf ("Unhandled intrinsic\n");
1837 midgard_tex_format(enum glsl_sampler_dim dim
)
1840 case GLSL_SAMPLER_DIM_2D
:
1841 case GLSL_SAMPLER_DIM_EXTERNAL
:
1844 case GLSL_SAMPLER_DIM_3D
:
1847 case GLSL_SAMPLER_DIM_CUBE
:
1848 return TEXTURE_CUBE
;
1851 DBG("Unknown sampler dim type\n");
1858 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1861 //assert (!instr->sampler);
1862 //assert (!instr->texture_array_size);
1863 assert (instr
->op
== nir_texop_tex
);
1865 /* Allocate registers via a round robin scheme to alternate between the two registers */
1866 int reg
= ctx
->texture_op_count
& 1;
1867 int in_reg
= reg
, out_reg
= reg
;
1869 /* Make room for the reg */
1871 if (ctx
->texture_index
[reg
] > -1)
1872 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1874 int texture_index
= instr
->texture_index
;
1875 int sampler_index
= texture_index
;
1877 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1878 switch (instr
->src
[i
].src_type
) {
1879 case nir_tex_src_coord
: {
1880 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1882 midgard_vector_alu_src alu_src
= blank_alu_src
;
1884 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1886 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1887 /* For cubemaps, we need to load coords into
1888 * special r27, and then use a special ld/st op
1889 * to copy into the texture register */
1891 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1893 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1894 emit_mir_instruction(ctx
, move
);
1896 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1897 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1898 st
.load_store
.mask
= 0x3; /* xy? */
1899 st
.load_store
.swizzle
= alu_src
.swizzle
;
1900 emit_mir_instruction(ctx
, st
);
1903 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1905 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1906 emit_mir_instruction(ctx
, ins
);
1913 DBG("Unknown source type\n");
1920 /* No helper to build texture words -- we do it all here */
1921 midgard_instruction ins
= {
1922 .type
= TAG_TEXTURE_4
,
1924 .op
= TEXTURE_OP_NORMAL
,
1925 .format
= midgard_tex_format(instr
->sampler_dim
),
1926 .texture_handle
= texture_index
,
1927 .sampler_handle
= sampler_index
,
1929 /* TODO: Don't force xyzw */
1930 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1942 /* Assume we can continue; hint it out later */
1947 /* Set registers to read and write from the same place */
1948 ins
.texture
.in_reg_select
= in_reg
;
1949 ins
.texture
.out_reg_select
= out_reg
;
1951 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1952 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1953 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1954 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1955 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1957 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1958 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1959 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1962 emit_mir_instruction(ctx
, ins
);
1964 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1966 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1967 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1968 ctx
->texture_index
[reg
] = o_index
;
1970 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1971 emit_mir_instruction(ctx
, ins2
);
1973 /* Used for .cont and .last hinting */
1974 ctx
->texture_op_count
++;
1978 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1980 switch (instr
->type
) {
1981 case nir_jump_break
: {
1982 /* Emit a branch out of the loop */
1983 struct midgard_instruction br
= v_branch(false, false);
1984 br
.branch
.target_type
= TARGET_BREAK
;
1985 br
.branch
.target_break
= ctx
->current_loop_depth
;
1986 emit_mir_instruction(ctx
, br
);
1993 DBG("Unknown jump type %d\n", instr
->type
);
1999 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
2001 switch (instr
->type
) {
2002 case nir_instr_type_load_const
:
2003 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2006 case nir_instr_type_intrinsic
:
2007 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2010 case nir_instr_type_alu
:
2011 emit_alu(ctx
, nir_instr_as_alu(instr
));
2014 case nir_instr_type_tex
:
2015 emit_tex(ctx
, nir_instr_as_tex(instr
));
2018 case nir_instr_type_jump
:
2019 emit_jump(ctx
, nir_instr_as_jump(instr
));
2022 case nir_instr_type_ssa_undef
:
2027 DBG("Unhandled instruction type\n");
2032 /* Determine the actual hardware from the index based on the RA results or special values */
2035 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
2037 if (reg
>= SSA_FIXED_MINIMUM
)
2038 return SSA_REG_FROM_FIXED(reg
);
2041 assert(reg
< maxreg
);
2043 int r
= ra_get_node_reg(g
, reg
);
2044 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
2049 /* fmov style unused */
2051 return REGISTER_UNUSED
;
2053 /* lut style unused */
2055 return REGISTER_UNUSED
;
2058 DBG("Unknown SSA register alias %d\n", reg
);
2065 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
2067 /* Choose the first available register to minimise reported register pressure */
2069 for (int i
= 0; i
< 16; ++i
) {
2070 if (BITSET_TEST(regs
, i
)) {
2080 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
2082 if (ins
->ssa_args
.src0
== src
) return true;
2083 if (ins
->ssa_args
.src1
== src
) return true;
2088 /* Determine if a variable is live in the successors of a block */
2090 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
2092 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
2093 midgard_block
*succ
= bl
->successors
[i
];
2095 /* If we already visited, the value we're seeking
2096 * isn't down this path (or we would have short
2099 if (succ
->visited
) continue;
2101 /* Otherwise (it's visited *now*), check the block */
2103 succ
->visited
= true;
2105 mir_foreach_instr_in_block(succ
, ins
) {
2106 if (midgard_is_live_in_instr(ins
, src
))
2110 /* ...and also, check *its* successors */
2111 if (is_live_after_successors(ctx
, succ
, src
))
2116 /* Welp. We're really not live. */
2122 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
2124 /* Check the rest of the block for liveness */
2126 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
2127 if (midgard_is_live_in_instr(ins
, src
))
2131 /* Check the rest of the blocks for liveness recursively */
2133 bool succ
= is_live_after_successors(ctx
, block
, src
);
2135 mir_foreach_block(ctx
, block
) {
2136 block
->visited
= false;
2142 /* Once registers have been decided via register allocation
2143 * (allocate_registers), we need to rewrite the MIR to use registers instead of
2147 install_registers(compiler_context
*ctx
, struct ra_graph
*g
)
2149 mir_foreach_block(ctx
, block
) {
2150 mir_foreach_instr_in_block(block
, ins
) {
2151 if (ins
->compact_branch
) continue;
2153 ssa_args args
= ins
->ssa_args
;
2155 switch (ins
->type
) {
2157 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, ctx
->temp_count
);
2159 ins
->registers
.src2_imm
= args
.inline_constant
;
2161 if (args
.inline_constant
) {
2162 /* Encode inline 16-bit constant as a vector by default */
2164 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2166 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2168 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2169 ins
->alu
.src2
= imm
<< 2;
2171 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, ctx
->temp_count
);
2174 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, ctx
->temp_count
);
2178 case TAG_LOAD_STORE_4
: {
2179 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2180 /* TODO: use ssa_args for store_vary */
2181 ins
->load_store
.reg
= 0;
2183 bool has_dest
= args
.dest
>= 0;
2184 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2186 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, ctx
->temp_count
);
2200 /* This routine performs the actual register allocation. It should be succeeded
2201 * by install_registers */
2203 static struct ra_graph
*
2204 allocate_registers(compiler_context
*ctx
)
2206 /* First, initialize the RA */
2207 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
2209 /* Create a primary (general purpose) class, as well as special purpose
2210 * pipeline register classes */
2212 int primary_class
= ra_alloc_reg_class(regs
);
2213 int varying_class
= ra_alloc_reg_class(regs
);
2215 /* Add the full set of work registers */
2216 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
2217 for (int i
= 0; i
< work_count
; ++i
)
2218 ra_class_add_reg(regs
, primary_class
, i
);
2220 /* Add special registers */
2221 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
2222 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
2224 /* We're done setting up */
2225 ra_set_finalize(regs
, NULL
);
2227 /* Transform the MIR into squeezed index form */
2228 mir_foreach_block(ctx
, block
) {
2229 mir_foreach_instr_in_block(block
, ins
) {
2230 if (ins
->compact_branch
) continue;
2232 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
2233 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
2234 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
2236 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2237 print_mir_block(block
);
2240 /* No register allocation to do with no SSA */
2242 if (!ctx
->temp_count
)
2245 /* Let's actually do register allocation */
2246 int nodes
= ctx
->temp_count
;
2247 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
2249 /* Set everything to the work register class, unless it has somewhere
2252 mir_foreach_block(ctx
, block
) {
2253 mir_foreach_instr_in_block(block
, ins
) {
2254 if (ins
->compact_branch
) continue;
2256 if (ins
->ssa_args
.dest
< 0) continue;
2258 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2260 int class = primary_class
;
2262 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2266 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2267 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2270 unsigned reg
= temp
- 1;
2271 int t
= find_or_allocate_temp(ctx
, index
);
2272 ra_set_node_reg(g
, t
, reg
);
2276 /* Determine liveness */
2278 int *live_start
= malloc(nodes
* sizeof(int));
2279 int *live_end
= malloc(nodes
* sizeof(int));
2281 /* Initialize as non-existent */
2283 for (int i
= 0; i
< nodes
; ++i
) {
2284 live_start
[i
] = live_end
[i
] = -1;
2289 mir_foreach_block(ctx
, block
) {
2290 mir_foreach_instr_in_block(block
, ins
) {
2291 if (ins
->compact_branch
) continue;
2293 /* Dest is < 0 for store_vary instructions, which break
2294 * the usual SSA conventions. Liveness analysis doesn't
2295 * make sense on these instructions, so skip them to
2296 * avoid memory corruption */
2298 if (ins
->ssa_args
.dest
< 0) continue;
2300 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2301 /* If this destination is not yet live, it is now since we just wrote it */
2303 int dest
= ins
->ssa_args
.dest
;
2305 if (live_start
[dest
] == -1)
2306 live_start
[dest
] = d
;
2309 /* Since we just used a source, the source might be
2310 * dead now. Scan the rest of the block for
2311 * invocations, and if there are none, the source dies
2314 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2316 for (int src
= 0; src
< 2; ++src
) {
2317 int s
= sources
[src
];
2319 if (s
< 0) continue;
2321 if (s
>= SSA_FIXED_MINIMUM
) continue;
2323 if (!is_live_after(ctx
, block
, ins
, s
)) {
2332 /* If a node still hasn't been killed, kill it now */
2334 for (int i
= 0; i
< nodes
; ++i
) {
2335 /* live_start == -1 most likely indicates a pinned output */
2337 if (live_end
[i
] == -1)
2341 /* Setup interference between nodes that are live at the same time */
2343 for (int i
= 0; i
< nodes
; ++i
) {
2344 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2345 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2346 ra_add_node_interference(g
, i
, j
);
2350 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2352 if (!ra_allocate(g
)) {
2353 DBG("Error allocating registers\n");
2364 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2365 * use scalar ALU instructions, for functional or performance reasons. To do
2366 * this, we just demote vector ALU payloads to scalar. */
2369 component_from_mask(unsigned mask
)
2371 for (int c
= 0; c
< 4; ++c
) {
2372 if (mask
& (3 << (2 * c
)))
2381 is_single_component_mask(unsigned mask
)
2385 for (int c
= 0; c
< 4; ++c
)
2386 if (mask
& (3 << (2 * c
)))
2389 return components
== 1;
2392 /* Create a mask of accessed components from a swizzle to figure out vector
2396 swizzle_to_access_mask(unsigned swizzle
)
2398 unsigned component_mask
= 0;
2400 for (int i
= 0; i
< 4; ++i
) {
2401 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2402 component_mask
|= (1 << c
);
2405 return component_mask
;
2409 vector_to_scalar_source(unsigned u
, bool is_int
)
2411 midgard_vector_alu_src v
;
2412 memcpy(&v
, &u
, sizeof(v
));
2414 /* TODO: Integers */
2416 midgard_scalar_alu_src s
= {
2418 .component
= (v
.swizzle
& 3) << 1
2424 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
2425 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
2429 memcpy(&o
, &s
, sizeof(s
));
2431 return o
& ((1 << 6) - 1);
2434 static midgard_scalar_alu
2435 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2437 bool is_int
= midgard_is_integer_op(v
.op
);
2439 /* The output component is from the mask */
2440 midgard_scalar_alu s
= {
2442 .src1
= vector_to_scalar_source(v
.src1
, is_int
),
2443 .src2
= vector_to_scalar_source(v
.src2
, is_int
),
2446 .output_full
= 1, /* TODO: Half */
2447 .output_component
= component_from_mask(v
.mask
) << 1,
2450 /* Inline constant is passed along rather than trying to extract it
2453 if (ins
->ssa_args
.inline_constant
) {
2455 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2456 imm
|= (lower_11
>> 9) & 3;
2457 imm
|= (lower_11
>> 6) & 4;
2458 imm
|= (lower_11
>> 2) & 0x38;
2459 imm
|= (lower_11
& 63) << 6;
2467 /* Midgard prefetches instruction types, so during emission we need to
2468 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2469 * if this is the second to last and the last is an ALU, then it's also 1... */
2471 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2472 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2474 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2475 bytes_emitted += sizeof(type)
2478 emit_binary_vector_instruction(midgard_instruction
*ains
,
2479 uint16_t *register_words
, int *register_words_count
,
2480 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2481 size_t *bytes_emitted
)
2483 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2484 *bytes_emitted
+= sizeof(midgard_reg_info
);
2486 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2487 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2488 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2491 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2492 * mind that we are a vector architecture and we can write to different
2493 * components simultaneously */
2496 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2498 /* Each instruction reads some registers and writes to a register. See
2499 * where the first writes */
2501 /* Figure out where exactly we wrote to */
2502 int source
= first
->ssa_args
.dest
;
2503 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2505 /* As long as the second doesn't read from the first, we're okay */
2506 if (second
->ssa_args
.src0
== source
) {
2507 if (first
->type
== TAG_ALU_4
) {
2508 /* Figure out which components we just read from */
2510 int q
= second
->alu
.src1
;
2511 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2513 /* Check if there are components in common, and fail if so */
2514 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2521 if (second
->ssa_args
.src1
== source
)
2524 /* Otherwise, it's safe in that regard. Another data hazard is both
2525 * writing to the same place, of course */
2527 if (second
->ssa_args
.dest
== source
) {
2528 /* ...but only if the components overlap */
2529 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2531 if (dest_mask
& source_mask
)
2541 midgard_instruction
**segment
, unsigned segment_size
,
2542 midgard_instruction
*ains
)
2544 for (int s
= 0; s
< segment_size
; ++s
)
2545 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2553 /* Schedules, but does not emit, a single basic block. After scheduling, the
2554 * final tag and size of the block are known, which are necessary for branching
2557 static midgard_bundle
2558 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2560 int instructions_emitted
= 0, instructions_consumed
= -1;
2561 midgard_bundle bundle
= { 0 };
2563 uint8_t tag
= ins
->type
;
2565 /* Default to the instruction's tag */
2568 switch (ins
->type
) {
2570 uint32_t control
= 0;
2571 size_t bytes_emitted
= sizeof(control
);
2573 /* TODO: Constant combining */
2574 int index
= 0, last_unit
= 0;
2576 /* Previous instructions, for the purpose of parallelism */
2577 midgard_instruction
*segment
[4] = {0};
2578 int segment_size
= 0;
2580 instructions_emitted
= -1;
2581 midgard_instruction
*pins
= ins
;
2584 midgard_instruction
*ains
= pins
;
2586 /* Advance instruction pointer */
2588 ains
= mir_next_op(pins
);
2592 /* Out-of-work condition */
2593 if ((struct list_head
*) ains
== &block
->instructions
)
2596 /* Ensure that the chain can continue */
2597 if (ains
->type
!= TAG_ALU_4
) break;
2599 /* According to the presentation "The ARM
2600 * Mali-T880 Mobile GPU" from HotChips 27,
2601 * there are two pipeline stages. Branching
2602 * position determined experimentally. Lines
2603 * are executed in parallel:
2606 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2608 * Verify that there are no ordering dependencies here.
2610 * TODO: Allow for parallelism!!!
2613 /* Pick a unit for it if it doesn't force a particular unit */
2615 int unit
= ains
->unit
;
2618 int op
= ains
->alu
.op
;
2619 int units
= alu_opcode_props
[op
].props
;
2621 /* TODO: Promotion of scalars to vectors */
2622 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2625 assert(units
& UNITS_SCALAR
);
2628 if (last_unit
>= UNIT_VADD
) {
2629 if (units
& UNIT_VLUT
)
2634 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2636 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2638 else if (units
& UNIT_VLUT
)
2644 if (last_unit
>= UNIT_VADD
) {
2645 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2647 else if (units
& UNIT_VLUT
)
2652 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2654 else if (units
& UNIT_SMUL
)
2655 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2656 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2663 assert(unit
& units
);
2666 /* Late unit check, this time for encoding (not parallelism) */
2667 if (unit
<= last_unit
) break;
2669 /* Clear the segment */
2670 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2673 if (midgard_has_hazard(segment
, segment_size
, ains
))
2676 /* We're good to go -- emit the instruction */
2679 segment
[segment_size
++] = ains
;
2681 /* Only one set of embedded constants per
2682 * bundle possible; if we have more, we must
2683 * break the chain early, unfortunately */
2685 if (ains
->has_constants
) {
2686 if (bundle
.has_embedded_constants
) {
2687 /* ...but if there are already
2688 * constants but these are the
2689 * *same* constants, we let it
2692 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2695 bundle
.has_embedded_constants
= true;
2696 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2698 /* If this is a blend shader special constant, track it for patching */
2699 if (ains
->has_blend_constant
)
2700 bundle
.has_blend_constant
= true;
2704 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2705 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2706 &bundle
.register_words_count
, bundle
.body_words
,
2707 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2708 } else if (ains
->compact_branch
) {
2709 /* All of r0 has to be written out
2710 * along with the branch writeout.
2713 if (ains
->writeout
) {
2715 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2716 ins
.unit
= UNIT_VMUL
;
2718 control
|= ins
.unit
;
2720 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2721 &bundle
.register_words_count
, bundle
.body_words
,
2722 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2724 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2725 bool written_late
= false;
2726 bool components
[4] = { 0 };
2727 uint16_t register_dep_mask
= 0;
2728 uint16_t written_mask
= 0;
2730 midgard_instruction
*qins
= ins
;
2731 for (int t
= 0; t
< index
; ++t
) {
2732 if (qins
->registers
.out_reg
!= 0) {
2733 /* Mark down writes */
2735 written_mask
|= (1 << qins
->registers
.out_reg
);
2737 /* Mark down the register dependencies for errata check */
2739 if (qins
->registers
.src1_reg
< 16)
2740 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2742 if (qins
->registers
.src2_reg
< 16)
2743 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2745 int mask
= qins
->alu
.mask
;
2747 for (int c
= 0; c
< 4; ++c
)
2748 if (mask
& (0x3 << (2 * c
)))
2749 components
[c
] = true;
2751 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2753 if (qins
->unit
== UNIT_VLUT
)
2754 written_late
= true;
2757 /* Advance instruction pointer */
2758 qins
= mir_next_op(qins
);
2762 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2763 if (register_dep_mask
& written_mask
) {
2764 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2771 /* If even a single component is not written, break it up (conservative check). */
2772 bool breakup
= false;
2774 for (int c
= 0; c
< 4; ++c
)
2781 /* Otherwise, we're free to proceed */
2785 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2786 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2787 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2788 bytes_emitted
+= sizeof(midgard_branch_extended
);
2790 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2791 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2792 bytes_emitted
+= sizeof(ains
->br_compact
);
2795 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2796 bytes_emitted
+= sizeof(midgard_reg_info
);
2798 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2799 bundle
.body_words_count
++;
2800 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2803 /* Defer marking until after writing to allow for break */
2804 control
|= ains
->unit
;
2805 last_unit
= ains
->unit
;
2806 ++instructions_emitted
;
2810 /* Bubble up the number of instructions for skipping */
2811 instructions_consumed
= index
- 1;
2815 /* Pad ALU op to nearest word */
2817 if (bytes_emitted
& 15) {
2818 padding
= 16 - (bytes_emitted
& 15);
2819 bytes_emitted
+= padding
;
2822 /* Constants must always be quadwords */
2823 if (bundle
.has_embedded_constants
)
2824 bytes_emitted
+= 16;
2826 /* Size ALU instruction for tag */
2827 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2828 bundle
.padding
= padding
;
2829 bundle
.control
= bundle
.tag
| control
;
2834 case TAG_LOAD_STORE_4
: {
2835 /* Load store instructions have two words at once. If
2836 * we only have one queued up, we need to NOP pad.
2837 * Otherwise, we store both in succession to save space
2838 * and cycles -- letting them go in parallel -- skip
2839 * the next. The usefulness of this optimisation is
2840 * greatly dependent on the quality of the instruction
2844 midgard_instruction
*next_op
= mir_next_op(ins
);
2846 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2847 /* As the two operate concurrently, make sure
2848 * they are not dependent */
2850 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2851 /* Skip ahead, since it's redundant with the pair */
2852 instructions_consumed
= 1 + (instructions_emitted
++);
2860 /* Texture ops default to single-op-per-bundle scheduling */
2864 /* Copy the instructions into the bundle */
2865 bundle
.instruction_count
= instructions_emitted
+ 1;
2869 midgard_instruction
*uins
= ins
;
2870 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2871 bundle
.instructions
[used_idx
++] = *uins
;
2872 uins
= mir_next_op(uins
);
2875 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2881 quadword_size(int tag
)
2896 case TAG_LOAD_STORE_4
:
2908 /* Schedule a single block by iterating its instruction to create bundles.
2909 * While we go, tally about the bundle sizes to compute the block size. */
2912 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2914 util_dynarray_init(&block
->bundles
, NULL
);
2916 block
->quadword_count
= 0;
2918 mir_foreach_instr_in_block(block
, ins
) {
2920 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2921 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2923 if (bundle
.has_blend_constant
) {
2924 /* TODO: Multiblock? */
2925 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2926 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2930 ins
= mir_next_op(ins
);
2932 block
->quadword_count
+= quadword_size(bundle
.tag
);
2935 block
->is_scheduled
= true;
2939 schedule_program(compiler_context
*ctx
)
2941 /* We run RA prior to scheduling */
2942 struct ra_graph
*g
= allocate_registers(ctx
);
2943 install_registers(ctx
, g
);
2945 mir_foreach_block(ctx
, block
) {
2946 schedule_block(ctx
, block
);
2950 /* After everything is scheduled, emit whole bundles at a time */
2953 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2955 int lookahead
= next_tag
<< 4;
2957 switch (bundle
->tag
) {
2962 /* Actually emit each component */
2963 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2965 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2966 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2968 /* Emit body words based on the instructions bundled */
2969 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2970 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2972 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2973 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2974 } else if (ins
->compact_branch
) {
2975 /* Dummy move, XXX DRY */
2976 if ((i
== 0) && ins
->writeout
) {
2977 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2978 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2981 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2982 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2984 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2988 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2989 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2993 /* Emit padding (all zero) */
2994 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2996 /* Tack on constants */
2998 if (bundle
->has_embedded_constants
) {
2999 util_dynarray_append(emission
, float, bundle
->constants
[0]);
3000 util_dynarray_append(emission
, float, bundle
->constants
[1]);
3001 util_dynarray_append(emission
, float, bundle
->constants
[2]);
3002 util_dynarray_append(emission
, float, bundle
->constants
[3]);
3008 case TAG_LOAD_STORE_4
: {
3009 /* One or two composing instructions */
3011 uint64_t current64
, next64
= LDST_NOP
;
3013 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
3015 if (bundle
->instruction_count
== 2)
3016 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
3018 midgard_load_store instruction
= {
3019 .type
= bundle
->tag
,
3020 .next_type
= next_tag
,
3025 util_dynarray_append(emission
, midgard_load_store
, instruction
);
3030 case TAG_TEXTURE_4
: {
3031 /* Texture instructions are easy, since there is no
3032 * pipelining nor VLIW to worry about. We may need to set the .last flag */
3034 midgard_instruction
*ins
= &bundle
->instructions
[0];
3036 ins
->texture
.type
= TAG_TEXTURE_4
;
3037 ins
->texture
.next_type
= next_tag
;
3039 ctx
->texture_op_count
--;
3041 if (!ctx
->texture_op_count
) {
3042 ins
->texture
.cont
= 0;
3043 ins
->texture
.last
= 1;
3046 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
3051 DBG("Unknown midgard instruction type\n");
3058 /* ALU instructions can inline or embed constants, which decreases register
3059 * pressure and saves space. */
3061 #define CONDITIONAL_ATTACH(src) { \
3062 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
3065 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
3066 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
3071 inline_alu_constants(compiler_context
*ctx
)
3073 mir_foreach_instr(ctx
, alu
) {
3074 /* Other instructions cannot inline constants */
3075 if (alu
->type
!= TAG_ALU_4
) continue;
3077 /* If there is already a constant here, we can do nothing */
3078 if (alu
->has_constants
) continue;
3080 /* It makes no sense to inline constants on a branch */
3081 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
3083 CONDITIONAL_ATTACH(src0
);
3085 if (!alu
->has_constants
) {
3086 CONDITIONAL_ATTACH(src1
)
3087 } else if (!alu
->inline_constant
) {
3088 /* Corner case: _two_ vec4 constants, for instance with a
3089 * csel. For this case, we can only use a constant
3090 * register for one, we'll have to emit a move for the
3091 * other. Note, if both arguments are constants, then
3092 * necessarily neither argument depends on the value of
3093 * any particular register. As the destination register
3094 * will be wiped, that means we can spill the constant
3095 * to the destination register.
3098 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
3099 unsigned scratch
= alu
->ssa_args
.dest
;
3102 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
3103 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
3105 /* Force a break XXX Defer r31 writes */
3106 ins
.unit
= UNIT_VLUT
;
3108 /* Set the source */
3109 alu
->ssa_args
.src1
= scratch
;
3111 /* Inject us -before- the last instruction which set r31 */
3112 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
3118 /* Midgard supports two types of constants, embedded constants (128-bit) and
3119 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
3120 * constants can be demoted to inline constants, for space savings and
3121 * sometimes a performance boost */
3124 embedded_to_inline_constant(compiler_context
*ctx
)
3126 mir_foreach_instr(ctx
, ins
) {
3127 if (!ins
->has_constants
) continue;
3129 if (ins
->ssa_args
.inline_constant
) continue;
3131 /* Blend constants must not be inlined by definition */
3132 if (ins
->has_blend_constant
) continue;
3134 /* src1 cannot be an inline constant due to encoding
3135 * restrictions. So, if possible we try to flip the arguments
3138 int op
= ins
->alu
.op
;
3140 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3142 /* These ops require an operational change to flip
3143 * their arguments TODO */
3144 case midgard_alu_op_flt
:
3145 case midgard_alu_op_fle
:
3146 case midgard_alu_op_ilt
:
3147 case midgard_alu_op_ile
:
3148 case midgard_alu_op_fcsel
:
3149 case midgard_alu_op_icsel
:
3150 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
3155 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
3156 /* Flip the SSA numbers */
3157 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
3158 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
3160 /* And flip the modifiers */
3164 src_temp
= ins
->alu
.src2
;
3165 ins
->alu
.src2
= ins
->alu
.src1
;
3166 ins
->alu
.src1
= src_temp
;
3170 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3171 /* Extract the source information */
3173 midgard_vector_alu_src
*src
;
3174 int q
= ins
->alu
.src2
;
3175 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
3178 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
3179 int component
= src
->swizzle
& 3;
3181 /* Scale constant appropriately, if we can legally */
3182 uint16_t scaled_constant
= 0;
3184 /* XXX: Check legality */
3185 if (midgard_is_integer_op(op
)) {
3186 /* TODO: Inline integer */
3189 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
3190 scaled_constant
= (uint16_t) iconstants
[component
];
3192 /* Constant overflow after resize */
3193 if (scaled_constant
!= iconstants
[component
])
3196 float original
= (float) ins
->constants
[component
];
3197 scaled_constant
= _mesa_float_to_half(original
);
3199 /* Check for loss of precision. If this is
3200 * mediump, we don't care, but for a highp
3201 * shader, we need to pay attention. NIR
3202 * doesn't yet tell us which mode we're in!
3203 * Practically this prevents most constants
3204 * from being inlined, sadly. */
3206 float fp32
= _mesa_half_to_float(scaled_constant
);
3208 if (fp32
!= original
)
3212 /* We don't know how to handle these with a constant */
3214 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
3215 DBG("Bailing inline constant...\n");
3219 /* Make sure that the constant is not itself a
3220 * vector by checking if all accessed values
3221 * (by the swizzle) are the same. */
3223 uint32_t *cons
= (uint32_t *) ins
->constants
;
3224 uint32_t value
= cons
[component
];
3226 bool is_vector
= false;
3227 unsigned mask
= effective_writemask(&ins
->alu
);
3229 for (int c
= 1; c
< 4; ++c
) {
3230 /* We only care if this component is actually used */
3231 if (!(mask
& (1 << c
)))
3234 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3236 if (test
!= value
) {
3245 /* Get rid of the embedded constant */
3246 ins
->has_constants
= false;
3247 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3248 ins
->ssa_args
.inline_constant
= true;
3249 ins
->inline_constant
= scaled_constant
;
3254 /* Map normal SSA sources to other SSA sources / fixed registers (like
3258 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3260 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3263 /* Remove entry in leftovers to avoid a redunant fmov */
3265 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3268 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3270 /* Assign the alias map */
3276 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3277 * texture pipeline */
3280 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3282 bool progress
= false;
3284 mir_foreach_instr_in_block_safe(block
, ins
) {
3285 if (ins
->type
!= TAG_ALU_4
) continue;
3286 if (ins
->compact_branch
) continue;
3288 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3289 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3290 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3292 mir_remove_instruction(ins
);
3300 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
3302 bool progress
= false;
3304 mir_foreach_instr_in_block_safe(block
, ins
) {
3305 if (ins
->type
!= TAG_ALU_4
) continue;
3306 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3308 unsigned from
= ins
->ssa_args
.src1
;
3309 unsigned to
= ins
->ssa_args
.dest
;
3311 /* We only work on pure SSA */
3313 if (to
>= SSA_FIXED_MINIMUM
) continue;
3314 if (from
>= SSA_FIXED_MINIMUM
) continue;
3315 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
3316 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
3318 /* Also, if the move has side effects, we're helpless */
3320 midgard_vector_alu_src src
=
3321 vector_alu_from_unsigned(ins
->alu
.src2
);
3322 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
3323 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
3325 if (mir_nontrivial_mod(src
, is_int
, mask
)) continue;
3326 if (ins
->alu
.outmod
!= midgard_outmod_none
) continue;
3328 mir_foreach_instr_in_block_from(block
, v
, mir_next_op(ins
)) {
3329 if (v
->ssa_args
.src0
== to
) {
3330 v
->ssa_args
.src0
= from
;
3334 if (v
->ssa_args
.src1
== to
&& !v
->ssa_args
.inline_constant
) {
3335 v
->ssa_args
.src1
= from
;
3345 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
3347 bool progress
= false;
3349 mir_foreach_instr_in_block_safe(block
, ins
) {
3350 if (ins
->type
!= TAG_ALU_4
) continue;
3351 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3353 unsigned from
= ins
->ssa_args
.src1
;
3354 unsigned to
= ins
->ssa_args
.dest
;
3356 /* Make sure it's simple enough for us to handle */
3358 if (from
>= SSA_FIXED_MINIMUM
) continue;
3359 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
3360 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
3361 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
3363 bool eliminated
= false;
3365 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
3366 /* The texture registers are not SSA so be careful.
3367 * Conservatively, just stop if we hit a texture op
3368 * (even if it may not write) to where we are */
3370 if (v
->type
!= TAG_ALU_4
)
3373 if (v
->ssa_args
.dest
== from
) {
3374 /* We don't want to track partial writes ... */
3375 if (v
->alu
.mask
== 0xF) {
3376 v
->ssa_args
.dest
= to
;
3385 mir_remove_instruction(ins
);
3387 progress
|= eliminated
;
3393 /* We don't really understand the imov/fmov split, so always use fmov (but let
3394 * it be imov in the IR so we don't do unsafe floating point "optimizations"
3395 * and break things */
3398 midgard_imov_workaround(compiler_context
*ctx
, midgard_block
*block
)
3400 mir_foreach_instr_in_block_safe(block
, ins
) {
3401 if (ins
->type
!= TAG_ALU_4
) continue;
3402 if (ins
->alu
.op
!= midgard_alu_op_imov
) continue;
3404 ins
->alu
.op
= midgard_alu_op_fmov
;
3405 ins
->alu
.outmod
= midgard_outmod_none
;
3407 /* Remove flags that don't make sense */
3409 midgard_vector_alu_src s
=
3410 vector_alu_from_unsigned(ins
->alu
.src2
);
3414 ins
->alu
.src2
= vector_alu_srco_unsigned(s
);
3418 /* The following passes reorder MIR instructions to enable better scheduling */
3421 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3423 mir_foreach_instr_in_block_safe(block
, ins
) {
3424 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3426 /* We've found a load/store op. Check if next is also load/store. */
3427 midgard_instruction
*next_op
= mir_next_op(ins
);
3428 if (&next_op
->link
!= &block
->instructions
) {
3429 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3430 /* If so, we're done since we're a pair */
3431 ins
= mir_next_op(ins
);
3435 /* Maximum search distance to pair, to avoid register pressure disasters */
3436 int search_distance
= 8;
3438 /* Otherwise, we have an orphaned load/store -- search for another load */
3439 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3440 /* Terminate search if necessary */
3441 if (!(search_distance
--)) break;
3443 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3445 /* Stores cannot be reordered, since they have
3446 * dependencies. For the same reason, indirect
3447 * loads cannot be reordered as their index is
3448 * loaded in r27.w */
3450 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3452 /* It appears the 0x800 bit is set whenever a
3453 * load is direct, unset when it is indirect.
3454 * Skip indirect loads. */
3456 if (!(c
->load_store
.unknown
& 0x800)) continue;
3458 /* We found one! Move it up to pair and remove it from the old location */
3460 mir_insert_instruction_before(ins
, *c
);
3461 mir_remove_instruction(c
);
3469 /* Emit varying stores late */
3472 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3473 /* Iterate in reverse to get the final write, rather than the first */
3475 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3476 /* Check if what we just wrote needs a store */
3477 int idx
= ins
->ssa_args
.dest
;
3478 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3480 if (!varying
) continue;
3484 /* We need to store to the appropriate varying, so emit the
3487 /* TODO: Integrate with special purpose RA (and scheduler?) */
3488 bool high_varying_register
= false;
3490 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3492 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3493 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3495 mir_insert_instruction_before(mir_next_op(ins
), st
);
3496 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3498 /* We no longer need to store this varying */
3499 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3503 /* If there are leftovers after the below pass, emit actual fmov
3504 * instructions for the slow-but-correct path */
3507 emit_leftover_move(compiler_context
*ctx
)
3509 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3510 int base
= ((uintptr_t) leftover
->key
) - 1;
3513 map_ssa_to_alias(ctx
, &mapped
);
3514 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3519 actualise_ssa_to_alias(compiler_context
*ctx
)
3521 mir_foreach_instr(ctx
, ins
) {
3522 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3523 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3526 emit_leftover_move(ctx
);
3530 emit_fragment_epilogue(compiler_context
*ctx
)
3532 /* Special case: writing out constants requires us to include the move
3533 * explicitly now, so shove it into r0 */
3535 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3537 if (constant_value
) {
3538 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3539 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3540 emit_mir_instruction(ctx
, ins
);
3543 /* Perform the actual fragment writeout. We have two writeout/branch
3544 * instructions, forming a loop until writeout is successful as per the
3545 * docs. TODO: gl_FragDepth */
3547 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3548 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3551 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3552 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3553 * with the int8 analogue to the fragment epilogue */
3556 emit_blend_epilogue(compiler_context
*ctx
)
3558 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3560 midgard_instruction scale
= {
3563 .inline_constant
= _mesa_float_to_half(255.0),
3565 .src0
= SSA_FIXED_REGISTER(0),
3566 .src1
= SSA_UNUSED_0
,
3567 .dest
= SSA_FIXED_REGISTER(24),
3568 .inline_constant
= true
3571 .op
= midgard_alu_op_fmul
,
3572 .reg_mode
= midgard_reg_mode_32
,
3573 .dest_override
= midgard_dest_override_lower
,
3575 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3576 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3580 emit_mir_instruction(ctx
, scale
);
3582 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3584 midgard_vector_alu_src alu_src
= blank_alu_src
;
3585 alu_src
.half
= true;
3587 midgard_instruction f2u8
= {
3590 .src0
= SSA_FIXED_REGISTER(24),
3591 .src1
= SSA_UNUSED_0
,
3592 .dest
= SSA_FIXED_REGISTER(0),
3593 .inline_constant
= true
3596 .op
= midgard_alu_op_f2u8
,
3597 .reg_mode
= midgard_reg_mode_16
,
3598 .dest_override
= midgard_dest_override_lower
,
3599 .outmod
= midgard_outmod_pos
,
3601 .src1
= vector_alu_srco_unsigned(alu_src
),
3602 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3606 emit_mir_instruction(ctx
, f2u8
);
3608 /* vmul.imov.quarter r0, r0, r0 */
3610 midgard_instruction imov_8
= {
3613 .src0
= SSA_UNUSED_1
,
3614 .src1
= SSA_FIXED_REGISTER(0),
3615 .dest
= SSA_FIXED_REGISTER(0),
3618 .op
= midgard_alu_op_imov
,
3619 .reg_mode
= midgard_reg_mode_8
,
3620 .dest_override
= midgard_dest_override_none
,
3622 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3623 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3627 /* Emit branch epilogue with the 8-bit move as the source */
3629 emit_mir_instruction(ctx
, imov_8
);
3630 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3632 emit_mir_instruction(ctx
, imov_8
);
3633 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3636 static midgard_block
*
3637 emit_block(compiler_context
*ctx
, nir_block
*block
)
3639 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3640 list_addtail(&this_block
->link
, &ctx
->blocks
);
3642 this_block
->is_scheduled
= false;
3645 ctx
->texture_index
[0] = -1;
3646 ctx
->texture_index
[1] = -1;
3648 /* Add us as a successor to the block we are following */
3649 if (ctx
->current_block
)
3650 midgard_block_add_successor(ctx
->current_block
, this_block
);
3652 /* Set up current block */
3653 list_inithead(&this_block
->instructions
);
3654 ctx
->current_block
= this_block
;
3656 nir_foreach_instr(instr
, block
) {
3657 emit_instr(ctx
, instr
);
3658 ++ctx
->instruction_count
;
3661 inline_alu_constants(ctx
);
3662 embedded_to_inline_constant(ctx
);
3664 /* Perform heavylifting for aliasing */
3665 actualise_ssa_to_alias(ctx
);
3667 midgard_emit_store(ctx
, this_block
);
3668 midgard_pair_load_store(ctx
, this_block
);
3669 midgard_imov_workaround(ctx
, this_block
);
3671 /* Append fragment shader epilogue (value writeout) */
3672 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3673 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3675 emit_blend_epilogue(ctx
);
3677 emit_fragment_epilogue(ctx
);
3681 if (block
== nir_start_block(ctx
->func
->impl
))
3682 ctx
->initial_block
= this_block
;
3684 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3685 ctx
->final_block
= this_block
;
3687 /* Allow the next control flow to access us retroactively, for
3689 ctx
->current_block
= this_block
;
3691 /* Document the fallthrough chain */
3692 ctx
->previous_source_block
= this_block
;
3697 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3700 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3702 /* Conditional branches expect the condition in r31.w; emit a move for
3703 * that in the _previous_ block (which is the current block). */
3704 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3706 /* Speculatively emit the branch, but we can't fill it in until later */
3707 EMIT(branch
, true, true);
3708 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3710 /* Emit the two subblocks */
3711 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3713 /* Emit a jump from the end of the then block to the end of the else */
3714 EMIT(branch
, false, false);
3715 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3717 /* Emit second block, and check if it's empty */
3719 int else_idx
= ctx
->block_count
;
3720 int count_in
= ctx
->instruction_count
;
3721 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3722 int after_else_idx
= ctx
->block_count
;
3724 /* Now that we have the subblocks emitted, fix up the branches */
3729 if (ctx
->instruction_count
== count_in
) {
3730 /* The else block is empty, so don't emit an exit jump */
3731 mir_remove_instruction(then_exit
);
3732 then_branch
->branch
.target_block
= after_else_idx
;
3734 then_branch
->branch
.target_block
= else_idx
;
3735 then_exit
->branch
.target_block
= after_else_idx
;
3740 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3742 /* Remember where we are */
3743 midgard_block
*start_block
= ctx
->current_block
;
3745 /* Allocate a loop number, growing the current inner loop depth */
3746 int loop_idx
= ++ctx
->current_loop_depth
;
3748 /* Get index from before the body so we can loop back later */
3749 int start_idx
= ctx
->block_count
;
3751 /* Emit the body itself */
3752 emit_cf_list(ctx
, &nloop
->body
);
3754 /* Branch back to loop back */
3755 struct midgard_instruction br_back
= v_branch(false, false);
3756 br_back
.branch
.target_block
= start_idx
;
3757 emit_mir_instruction(ctx
, br_back
);
3759 /* Mark down that branch in the graph. Note that we're really branching
3760 * to the block *after* we started in. TODO: Why doesn't the branch
3761 * itself have an off-by-one then...? */
3762 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
3764 /* Find the index of the block about to follow us (note: we don't add
3765 * one; blocks are 0-indexed so we get a fencepost problem) */
3766 int break_block_idx
= ctx
->block_count
;
3768 /* Fix up the break statements we emitted to point to the right place,
3769 * now that we can allocate a block number for them */
3771 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3772 mir_foreach_instr_in_block(block
, ins
) {
3773 if (ins
->type
!= TAG_ALU_4
) continue;
3774 if (!ins
->compact_branch
) continue;
3775 if (ins
->prepacked_branch
) continue;
3777 /* We found a branch -- check the type to see if we need to do anything */
3778 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3780 /* It's a break! Check if it's our break */
3781 if (ins
->branch
.target_break
!= loop_idx
) continue;
3783 /* Okay, cool, we're breaking out of this loop.
3784 * Rewrite from a break to a goto */
3786 ins
->branch
.target_type
= TARGET_GOTO
;
3787 ins
->branch
.target_block
= break_block_idx
;
3791 /* Now that we've finished emitting the loop, free up the depth again
3792 * so we play nice with recursion amid nested loops */
3793 --ctx
->current_loop_depth
;
3796 static midgard_block
*
3797 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3799 midgard_block
*start_block
= NULL
;
3801 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3802 switch (node
->type
) {
3803 case nir_cf_node_block
: {
3804 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3807 start_block
= block
;
3812 case nir_cf_node_if
:
3813 emit_if(ctx
, nir_cf_node_as_if(node
));
3816 case nir_cf_node_loop
:
3817 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3820 case nir_cf_node_function
:
3829 /* Due to lookahead, we need to report the first tag executed in the command
3830 * stream and in branch targets. An initial block might be empty, so iterate
3831 * until we find one that 'works' */
3834 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3836 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3838 unsigned first_tag
= 0;
3841 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3843 if (initial_bundle
) {
3844 first_tag
= initial_bundle
->tag
;
3848 /* Initial block is empty, try the next block */
3849 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3850 } while(initial_block
!= NULL
);
3857 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3859 struct util_dynarray
*compiled
= &program
->compiled
;
3861 midgard_debug
= debug_get_option_midgard_debug();
3863 compiler_context ictx
= {
3865 .stage
= nir
->info
.stage
,
3867 .is_blend
= is_blend
,
3868 .blend_constant_offset
= -1,
3870 .alpha_ref
= program
->alpha_ref
3873 compiler_context
*ctx
= &ictx
;
3875 /* TODO: Decide this at runtime */
3876 ctx
->uniform_cutoff
= 8;
3878 /* Assign var locations early, so the epilogue can use them if necessary */
3880 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3881 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3882 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3884 /* Initialize at a global (not block) level hash tables */
3886 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3887 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3888 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3889 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3890 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3891 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3892 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3894 /* Record the varying mapping for the command stream's bookkeeping */
3896 struct exec_list
*varyings
=
3897 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3899 nir_foreach_variable(var
, varyings
) {
3900 unsigned loc
= var
->data
.driver_location
;
3901 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3903 for (int c
= 0; c
< sz
; ++c
) {
3904 program
->varyings
[loc
+ c
] = var
->data
.location
;
3908 /* Lower gl_Position pre-optimisation */
3910 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3911 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3913 NIR_PASS_V(nir
, nir_lower_var_copies
);
3914 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3915 NIR_PASS_V(nir
, nir_split_var_copies
);
3916 NIR_PASS_V(nir
, nir_lower_var_copies
);
3917 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3918 NIR_PASS_V(nir
, nir_lower_var_copies
);
3919 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3921 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3923 /* Optimisation passes */
3927 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3928 nir_print_shader(nir
, stdout
);
3931 /* Assign sysvals and counts, now that we're sure
3932 * (post-optimisation) */
3934 midgard_nir_assign_sysvals(ctx
, nir
);
3936 program
->uniform_count
= nir
->num_uniforms
;
3937 program
->sysval_count
= ctx
->sysval_count
;
3938 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3940 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3941 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3943 nir_foreach_function(func
, nir
) {
3947 list_inithead(&ctx
->blocks
);
3948 ctx
->block_count
= 0;
3951 emit_cf_list(ctx
, &func
->impl
->body
);
3952 emit_block(ctx
, func
->impl
->end_block
);
3954 break; /* TODO: Multi-function shaders */
3957 util_dynarray_init(compiled
, NULL
);
3959 /* MIR-level optimizations */
3961 bool progress
= false;
3966 mir_foreach_block(ctx
, block
) {
3967 progress
|= midgard_opt_copy_prop(ctx
, block
);
3968 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
3969 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
3974 schedule_program(ctx
);
3976 /* Now that all the bundles are scheduled and we can calculate block
3977 * sizes, emit actual branch instructions rather than placeholders */
3979 int br_block_idx
= 0;
3981 mir_foreach_block(ctx
, block
) {
3982 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3983 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3984 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3986 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3988 if (ins
->prepacked_branch
) continue;
3990 /* Parse some basic branch info */
3991 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3992 bool is_conditional
= ins
->branch
.conditional
;
3993 bool is_inverted
= ins
->branch
.invert_conditional
;
3994 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3996 /* Determine the block we're jumping to */
3997 int target_number
= ins
->branch
.target_block
;
3999 /* Report the destination tag. Discards don't need this */
4000 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
4002 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
4003 int quadword_offset
= 0;
4006 /* Jump to the end of the shader. We
4007 * need to include not only the
4008 * following blocks, but also the
4009 * contents of our current block (since
4010 * discard can come in the middle of
4013 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
4015 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
4016 quadword_offset
+= quadword_size(bun
->tag
);
4019 mir_foreach_block_from(ctx
, blk
, b
) {
4020 quadword_offset
+= b
->quadword_count
;
4023 } else if (target_number
> br_block_idx
) {
4026 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
4027 midgard_block
*blk
= mir_get_block(ctx
, idx
);
4030 quadword_offset
+= blk
->quadword_count
;
4033 /* Jump backwards */
4035 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
4036 midgard_block
*blk
= mir_get_block(ctx
, idx
);
4039 quadword_offset
-= blk
->quadword_count
;
4043 /* Unconditional extended branches (far jumps)
4044 * have issues, so we always use a conditional
4045 * branch, setting the condition to always for
4046 * unconditional. For compact unconditional
4047 * branches, cond isn't used so it doesn't
4048 * matter what we pick. */
4050 midgard_condition cond
=
4051 !is_conditional
? midgard_condition_always
:
4052 is_inverted
? midgard_condition_false
:
4053 midgard_condition_true
;
4055 midgard_jmp_writeout_op op
=
4056 is_discard
? midgard_jmp_writeout_op_discard
:
4057 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
4058 midgard_jmp_writeout_op_branch_cond
;
4061 midgard_branch_extended branch
=
4062 midgard_create_branch_extended(
4067 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
4068 } else if (is_conditional
|| is_discard
) {
4069 midgard_branch_cond branch
= {
4071 .dest_tag
= dest_tag
,
4072 .offset
= quadword_offset
,
4076 assert(branch
.offset
== quadword_offset
);
4078 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
4080 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
4082 midgard_branch_uncond branch
= {
4084 .dest_tag
= dest_tag
,
4085 .offset
= quadword_offset
,
4089 assert(branch
.offset
== quadword_offset
);
4091 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
4099 /* Emit flat binary from the instruction arrays. Iterate each block in
4100 * sequence. Save instruction boundaries such that lookahead tags can
4101 * be assigned easily */
4103 /* Cache _all_ bundles in source order for lookahead across failed branches */
4105 int bundle_count
= 0;
4106 mir_foreach_block(ctx
, block
) {
4107 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
4109 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
4111 mir_foreach_block(ctx
, block
) {
4112 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
4113 source_order_bundles
[bundle_idx
++] = bundle
;
4117 int current_bundle
= 0;
4119 mir_foreach_block(ctx
, block
) {
4120 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
4123 if (current_bundle
+ 1 < bundle_count
) {
4124 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
4126 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
4133 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
4137 /* TODO: Free deeper */
4138 //util_dynarray_fini(&block->instructions);
4141 free(source_order_bundles
);
4143 /* Report the very first tag executed */
4144 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
4146 /* Deal with off-by-one related to the fencepost problem */
4147 program
->work_register_count
= ctx
->work_registers
+ 1;
4149 program
->can_discard
= ctx
->can_discard
;
4150 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
4152 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
4154 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
4155 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);