2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
51 #include "disassemble.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
61 int midgard_debug
= 0;
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
69 midgard_is_branch_unit(unsigned unit
)
71 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
75 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
77 block
->successors
[block
->nr_successors
++] = successor
;
78 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
86 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
87 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
88 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
89 #define SWIZZLE_XYZZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_Z)
90 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
91 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
93 static inline unsigned
94 swizzle_of(unsigned comp
)
106 unreachable("Invalid component count");
110 static inline unsigned
111 mask_of(unsigned nr_comp
)
113 return (1 << nr_comp
) - 1;
116 #define M_LOAD_STORE(name, rname, uname) \
117 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
118 midgard_instruction i = { \
119 .type = TAG_LOAD_STORE_4, \
126 .op = midgard_op_##name, \
128 .swizzle = SWIZZLE_XYZW, \
136 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
137 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
139 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
140 * the corresponding Midgard source */
142 static midgard_vector_alu_src
143 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
)
145 if (!src
) return blank_alu_src
;
147 /* Figure out how many components there are so we can adjust the
148 * swizzle. Specifically we want to broadcast the last channel so
149 * things like ball2/3 work
152 if (broadcast_count
) {
153 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
155 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
156 src
->swizzle
[c
] = last_component
;
160 midgard_vector_alu_src alu_src
= {
163 .half
= 0, /* TODO */
164 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
168 /* TODO: sign-extend/zero-extend */
169 alu_src
.mod
= midgard_int_normal
;
171 /* These should have been lowered away */
172 assert(!(src
->abs
|| src
->negate
));
174 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
180 /* load/store instructions have both 32-bit and 16-bit variants, depending on
181 * whether we are using vectors composed of highp or mediump. At the moment, we
182 * don't support half-floats -- this requires changes in other parts of the
183 * compiler -- therefore the 16-bit versions are commented out. */
185 //M_LOAD(ld_attr_16);
187 //M_LOAD(ld_vary_16);
189 //M_LOAD(ld_uniform_16);
190 M_LOAD(ld_uniform_32
);
191 M_LOAD(ld_color_buffer_8
);
192 //M_STORE(st_vary_16);
194 M_STORE(st_cubemap_coords
);
196 static midgard_instruction
197 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
199 midgard_branch_cond branch
= {
207 memcpy(&compact
, &branch
, sizeof(branch
));
209 midgard_instruction ins
= {
211 .unit
= ALU_ENAB_BR_COMPACT
,
212 .prepacked_branch
= true,
213 .compact_branch
= true,
214 .br_compact
= compact
217 if (op
== midgard_jmp_writeout_op_writeout
)
223 static midgard_instruction
224 v_branch(bool conditional
, bool invert
)
226 midgard_instruction ins
= {
228 .unit
= ALU_ENAB_BRANCH
,
229 .compact_branch
= true,
231 .conditional
= conditional
,
232 .invert_conditional
= invert
239 static midgard_branch_extended
240 midgard_create_branch_extended( midgard_condition cond
,
241 midgard_jmp_writeout_op op
,
243 signed quadword_offset
)
245 /* For unclear reasons, the condition code is repeated 8 times */
246 uint16_t duplicated_cond
=
256 midgard_branch_extended branch
= {
258 .dest_tag
= dest_tag
,
259 .offset
= quadword_offset
,
260 .cond
= duplicated_cond
267 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
269 ins
->has_constants
= true;
270 memcpy(&ins
->constants
, constants
, 16);
274 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
276 return glsl_count_attribute_slots(type
, false);
279 /* Lower fdot2 to a vector multiplication followed by channel addition */
281 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
283 if (alu
->op
!= nir_op_fdot2
)
286 b
->cursor
= nir_before_instr(&alu
->instr
);
288 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
289 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
291 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
293 nir_ssa_def
*sum
= nir_fadd(b
,
294 nir_channel(b
, product
, 0),
295 nir_channel(b
, product
, 1));
297 /* Replace the fdot2 with this sum */
298 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
302 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
304 switch (instr
->intrinsic
) {
305 case nir_intrinsic_load_viewport_scale
:
306 return PAN_SYSVAL_VIEWPORT_SCALE
;
307 case nir_intrinsic_load_viewport_offset
:
308 return PAN_SYSVAL_VIEWPORT_OFFSET
;
315 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
318 return dst
->ssa
.index
;
320 assert(!dst
->reg
.indirect
);
321 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
325 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
328 nir_intrinsic_instr
*intr
;
329 nir_dest
*dst
= NULL
;
333 switch (instr
->type
) {
334 case nir_instr_type_intrinsic
:
335 intr
= nir_instr_as_intrinsic(instr
);
336 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
339 case nir_instr_type_tex
:
340 tex
= nir_instr_as_tex(instr
);
341 if (tex
->op
!= nir_texop_txs
)
344 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
345 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
346 nir_tex_instr_dest_size(tex
) -
347 (tex
->is_array
? 1 : 0),
356 *dest
= nir_dest_index(ctx
, dst
);
362 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
366 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
370 /* We have a sysval load; check if it's already been assigned */
372 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
375 /* It hasn't -- so assign it now! */
377 unsigned id
= ctx
->sysval_count
++;
378 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
379 ctx
->sysvals
[id
] = sysval
;
383 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
385 ctx
->sysval_count
= 0;
387 nir_foreach_function(function
, shader
) {
388 if (!function
->impl
) continue;
390 nir_foreach_block(block
, function
->impl
) {
391 nir_foreach_instr_safe(instr
, block
) {
392 midgard_nir_assign_sysval_body(ctx
, instr
);
399 midgard_nir_lower_fdot2(nir_shader
*shader
)
401 bool progress
= false;
403 nir_foreach_function(function
, shader
) {
404 if (!function
->impl
) continue;
407 nir_builder
*b
= &_b
;
408 nir_builder_init(b
, function
->impl
);
410 nir_foreach_block(block
, function
->impl
) {
411 nir_foreach_instr_safe(instr
, block
) {
412 if (instr
->type
!= nir_instr_type_alu
) continue;
414 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
415 midgard_nir_lower_fdot2_body(b
, alu
);
421 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
429 optimise_nir(nir_shader
*nir
)
432 unsigned lower_flrp
=
433 (nir
->options
->lower_flrp16
? 16 : 0) |
434 (nir
->options
->lower_flrp32
? 32 : 0) |
435 (nir
->options
->lower_flrp64
? 64 : 0);
437 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
438 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
439 NIR_PASS(progress
, nir
, nir_lower_idiv
);
441 nir_lower_tex_options lower_tex_1st_pass_options
= {
446 nir_lower_tex_options lower_tex_2nd_pass_options
= {
447 .lower_txs_lod
= true,
450 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
451 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
456 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
457 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
459 NIR_PASS(progress
, nir
, nir_copy_prop
);
460 NIR_PASS(progress
, nir
, nir_opt_dce
);
461 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
462 NIR_PASS(progress
, nir
, nir_opt_cse
);
463 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
464 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
465 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
467 if (lower_flrp
!= 0) {
468 bool lower_flrp_progress
= false;
469 NIR_PASS(lower_flrp_progress
,
473 false /* always_precise */,
474 nir
->options
->lower_ffma
);
475 if (lower_flrp_progress
) {
476 NIR_PASS(progress
, nir
,
477 nir_opt_constant_folding
);
481 /* Nothing should rematerialize any flrps, so we only
482 * need to do this lowering once.
487 NIR_PASS(progress
, nir
, nir_opt_undef
);
488 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
491 nir_var_function_temp
);
493 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
496 /* Must be run at the end to prevent creation of fsin/fcos ops */
497 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
502 NIR_PASS(progress
, nir
, nir_opt_dce
);
503 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
504 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
505 NIR_PASS(progress
, nir
, nir_copy_prop
);
508 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
510 /* We implement booleans as 32-bit 0/~0 */
511 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
513 /* Now that booleans are lowered, we can run out late opts */
514 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
516 /* Lower mods for float ops only. Integer ops don't support modifiers
517 * (saturate doesn't make sense on integers, neg/abs require dedicated
520 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
521 NIR_PASS(progress
, nir
, nir_copy_prop
);
522 NIR_PASS(progress
, nir
, nir_opt_dce
);
524 /* Take us out of SSA */
525 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
526 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
528 /* We are a vector architecture; write combine where possible */
529 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
530 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
532 NIR_PASS(progress
, nir
, nir_opt_dce
);
535 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
536 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
537 * r0. See the comments in compiler_context */
540 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
542 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
543 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
546 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
549 unalias_ssa(compiler_context
*ctx
, int dest
)
551 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
552 /* TODO: Remove from leftover or no? */
555 /* Do not actually emit a load; instead, cache the constant for inlining */
558 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
560 nir_ssa_def def
= instr
->def
;
562 float *v
= rzalloc_array(NULL
, float, 4);
563 nir_const_load_to_arr(v
, instr
, f32
);
564 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
568 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
571 return src
->ssa
->index
;
573 assert(!src
->reg
.indirect
);
574 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
579 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
581 return nir_src_index(ctx
, &src
->src
);
585 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
587 unsigned comp
= src
->swizzle
[0];
589 for (unsigned c
= 1; c
< nr_components
; ++c
) {
590 if (src
->swizzle
[c
] != comp
)
597 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
598 * output of a conditional test) into that register */
601 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
603 int condition
= nir_src_index(ctx
, src
);
605 /* Source to swizzle the desired component into w */
607 const midgard_vector_alu_src alu_src
= {
608 .swizzle
= SWIZZLE(component
, component
, component
, component
),
611 /* There is no boolean move instruction. Instead, we simulate a move by
612 * ANDing the condition with itself to get it into r31.w */
614 midgard_instruction ins
= {
617 /* We need to set the conditional as close as possible */
618 .precede_break
= true,
619 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
624 .dest
= SSA_FIXED_REGISTER(31),
628 .op
= midgard_alu_op_iand
,
629 .outmod
= midgard_outmod_int_wrap
,
630 .reg_mode
= midgard_reg_mode_32
,
631 .dest_override
= midgard_dest_override_none
,
632 .mask
= (0x3 << 6), /* w */
633 .src1
= vector_alu_srco_unsigned(alu_src
),
634 .src2
= vector_alu_srco_unsigned(alu_src
)
638 emit_mir_instruction(ctx
, ins
);
641 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
645 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
647 int condition
= nir_src_index(ctx
, &src
->src
);
649 /* Source to swizzle the desired component into w */
651 const midgard_vector_alu_src alu_src
= {
652 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
655 /* There is no boolean move instruction. Instead, we simulate a move by
656 * ANDing the condition with itself to get it into r31.w */
658 midgard_instruction ins
= {
660 .precede_break
= true,
664 .dest
= SSA_FIXED_REGISTER(31),
667 .op
= midgard_alu_op_iand
,
668 .outmod
= midgard_outmod_int_wrap
,
669 .reg_mode
= midgard_reg_mode_32
,
670 .dest_override
= midgard_dest_override_none
,
671 .mask
= expand_writemask(mask_of(nr_comp
)),
672 .src1
= vector_alu_srco_unsigned(alu_src
),
673 .src2
= vector_alu_srco_unsigned(alu_src
)
677 emit_mir_instruction(ctx
, ins
);
682 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
683 * pinning to eliminate this move in all known cases */
686 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
688 int offset
= nir_src_index(ctx
, src
);
690 midgard_instruction ins
= {
693 .src0
= SSA_UNUSED_1
,
695 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
698 .op
= midgard_alu_op_imov
,
699 .outmod
= midgard_outmod_int_wrap
,
700 .reg_mode
= midgard_reg_mode_32
,
701 .dest_override
= midgard_dest_override_none
,
702 .mask
= (0x3 << 6), /* w */
703 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
704 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
708 emit_mir_instruction(ctx
, ins
);
711 #define ALU_CASE(nir, _op) \
713 op = midgard_alu_op_##_op; \
716 #define ALU_CASE_BCAST(nir, _op, count) \
718 op = midgard_alu_op_##_op; \
719 broadcast_swizzle = count; \
722 nir_is_fzero_constant(nir_src src
)
724 if (!nir_src_is_const(src
))
727 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
728 if (nir_src_comp_as_float(src
, c
) != 0.0)
736 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
738 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
740 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
741 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
742 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
744 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
745 * supported. A few do not and are commented for now. Also, there are a
746 * number of NIR ops which Midgard does not support and need to be
747 * lowered, also TODO. This switch block emits the opcode and calling
748 * convention of the Midgard instruction; actual packing is done in
753 /* Number of components valid to check for the instruction (the rest
754 * will be forced to the last), or 0 to use as-is. Relevant as
755 * ball-type instructions have a channel count in NIR but are all vec4
758 unsigned broadcast_swizzle
= 0;
761 ALU_CASE(fadd
, fadd
);
762 ALU_CASE(fmul
, fmul
);
763 ALU_CASE(fmin
, fmin
);
764 ALU_CASE(fmax
, fmax
);
765 ALU_CASE(imin
, imin
);
766 ALU_CASE(imax
, imax
);
767 ALU_CASE(umin
, umin
);
768 ALU_CASE(umax
, umax
);
769 ALU_CASE(ffloor
, ffloor
);
770 ALU_CASE(fround_even
, froundeven
);
771 ALU_CASE(ftrunc
, ftrunc
);
772 ALU_CASE(fceil
, fceil
);
773 ALU_CASE(fdot3
, fdot3
);
774 ALU_CASE(fdot4
, fdot4
);
775 ALU_CASE(iadd
, iadd
);
776 ALU_CASE(isub
, isub
);
777 ALU_CASE(imul
, imul
);
779 /* Zero shoved as second-arg */
780 ALU_CASE(iabs
, iabsdiff
);
784 ALU_CASE(feq32
, feq
);
785 ALU_CASE(fne32
, fne
);
786 ALU_CASE(flt32
, flt
);
787 ALU_CASE(ieq32
, ieq
);
788 ALU_CASE(ine32
, ine
);
789 ALU_CASE(ilt32
, ilt
);
790 ALU_CASE(ult32
, ult
);
792 /* We don't have a native b2f32 instruction. Instead, like many
793 * GPUs, we exploit booleans as 0/~0 for false/true, and
794 * correspondingly AND
795 * by 1.0 to do the type conversion. For the moment, prime us
798 * iand [whatever], #0
800 * At the end of emit_alu (as MIR), we'll fix-up the constant
803 ALU_CASE(b2f32
, iand
);
804 ALU_CASE(b2i32
, iand
);
806 /* Likewise, we don't have a dedicated f2b32 instruction, but
807 * we can do a "not equal to 0.0" test. */
809 ALU_CASE(f2b32
, fne
);
810 ALU_CASE(i2b32
, ine
);
812 ALU_CASE(frcp
, frcp
);
813 ALU_CASE(frsq
, frsqrt
);
814 ALU_CASE(fsqrt
, fsqrt
);
815 ALU_CASE(fexp2
, fexp2
);
816 ALU_CASE(flog2
, flog2
);
818 ALU_CASE(f2i32
, f2i_rtz
);
819 ALU_CASE(f2u32
, f2u_rtz
);
820 ALU_CASE(i2f32
, i2f_rtz
);
821 ALU_CASE(u2f32
, u2f_rtz
);
823 ALU_CASE(fsin
, fsin
);
824 ALU_CASE(fcos
, fcos
);
826 /* Second op implicit #0 */
827 ALU_CASE(inot
, inor
);
828 ALU_CASE(iand
, iand
);
830 ALU_CASE(ixor
, ixor
);
831 ALU_CASE(ishl
, ishl
);
832 ALU_CASE(ishr
, iasr
);
833 ALU_CASE(ushr
, ilsr
);
835 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
836 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
837 ALU_CASE(b32all_fequal4
, fball_eq
);
839 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
840 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
841 ALU_CASE(b32any_fnequal4
, fbany_neq
);
843 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
844 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
845 ALU_CASE(b32all_iequal4
, iball_eq
);
847 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
848 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
849 ALU_CASE(b32any_inequal4
, ibany_neq
);
851 /* Source mods will be shoved in later */
852 ALU_CASE(fabs
, fmov
);
853 ALU_CASE(fneg
, fmov
);
854 ALU_CASE(fsat
, fmov
);
856 /* For greater-or-equal, we lower to less-or-equal and flip the
864 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
865 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
866 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
867 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
870 /* Swap via temporary */
871 nir_alu_src temp
= instr
->src
[1];
872 instr
->src
[1] = instr
->src
[0];
873 instr
->src
[0] = temp
;
878 case nir_op_b32csel
: {
879 /* Midgard features both fcsel and icsel, depending on
880 * the type of the arguments/output. However, as long
881 * as we're careful we can _always_ use icsel and
882 * _never_ need fcsel, since the latter does additional
883 * floating-point-specific processing whereas the
884 * former just moves bits on the wire. It's not obvious
885 * why these are separate opcodes, save for the ability
886 * to do things like sat/pos/abs/neg for free */
888 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
889 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
891 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
894 /* Emit the condition into r31 */
897 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
899 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
901 /* The condition is the first argument; move the other
902 * arguments up one to be a binary instruction for
905 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
910 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
915 /* Midgard can perform certain modifiers on output of an ALU op */
918 if (midgard_is_integer_out_op(op
)) {
919 outmod
= midgard_outmod_int_wrap
;
921 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
922 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
925 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
927 if (instr
->op
== nir_op_fmax
) {
928 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
929 op
= midgard_alu_op_fmov
;
931 outmod
= midgard_outmod_pos
;
932 instr
->src
[0] = instr
->src
[1];
933 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
934 op
= midgard_alu_op_fmov
;
936 outmod
= midgard_outmod_pos
;
940 /* Fetch unit, quirks, etc information */
941 unsigned opcode_props
= alu_opcode_props
[op
].props
;
942 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
944 /* src0 will always exist afaik, but src1 will not for 1-argument
945 * instructions. The latter can only be fetched if the instruction
946 * needs it, or else we may segfault. */
948 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
949 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
951 /* Rather than use the instruction generation helpers, we do it
952 * ourselves here to avoid the mess */
954 midgard_instruction ins
= {
957 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
958 .src1
= quirk_flipped_r24
? src0
: src1
,
963 nir_alu_src
*nirmods
[2] = { NULL
};
965 if (nr_inputs
== 2) {
966 nirmods
[0] = &instr
->src
[0];
967 nirmods
[1] = &instr
->src
[1];
968 } else if (nr_inputs
== 1) {
969 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
974 /* These were lowered to a move, so apply the corresponding mod */
976 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
977 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
979 if (instr
->op
== nir_op_fneg
)
980 s
->negate
= !s
->negate
;
982 if (instr
->op
== nir_op_fabs
)
986 bool is_int
= midgard_is_integer_op(op
);
988 midgard_vector_alu alu
= {
990 .reg_mode
= midgard_reg_mode_32
,
991 .dest_override
= midgard_dest_override_none
,
994 /* Writemask only valid for non-SSA NIR */
995 .mask
= expand_writemask(mask_of(nr_components
)),
997 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
)),
998 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
)),
1001 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1004 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1008 /* Late fixup for emulated instructions */
1010 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1011 /* Presently, our second argument is an inline #0 constant.
1012 * Switch over to an embedded 1.0 constant (that can't fit
1013 * inline, since we're 32-bit, not 16-bit like the inline
1016 ins
.ssa_args
.inline_constant
= false;
1017 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1018 ins
.has_constants
= true;
1020 if (instr
->op
== nir_op_b2f32
) {
1021 ins
.constants
[0] = 1.0f
;
1023 /* Type pun it into place */
1025 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1028 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1029 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1030 /* Lots of instructions need a 0 plonked in */
1031 ins
.ssa_args
.inline_constant
= false;
1032 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1033 ins
.has_constants
= true;
1034 ins
.constants
[0] = 0.0f
;
1035 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1036 } else if (instr
->op
== nir_op_inot
) {
1037 /* ~b = ~(b & b), so duplicate the source */
1038 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1039 ins
.alu
.src2
= ins
.alu
.src1
;
1042 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1043 /* To avoid duplicating the lookup tables (probably), true LUT
1044 * instructions can only operate as if they were scalars. Lower
1045 * them here by changing the component. */
1047 uint8_t original_swizzle
[4];
1048 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1050 for (int i
= 0; i
< nr_components
; ++i
) {
1051 /* Mask the associated component, dropping the
1052 * instruction if needed */
1054 ins
.alu
.mask
= (0x3) << (2 * i
);
1055 ins
.alu
.mask
&= alu
.mask
;
1060 for (int j
= 0; j
< 4; ++j
)
1061 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1063 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
));
1064 emit_mir_instruction(ctx
, ins
);
1067 emit_mir_instruction(ctx
, ins
);
1073 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1074 * optimized) versions of UBO #0 */
1078 compiler_context
*ctx
,
1081 nir_src
*indirect_offset
,
1084 /* TODO: half-floats */
1086 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
&& index
== 0) {
1087 /* Fast path: For the first 16 uniforms, direct accesses are
1088 * 0-cycle, since they're just a register fetch in the usual
1089 * case. So, we alias the registers while we're still in
1092 int reg_slot
= 23 - offset
;
1093 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1095 /* Otherwise, read from the 'special' UBO to access
1096 * higher-indexed uniforms, at a performance cost. More
1097 * generally, we're emitting a UBO read instruction. */
1099 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1101 /* TODO: Don't split */
1102 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1103 ins
.load_store
.address
= offset
>> 3;
1105 if (indirect_offset
) {
1106 emit_indirect_offset(ctx
, indirect_offset
);
1107 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1109 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1112 /* TODO respect index */
1114 emit_mir_instruction(ctx
, ins
);
1120 compiler_context
*ctx
,
1121 unsigned dest
, unsigned offset
,
1122 unsigned nr_comp
, unsigned component
,
1123 nir_src
*indirect_offset
)
1125 /* XXX: Half-floats? */
1126 /* TODO: swizzle, mask */
1128 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1129 ins
.load_store
.mask
= mask_of(nr_comp
);
1130 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1132 midgard_varying_parameter p
= {
1134 .interpolation
= midgard_interp_default
,
1135 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1139 memcpy(&u
, &p
, sizeof(p
));
1140 ins
.load_store
.varying_parameters
= u
;
1142 if (indirect_offset
) {
1143 /* We need to add in the dynamic index, moved to r27.w */
1144 emit_indirect_offset(ctx
, indirect_offset
);
1145 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1147 /* Just a direct load */
1148 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1151 emit_mir_instruction(ctx
, ins
);
1155 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1158 /* Figure out which uniform this is */
1159 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1160 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1162 /* Sysvals are prefix uniforms */
1163 unsigned uniform
= ((uintptr_t) val
) - 1;
1165 /* Emit the read itself -- this is never indirect */
1166 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1169 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1170 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1171 * generations have faster vectorized reads. This operation is for blend
1172 * shaders in particular; reading the tilebuffer from the fragment shader
1173 * remains an open problem. */
1176 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1178 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1179 ins
.load_store
.swizzle
= 0; /* xxxx */
1181 /* Read each component sequentially */
1183 for (unsigned c
= 0; c
< 4; ++c
) {
1184 ins
.load_store
.mask
= (1 << c
);
1185 ins
.load_store
.unknown
= c
;
1186 emit_mir_instruction(ctx
, ins
);
1189 /* vadd.u2f hr2, zext(hr2), #0 */
1191 midgard_vector_alu_src alu_src
= blank_alu_src
;
1192 alu_src
.mod
= midgard_int_zero_extend
;
1193 alu_src
.half
= true;
1195 midgard_instruction u2f
= {
1199 .src1
= SSA_UNUSED_0
,
1201 .inline_constant
= true
1204 .op
= midgard_alu_op_u2f_rtz
,
1205 .reg_mode
= midgard_reg_mode_16
,
1206 .dest_override
= midgard_dest_override_none
,
1208 .src1
= vector_alu_srco_unsigned(alu_src
),
1209 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1213 emit_mir_instruction(ctx
, u2f
);
1215 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1219 midgard_instruction fmul
= {
1221 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1225 .src1
= SSA_UNUSED_0
,
1226 .inline_constant
= true
1229 .op
= midgard_alu_op_fmul
,
1230 .reg_mode
= midgard_reg_mode_32
,
1231 .dest_override
= midgard_dest_override_none
,
1232 .outmod
= midgard_outmod_sat
,
1234 .src1
= vector_alu_srco_unsigned(alu_src
),
1235 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1239 emit_mir_instruction(ctx
, fmul
);
1243 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1245 unsigned offset
= 0, reg
;
1247 switch (instr
->intrinsic
) {
1248 case nir_intrinsic_discard_if
:
1249 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1253 case nir_intrinsic_discard
: {
1254 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1255 struct midgard_instruction discard
= v_branch(conditional
, false);
1256 discard
.branch
.target_type
= TARGET_DISCARD
;
1257 emit_mir_instruction(ctx
, discard
);
1259 ctx
->can_discard
= true;
1263 case nir_intrinsic_load_uniform
:
1264 case nir_intrinsic_load_ubo
:
1265 case nir_intrinsic_load_input
: {
1266 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1267 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1270 offset
= nir_intrinsic_base(instr
);
1273 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1275 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1277 bool direct
= nir_src_is_const(*src_offset
);
1280 offset
+= nir_src_as_uint(*src_offset
);
1282 /* We may need to apply a fractional offset */
1283 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1284 nir_intrinsic_component(instr
) : 0;
1285 reg
= nir_dest_index(ctx
, &instr
->dest
);
1287 if (is_uniform
&& !ctx
->is_blend
) {
1288 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1289 } else if (is_ubo
) {
1290 nir_src index
= instr
->src
[0];
1292 /* We don't yet support indirect UBOs. For indirect
1293 * block numbers (if that's possible), we don't know
1294 * enough about the hardware yet. For indirect sources,
1295 * we know what we need but we need to add some NIR
1296 * support for lowering correctly with respect to
1299 assert(nir_src_is_const(index
));
1300 assert(nir_src_is_const(*src_offset
));
1302 /* TODO: Alignment */
1303 assert((offset
& 0xF) == 0);
1305 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1306 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1307 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1308 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
);
1309 } else if (ctx
->is_blend
) {
1310 /* For blend shaders, load the input color, which is
1311 * preloaded to r0 */
1313 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1314 emit_mir_instruction(ctx
, move
);
1315 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1316 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1317 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1318 ins
.load_store
.mask
= mask_of(nr_comp
);
1319 emit_mir_instruction(ctx
, ins
);
1321 DBG("Unknown load\n");
1328 case nir_intrinsic_load_output
:
1329 assert(nir_src_is_const(instr
->src
[0]));
1330 reg
= nir_dest_index(ctx
, &instr
->dest
);
1332 if (ctx
->is_blend
) {
1334 emit_fb_read_blend_scalar(ctx
, reg
);
1336 DBG("Unknown output load\n");
1342 case nir_intrinsic_load_blend_const_color_rgba
: {
1343 assert(ctx
->is_blend
);
1344 reg
= nir_dest_index(ctx
, &instr
->dest
);
1346 /* Blend constants are embedded directly in the shader and
1347 * patched in, so we use some magic routing */
1349 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1350 ins
.has_constants
= true;
1351 ins
.has_blend_constant
= true;
1352 emit_mir_instruction(ctx
, ins
);
1356 case nir_intrinsic_store_output
:
1357 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1359 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1361 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1363 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1364 /* gl_FragColor is not emitted with load/store
1365 * instructions. Instead, it gets plonked into
1366 * r0 at the end of the shader and we do the
1367 * framebuffer writeout dance. TODO: Defer
1370 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1371 emit_mir_instruction(ctx
, move
);
1373 /* Save the index we're writing to for later reference
1374 * in the epilogue */
1376 ctx
->fragment_output
= reg
;
1377 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1378 /* Varyings are written into one of two special
1379 * varying register, r26 or r27. The register itself is
1380 * selected as the register in the st_vary instruction,
1381 * minus the base of 26. E.g. write into r27 and then
1382 * call st_vary(1) */
1384 midgard_instruction ins
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1385 emit_mir_instruction(ctx
, ins
);
1387 /* We should have been vectorized, though we don't
1388 * currently check that st_vary is emitted only once
1389 * per slot (this is relevant, since there's not a mask
1390 * parameter available on the store [set to 0 by the
1391 * blob]). We do respect the component by adjusting the
1394 unsigned component
= nir_intrinsic_component(instr
);
1396 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1397 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1398 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1399 emit_mir_instruction(ctx
, st
);
1401 DBG("Unknown store\n");
1407 case nir_intrinsic_load_alpha_ref_float
:
1408 assert(instr
->dest
.is_ssa
);
1410 float ref_value
= ctx
->alpha_ref
;
1412 float *v
= ralloc_array(NULL
, float, 4);
1413 memcpy(v
, &ref_value
, sizeof(float));
1414 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1417 case nir_intrinsic_load_viewport_scale
:
1418 case nir_intrinsic_load_viewport_offset
:
1419 emit_sysval_read(ctx
, &instr
->instr
);
1423 printf ("Unhandled intrinsic\n");
1430 midgard_tex_format(enum glsl_sampler_dim dim
)
1433 case GLSL_SAMPLER_DIM_1D
:
1434 case GLSL_SAMPLER_DIM_BUF
:
1437 case GLSL_SAMPLER_DIM_2D
:
1438 case GLSL_SAMPLER_DIM_EXTERNAL
:
1441 case GLSL_SAMPLER_DIM_3D
:
1444 case GLSL_SAMPLER_DIM_CUBE
:
1445 return MALI_TEX_CUBE
;
1448 DBG("Unknown sampler dim type\n");
1455 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1456 unsigned midgard_texop
)
1459 //assert (!instr->sampler);
1460 //assert (!instr->texture_array_size);
1462 /* Allocate registers via a round robin scheme to alternate between the two registers */
1463 int reg
= ctx
->texture_op_count
& 1;
1464 int in_reg
= reg
, out_reg
= reg
;
1466 /* Make room for the reg */
1468 if (ctx
->texture_index
[reg
] > -1)
1469 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1471 int texture_index
= instr
->texture_index
;
1472 int sampler_index
= texture_index
;
1474 unsigned position_swizzle
= 0;
1476 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1477 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1478 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1479 int nr_comp
= nir_src_num_components(instr
->src
[i
].src
);
1480 midgard_vector_alu_src alu_src
= blank_alu_src
;
1482 switch (instr
->src
[i
].src_type
) {
1483 case nir_tex_src_coord
: {
1484 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1485 /* For cubemaps, we need to load coords into
1486 * special r27, and then use a special ld/st op
1487 * to select the face and copy the xy into the
1488 * texture register */
1490 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1492 midgard_instruction move
= v_mov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1493 emit_mir_instruction(ctx
, move
);
1495 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1496 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1497 st
.load_store
.mask
= 0x3; /* xy */
1498 st
.load_store
.swizzle
= alu_src
.swizzle
;
1499 emit_mir_instruction(ctx
, st
);
1501 position_swizzle
= swizzle_of(2);
1503 position_swizzle
= alu_src
.swizzle
= swizzle_of(nr_comp
);
1505 midgard_instruction ins
= v_mov(index
, alu_src
, reg
);
1506 ins
.alu
.mask
= expand_writemask(mask_of(nr_comp
));
1507 emit_mir_instruction(ctx
, ins
);
1509 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1510 /* Texel fetch opcodes care about the
1511 * values of z and w, so we actually
1512 * need to spill into a second register
1513 * for a texel fetch with register bias
1514 * (for non-2D). TODO: Implement that
1517 assert(instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
);
1519 midgard_instruction zero
= v_mov(index
, alu_src
, reg
);
1520 zero
.ssa_args
.inline_constant
= true;
1521 zero
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1522 zero
.has_constants
= true;
1523 zero
.alu
.mask
= ~ins
.alu
.mask
;
1524 emit_mir_instruction(ctx
, zero
);
1526 position_swizzle
= SWIZZLE_XYZZ
;
1528 /* To the hardware, z is depth, w is array
1529 * layer. To NIR, z is array layer for a 2D
1532 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
)
1533 position_swizzle
= SWIZZLE_XYXZ
;
1540 case nir_tex_src_bias
:
1541 case nir_tex_src_lod
: {
1542 /* To keep RA simple, we put the bias/LOD into the w
1543 * component of the input source, which is otherwise in xy */
1545 alu_src
.swizzle
= SWIZZLE_XXXX
;
1547 midgard_instruction ins
= v_mov(index
, alu_src
, reg
);
1548 ins
.alu
.mask
= expand_writemask(1 << COMPONENT_W
);
1549 emit_mir_instruction(ctx
, ins
);
1554 unreachable("Unknown texture source type\n");
1558 /* No helper to build texture words -- we do it all here */
1559 midgard_instruction ins
= {
1560 .type
= TAG_TEXTURE_4
,
1562 .op
= midgard_texop
,
1563 .format
= midgard_tex_format(instr
->sampler_dim
),
1564 .texture_handle
= texture_index
,
1565 .sampler_handle
= sampler_index
,
1567 /* TODO: Regalloc it in */
1568 .swizzle
= SWIZZLE_XYZW
,
1573 .in_reg_swizzle
= position_swizzle
,
1581 /* Set registers to read and write from the same place */
1582 ins
.texture
.in_reg_select
= in_reg
;
1583 ins
.texture
.out_reg_select
= out_reg
;
1585 /* Setup bias/LOD if necessary. Only register mode support right now.
1586 * TODO: Immediate mode for performance gains */
1589 instr
->op
== nir_texop_txb
||
1590 instr
->op
== nir_texop_txl
||
1591 instr
->op
== nir_texop_txf
;
1594 ins
.texture
.lod_register
= true;
1596 midgard_tex_register_select sel
= {
1606 memcpy(&packed
, &sel
, sizeof(packed
));
1607 ins
.texture
.bias
= packed
;
1610 emit_mir_instruction(ctx
, ins
);
1612 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1614 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1615 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1616 ctx
->texture_index
[reg
] = o_index
;
1618 midgard_instruction ins2
= v_mov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1619 emit_mir_instruction(ctx
, ins2
);
1621 /* Used for .cont and .last hinting */
1622 ctx
->texture_op_count
++;
1626 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1628 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1629 * generic tex in some cases (which confuses the hardware) */
1631 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1633 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1634 instr
->op
= nir_texop_txl
;
1636 switch (instr
->op
) {
1639 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1642 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1645 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1648 emit_sysval_read(ctx
, &instr
->instr
);
1651 unreachable("Unhanlded texture op");
1656 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1658 switch (instr
->type
) {
1659 case nir_jump_break
: {
1660 /* Emit a branch out of the loop */
1661 struct midgard_instruction br
= v_branch(false, false);
1662 br
.branch
.target_type
= TARGET_BREAK
;
1663 br
.branch
.target_break
= ctx
->current_loop_depth
;
1664 emit_mir_instruction(ctx
, br
);
1671 DBG("Unknown jump type %d\n", instr
->type
);
1677 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1679 switch (instr
->type
) {
1680 case nir_instr_type_load_const
:
1681 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1684 case nir_instr_type_intrinsic
:
1685 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1688 case nir_instr_type_alu
:
1689 emit_alu(ctx
, nir_instr_as_alu(instr
));
1692 case nir_instr_type_tex
:
1693 emit_tex(ctx
, nir_instr_as_tex(instr
));
1696 case nir_instr_type_jump
:
1697 emit_jump(ctx
, nir_instr_as_jump(instr
));
1700 case nir_instr_type_ssa_undef
:
1705 DBG("Unhandled instruction type\n");
1711 /* ALU instructions can inline or embed constants, which decreases register
1712 * pressure and saves space. */
1714 #define CONDITIONAL_ATTACH(src) { \
1715 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1718 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1719 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1724 inline_alu_constants(compiler_context
*ctx
)
1726 mir_foreach_instr(ctx
, alu
) {
1727 /* Other instructions cannot inline constants */
1728 if (alu
->type
!= TAG_ALU_4
) continue;
1730 /* If there is already a constant here, we can do nothing */
1731 if (alu
->has_constants
) continue;
1733 /* It makes no sense to inline constants on a branch */
1734 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1736 CONDITIONAL_ATTACH(src0
);
1738 if (!alu
->has_constants
) {
1739 CONDITIONAL_ATTACH(src1
)
1740 } else if (!alu
->inline_constant
) {
1741 /* Corner case: _two_ vec4 constants, for instance with a
1742 * csel. For this case, we can only use a constant
1743 * register for one, we'll have to emit a move for the
1744 * other. Note, if both arguments are constants, then
1745 * necessarily neither argument depends on the value of
1746 * any particular register. As the destination register
1747 * will be wiped, that means we can spill the constant
1748 * to the destination register.
1751 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1752 unsigned scratch
= alu
->ssa_args
.dest
;
1755 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1756 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1758 /* Force a break XXX Defer r31 writes */
1759 ins
.unit
= UNIT_VLUT
;
1761 /* Set the source */
1762 alu
->ssa_args
.src1
= scratch
;
1764 /* Inject us -before- the last instruction which set r31 */
1765 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1771 /* Midgard supports two types of constants, embedded constants (128-bit) and
1772 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1773 * constants can be demoted to inline constants, for space savings and
1774 * sometimes a performance boost */
1777 embedded_to_inline_constant(compiler_context
*ctx
)
1779 mir_foreach_instr(ctx
, ins
) {
1780 if (!ins
->has_constants
) continue;
1782 if (ins
->ssa_args
.inline_constant
) continue;
1784 /* Blend constants must not be inlined by definition */
1785 if (ins
->has_blend_constant
) continue;
1787 /* src1 cannot be an inline constant due to encoding
1788 * restrictions. So, if possible we try to flip the arguments
1791 int op
= ins
->alu
.op
;
1793 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1795 /* These ops require an operational change to flip
1796 * their arguments TODO */
1797 case midgard_alu_op_flt
:
1798 case midgard_alu_op_fle
:
1799 case midgard_alu_op_ilt
:
1800 case midgard_alu_op_ile
:
1801 case midgard_alu_op_fcsel
:
1802 case midgard_alu_op_icsel
:
1803 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1808 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1809 /* Flip the SSA numbers */
1810 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1811 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1813 /* And flip the modifiers */
1817 src_temp
= ins
->alu
.src2
;
1818 ins
->alu
.src2
= ins
->alu
.src1
;
1819 ins
->alu
.src1
= src_temp
;
1823 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1824 /* Extract the source information */
1826 midgard_vector_alu_src
*src
;
1827 int q
= ins
->alu
.src2
;
1828 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1831 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1832 int component
= src
->swizzle
& 3;
1834 /* Scale constant appropriately, if we can legally */
1835 uint16_t scaled_constant
= 0;
1837 if (midgard_is_integer_op(op
)) {
1838 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1839 scaled_constant
= (uint16_t) iconstants
[component
];
1841 /* Constant overflow after resize */
1842 if (scaled_constant
!= iconstants
[component
])
1845 float original
= (float) ins
->constants
[component
];
1846 scaled_constant
= _mesa_float_to_half(original
);
1848 /* Check for loss of precision. If this is
1849 * mediump, we don't care, but for a highp
1850 * shader, we need to pay attention. NIR
1851 * doesn't yet tell us which mode we're in!
1852 * Practically this prevents most constants
1853 * from being inlined, sadly. */
1855 float fp32
= _mesa_half_to_float(scaled_constant
);
1857 if (fp32
!= original
)
1861 /* We don't know how to handle these with a constant */
1863 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1864 DBG("Bailing inline constant...\n");
1868 /* Make sure that the constant is not itself a
1869 * vector by checking if all accessed values
1870 * (by the swizzle) are the same. */
1872 uint32_t *cons
= (uint32_t *) ins
->constants
;
1873 uint32_t value
= cons
[component
];
1875 bool is_vector
= false;
1876 unsigned mask
= effective_writemask(&ins
->alu
);
1878 for (int c
= 1; c
< 4; ++c
) {
1879 /* We only care if this component is actually used */
1880 if (!(mask
& (1 << c
)))
1883 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1885 if (test
!= value
) {
1894 /* Get rid of the embedded constant */
1895 ins
->has_constants
= false;
1896 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1897 ins
->ssa_args
.inline_constant
= true;
1898 ins
->inline_constant
= scaled_constant
;
1903 /* Map normal SSA sources to other SSA sources / fixed registers (like
1907 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
1909 /* Sign is used quite deliberately for unused */
1913 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
1916 /* Remove entry in leftovers to avoid a redunant fmov */
1918 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
1921 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
1923 /* Assign the alias map */
1929 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1930 * texture pipeline */
1933 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
1935 bool progress
= false;
1937 mir_foreach_instr_in_block_safe(block
, ins
) {
1938 if (ins
->type
!= TAG_ALU_4
) continue;
1939 if (ins
->compact_branch
) continue;
1941 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1942 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
1944 mir_remove_instruction(ins
);
1951 /* Dead code elimination for branches at the end of a block - only one branch
1952 * per block is legal semantically */
1955 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1957 bool branched
= false;
1959 mir_foreach_instr_in_block_safe(block
, ins
) {
1960 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1962 /* We ignore prepacked branches since the fragment epilogue is
1963 * just generally special */
1964 if (ins
->prepacked_branch
) continue;
1966 /* Discards are similarly special and may not correspond to the
1969 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
1972 /* We already branched, so this is dead */
1973 mir_remove_instruction(ins
);
1981 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
1984 if (!is_int
&& src
.mod
) return true;
1987 for (unsigned c
= 0; c
< 4; ++c
) {
1988 if (!(mask
& (1 << c
))) continue;
1989 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
1996 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
1998 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
1999 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2001 midgard_vector_alu_src src2
=
2002 vector_alu_from_unsigned(ins
->alu
.src2
);
2004 return mir_nontrivial_mod(src2
, is_int
, mask
);
2008 mir_nontrivial_outmod(midgard_instruction
*ins
)
2010 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2011 unsigned mod
= ins
->alu
.outmod
;
2014 return mod
!= midgard_outmod_int_wrap
;
2016 return mod
!= midgard_outmod_none
;
2020 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
2022 bool progress
= false;
2024 mir_foreach_instr_in_block_safe(block
, ins
) {
2025 if (ins
->type
!= TAG_ALU_4
) continue;
2026 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2028 unsigned from
= ins
->ssa_args
.src1
;
2029 unsigned to
= ins
->ssa_args
.dest
;
2031 /* We only work on pure SSA */
2033 if (to
>= SSA_FIXED_MINIMUM
) continue;
2034 if (from
>= SSA_FIXED_MINIMUM
) continue;
2035 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
2036 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2038 /* Constant propagation is not handled here, either */
2039 if (ins
->ssa_args
.inline_constant
) continue;
2040 if (ins
->has_constants
) continue;
2042 if (mir_nontrivial_source2_mod(ins
)) continue;
2043 if (mir_nontrivial_outmod(ins
)) continue;
2045 /* We're clear -- rewrite */
2046 mir_rewrite_index_src(ctx
, to
, from
);
2047 mir_remove_instruction(ins
);
2054 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2055 * the move can be propagated away entirely */
2058 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2061 if (comp
== midgard_outmod_none
)
2064 if (*outmod
== midgard_outmod_none
) {
2069 /* TODO: Compose rules */
2074 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2076 bool progress
= false;
2078 mir_foreach_instr_in_block_safe(block
, ins
) {
2079 if (ins
->type
!= TAG_ALU_4
) continue;
2080 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2081 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2083 /* TODO: Registers? */
2084 unsigned src
= ins
->ssa_args
.src1
;
2085 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
2086 assert(!mir_has_multiple_writes(ctx
, src
));
2088 /* There might be a source modifier, too */
2089 if (mir_nontrivial_source2_mod(ins
)) continue;
2091 /* Backpropagate the modifier */
2092 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2093 if (v
->type
!= TAG_ALU_4
) continue;
2094 if (v
->ssa_args
.dest
!= src
) continue;
2096 /* Can we even take a float outmod? */
2097 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2099 midgard_outmod_float temp
= v
->alu
.outmod
;
2100 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2102 /* Throw in the towel.. */
2103 if (!progress
) break;
2105 /* Otherwise, transfer the modifier */
2106 v
->alu
.outmod
= temp
;
2107 ins
->alu
.outmod
= midgard_outmod_none
;
2117 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
2119 bool progress
= false;
2121 mir_foreach_instr_in_block_safe(block
, ins
) {
2122 if (ins
->type
!= TAG_ALU_4
) continue;
2123 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2125 unsigned from
= ins
->ssa_args
.src1
;
2126 unsigned to
= ins
->ssa_args
.dest
;
2128 /* Make sure it's simple enough for us to handle */
2130 if (from
>= SSA_FIXED_MINIMUM
) continue;
2131 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2132 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
2133 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
2135 bool eliminated
= false;
2137 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2138 /* The texture registers are not SSA so be careful.
2139 * Conservatively, just stop if we hit a texture op
2140 * (even if it may not write) to where we are */
2142 if (v
->type
!= TAG_ALU_4
)
2145 if (v
->ssa_args
.dest
== from
) {
2146 /* We don't want to track partial writes ... */
2147 if (v
->alu
.mask
== 0xF) {
2148 v
->ssa_args
.dest
= to
;
2157 mir_remove_instruction(ins
);
2159 progress
|= eliminated
;
2165 /* The following passes reorder MIR instructions to enable better scheduling */
2168 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2170 mir_foreach_instr_in_block_safe(block
, ins
) {
2171 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2173 /* We've found a load/store op. Check if next is also load/store. */
2174 midgard_instruction
*next_op
= mir_next_op(ins
);
2175 if (&next_op
->link
!= &block
->instructions
) {
2176 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2177 /* If so, we're done since we're a pair */
2178 ins
= mir_next_op(ins
);
2182 /* Maximum search distance to pair, to avoid register pressure disasters */
2183 int search_distance
= 8;
2185 /* Otherwise, we have an orphaned load/store -- search for another load */
2186 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2187 /* Terminate search if necessary */
2188 if (!(search_distance
--)) break;
2190 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2192 /* Stores cannot be reordered, since they have
2193 * dependencies. For the same reason, indirect
2194 * loads cannot be reordered as their index is
2195 * loaded in r27.w */
2197 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2199 /* It appears the 0x800 bit is set whenever a
2200 * load is direct, unset when it is indirect.
2201 * Skip indirect loads. */
2203 if (!(c
->load_store
.unknown
& 0x800)) continue;
2205 /* We found one! Move it up to pair and remove it from the old location */
2207 mir_insert_instruction_before(ins
, *c
);
2208 mir_remove_instruction(c
);
2216 /* If there are leftovers after the below pass, emit actual fmov
2217 * instructions for the slow-but-correct path */
2220 emit_leftover_move(compiler_context
*ctx
)
2222 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2223 int base
= ((uintptr_t) leftover
->key
) - 1;
2226 map_ssa_to_alias(ctx
, &mapped
);
2227 EMIT(mov
, mapped
, blank_alu_src
, base
);
2232 actualise_ssa_to_alias(compiler_context
*ctx
)
2234 mir_foreach_instr(ctx
, ins
) {
2235 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2236 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2239 emit_leftover_move(ctx
);
2243 emit_fragment_epilogue(compiler_context
*ctx
)
2245 /* Special case: writing out constants requires us to include the move
2246 * explicitly now, so shove it into r0 */
2248 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2250 if (constant_value
) {
2251 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2252 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2253 emit_mir_instruction(ctx
, ins
);
2256 /* Perform the actual fragment writeout. We have two writeout/branch
2257 * instructions, forming a loop until writeout is successful as per the
2258 * docs. TODO: gl_FragDepth */
2260 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2261 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2264 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2265 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2266 * with the int8 analogue to the fragment epilogue */
2269 emit_blend_epilogue(compiler_context
*ctx
)
2271 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2273 midgard_instruction scale
= {
2276 .inline_constant
= _mesa_float_to_half(255.0),
2278 .src0
= SSA_FIXED_REGISTER(0),
2279 .src1
= SSA_UNUSED_0
,
2280 .dest
= SSA_FIXED_REGISTER(24),
2281 .inline_constant
= true
2284 .op
= midgard_alu_op_fmul
,
2285 .reg_mode
= midgard_reg_mode_32
,
2286 .dest_override
= midgard_dest_override_lower
,
2288 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2289 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2293 emit_mir_instruction(ctx
, scale
);
2295 /* vadd.f2u_rte.pos.low hr0, hr48, #0 */
2297 midgard_vector_alu_src alu_src
= blank_alu_src
;
2298 alu_src
.half
= true;
2300 midgard_instruction f2u_rte
= {
2303 .src0
= SSA_FIXED_REGISTER(24),
2304 .src1
= SSA_UNUSED_0
,
2305 .dest
= SSA_FIXED_REGISTER(0),
2306 .inline_constant
= true
2309 .op
= midgard_alu_op_f2u_rte
,
2310 .reg_mode
= midgard_reg_mode_16
,
2311 .dest_override
= midgard_dest_override_lower
,
2312 .outmod
= midgard_outmod_pos
,
2314 .src1
= vector_alu_srco_unsigned(alu_src
),
2315 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2319 emit_mir_instruction(ctx
, f2u_rte
);
2321 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2322 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2325 static midgard_block
*
2326 emit_block(compiler_context
*ctx
, nir_block
*block
)
2328 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2329 list_addtail(&this_block
->link
, &ctx
->blocks
);
2331 this_block
->is_scheduled
= false;
2334 ctx
->texture_index
[0] = -1;
2335 ctx
->texture_index
[1] = -1;
2337 /* Add us as a successor to the block we are following */
2338 if (ctx
->current_block
)
2339 midgard_block_add_successor(ctx
->current_block
, this_block
);
2341 /* Set up current block */
2342 list_inithead(&this_block
->instructions
);
2343 ctx
->current_block
= this_block
;
2345 nir_foreach_instr(instr
, block
) {
2346 emit_instr(ctx
, instr
);
2347 ++ctx
->instruction_count
;
2350 inline_alu_constants(ctx
);
2351 embedded_to_inline_constant(ctx
);
2353 /* Perform heavylifting for aliasing */
2354 actualise_ssa_to_alias(ctx
);
2356 midgard_pair_load_store(ctx
, this_block
);
2358 /* Append fragment shader epilogue (value writeout) */
2359 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2360 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2362 emit_blend_epilogue(ctx
);
2364 emit_fragment_epilogue(ctx
);
2368 if (block
== nir_start_block(ctx
->func
->impl
))
2369 ctx
->initial_block
= this_block
;
2371 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2372 ctx
->final_block
= this_block
;
2374 /* Allow the next control flow to access us retroactively, for
2376 ctx
->current_block
= this_block
;
2378 /* Document the fallthrough chain */
2379 ctx
->previous_source_block
= this_block
;
2384 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2387 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2389 /* Conditional branches expect the condition in r31.w; emit a move for
2390 * that in the _previous_ block (which is the current block). */
2391 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2393 /* Speculatively emit the branch, but we can't fill it in until later */
2394 EMIT(branch
, true, true);
2395 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2397 /* Emit the two subblocks */
2398 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2400 /* Emit a jump from the end of the then block to the end of the else */
2401 EMIT(branch
, false, false);
2402 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2404 /* Emit second block, and check if it's empty */
2406 int else_idx
= ctx
->block_count
;
2407 int count_in
= ctx
->instruction_count
;
2408 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2409 int after_else_idx
= ctx
->block_count
;
2411 /* Now that we have the subblocks emitted, fix up the branches */
2416 if (ctx
->instruction_count
== count_in
) {
2417 /* The else block is empty, so don't emit an exit jump */
2418 mir_remove_instruction(then_exit
);
2419 then_branch
->branch
.target_block
= after_else_idx
;
2421 then_branch
->branch
.target_block
= else_idx
;
2422 then_exit
->branch
.target_block
= after_else_idx
;
2427 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2429 /* Remember where we are */
2430 midgard_block
*start_block
= ctx
->current_block
;
2432 /* Allocate a loop number, growing the current inner loop depth */
2433 int loop_idx
= ++ctx
->current_loop_depth
;
2435 /* Get index from before the body so we can loop back later */
2436 int start_idx
= ctx
->block_count
;
2438 /* Emit the body itself */
2439 emit_cf_list(ctx
, &nloop
->body
);
2441 /* Branch back to loop back */
2442 struct midgard_instruction br_back
= v_branch(false, false);
2443 br_back
.branch
.target_block
= start_idx
;
2444 emit_mir_instruction(ctx
, br_back
);
2446 /* Mark down that branch in the graph. Note that we're really branching
2447 * to the block *after* we started in. TODO: Why doesn't the branch
2448 * itself have an off-by-one then...? */
2449 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2451 /* Find the index of the block about to follow us (note: we don't add
2452 * one; blocks are 0-indexed so we get a fencepost problem) */
2453 int break_block_idx
= ctx
->block_count
;
2455 /* Fix up the break statements we emitted to point to the right place,
2456 * now that we can allocate a block number for them */
2458 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2459 mir_foreach_instr_in_block(block
, ins
) {
2460 if (ins
->type
!= TAG_ALU_4
) continue;
2461 if (!ins
->compact_branch
) continue;
2462 if (ins
->prepacked_branch
) continue;
2464 /* We found a branch -- check the type to see if we need to do anything */
2465 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2467 /* It's a break! Check if it's our break */
2468 if (ins
->branch
.target_break
!= loop_idx
) continue;
2470 /* Okay, cool, we're breaking out of this loop.
2471 * Rewrite from a break to a goto */
2473 ins
->branch
.target_type
= TARGET_GOTO
;
2474 ins
->branch
.target_block
= break_block_idx
;
2478 /* Now that we've finished emitting the loop, free up the depth again
2479 * so we play nice with recursion amid nested loops */
2480 --ctx
->current_loop_depth
;
2483 static midgard_block
*
2484 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2486 midgard_block
*start_block
= NULL
;
2488 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2489 switch (node
->type
) {
2490 case nir_cf_node_block
: {
2491 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2494 start_block
= block
;
2499 case nir_cf_node_if
:
2500 emit_if(ctx
, nir_cf_node_as_if(node
));
2503 case nir_cf_node_loop
:
2504 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2507 case nir_cf_node_function
:
2516 /* Due to lookahead, we need to report the first tag executed in the command
2517 * stream and in branch targets. An initial block might be empty, so iterate
2518 * until we find one that 'works' */
2521 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2523 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2525 unsigned first_tag
= 0;
2528 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2530 if (initial_bundle
) {
2531 first_tag
= initial_bundle
->tag
;
2535 /* Initial block is empty, try the next block */
2536 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2537 } while(initial_block
!= NULL
);
2544 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2546 struct util_dynarray
*compiled
= &program
->compiled
;
2548 midgard_debug
= debug_get_option_midgard_debug();
2550 compiler_context ictx
= {
2552 .stage
= nir
->info
.stage
,
2554 .is_blend
= is_blend
,
2555 .blend_constant_offset
= -1,
2557 .alpha_ref
= program
->alpha_ref
2560 compiler_context
*ctx
= &ictx
;
2562 /* TODO: Decide this at runtime */
2563 ctx
->uniform_cutoff
= 8;
2565 /* Initialize at a global (not block) level hash tables */
2567 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2568 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2569 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2570 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2571 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2573 /* Record the varying mapping for the command stream's bookkeeping */
2575 struct exec_list
*varyings
=
2576 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2578 unsigned max_varying
= 0;
2579 nir_foreach_variable(var
, varyings
) {
2580 unsigned loc
= var
->data
.driver_location
;
2581 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2583 for (int c
= 0; c
< sz
; ++c
) {
2584 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2585 max_varying
= MAX2(max_varying
, loc
+ c
);
2589 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2590 * (so we don't accidentally duplicate the epilogue since mesa/st has
2591 * messed with our I/O quite a bit already) */
2593 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2595 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2596 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2598 NIR_PASS_V(nir
, nir_lower_var_copies
);
2599 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2600 NIR_PASS_V(nir
, nir_split_var_copies
);
2601 NIR_PASS_V(nir
, nir_lower_var_copies
);
2602 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2603 NIR_PASS_V(nir
, nir_lower_var_copies
);
2604 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2606 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2608 /* Optimisation passes */
2612 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2613 nir_print_shader(nir
, stdout
);
2616 /* Assign sysvals and counts, now that we're sure
2617 * (post-optimisation) */
2619 midgard_nir_assign_sysvals(ctx
, nir
);
2621 program
->uniform_count
= nir
->num_uniforms
;
2622 program
->sysval_count
= ctx
->sysval_count
;
2623 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2625 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2626 program
->varying_count
= max_varying
+ 1; /* Fencepost off-by-one */
2628 nir_foreach_function(func
, nir
) {
2632 list_inithead(&ctx
->blocks
);
2633 ctx
->block_count
= 0;
2636 emit_cf_list(ctx
, &func
->impl
->body
);
2637 emit_block(ctx
, func
->impl
->end_block
);
2639 break; /* TODO: Multi-function shaders */
2642 util_dynarray_init(compiled
, NULL
);
2644 /* MIR-level optimizations */
2646 bool progress
= false;
2651 mir_foreach_block(ctx
, block
) {
2652 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2653 progress
|= midgard_opt_copy_prop(ctx
, block
);
2654 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
2655 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2659 /* Nested control-flow can result in dead branches at the end of the
2660 * block. This messes with our analysis and is just dead code, so cull
2662 mir_foreach_block(ctx
, block
) {
2663 midgard_opt_cull_dead_branch(ctx
, block
);
2667 schedule_program(ctx
);
2669 /* Now that all the bundles are scheduled and we can calculate block
2670 * sizes, emit actual branch instructions rather than placeholders */
2672 int br_block_idx
= 0;
2674 mir_foreach_block(ctx
, block
) {
2675 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2676 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2677 midgard_instruction
*ins
= bundle
->instructions
[c
];
2679 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2681 if (ins
->prepacked_branch
) continue;
2683 /* Parse some basic branch info */
2684 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2685 bool is_conditional
= ins
->branch
.conditional
;
2686 bool is_inverted
= ins
->branch
.invert_conditional
;
2687 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2689 /* Determine the block we're jumping to */
2690 int target_number
= ins
->branch
.target_block
;
2692 /* Report the destination tag */
2693 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2695 /* Count up the number of quadwords we're
2696 * jumping over = number of quadwords until
2697 * (br_block_idx, target_number) */
2699 int quadword_offset
= 0;
2702 /* Jump to the end of the shader. We
2703 * need to include not only the
2704 * following blocks, but also the
2705 * contents of our current block (since
2706 * discard can come in the middle of
2709 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2711 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2712 quadword_offset
+= quadword_size(bun
->tag
);
2715 mir_foreach_block_from(ctx
, blk
, b
) {
2716 quadword_offset
+= b
->quadword_count
;
2719 } else if (target_number
> br_block_idx
) {
2722 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2723 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2726 quadword_offset
+= blk
->quadword_count
;
2729 /* Jump backwards */
2731 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2732 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2735 quadword_offset
-= blk
->quadword_count
;
2739 /* Unconditional extended branches (far jumps)
2740 * have issues, so we always use a conditional
2741 * branch, setting the condition to always for
2742 * unconditional. For compact unconditional
2743 * branches, cond isn't used so it doesn't
2744 * matter what we pick. */
2746 midgard_condition cond
=
2747 !is_conditional
? midgard_condition_always
:
2748 is_inverted
? midgard_condition_false
:
2749 midgard_condition_true
;
2751 midgard_jmp_writeout_op op
=
2752 is_discard
? midgard_jmp_writeout_op_discard
:
2753 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2754 midgard_jmp_writeout_op_branch_cond
;
2757 midgard_branch_extended branch
=
2758 midgard_create_branch_extended(
2763 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2764 } else if (is_conditional
|| is_discard
) {
2765 midgard_branch_cond branch
= {
2767 .dest_tag
= dest_tag
,
2768 .offset
= quadword_offset
,
2772 assert(branch
.offset
== quadword_offset
);
2774 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2776 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2778 midgard_branch_uncond branch
= {
2780 .dest_tag
= dest_tag
,
2781 .offset
= quadword_offset
,
2785 assert(branch
.offset
== quadword_offset
);
2787 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2795 /* Emit flat binary from the instruction arrays. Iterate each block in
2796 * sequence. Save instruction boundaries such that lookahead tags can
2797 * be assigned easily */
2799 /* Cache _all_ bundles in source order for lookahead across failed branches */
2801 int bundle_count
= 0;
2802 mir_foreach_block(ctx
, block
) {
2803 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2805 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2807 mir_foreach_block(ctx
, block
) {
2808 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2809 source_order_bundles
[bundle_idx
++] = bundle
;
2813 int current_bundle
= 0;
2815 /* Midgard prefetches instruction types, so during emission we
2816 * need to lookahead. Unless this is the last instruction, in
2817 * which we return 1. Or if this is the second to last and the
2818 * last is an ALU, then it's also 1... */
2820 mir_foreach_block(ctx
, block
) {
2821 mir_foreach_bundle_in_block(block
, bundle
) {
2824 if (current_bundle
+ 1 < bundle_count
) {
2825 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2827 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2834 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2838 /* TODO: Free deeper */
2839 //util_dynarray_fini(&block->instructions);
2842 free(source_order_bundles
);
2844 /* Report the very first tag executed */
2845 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2847 /* Deal with off-by-one related to the fencepost problem */
2848 program
->work_register_count
= ctx
->work_registers
+ 1;
2850 program
->can_discard
= ctx
->can_discard
;
2851 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2853 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2855 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2856 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);