2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 struct midgard_block
*next_fallthrough
;
175 /* Helpers to generate midgard_instruction's using macro magic, since every
176 * driver seems to do it that way */
178 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
180 #define M_LOAD_STORE(name, rname, uname) \
181 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
182 midgard_instruction i = { \
183 .type = TAG_LOAD_STORE_4, \
190 .op = midgard_op_##name, \
192 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
200 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
201 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
203 const midgard_vector_alu_src blank_alu_src
= {
204 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
207 const midgard_vector_alu_src blank_alu_src_xxxx
= {
208 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
211 const midgard_scalar_alu_src blank_scalar_alu_src
= {
215 /* Used for encoding the unused source of 1-op instructions */
216 const midgard_vector_alu_src zero_alu_src
= { 0 };
218 /* Coerce structs to integer */
221 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
224 memcpy(&u
, &src
, sizeof(src
));
228 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
229 * the corresponding Midgard source */
231 static midgard_vector_alu_src
232 vector_alu_modifiers(nir_alu_src
*src
)
234 if (!src
) return blank_alu_src
;
236 midgard_vector_alu_src alu_src
= {
238 .negate
= src
->negate
,
241 .half
= 0, /* TODO */
242 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
248 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
250 static midgard_instruction
251 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
253 midgard_instruction ins
= {
256 .src0
= SSA_UNUSED_1
,
261 .op
= midgard_alu_op_fmov
,
262 .reg_mode
= midgard_reg_mode_full
,
263 .dest_override
= midgard_dest_override_none
,
265 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
266 .src2
= vector_alu_srco_unsigned(mod
)
273 /* load/store instructions have both 32-bit and 16-bit variants, depending on
274 * whether we are using vectors composed of highp or mediump. At the moment, we
275 * don't support half-floats -- this requires changes in other parts of the
276 * compiler -- therefore the 16-bit versions are commented out. */
278 //M_LOAD(load_attr_16);
279 M_LOAD(load_attr_32
);
280 //M_LOAD(load_vary_16);
281 M_LOAD(load_vary_32
);
282 //M_LOAD(load_uniform_16);
283 M_LOAD(load_uniform_32
);
284 M_LOAD(load_color_buffer_8
);
285 //M_STORE(store_vary_16);
286 M_STORE(store_vary_32
);
287 M_STORE(store_cubemap_coords
);
289 static midgard_instruction
290 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
292 midgard_branch_cond branch
= {
300 memcpy(&compact
, &branch
, sizeof(branch
));
302 midgard_instruction ins
= {
304 .unit
= ALU_ENAB_BR_COMPACT
,
305 .prepacked_branch
= true,
306 .compact_branch
= true,
307 .br_compact
= compact
310 if (op
== midgard_jmp_writeout_op_writeout
)
316 static midgard_instruction
317 v_branch(bool conditional
, bool invert
)
319 midgard_instruction ins
= {
321 .unit
= ALU_ENAB_BRANCH
,
322 .compact_branch
= true,
324 .conditional
= conditional
,
325 .invert_conditional
= invert
332 static midgard_branch_extended
333 midgard_create_branch_extended( midgard_condition cond
,
334 midgard_jmp_writeout_op op
,
336 signed quadword_offset
)
338 /* For unclear reasons, the condition code is repeated 8 times */
339 uint16_t duplicated_cond
=
349 midgard_branch_extended branch
= {
351 .dest_tag
= dest_tag
,
352 .offset
= quadword_offset
,
353 .cond
= duplicated_cond
359 typedef struct midgard_bundle
{
360 /* Tag for the overall bundle */
363 /* Instructions contained by the bundle */
364 int instruction_count
;
365 midgard_instruction instructions
[5];
367 /* Bundle-wide ALU configuration */
370 bool has_embedded_constants
;
372 bool has_blend_constant
;
374 uint16_t register_words
[8];
375 int register_words_count
;
377 uint64_t body_words
[8];
379 int body_words_count
;
382 typedef struct compiler_context
{
384 gl_shader_stage stage
;
386 /* Is internally a blend shader? Depends on stage == FRAGMENT */
389 /* Tracking for blend constant patching */
390 int blend_constant_number
;
391 int blend_constant_offset
;
393 /* Current NIR function */
396 /* Unordered list of midgard_blocks */
398 struct list_head blocks
;
400 midgard_block
*initial_block
;
401 midgard_block
*previous_source_block
;
402 midgard_block
*final_block
;
404 /* List of midgard_instructions emitted for the current block */
405 midgard_block
*current_block
;
407 /* The index corresponding to the current loop, e.g. for breaks/contineus */
410 /* Constants which have been loaded, for later inlining */
411 struct hash_table_u64
*ssa_constants
;
413 /* SSA indices to be outputted to corresponding varying offset */
414 struct hash_table_u64
*ssa_varyings
;
416 /* SSA values / registers which have been aliased. Naively, these
417 * demand a fmov output; instead, we alias them in a later pass to
418 * avoid the wasted op.
420 * A note on encoding: to avoid dynamic memory management here, rather
421 * than ampping to a pointer, we map to the source index; the key
422 * itself is just the destination index. */
424 struct hash_table_u64
*ssa_to_alias
;
425 struct set
*leftover_ssa_to_alias
;
427 /* Actual SSA-to-register for RA */
428 struct hash_table_u64
*ssa_to_register
;
430 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
431 struct hash_table_u64
*hash_to_temp
;
435 /* Uniform IDs for mdg */
436 struct hash_table_u64
*uniform_nir_to_mdg
;
439 /* Just the count of the max register used. Higher count => higher
440 * register pressure */
443 /* Used for cont/last hinting. Increase when a tex op is added.
444 * Decrease when a tex op is removed. */
445 int texture_op_count
;
447 /* Mapping of texture register -> SSA index for unaliasing */
448 int texture_index
[2];
450 /* Count of special uniforms (viewport, etc) in vec4 units */
451 int special_uniforms
;
453 /* If any path hits a discard instruction */
456 /* The number of uniforms allowable for the fast path */
459 /* Count of instructions emitted from NIR overall, across all blocks */
460 int instruction_count
;
462 /* Alpha ref value passed in */
465 /* The index corresponding to the fragment output */
466 unsigned fragment_output
;
469 /* Append instruction to end of current block */
471 static midgard_instruction
*
472 mir_upload_ins(struct midgard_instruction ins
)
474 midgard_instruction
*heap
= malloc(sizeof(ins
));
475 memcpy(heap
, &ins
, sizeof(ins
));
480 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
482 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
486 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
488 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
492 mir_remove_instruction(struct midgard_instruction
*ins
)
494 list_del(&ins
->link
);
497 static midgard_instruction
*
498 mir_prev_op(struct midgard_instruction
*ins
)
500 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
503 static midgard_instruction
*
504 mir_next_op(struct midgard_instruction
*ins
)
506 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
509 static midgard_block
*
510 mir_next_block(struct midgard_block
*blk
)
512 return list_first_entry(&(blk
->link
), midgard_block
, link
);
516 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
517 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
519 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
520 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
521 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
522 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
523 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
524 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
527 static midgard_instruction
*
528 mir_last_in_block(struct midgard_block
*block
)
530 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
533 static midgard_block
*
534 mir_get_block(compiler_context
*ctx
, int idx
)
536 struct list_head
*lst
= &ctx
->blocks
;
541 return (struct midgard_block
*) lst
;
544 /* Pretty printer for internal Midgard IR */
547 print_mir_source(int source
)
549 if (source
>= SSA_FIXED_MINIMUM
) {
550 /* Specific register */
551 int reg
= SSA_REG_FROM_FIXED(source
);
553 /* TODO: Moving threshold */
554 if (reg
> 16 && reg
< 24)
555 printf("u%d", 23 - reg
);
559 printf("%d", source
);
564 print_mir_instruction(midgard_instruction
*ins
)
570 midgard_alu_op op
= ins
->alu
.op
;
571 const char *name
= alu_opcode_names
[op
];
574 printf("%d.", ins
->unit
);
576 printf("%s", name
? name
: "??");
580 case TAG_LOAD_STORE_4
: {
581 midgard_load_store_op op
= ins
->load_store
.op
;
582 const char *name
= load_store_opcode_names
[op
];
589 case TAG_TEXTURE_4
: {
598 ssa_args
*args
= &ins
->ssa_args
;
600 printf(" %d, ", args
->dest
);
602 print_mir_source(args
->src0
);
605 if (args
->inline_constant
)
606 printf("#%d", ins
->inline_constant
);
608 print_mir_source(args
->src1
);
610 if (ins
->has_constants
)
611 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
617 print_mir_block(midgard_block
*block
)
621 mir_foreach_instr_in_block(block
, ins
) {
622 print_mir_instruction(ins
);
631 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
633 ins
->has_constants
= true;
634 memcpy(&ins
->constants
, constants
, 16);
636 /* If this is the special blend constant, mark this instruction */
638 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
639 ins
->has_blend_constant
= true;
643 glsl_type_size(const struct glsl_type
*type
)
645 return glsl_count_attribute_slots(type
, false);
648 /* Lower fdot2 to a vector multiplication followed by channel addition */
650 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
652 if (alu
->op
!= nir_op_fdot2
)
655 b
->cursor
= nir_before_instr(&alu
->instr
);
657 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
658 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
660 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
662 nir_ssa_def
*sum
= nir_fadd(b
,
663 nir_channel(b
, product
, 0),
664 nir_channel(b
, product
, 1));
666 /* Replace the fdot2 with this sum */
667 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
671 midgard_nir_lower_fdot2(nir_shader
*shader
)
673 bool progress
= false;
675 nir_foreach_function(function
, shader
) {
676 if (!function
->impl
) continue;
679 nir_builder
*b
= &_b
;
680 nir_builder_init(b
, function
->impl
);
682 nir_foreach_block(block
, function
->impl
) {
683 nir_foreach_instr_safe(instr
, block
) {
684 if (instr
->type
!= nir_instr_type_alu
) continue;
686 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
687 midgard_nir_lower_fdot2_body(b
, alu
);
693 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
701 optimise_nir(nir_shader
*nir
)
705 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
706 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
708 nir_lower_tex_options lower_tex_options
= {
712 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
717 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
718 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
719 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
720 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
722 NIR_PASS(progress
, nir
, nir_copy_prop
);
723 NIR_PASS(progress
, nir
, nir_opt_dce
);
724 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
725 NIR_PASS(progress
, nir
, nir_opt_cse
);
726 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
727 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
728 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
729 NIR_PASS(progress
, nir
, nir_opt_undef
);
730 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
733 nir_var_function_temp
);
735 /* TODO: Enable vectorize when merged upstream */
736 // NIR_PASS(progress, nir, nir_opt_vectorize);
739 /* Must be run at the end to prevent creation of fsin/fcos ops */
740 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
745 NIR_PASS(progress
, nir
, nir_opt_dce
);
746 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
747 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
748 NIR_PASS(progress
, nir
, nir_copy_prop
);
751 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
752 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
754 /* Lower mods for float ops only. Integer ops don't support modifiers
755 * (saturate doesn't make sense on integers, neg/abs require dedicated
758 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
759 NIR_PASS(progress
, nir
, nir_copy_prop
);
760 NIR_PASS(progress
, nir
, nir_opt_dce
);
762 /* We implement booleans as 32-bit 0/~0 */
763 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
765 /* Take us out of SSA */
766 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
767 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
769 /* We are a vector architecture; write combine where possible */
770 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
771 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
773 NIR_PASS(progress
, nir
, nir_opt_dce
);
776 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
777 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
778 * r0. See the comments in compiler_context */
781 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
783 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
784 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
787 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
790 unalias_ssa(compiler_context
*ctx
, int dest
)
792 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
793 /* TODO: Remove from leftover or no? */
797 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
799 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
803 midgard_is_pinned(compiler_context
*ctx
, int index
)
805 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
808 /* Do not actually emit a load; instead, cache the constant for inlining */
811 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
813 nir_ssa_def def
= instr
->def
;
815 float *v
= ralloc_array(NULL
, float, 4);
816 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
817 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
820 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
824 expand_writemask(unsigned mask
)
828 for (int i
= 0; i
< 4; ++i
)
836 squeeze_writemask(unsigned mask
)
840 for (int i
= 0; i
< 4; ++i
)
841 if (mask
& (3 << (2 * i
)))
848 /* Determines effective writemask, taking quirks and expansion into account */
850 effective_writemask(midgard_vector_alu
*alu
)
852 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
855 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
857 /* If there is a fixed channel count, construct the appropriate mask */
860 return (1 << channel_count
) - 1;
862 /* Otherwise, just squeeze the existing mask */
863 return squeeze_writemask(alu
->mask
);
867 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
869 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
872 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
877 /* If no temp is find, allocate one */
878 temp
= ctx
->temp_count
++;
879 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
881 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
887 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
890 return src
->ssa
->index
;
892 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
896 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
899 return dst
->ssa
.index
;
901 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
905 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
907 return nir_src_index(ctx
, &src
->src
);
910 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
911 * a conditional test) into that register */
914 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
916 /* XXX: Force component correct */
917 int condition
= nir_src_index(ctx
, src
);
919 /* There is no boolean move instruction. Instead, we simulate a move by
920 * ANDing the condition with itself to get it into r31.w */
922 midgard_instruction ins
= {
924 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
928 .dest
= SSA_FIXED_REGISTER(31),
931 .op
= midgard_alu_op_iand
,
932 .reg_mode
= midgard_reg_mode_full
,
933 .dest_override
= midgard_dest_override_none
,
934 .mask
= (0x3 << 6), /* w */
935 .src1
= vector_alu_srco_unsigned(blank_alu_src_xxxx
),
936 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
940 emit_mir_instruction(ctx
, ins
);
943 #define ALU_CASE(nir, _op) \
945 op = midgard_alu_op_##_op; \
949 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
951 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
953 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
954 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
955 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
957 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
958 * supported. A few do not and are commented for now. Also, there are a
959 * number of NIR ops which Midgard does not support and need to be
960 * lowered, also TODO. This switch block emits the opcode and calling
961 * convention of the Midgard instruction; actual packing is done in
967 ALU_CASE(fadd
, fadd
);
968 ALU_CASE(fmul
, fmul
);
969 ALU_CASE(fmin
, fmin
);
970 ALU_CASE(fmax
, fmax
);
971 ALU_CASE(imin
, imin
);
972 ALU_CASE(imax
, imax
);
973 ALU_CASE(fmov
, fmov
);
974 ALU_CASE(ffloor
, ffloor
);
975 ALU_CASE(fround_even
, froundeven
);
976 ALU_CASE(ftrunc
, ftrunc
);
977 ALU_CASE(fceil
, fceil
);
978 ALU_CASE(fdot3
, fdot3
);
979 ALU_CASE(fdot4
, fdot4
);
980 ALU_CASE(iadd
, iadd
);
981 ALU_CASE(isub
, isub
);
982 ALU_CASE(imul
, imul
);
983 ALU_CASE(iabs
, iabs
);
985 /* XXX: Use fmov, not imov, since imov was causing major
986 * issues with texture precision? XXX research */
987 ALU_CASE(imov
, fmov
);
989 ALU_CASE(feq32
, feq
);
990 ALU_CASE(fne32
, fne
);
991 ALU_CASE(flt32
, flt
);
992 ALU_CASE(ieq32
, ieq
);
993 ALU_CASE(ine32
, ine
);
994 ALU_CASE(ilt32
, ilt
);
995 ALU_CASE(ult32
, ult
);
997 /* We don't have a native b2f32 instruction. Instead, like many
998 * GPUs, we exploit booleans as 0/~0 for false/true, and
999 * correspondingly AND
1000 * by 1.0 to do the type conversion. For the moment, prime us
1003 * iand [whatever], #0
1005 * At the end of emit_alu (as MIR), we'll fix-up the constant
1008 ALU_CASE(b2f32
, iand
);
1009 ALU_CASE(b2i32
, iand
);
1011 /* Likewise, we don't have a dedicated f2b32 instruction, but
1012 * we can do a "not equal to 0.0" test. */
1014 ALU_CASE(f2b32
, fne
);
1015 ALU_CASE(i2b32
, ine
);
1017 ALU_CASE(frcp
, frcp
);
1018 ALU_CASE(frsq
, frsqrt
);
1019 ALU_CASE(fsqrt
, fsqrt
);
1020 ALU_CASE(fexp2
, fexp2
);
1021 ALU_CASE(flog2
, flog2
);
1023 ALU_CASE(f2i32
, f2i
);
1024 ALU_CASE(f2u32
, f2u
);
1025 ALU_CASE(i2f32
, i2f
);
1026 ALU_CASE(u2f32
, u2f
);
1028 ALU_CASE(fsin
, fsin
);
1029 ALU_CASE(fcos
, fcos
);
1031 ALU_CASE(iand
, iand
);
1033 ALU_CASE(ixor
, ixor
);
1034 ALU_CASE(inot
, inot
);
1035 ALU_CASE(ishl
, ishl
);
1036 ALU_CASE(ishr
, iasr
);
1037 ALU_CASE(ushr
, ilsr
);
1039 ALU_CASE(b32all_fequal2
, fball_eq
);
1040 ALU_CASE(b32all_fequal3
, fball_eq
);
1041 ALU_CASE(b32all_fequal4
, fball_eq
);
1043 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1044 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1045 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1047 ALU_CASE(b32all_iequal2
, iball_eq
);
1048 ALU_CASE(b32all_iequal3
, iball_eq
);
1049 ALU_CASE(b32all_iequal4
, iball_eq
);
1051 ALU_CASE(b32any_inequal2
, ibany_neq
);
1052 ALU_CASE(b32any_inequal3
, ibany_neq
);
1053 ALU_CASE(b32any_inequal4
, ibany_neq
);
1055 /* For greater-or-equal, we lower to less-or-equal and flip the
1061 case nir_op_uge32
: {
1063 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1064 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1065 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1066 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1069 /* Swap via temporary */
1070 nir_alu_src temp
= instr
->src
[1];
1071 instr
->src
[1] = instr
->src
[0];
1072 instr
->src
[0] = temp
;
1077 case nir_op_b32csel
: {
1078 op
= midgard_alu_op_fcsel
;
1080 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1083 emit_condition(ctx
, &instr
->src
[0].src
, false);
1085 /* The condition is the first argument; move the other
1086 * arguments up one to be a binary instruction for
1089 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1094 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1099 /* Fetch unit, quirks, etc information */
1100 unsigned opcode_props
= alu_opcode_props
[op
];
1101 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1103 /* Initialise fields common between scalar/vector instructions */
1104 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1106 /* src0 will always exist afaik, but src1 will not for 1-argument
1107 * instructions. The latter can only be fetched if the instruction
1108 * needs it, or else we may segfault. */
1110 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1111 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1113 /* Rather than use the instruction generation helpers, we do it
1114 * ourselves here to avoid the mess */
1116 midgard_instruction ins
= {
1119 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1120 .src1
= quirk_flipped_r24
? src0
: src1
,
1125 nir_alu_src
*nirmods
[2] = { NULL
};
1127 if (nr_inputs
== 2) {
1128 nirmods
[0] = &instr
->src
[0];
1129 nirmods
[1] = &instr
->src
[1];
1130 } else if (nr_inputs
== 1) {
1131 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1136 midgard_vector_alu alu
= {
1138 .reg_mode
= midgard_reg_mode_full
,
1139 .dest_override
= midgard_dest_override_none
,
1142 /* Writemask only valid for non-SSA NIR */
1143 .mask
= expand_writemask((1 << nr_components
) - 1),
1145 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1146 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1149 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1152 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1156 /* Late fixup for emulated instructions */
1158 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1159 /* Presently, our second argument is an inline #0 constant.
1160 * Switch over to an embedded 1.0 constant (that can't fit
1161 * inline, since we're 32-bit, not 16-bit like the inline
1164 ins
.ssa_args
.inline_constant
= false;
1165 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1166 ins
.has_constants
= true;
1168 if (instr
->op
== nir_op_b2f32
) {
1169 ins
.constants
[0] = 1.0f
;
1171 /* Type pun it into place */
1173 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1176 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1177 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1178 ins
.ssa_args
.inline_constant
= false;
1179 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1180 ins
.has_constants
= true;
1181 ins
.constants
[0] = 0.0f
;
1182 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1185 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1186 /* To avoid duplicating the lookup tables (probably), true LUT
1187 * instructions can only operate as if they were scalars. Lower
1188 * them here by changing the component. */
1190 uint8_t original_swizzle
[4];
1191 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1193 for (int i
= 0; i
< nr_components
; ++i
) {
1194 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1196 for (int j
= 0; j
< 4; ++j
)
1197 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1199 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1200 emit_mir_instruction(ctx
, ins
);
1203 emit_mir_instruction(ctx
, ins
);
1210 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1212 nir_const_value
*const_offset
;
1213 unsigned offset
, reg
;
1215 switch (instr
->intrinsic
) {
1216 case nir_intrinsic_discard_if
:
1217 emit_condition(ctx
, &instr
->src
[0], true);
1221 case nir_intrinsic_discard
: {
1222 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1223 struct midgard_instruction discard
= v_branch(conditional
, false);
1224 discard
.branch
.target_type
= TARGET_DISCARD
;
1225 emit_mir_instruction(ctx
, discard
);
1227 ctx
->can_discard
= true;
1231 case nir_intrinsic_load_uniform
:
1232 case nir_intrinsic_load_input
:
1233 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1234 assert (const_offset
&& "no indirect inputs");
1236 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1238 reg
= nir_dest_index(ctx
, &instr
->dest
);
1240 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1241 /* TODO: half-floats */
1243 int uniform_offset
= 0;
1245 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1246 /* XXX: Resolve which uniform */
1249 /* Offset away from the special
1252 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1256 DBG("WARNING: Unknown uniform %d\n", offset
);
1260 uniform_offset
= (uintptr_t) (entry
) - 1;
1261 uniform_offset
+= ctx
->special_uniforms
;
1264 if (uniform_offset
< ctx
->uniform_cutoff
) {
1265 /* Fast path: For the first 16 uniform,
1266 * accesses are 0-cycle, since they're
1267 * just a register fetch in the usual
1268 * case. So, we alias the registers
1269 * while we're still in SSA-space */
1271 int reg_slot
= 23 - uniform_offset
;
1272 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1274 /* Otherwise, read from the 'special'
1275 * UBO to access higher-indexed
1276 * uniforms, at a performance cost */
1278 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1280 /* TODO: Don't split */
1281 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1282 ins
.load_store
.address
= uniform_offset
>> 3;
1284 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1285 emit_mir_instruction(ctx
, ins
);
1287 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1288 /* XXX: Half-floats? */
1289 /* TODO: swizzle, mask */
1291 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1293 midgard_varying_parameter p
= {
1295 .interpolation
= midgard_interp_default
,
1296 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1300 memcpy(&u
, &p
, sizeof(p
));
1301 ins
.load_store
.varying_parameters
= u
;
1303 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1304 emit_mir_instruction(ctx
, ins
);
1305 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1306 /* Constant encoded as a pinned constant */
1308 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1309 ins
.has_constants
= true;
1310 ins
.has_blend_constant
= true;
1311 emit_mir_instruction(ctx
, ins
);
1312 } else if (ctx
->is_blend
) {
1313 /* For blend shaders, a load might be
1314 * translated various ways depending on what
1315 * we're loading. Figure out how this is used */
1317 nir_variable
*out
= NULL
;
1319 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1320 int drvloc
= var
->data
.driver_location
;
1322 if (nir_intrinsic_base(instr
) == drvloc
) {
1330 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1331 /* Source color preloaded to r0 */
1333 midgard_pin_output(ctx
, reg
, 0);
1334 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1335 /* Destination color must be read from framebuffer */
1337 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1338 ins
.load_store
.swizzle
= 0; /* xxxx */
1340 /* Read each component sequentially */
1342 for (int c
= 0; c
< 4; ++c
) {
1343 ins
.load_store
.mask
= (1 << c
);
1344 ins
.load_store
.unknown
= c
;
1345 emit_mir_instruction(ctx
, ins
);
1348 /* vadd.u2f hr2, abs(hr2), #0 */
1350 midgard_vector_alu_src alu_src
= blank_alu_src
;
1352 alu_src
.half
= true;
1354 midgard_instruction u2f
= {
1358 .src1
= SSA_UNUSED_0
,
1360 .inline_constant
= true
1363 .op
= midgard_alu_op_u2f
,
1364 .reg_mode
= midgard_reg_mode_half
,
1365 .dest_override
= midgard_dest_override_none
,
1367 .src1
= vector_alu_srco_unsigned(alu_src
),
1368 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1372 emit_mir_instruction(ctx
, u2f
);
1374 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1376 alu_src
.abs
= false;
1378 midgard_instruction fmul
= {
1380 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1384 .src1
= SSA_UNUSED_0
,
1385 .inline_constant
= true
1388 .op
= midgard_alu_op_fmul
,
1389 .reg_mode
= midgard_reg_mode_full
,
1390 .dest_override
= midgard_dest_override_none
,
1391 .outmod
= midgard_outmod_sat
,
1393 .src1
= vector_alu_srco_unsigned(alu_src
),
1394 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1398 emit_mir_instruction(ctx
, fmul
);
1400 DBG("Unknown input in blend shader\n");
1403 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1404 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1405 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1406 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1407 emit_mir_instruction(ctx
, ins
);
1409 DBG("Unknown load\n");
1415 case nir_intrinsic_store_output
:
1416 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1417 assert(const_offset
&& "no indirect outputs");
1419 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1421 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1423 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1424 /* gl_FragColor is not emitted with load/store
1425 * instructions. Instead, it gets plonked into
1426 * r0 at the end of the shader and we do the
1427 * framebuffer writeout dance. TODO: Defer
1430 midgard_pin_output(ctx
, reg
, 0);
1432 /* Save the index we're writing to for later reference
1433 * in the epilogue */
1435 ctx
->fragment_output
= reg
;
1436 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1437 /* Varyings are written into one of two special
1438 * varying register, r26 or r27. The register itself is selected as the register
1439 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1441 * Normally emitting fmov's is frowned upon,
1442 * but due to unique constraints of
1443 * REGISTER_VARYING, fmov emission + a
1444 * dedicated cleanup pass is the only way to
1445 * guarantee correctness when considering some
1446 * (common) edge cases XXX: FIXME */
1448 /* If this varying corresponds to a constant (why?!),
1449 * emit that now since it won't get picked up by
1450 * hoisting (since there is no corresponding move
1451 * emitted otherwise) */
1453 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1455 if (constant_value
) {
1456 /* Special case: emit the varying write
1457 * directly to r26 (looks funny in asm but it's
1458 * fine) and emit the store _now_. Possibly
1459 * slightly slower, but this is a really stupid
1460 * special case anyway (why on earth would you
1461 * have a constant varying? Your own fault for
1462 * slightly worse perf :P) */
1464 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1465 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1466 emit_mir_instruction(ctx
, ins
);
1468 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1469 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1470 emit_mir_instruction(ctx
, st
);
1472 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1474 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1477 DBG("Unknown store\n");
1483 case nir_intrinsic_load_alpha_ref_float
:
1484 assert(instr
->dest
.is_ssa
);
1486 float ref_value
= ctx
->alpha_ref
;
1488 float *v
= ralloc_array(NULL
, float, 4);
1489 memcpy(v
, &ref_value
, sizeof(float));
1490 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1495 printf ("Unhandled intrinsic\n");
1502 midgard_tex_format(enum glsl_sampler_dim dim
)
1505 case GLSL_SAMPLER_DIM_2D
:
1506 case GLSL_SAMPLER_DIM_EXTERNAL
:
1509 case GLSL_SAMPLER_DIM_3D
:
1512 case GLSL_SAMPLER_DIM_CUBE
:
1513 return TEXTURE_CUBE
;
1516 DBG("Unknown sampler dim type\n");
1523 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1526 //assert (!instr->sampler);
1527 //assert (!instr->texture_array_size);
1528 assert (instr
->op
== nir_texop_tex
);
1530 /* Allocate registers via a round robin scheme to alternate between the two registers */
1531 int reg
= ctx
->texture_op_count
& 1;
1532 int in_reg
= reg
, out_reg
= reg
;
1534 /* Make room for the reg */
1536 if (ctx
->texture_index
[reg
] > -1)
1537 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1539 int texture_index
= instr
->texture_index
;
1540 int sampler_index
= texture_index
;
1542 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1543 switch (instr
->src
[i
].src_type
) {
1544 case nir_tex_src_coord
: {
1545 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1547 midgard_vector_alu_src alu_src
= blank_alu_src
;
1549 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1551 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1552 /* For cubemaps, we need to load coords into
1553 * special r27, and then use a special ld/st op
1554 * to copy into the texture register */
1556 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1558 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1559 emit_mir_instruction(ctx
, move
);
1561 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1562 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1563 st
.load_store
.mask
= 0x3; /* xy? */
1564 st
.load_store
.swizzle
= alu_src
.swizzle
;
1565 emit_mir_instruction(ctx
, st
);
1568 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1570 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1571 emit_mir_instruction(ctx
, ins
);
1574 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1580 DBG("Unknown source type\n");
1587 /* No helper to build texture words -- we do it all here */
1588 midgard_instruction ins
= {
1589 .type
= TAG_TEXTURE_4
,
1591 .op
= TEXTURE_OP_NORMAL
,
1592 .format
= midgard_tex_format(instr
->sampler_dim
),
1593 .texture_handle
= texture_index
,
1594 .sampler_handle
= sampler_index
,
1596 /* TODO: Don't force xyzw */
1597 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1609 /* Assume we can continue; hint it out later */
1614 /* Set registers to read and write from the same place */
1615 ins
.texture
.in_reg_select
= in_reg
;
1616 ins
.texture
.out_reg_select
= out_reg
;
1618 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1619 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1620 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1621 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1622 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1624 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1625 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1626 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1629 emit_mir_instruction(ctx
, ins
);
1631 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1633 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1634 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1635 ctx
->texture_index
[reg
] = o_index
;
1637 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1638 emit_mir_instruction(ctx
, ins2
);
1640 /* Used for .cont and .last hinting */
1641 ctx
->texture_op_count
++;
1645 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1647 switch (instr
->type
) {
1648 case nir_jump_break
: {
1649 /* Emit a branch out of the loop */
1650 struct midgard_instruction br
= v_branch(false, false);
1651 br
.branch
.target_type
= TARGET_BREAK
;
1652 br
.branch
.target_break
= ctx
->current_loop
;
1653 emit_mir_instruction(ctx
, br
);
1660 DBG("Unknown jump type %d\n", instr
->type
);
1666 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1668 switch (instr
->type
) {
1669 case nir_instr_type_load_const
:
1670 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1673 case nir_instr_type_intrinsic
:
1674 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1677 case nir_instr_type_alu
:
1678 emit_alu(ctx
, nir_instr_as_alu(instr
));
1681 case nir_instr_type_tex
:
1682 emit_tex(ctx
, nir_instr_as_tex(instr
));
1685 case nir_instr_type_jump
:
1686 emit_jump(ctx
, nir_instr_as_jump(instr
));
1689 case nir_instr_type_ssa_undef
:
1694 DBG("Unhandled instruction type\n");
1699 /* Determine the actual hardware from the index based on the RA results or special values */
1702 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1704 if (reg
>= SSA_FIXED_MINIMUM
)
1705 return SSA_REG_FROM_FIXED(reg
);
1708 assert(reg
< maxreg
);
1709 int r
= ra_get_node_reg(g
, reg
);
1710 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1715 /* fmov style unused */
1717 return REGISTER_UNUSED
;
1719 /* lut style unused */
1721 return REGISTER_UNUSED
;
1724 DBG("Unknown SSA register alias %d\n", reg
);
1731 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1733 /* Choose the first available register to minimise reported register pressure */
1735 for (int i
= 0; i
< 16; ++i
) {
1736 if (BITSET_TEST(regs
, i
)) {
1746 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1748 if (ins
->ssa_args
.src0
== src
) return true;
1749 if (ins
->ssa_args
.src1
== src
) return true;
1755 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1757 /* Check the rest of the block for liveness */
1758 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1759 if (midgard_is_live_in_instr(ins
, src
))
1763 /* Check the rest of the blocks for liveness */
1764 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1765 mir_foreach_instr_in_block(b
, ins
) {
1766 if (midgard_is_live_in_instr(ins
, src
))
1771 /* TODO: How does control flow interact in complex shaders? */
1777 allocate_registers(compiler_context
*ctx
)
1779 /* First, initialize the RA */
1780 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1782 /* Create a primary (general purpose) class, as well as special purpose
1783 * pipeline register classes */
1785 int primary_class
= ra_alloc_reg_class(regs
);
1786 int varying_class
= ra_alloc_reg_class(regs
);
1788 /* Add the full set of work registers */
1789 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1790 for (int i
= 0; i
< work_count
; ++i
)
1791 ra_class_add_reg(regs
, primary_class
, i
);
1793 /* Add special registers */
1794 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1795 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1797 /* We're done setting up */
1798 ra_set_finalize(regs
, NULL
);
1800 /* Transform the MIR into squeezed index form */
1801 mir_foreach_block(ctx
, block
) {
1802 mir_foreach_instr_in_block(block
, ins
) {
1803 if (ins
->compact_branch
) continue;
1805 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1806 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1807 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1809 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1810 print_mir_block(block
);
1813 /* Let's actually do register allocation */
1814 int nodes
= ctx
->temp_count
;
1815 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1817 /* Set everything to the work register class, unless it has somewhere
1820 mir_foreach_block(ctx
, block
) {
1821 mir_foreach_instr_in_block(block
, ins
) {
1822 if (ins
->compact_branch
) continue;
1824 if (ins
->ssa_args
.dest
< 0) continue;
1826 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1828 int class = primary_class
;
1830 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1834 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1835 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1838 unsigned reg
= temp
- 1;
1839 int t
= find_or_allocate_temp(ctx
, index
);
1840 ra_set_node_reg(g
, t
, reg
);
1844 /* Determine liveness */
1846 int *live_start
= malloc(nodes
* sizeof(int));
1847 int *live_end
= malloc(nodes
* sizeof(int));
1849 /* Initialize as non-existent */
1851 for (int i
= 0; i
< nodes
; ++i
) {
1852 live_start
[i
] = live_end
[i
] = -1;
1857 mir_foreach_block(ctx
, block
) {
1858 mir_foreach_instr_in_block(block
, ins
) {
1859 if (ins
->compact_branch
) continue;
1861 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1862 /* If this destination is not yet live, it is now since we just wrote it */
1864 int dest
= ins
->ssa_args
.dest
;
1866 if (live_start
[dest
] == -1)
1867 live_start
[dest
] = d
;
1870 /* Since we just used a source, the source might be
1871 * dead now. Scan the rest of the block for
1872 * invocations, and if there are none, the source dies
1875 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1877 for (int src
= 0; src
< 2; ++src
) {
1878 int s
= sources
[src
];
1880 if (s
< 0) continue;
1882 if (s
>= SSA_FIXED_MINIMUM
) continue;
1884 if (!is_live_after(ctx
, block
, ins
, s
)) {
1893 /* If a node still hasn't been killed, kill it now */
1895 for (int i
= 0; i
< nodes
; ++i
) {
1896 /* live_start == -1 most likely indicates a pinned output */
1898 if (live_end
[i
] == -1)
1902 /* Setup interference between nodes that are live at the same time */
1904 for (int i
= 0; i
< nodes
; ++i
) {
1905 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1906 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1907 ra_add_node_interference(g
, i
, j
);
1911 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1913 if (!ra_allocate(g
)) {
1914 DBG("Error allocating registers\n");
1922 mir_foreach_block(ctx
, block
) {
1923 mir_foreach_instr_in_block(block
, ins
) {
1924 if (ins
->compact_branch
) continue;
1926 ssa_args args
= ins
->ssa_args
;
1928 switch (ins
->type
) {
1930 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1932 ins
->registers
.src2_imm
= args
.inline_constant
;
1934 if (args
.inline_constant
) {
1935 /* Encode inline 16-bit constant as a vector by default */
1937 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1939 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1941 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1942 ins
->alu
.src2
= imm
<< 2;
1944 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1947 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1951 case TAG_LOAD_STORE_4
: {
1952 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
1953 /* TODO: use ssa_args for store_vary */
1954 ins
->load_store
.reg
= 0;
1956 bool has_dest
= args
.dest
>= 0;
1957 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1959 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1972 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1973 * use scalar ALU instructions, for functional or performance reasons. To do
1974 * this, we just demote vector ALU payloads to scalar. */
1977 component_from_mask(unsigned mask
)
1979 for (int c
= 0; c
< 4; ++c
) {
1980 if (mask
& (3 << (2 * c
)))
1989 is_single_component_mask(unsigned mask
)
1993 for (int c
= 0; c
< 4; ++c
)
1994 if (mask
& (3 << (2 * c
)))
1997 return components
== 1;
2000 /* Create a mask of accessed components from a swizzle to figure out vector
2004 swizzle_to_access_mask(unsigned swizzle
)
2006 unsigned component_mask
= 0;
2008 for (int i
= 0; i
< 4; ++i
) {
2009 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2010 component_mask
|= (1 << c
);
2013 return component_mask
;
2017 vector_to_scalar_source(unsigned u
)
2019 midgard_vector_alu_src v
;
2020 memcpy(&v
, &u
, sizeof(v
));
2022 midgard_scalar_alu_src s
= {
2026 .component
= (v
.swizzle
& 3) << 1
2030 memcpy(&o
, &s
, sizeof(s
));
2032 return o
& ((1 << 6) - 1);
2035 static midgard_scalar_alu
2036 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2038 /* The output component is from the mask */
2039 midgard_scalar_alu s
= {
2041 .src1
= vector_to_scalar_source(v
.src1
),
2042 .src2
= vector_to_scalar_source(v
.src2
),
2045 .output_full
= 1, /* TODO: Half */
2046 .output_component
= component_from_mask(v
.mask
) << 1,
2049 /* Inline constant is passed along rather than trying to extract it
2052 if (ins
->ssa_args
.inline_constant
) {
2054 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2055 imm
|= (lower_11
>> 9) & 3;
2056 imm
|= (lower_11
>> 6) & 4;
2057 imm
|= (lower_11
>> 2) & 0x38;
2058 imm
|= (lower_11
& 63) << 6;
2066 /* Midgard prefetches instruction types, so during emission we need to
2067 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2068 * if this is the second to last and the last is an ALU, then it's also 1... */
2070 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2071 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2073 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2074 bytes_emitted += sizeof(type)
2077 emit_binary_vector_instruction(midgard_instruction
*ains
,
2078 uint16_t *register_words
, int *register_words_count
,
2079 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2080 size_t *bytes_emitted
)
2082 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2083 *bytes_emitted
+= sizeof(midgard_reg_info
);
2085 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2086 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2087 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2090 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2091 * mind that we are a vector architecture and we can write to different
2092 * components simultaneously */
2095 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2097 /* Each instruction reads some registers and writes to a register. See
2098 * where the first writes */
2100 /* Figure out where exactly we wrote to */
2101 int source
= first
->ssa_args
.dest
;
2102 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2104 /* As long as the second doesn't read from the first, we're okay */
2105 if (second
->ssa_args
.src0
== source
) {
2106 if (first
->type
== TAG_ALU_4
) {
2107 /* Figure out which components we just read from */
2109 int q
= second
->alu
.src1
;
2110 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2112 /* Check if there are components in common, and fail if so */
2113 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2120 if (second
->ssa_args
.src1
== source
)
2123 /* Otherwise, it's safe in that regard. Another data hazard is both
2124 * writing to the same place, of course */
2126 if (second
->ssa_args
.dest
== source
) {
2127 /* ...but only if the components overlap */
2128 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2130 if (dest_mask
& source_mask
)
2140 midgard_instruction
**segment
, unsigned segment_size
,
2141 midgard_instruction
*ains
)
2143 for (int s
= 0; s
< segment_size
; ++s
)
2144 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2152 /* Schedules, but does not emit, a single basic block. After scheduling, the
2153 * final tag and size of the block are known, which are necessary for branching
2156 static midgard_bundle
2157 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2159 int instructions_emitted
= 0, instructions_consumed
= -1;
2160 midgard_bundle bundle
= { 0 };
2162 uint8_t tag
= ins
->type
;
2164 /* Default to the instruction's tag */
2167 switch (ins
->type
) {
2169 uint32_t control
= 0;
2170 size_t bytes_emitted
= sizeof(control
);
2172 /* TODO: Constant combining */
2173 int index
= 0, last_unit
= 0;
2175 /* Previous instructions, for the purpose of parallelism */
2176 midgard_instruction
*segment
[4] = {0};
2177 int segment_size
= 0;
2179 instructions_emitted
= -1;
2180 midgard_instruction
*pins
= ins
;
2183 midgard_instruction
*ains
= pins
;
2185 /* Advance instruction pointer */
2187 ains
= mir_next_op(pins
);
2191 /* Out-of-work condition */
2192 if ((struct list_head
*) ains
== &block
->instructions
)
2195 /* Ensure that the chain can continue */
2196 if (ains
->type
!= TAG_ALU_4
) break;
2198 /* According to the presentation "The ARM
2199 * Mali-T880 Mobile GPU" from HotChips 27,
2200 * there are two pipeline stages. Branching
2201 * position determined experimentally. Lines
2202 * are executed in parallel:
2205 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2207 * Verify that there are no ordering dependencies here.
2209 * TODO: Allow for parallelism!!!
2212 /* Pick a unit for it if it doesn't force a particular unit */
2214 int unit
= ains
->unit
;
2217 int op
= ains
->alu
.op
;
2218 int units
= alu_opcode_props
[op
];
2220 /* TODO: Promotion of scalars to vectors */
2221 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2224 assert(units
& UNITS_SCALAR
);
2227 if (last_unit
>= UNIT_VADD
) {
2228 if (units
& UNIT_VLUT
)
2233 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2235 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2237 else if (units
& UNIT_VLUT
)
2243 if (last_unit
>= UNIT_VADD
) {
2244 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2246 else if (units
& UNIT_VLUT
)
2251 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2253 else if (units
& UNIT_SMUL
)
2254 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2255 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2262 assert(unit
& units
);
2265 /* Late unit check, this time for encoding (not parallelism) */
2266 if (unit
<= last_unit
) break;
2268 /* Clear the segment */
2269 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2272 if (midgard_has_hazard(segment
, segment_size
, ains
))
2275 /* We're good to go -- emit the instruction */
2278 segment
[segment_size
++] = ains
;
2280 /* Only one set of embedded constants per
2281 * bundle possible; if we have more, we must
2282 * break the chain early, unfortunately */
2284 if (ains
->has_constants
) {
2285 if (bundle
.has_embedded_constants
) {
2286 /* ...but if there are already
2287 * constants but these are the
2288 * *same* constants, we let it
2291 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2294 bundle
.has_embedded_constants
= true;
2295 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2297 /* If this is a blend shader special constant, track it for patching */
2298 if (ains
->has_blend_constant
)
2299 bundle
.has_blend_constant
= true;
2303 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2304 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2305 &bundle
.register_words_count
, bundle
.body_words
,
2306 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2307 } else if (ains
->compact_branch
) {
2308 /* All of r0 has to be written out
2309 * along with the branch writeout.
2312 if (ains
->writeout
) {
2314 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2315 ins
.unit
= UNIT_VMUL
;
2317 control
|= ins
.unit
;
2319 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2320 &bundle
.register_words_count
, bundle
.body_words
,
2321 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2323 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2324 bool written_late
= false;
2325 bool components
[4] = { 0 };
2326 uint16_t register_dep_mask
= 0;
2327 uint16_t written_mask
= 0;
2329 midgard_instruction
*qins
= ins
;
2330 for (int t
= 0; t
< index
; ++t
) {
2331 if (qins
->registers
.out_reg
!= 0) {
2332 /* Mark down writes */
2334 written_mask
|= (1 << qins
->registers
.out_reg
);
2336 /* Mark down the register dependencies for errata check */
2338 if (qins
->registers
.src1_reg
< 16)
2339 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2341 if (qins
->registers
.src2_reg
< 16)
2342 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2344 int mask
= qins
->alu
.mask
;
2346 for (int c
= 0; c
< 4; ++c
)
2347 if (mask
& (0x3 << (2 * c
)))
2348 components
[c
] = true;
2350 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2352 if (qins
->unit
== UNIT_VLUT
)
2353 written_late
= true;
2356 /* Advance instruction pointer */
2357 qins
= mir_next_op(qins
);
2361 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2362 if (register_dep_mask
& written_mask
) {
2363 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2370 /* If even a single component is not written, break it up (conservative check). */
2371 bool breakup
= false;
2373 for (int c
= 0; c
< 4; ++c
)
2380 /* Otherwise, we're free to proceed */
2384 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2385 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2386 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2387 bytes_emitted
+= sizeof(midgard_branch_extended
);
2389 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2390 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2391 bytes_emitted
+= sizeof(ains
->br_compact
);
2394 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2395 bytes_emitted
+= sizeof(midgard_reg_info
);
2397 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2398 bundle
.body_words_count
++;
2399 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2402 /* Defer marking until after writing to allow for break */
2403 control
|= ains
->unit
;
2404 last_unit
= ains
->unit
;
2405 ++instructions_emitted
;
2409 /* Bubble up the number of instructions for skipping */
2410 instructions_consumed
= index
- 1;
2414 /* Pad ALU op to nearest word */
2416 if (bytes_emitted
& 15) {
2417 padding
= 16 - (bytes_emitted
& 15);
2418 bytes_emitted
+= padding
;
2421 /* Constants must always be quadwords */
2422 if (bundle
.has_embedded_constants
)
2423 bytes_emitted
+= 16;
2425 /* Size ALU instruction for tag */
2426 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2427 bundle
.padding
= padding
;
2428 bundle
.control
= bundle
.tag
| control
;
2433 case TAG_LOAD_STORE_4
: {
2434 /* Load store instructions have two words at once. If
2435 * we only have one queued up, we need to NOP pad.
2436 * Otherwise, we store both in succession to save space
2437 * and cycles -- letting them go in parallel -- skip
2438 * the next. The usefulness of this optimisation is
2439 * greatly dependent on the quality of the instruction
2443 midgard_instruction
*next_op
= mir_next_op(ins
);
2445 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2446 /* As the two operate concurrently, make sure
2447 * they are not dependent */
2449 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2450 /* Skip ahead, since it's redundant with the pair */
2451 instructions_consumed
= 1 + (instructions_emitted
++);
2459 /* Texture ops default to single-op-per-bundle scheduling */
2463 /* Copy the instructions into the bundle */
2464 bundle
.instruction_count
= instructions_emitted
+ 1;
2468 midgard_instruction
*uins
= ins
;
2469 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2470 bundle
.instructions
[used_idx
++] = *uins
;
2471 uins
= mir_next_op(uins
);
2474 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2480 quadword_size(int tag
)
2495 case TAG_LOAD_STORE_4
:
2507 /* Schedule a single block by iterating its instruction to create bundles.
2508 * While we go, tally about the bundle sizes to compute the block size. */
2511 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2513 util_dynarray_init(&block
->bundles
, NULL
);
2515 block
->quadword_count
= 0;
2517 mir_foreach_instr_in_block(block
, ins
) {
2519 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2520 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2522 if (bundle
.has_blend_constant
) {
2523 /* TODO: Multiblock? */
2524 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2525 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2529 ins
= mir_next_op(ins
);
2531 block
->quadword_count
+= quadword_size(bundle
.tag
);
2534 block
->is_scheduled
= true;
2538 schedule_program(compiler_context
*ctx
)
2540 allocate_registers(ctx
);
2542 mir_foreach_block(ctx
, block
) {
2543 schedule_block(ctx
, block
);
2547 /* After everything is scheduled, emit whole bundles at a time */
2550 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2552 int lookahead
= next_tag
<< 4;
2554 switch (bundle
->tag
) {
2559 /* Actually emit each component */
2560 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2562 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2563 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2565 /* Emit body words based on the instructions bundled */
2566 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2567 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2569 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2570 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2571 } else if (ins
->compact_branch
) {
2572 /* Dummy move, XXX DRY */
2573 if ((i
== 0) && ins
->writeout
) {
2574 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2575 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2578 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2579 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2581 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2585 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2586 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2590 /* Emit padding (all zero) */
2591 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2593 /* Tack on constants */
2595 if (bundle
->has_embedded_constants
) {
2596 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2597 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2598 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2599 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2605 case TAG_LOAD_STORE_4
: {
2606 /* One or two composing instructions */
2608 uint64_t current64
, next64
= LDST_NOP
;
2610 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2612 if (bundle
->instruction_count
== 2)
2613 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2615 midgard_load_store instruction
= {
2616 .type
= bundle
->tag
,
2617 .next_type
= next_tag
,
2622 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2627 case TAG_TEXTURE_4
: {
2628 /* Texture instructions are easy, since there is no
2629 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2631 midgard_instruction
*ins
= &bundle
->instructions
[0];
2633 ins
->texture
.type
= TAG_TEXTURE_4
;
2634 ins
->texture
.next_type
= next_tag
;
2636 ctx
->texture_op_count
--;
2638 if (!ctx
->texture_op_count
) {
2639 ins
->texture
.cont
= 0;
2640 ins
->texture
.last
= 1;
2643 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2648 DBG("Unknown midgard instruction type\n");
2655 /* ALU instructions can inline or embed constants, which decreases register
2656 * pressure and saves space. */
2658 #define CONDITIONAL_ATTACH(src) { \
2659 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2662 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2663 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2668 inline_alu_constants(compiler_context
*ctx
)
2670 mir_foreach_instr(ctx
, alu
) {
2671 /* Other instructions cannot inline constants */
2672 if (alu
->type
!= TAG_ALU_4
) continue;
2674 /* If there is already a constant here, we can do nothing */
2675 if (alu
->has_constants
) continue;
2677 CONDITIONAL_ATTACH(src0
);
2679 if (!alu
->has_constants
) {
2680 CONDITIONAL_ATTACH(src1
)
2681 } else if (!alu
->inline_constant
) {
2682 /* Corner case: _two_ vec4 constants, for instance with a
2683 * csel. For this case, we can only use a constant
2684 * register for one, we'll have to emit a move for the
2685 * other. Note, if both arguments are constants, then
2686 * necessarily neither argument depends on the value of
2687 * any particular register. As the destination register
2688 * will be wiped, that means we can spill the constant
2689 * to the destination register.
2692 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2693 unsigned scratch
= alu
->ssa_args
.dest
;
2696 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2697 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2699 /* Force a break XXX Defer r31 writes */
2700 ins
.unit
= UNIT_VLUT
;
2702 /* Set the source */
2703 alu
->ssa_args
.src1
= scratch
;
2705 /* Inject us -before- the last instruction which set r31 */
2706 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2712 /* Midgard supports two types of constants, embedded constants (128-bit) and
2713 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2714 * constants can be demoted to inline constants, for space savings and
2715 * sometimes a performance boost */
2718 embedded_to_inline_constant(compiler_context
*ctx
)
2720 mir_foreach_instr(ctx
, ins
) {
2721 if (!ins
->has_constants
) continue;
2723 if (ins
->ssa_args
.inline_constant
) continue;
2725 /* Blend constants must not be inlined by definition */
2726 if (ins
->has_blend_constant
) continue;
2728 /* src1 cannot be an inline constant due to encoding
2729 * restrictions. So, if possible we try to flip the arguments
2732 int op
= ins
->alu
.op
;
2734 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2735 /* Flip based on op. Fallthrough intentional */
2738 /* These ops require an operational change to flip their arguments TODO */
2739 case midgard_alu_op_flt
:
2740 case midgard_alu_op_fle
:
2741 case midgard_alu_op_ilt
:
2742 case midgard_alu_op_ile
:
2743 case midgard_alu_op_fcsel
:
2744 case midgard_alu_op_icsel
:
2745 case midgard_alu_op_isub
:
2746 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2749 /* These ops are commutative and Just Flip */
2750 case midgard_alu_op_fne
:
2751 case midgard_alu_op_fadd
:
2752 case midgard_alu_op_fmul
:
2753 case midgard_alu_op_fmin
:
2754 case midgard_alu_op_fmax
:
2755 case midgard_alu_op_iadd
:
2756 case midgard_alu_op_imul
:
2757 case midgard_alu_op_feq
:
2758 case midgard_alu_op_ieq
:
2759 case midgard_alu_op_ine
:
2760 case midgard_alu_op_iand
:
2761 case midgard_alu_op_ior
:
2762 case midgard_alu_op_ixor
:
2763 /* Flip the SSA numbers */
2764 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2765 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2767 /* And flip the modifiers */
2771 src_temp
= ins
->alu
.src2
;
2772 ins
->alu
.src2
= ins
->alu
.src1
;
2773 ins
->alu
.src1
= src_temp
;
2780 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2781 /* Extract the source information */
2783 midgard_vector_alu_src
*src
;
2784 int q
= ins
->alu
.src2
;
2785 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2788 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2789 int component
= src
->swizzle
& 3;
2791 /* Scale constant appropriately, if we can legally */
2792 uint16_t scaled_constant
= 0;
2794 /* XXX: Check legality */
2795 if (midgard_is_integer_op(op
)) {
2796 /* TODO: Inline integer */
2799 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2800 scaled_constant
= (uint16_t) iconstants
[component
];
2802 /* Constant overflow after resize */
2803 if (scaled_constant
!= iconstants
[component
])
2806 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2809 /* We don't know how to handle these with a constant */
2811 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2812 DBG("Bailing inline constant...\n");
2816 /* Make sure that the constant is not itself a
2817 * vector by checking if all accessed values
2818 * (by the swizzle) are the same. */
2820 uint32_t *cons
= (uint32_t *) ins
->constants
;
2821 uint32_t value
= cons
[component
];
2823 bool is_vector
= false;
2824 unsigned mask
= effective_writemask(&ins
->alu
);
2826 for (int c
= 1; c
< 4; ++c
) {
2827 /* We only care if this component is actually used */
2828 if (!(mask
& (1 << c
)))
2831 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2833 if (test
!= value
) {
2842 /* Get rid of the embedded constant */
2843 ins
->has_constants
= false;
2844 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2845 ins
->ssa_args
.inline_constant
= true;
2846 ins
->inline_constant
= scaled_constant
;
2851 /* Map normal SSA sources to other SSA sources / fixed registers (like
2855 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2857 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2860 /* Remove entry in leftovers to avoid a redunant fmov */
2862 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2865 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2867 /* Assign the alias map */
2873 #define AS_SRC(to, u) \
2874 int q##to = ins->alu.src2; \
2875 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2877 /* Removing unused moves is necessary to clean up the texture pipeline results.
2879 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2882 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2884 mir_foreach_instr_in_block_safe(block
, ins
) {
2885 if (ins
->type
!= TAG_ALU_4
) continue;
2887 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2889 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2891 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2893 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2895 mir_remove_instruction(ins
);
2899 /* The following passes reorder MIR instructions to enable better scheduling */
2902 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2904 mir_foreach_instr_in_block_safe(block
, ins
) {
2905 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2907 /* We've found a load/store op. Check if next is also load/store. */
2908 midgard_instruction
*next_op
= mir_next_op(ins
);
2909 if (&next_op
->link
!= &block
->instructions
) {
2910 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2911 /* If so, we're done since we're a pair */
2912 ins
= mir_next_op(ins
);
2916 /* Maximum search distance to pair, to avoid register pressure disasters */
2917 int search_distance
= 8;
2919 /* Otherwise, we have an orphaned load/store -- search for another load */
2920 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2921 /* Terminate search if necessary */
2922 if (!(search_distance
--)) break;
2924 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2926 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2928 /* We found one! Move it up to pair and remove it from the old location */
2930 mir_insert_instruction_before(ins
, *c
);
2931 mir_remove_instruction(c
);
2939 /* Emit varying stores late */
2942 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2943 /* Iterate in reverse to get the final write, rather than the first */
2945 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2946 /* Check if what we just wrote needs a store */
2947 int idx
= ins
->ssa_args
.dest
;
2948 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2950 if (!varying
) continue;
2954 /* We need to store to the appropriate varying, so emit the
2957 /* TODO: Integrate with special purpose RA (and scheduler?) */
2958 bool high_varying_register
= false;
2960 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2962 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2963 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2965 mir_insert_instruction_before(mir_next_op(ins
), st
);
2966 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2968 /* We no longer need to store this varying */
2969 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2973 /* If there are leftovers after the below pass, emit actual fmov
2974 * instructions for the slow-but-correct path */
2977 emit_leftover_move(compiler_context
*ctx
)
2979 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2980 int base
= ((uintptr_t) leftover
->key
) - 1;
2983 map_ssa_to_alias(ctx
, &mapped
);
2984 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2989 actualise_ssa_to_alias(compiler_context
*ctx
)
2991 mir_foreach_instr(ctx
, ins
) {
2992 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2993 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2996 emit_leftover_move(ctx
);
2999 /* Vertex shaders do not write gl_Position as is; instead, they write a
3000 * transformed screen space position as a varying. See section 12.5 "Coordinate
3001 * Transformation" of the ES 3.2 full specification for details.
3003 * This transformation occurs early on, as NIR and prior to optimisation, in
3004 * order to take advantage of NIR optimisation passes of the transform itself.
3008 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
3010 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
3012 /* Get viewport from the uniforms */
3013 nir_intrinsic_instr
*load
;
3014 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
3015 load
->num_components
= 4;
3016 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
3017 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
3018 nir_builder_instr_insert(b
, &load
->instr
);
3020 /* Formatted as <width, height, centerx, centery> */
3021 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
3022 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
3023 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
3024 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
3026 /* XXX: From uniforms? */
3027 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
3028 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
3030 /* World space to normalised device coordinates */
3032 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
3033 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
3035 /* Normalised device coordinates to screen space */
3037 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
3038 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
3040 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
3041 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
3042 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
3044 /* gl_Position will be written out in screenspace xyz, with w set to
3045 * the reciprocal we computed earlier. The transformed w component is
3046 * then used for perspective-correct varying interpolation. The
3047 * transformed w component must preserve its original sign; this is
3048 * used in depth clipping computations */
3050 nir_ssa_def
*screen_space
= nir_vec4(b
,
3051 nir_channel(b
, viewport_xy
, 0),
3052 nir_channel(b
, viewport_xy
, 1),
3056 /* Finally, write out the transformed values to the varying */
3058 nir_intrinsic_instr
*store
;
3059 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
3060 store
->num_components
= 4;
3061 nir_intrinsic_set_base(store
, 0);
3062 nir_intrinsic_set_write_mask(store
, 0xf);
3063 store
->src
[0].ssa
= screen_space
;
3064 store
->src
[0].is_ssa
= true;
3065 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
3066 nir_builder_instr_insert(b
, &store
->instr
);
3070 transform_position_writes(nir_shader
*shader
)
3072 nir_foreach_function(func
, shader
) {
3073 nir_foreach_block(block
, func
->impl
) {
3074 nir_foreach_instr_safe(instr
, block
) {
3075 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
3077 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
3078 nir_variable
*out
= NULL
;
3080 switch (intr
->intrinsic
) {
3081 case nir_intrinsic_store_output
:
3082 /* already had i/o lowered.. lookup the matching output var: */
3083 nir_foreach_variable(var
, &shader
->outputs
) {
3084 int drvloc
= var
->data
.driver_location
;
3086 if (nir_intrinsic_base(intr
) == drvloc
) {
3100 if (out
->data
.mode
!= nir_var_shader_out
)
3103 if (out
->data
.location
!= VARYING_SLOT_POS
)
3107 nir_builder_init(&b
, func
->impl
);
3108 b
.cursor
= nir_before_instr(instr
);
3110 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
3111 nir_instr_remove(instr
);
3118 emit_fragment_epilogue(compiler_context
*ctx
)
3120 /* Special case: writing out constants requires us to include the move
3121 * explicitly now, so shove it into r0 */
3123 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3125 if (constant_value
) {
3126 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3127 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3128 emit_mir_instruction(ctx
, ins
);
3131 /* Perform the actual fragment writeout. We have two writeout/branch
3132 * instructions, forming a loop until writeout is successful as per the
3133 * docs. TODO: gl_FragDepth */
3135 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3136 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3139 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3140 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3141 * with the int8 analogue to the fragment epilogue */
3144 emit_blend_epilogue(compiler_context
*ctx
)
3146 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3148 midgard_instruction scale
= {
3151 .inline_constant
= _mesa_float_to_half(255.0),
3153 .src0
= SSA_FIXED_REGISTER(0),
3154 .src1
= SSA_UNUSED_0
,
3155 .dest
= SSA_FIXED_REGISTER(24),
3156 .inline_constant
= true
3159 .op
= midgard_alu_op_fmul
,
3160 .reg_mode
= midgard_reg_mode_full
,
3161 .dest_override
= midgard_dest_override_lower
,
3163 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3164 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3168 emit_mir_instruction(ctx
, scale
);
3170 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3172 midgard_vector_alu_src alu_src
= blank_alu_src
;
3173 alu_src
.half
= true;
3175 midgard_instruction f2u8
= {
3178 .src0
= SSA_FIXED_REGISTER(24),
3179 .src1
= SSA_UNUSED_0
,
3180 .dest
= SSA_FIXED_REGISTER(0),
3181 .inline_constant
= true
3184 .op
= midgard_alu_op_f2u8
,
3185 .reg_mode
= midgard_reg_mode_half
,
3186 .dest_override
= midgard_dest_override_lower
,
3187 .outmod
= midgard_outmod_pos
,
3189 .src1
= vector_alu_srco_unsigned(alu_src
),
3190 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3194 emit_mir_instruction(ctx
, f2u8
);
3196 /* vmul.imov.quarter r0, r0, r0 */
3198 midgard_instruction imov_8
= {
3201 .src0
= SSA_UNUSED_1
,
3202 .src1
= SSA_FIXED_REGISTER(0),
3203 .dest
= SSA_FIXED_REGISTER(0),
3206 .op
= midgard_alu_op_imov
,
3207 .reg_mode
= midgard_reg_mode_quarter
,
3208 .dest_override
= midgard_dest_override_none
,
3210 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3211 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3215 /* Emit branch epilogue with the 8-bit move as the source */
3217 emit_mir_instruction(ctx
, imov_8
);
3218 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3220 emit_mir_instruction(ctx
, imov_8
);
3221 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3224 static midgard_block
*
3225 emit_block(compiler_context
*ctx
, nir_block
*block
)
3227 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3228 list_addtail(&this_block
->link
, &ctx
->blocks
);
3230 this_block
->is_scheduled
= false;
3233 ctx
->texture_index
[0] = -1;
3234 ctx
->texture_index
[1] = -1;
3236 /* Set up current block */
3237 list_inithead(&this_block
->instructions
);
3238 ctx
->current_block
= this_block
;
3240 nir_foreach_instr(instr
, block
) {
3241 emit_instr(ctx
, instr
);
3242 ++ctx
->instruction_count
;
3245 inline_alu_constants(ctx
);
3246 embedded_to_inline_constant(ctx
);
3248 /* Perform heavylifting for aliasing */
3249 actualise_ssa_to_alias(ctx
);
3251 midgard_emit_store(ctx
, this_block
);
3252 midgard_eliminate_orphan_moves(ctx
, this_block
);
3253 midgard_pair_load_store(ctx
, this_block
);
3255 /* Append fragment shader epilogue (value writeout) */
3256 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3257 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3259 emit_blend_epilogue(ctx
);
3261 emit_fragment_epilogue(ctx
);
3265 /* Fallthrough save */
3266 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3268 if (block
== nir_start_block(ctx
->func
->impl
))
3269 ctx
->initial_block
= this_block
;
3271 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3272 ctx
->final_block
= this_block
;
3274 /* Allow the next control flow to access us retroactively, for
3276 ctx
->current_block
= this_block
;
3278 /* Document the fallthrough chain */
3279 ctx
->previous_source_block
= this_block
;
3284 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3287 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3289 /* Conditional branches expect the condition in r31.w; emit a move for
3290 * that in the _previous_ block (which is the current block). */
3291 emit_condition(ctx
, &nif
->condition
, true);
3293 /* Speculatively emit the branch, but we can't fill it in until later */
3294 EMIT(branch
, true, true);
3295 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3297 /* Emit the two subblocks */
3298 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3300 /* Emit a jump from the end of the then block to the end of the else */
3301 EMIT(branch
, false, false);
3302 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3304 /* Emit second block, and check if it's empty */
3306 int else_idx
= ctx
->block_count
;
3307 int count_in
= ctx
->instruction_count
;
3308 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3309 int after_else_idx
= ctx
->block_count
;
3311 /* Now that we have the subblocks emitted, fix up the branches */
3316 if (ctx
->instruction_count
== count_in
) {
3317 /* The else block is empty, so don't emit an exit jump */
3318 mir_remove_instruction(then_exit
);
3319 then_branch
->branch
.target_block
= after_else_idx
;
3321 then_branch
->branch
.target_block
= else_idx
;
3322 then_exit
->branch
.target_block
= after_else_idx
;
3327 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3329 /* Remember where we are */
3330 midgard_block
*start_block
= ctx
->current_block
;
3332 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3333 * single current_loop variable, maybe we need a stack */
3335 int loop_idx
= ++ctx
->current_loop
;
3337 /* Get index from before the body so we can loop back later */
3338 int start_idx
= ctx
->block_count
;
3340 /* Emit the body itself */
3341 emit_cf_list(ctx
, &nloop
->body
);
3343 /* Branch back to loop back */
3344 struct midgard_instruction br_back
= v_branch(false, false);
3345 br_back
.branch
.target_block
= start_idx
;
3346 emit_mir_instruction(ctx
, br_back
);
3348 /* Find the index of the block about to follow us (note: we don't add
3349 * one; blocks are 0-indexed so we get a fencepost problem) */
3350 int break_block_idx
= ctx
->block_count
;
3352 /* Fix up the break statements we emitted to point to the right place,
3353 * now that we can allocate a block number for them */
3355 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3356 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3357 print_mir_block(block
);
3358 mir_foreach_instr_in_block(block
, ins
) {
3359 if (ins
->type
!= TAG_ALU_4
) continue;
3360 if (!ins
->compact_branch
) continue;
3361 if (ins
->prepacked_branch
) continue;
3363 /* We found a branch -- check the type to see if we need to do anything */
3364 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3366 /* It's a break! Check if it's our break */
3367 if (ins
->branch
.target_break
!= loop_idx
) continue;
3369 /* Okay, cool, we're breaking out of this loop.
3370 * Rewrite from a break to a goto */
3372 ins
->branch
.target_type
= TARGET_GOTO
;
3373 ins
->branch
.target_block
= break_block_idx
;
3378 static midgard_block
*
3379 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3381 midgard_block
*start_block
= NULL
;
3383 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3384 switch (node
->type
) {
3385 case nir_cf_node_block
: {
3386 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3389 start_block
= block
;
3394 case nir_cf_node_if
:
3395 emit_if(ctx
, nir_cf_node_as_if(node
));
3398 case nir_cf_node_loop
:
3399 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3402 case nir_cf_node_function
:
3411 /* Due to lookahead, we need to report the first tag executed in the command
3412 * stream and in branch targets. An initial block might be empty, so iterate
3413 * until we find one that 'works' */
3416 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3418 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3420 unsigned first_tag
= 0;
3423 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3425 if (initial_bundle
) {
3426 first_tag
= initial_bundle
->tag
;
3430 /* Initial block is empty, try the next block */
3431 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3432 } while(initial_block
!= NULL
);
3439 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3441 struct util_dynarray
*compiled
= &program
->compiled
;
3443 midgard_debug
= debug_get_option_midgard_debug();
3445 compiler_context ictx
= {
3447 .stage
= nir
->info
.stage
,
3449 .is_blend
= is_blend
,
3450 .blend_constant_offset
= -1,
3452 .alpha_ref
= program
->alpha_ref
3455 compiler_context
*ctx
= &ictx
;
3457 /* TODO: Decide this at runtime */
3458 ctx
->uniform_cutoff
= 8;
3460 switch (ctx
->stage
) {
3461 case MESA_SHADER_VERTEX
:
3462 ctx
->special_uniforms
= 1;
3466 ctx
->special_uniforms
= 0;
3470 /* Append epilogue uniforms if necessary. The cmdstream depends on
3471 * these being at the -end-; see assign_var_locations. */
3473 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3474 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3477 /* Assign var locations early, so the epilogue can use them if necessary */
3479 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3480 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3481 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3483 /* Initialize at a global (not block) level hash tables */
3485 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3486 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3487 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3488 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3489 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3490 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3492 /* Assign actual uniform location, skipping over samplers */
3494 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3496 nir_foreach_variable(var
, &nir
->uniforms
) {
3497 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3499 unsigned length
= glsl_get_aoa_size(var
->type
);
3502 length
= glsl_get_length(var
->type
);
3506 length
= glsl_get_matrix_columns(var
->type
);
3509 for (int col
= 0; col
< length
; ++col
) {
3510 int id
= ctx
->uniform_count
++;
3511 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3515 /* Record the varying mapping for the command stream's bookkeeping */
3517 struct exec_list
*varyings
=
3518 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3520 nir_foreach_variable(var
, varyings
) {
3521 unsigned loc
= var
->data
.driver_location
;
3522 program
->varyings
[loc
] = var
->data
.location
;
3525 /* Lower vars -- not I/O -- before epilogue */
3527 NIR_PASS_V(nir
, nir_lower_var_copies
);
3528 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3529 NIR_PASS_V(nir
, nir_split_var_copies
);
3530 NIR_PASS_V(nir
, nir_lower_var_copies
);
3531 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3532 NIR_PASS_V(nir
, nir_lower_var_copies
);
3533 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3534 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3536 /* Append vertex epilogue before optimisation, so the epilogue itself
3539 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3540 transform_position_writes(nir
);
3542 /* Optimisation passes */
3546 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3547 nir_print_shader(nir
, stdout
);
3550 /* Assign counts, now that we're sure (post-optimisation) */
3551 program
->uniform_count
= nir
->num_uniforms
;
3553 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3554 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3557 nir_foreach_function(func
, nir
) {
3561 list_inithead(&ctx
->blocks
);
3562 ctx
->block_count
= 0;
3565 emit_cf_list(ctx
, &func
->impl
->body
);
3566 emit_block(ctx
, func
->impl
->end_block
);
3568 break; /* TODO: Multi-function shaders */
3571 util_dynarray_init(compiled
, NULL
);
3574 schedule_program(ctx
);
3576 /* Now that all the bundles are scheduled and we can calculate block
3577 * sizes, emit actual branch instructions rather than placeholders */
3579 int br_block_idx
= 0;
3581 mir_foreach_block(ctx
, block
) {
3582 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3583 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3584 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3586 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3588 if (ins
->prepacked_branch
) continue;
3590 /* Parse some basic branch info */
3591 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3592 bool is_conditional
= ins
->branch
.conditional
;
3593 bool is_inverted
= ins
->branch
.invert_conditional
;
3594 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3596 /* Determine the block we're jumping to */
3597 int target_number
= ins
->branch
.target_block
;
3599 /* Report the destination tag. Discards don't need this */
3600 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3602 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3603 int quadword_offset
= 0;
3606 /* Jump to the end of the shader. We
3607 * need to include not only the
3608 * following blocks, but also the
3609 * contents of our current block (since
3610 * discard can come in the middle of
3613 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3615 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3616 quadword_offset
+= quadword_size(bun
->tag
);
3619 mir_foreach_block_from(ctx
, blk
, b
) {
3620 quadword_offset
+= b
->quadword_count
;
3623 } else if (target_number
> br_block_idx
) {
3626 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3627 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3630 quadword_offset
+= blk
->quadword_count
;
3633 /* Jump backwards */
3635 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3636 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3639 quadword_offset
-= blk
->quadword_count
;
3643 /* Unconditional extended branches (far jumps)
3644 * have issues, so we always use a conditional
3645 * branch, setting the condition to always for
3646 * unconditional. For compact unconditional
3647 * branches, cond isn't used so it doesn't
3648 * matter what we pick. */
3650 midgard_condition cond
=
3651 !is_conditional
? midgard_condition_always
:
3652 is_inverted
? midgard_condition_false
:
3653 midgard_condition_true
;
3655 midgard_jmp_writeout_op op
=
3656 is_discard
? midgard_jmp_writeout_op_discard
:
3657 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3658 midgard_jmp_writeout_op_branch_cond
;
3661 midgard_branch_extended branch
=
3662 midgard_create_branch_extended(
3667 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3668 } else if (is_conditional
|| is_discard
) {
3669 midgard_branch_cond branch
= {
3671 .dest_tag
= dest_tag
,
3672 .offset
= quadword_offset
,
3676 assert(branch
.offset
== quadword_offset
);
3678 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3680 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3682 midgard_branch_uncond branch
= {
3684 .dest_tag
= dest_tag
,
3685 .offset
= quadword_offset
,
3689 assert(branch
.offset
== quadword_offset
);
3691 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3699 /* Emit flat binary from the instruction arrays. Iterate each block in
3700 * sequence. Save instruction boundaries such that lookahead tags can
3701 * be assigned easily */
3703 /* Cache _all_ bundles in source order for lookahead across failed branches */
3705 int bundle_count
= 0;
3706 mir_foreach_block(ctx
, block
) {
3707 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3709 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3711 mir_foreach_block(ctx
, block
) {
3712 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3713 source_order_bundles
[bundle_idx
++] = bundle
;
3717 int current_bundle
= 0;
3719 mir_foreach_block(ctx
, block
) {
3720 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3723 if (current_bundle
+ 1 < bundle_count
) {
3724 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3726 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3733 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3737 /* TODO: Free deeper */
3738 //util_dynarray_fini(&block->instructions);
3741 free(source_order_bundles
);
3743 /* Report the very first tag executed */
3744 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3746 /* Deal with off-by-one related to the fencepost problem */
3747 program
->work_register_count
= ctx
->work_registers
+ 1;
3749 program
->can_discard
= ctx
->can_discard
;
3750 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3752 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3754 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3755 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);