2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 struct midgard_block
*next_fallthrough
;
175 /* Helpers to generate midgard_instruction's using macro magic, since every
176 * driver seems to do it that way */
178 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
179 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
181 #define M_LOAD_STORE(name, rname, uname) \
182 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
183 midgard_instruction i = { \
184 .type = TAG_LOAD_STORE_4, \
191 .op = midgard_op_##name, \
193 .swizzle = SWIZZLE_XYZW, \
201 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
202 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
204 const midgard_vector_alu_src blank_alu_src
= {
205 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
208 const midgard_vector_alu_src blank_alu_src_xxxx
= {
209 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
212 const midgard_scalar_alu_src blank_scalar_alu_src
= {
216 /* Used for encoding the unused source of 1-op instructions */
217 const midgard_vector_alu_src zero_alu_src
= { 0 };
219 /* Coerce structs to integer */
222 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
225 memcpy(&u
, &src
, sizeof(src
));
229 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
230 * the corresponding Midgard source */
232 static midgard_vector_alu_src
233 vector_alu_modifiers(nir_alu_src
*src
)
235 if (!src
) return blank_alu_src
;
237 midgard_vector_alu_src alu_src
= {
239 .negate
= src
->negate
,
242 .half
= 0, /* TODO */
243 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
249 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
251 static midgard_instruction
252 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
254 midgard_instruction ins
= {
257 .src0
= SSA_UNUSED_1
,
262 .op
= midgard_alu_op_fmov
,
263 .reg_mode
= midgard_reg_mode_full
,
264 .dest_override
= midgard_dest_override_none
,
266 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
267 .src2
= vector_alu_srco_unsigned(mod
)
274 /* load/store instructions have both 32-bit and 16-bit variants, depending on
275 * whether we are using vectors composed of highp or mediump. At the moment, we
276 * don't support half-floats -- this requires changes in other parts of the
277 * compiler -- therefore the 16-bit versions are commented out. */
279 //M_LOAD(load_attr_16);
280 M_LOAD(load_attr_32
);
281 //M_LOAD(load_vary_16);
282 M_LOAD(load_vary_32
);
283 //M_LOAD(load_uniform_16);
284 M_LOAD(load_uniform_32
);
285 M_LOAD(load_color_buffer_8
);
286 //M_STORE(store_vary_16);
287 M_STORE(store_vary_32
);
288 M_STORE(store_cubemap_coords
);
290 static midgard_instruction
291 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
293 midgard_branch_cond branch
= {
301 memcpy(&compact
, &branch
, sizeof(branch
));
303 midgard_instruction ins
= {
305 .unit
= ALU_ENAB_BR_COMPACT
,
306 .prepacked_branch
= true,
307 .compact_branch
= true,
308 .br_compact
= compact
311 if (op
== midgard_jmp_writeout_op_writeout
)
317 static midgard_instruction
318 v_branch(bool conditional
, bool invert
)
320 midgard_instruction ins
= {
322 .unit
= ALU_ENAB_BRANCH
,
323 .compact_branch
= true,
325 .conditional
= conditional
,
326 .invert_conditional
= invert
333 static midgard_branch_extended
334 midgard_create_branch_extended( midgard_condition cond
,
335 midgard_jmp_writeout_op op
,
337 signed quadword_offset
)
339 /* For unclear reasons, the condition code is repeated 8 times */
340 uint16_t duplicated_cond
=
350 midgard_branch_extended branch
= {
352 .dest_tag
= dest_tag
,
353 .offset
= quadword_offset
,
354 .cond
= duplicated_cond
360 typedef struct midgard_bundle
{
361 /* Tag for the overall bundle */
364 /* Instructions contained by the bundle */
365 int instruction_count
;
366 midgard_instruction instructions
[5];
368 /* Bundle-wide ALU configuration */
371 bool has_embedded_constants
;
373 bool has_blend_constant
;
375 uint16_t register_words
[8];
376 int register_words_count
;
378 uint64_t body_words
[8];
380 int body_words_count
;
383 typedef struct compiler_context
{
385 gl_shader_stage stage
;
387 /* Is internally a blend shader? Depends on stage == FRAGMENT */
390 /* Tracking for blend constant patching */
391 int blend_constant_number
;
392 int blend_constant_offset
;
394 /* Current NIR function */
397 /* Unordered list of midgard_blocks */
399 struct list_head blocks
;
401 midgard_block
*initial_block
;
402 midgard_block
*previous_source_block
;
403 midgard_block
*final_block
;
405 /* List of midgard_instructions emitted for the current block */
406 midgard_block
*current_block
;
408 /* The index corresponding to the current loop, e.g. for breaks/contineus */
411 /* Constants which have been loaded, for later inlining */
412 struct hash_table_u64
*ssa_constants
;
414 /* SSA indices to be outputted to corresponding varying offset */
415 struct hash_table_u64
*ssa_varyings
;
417 /* SSA values / registers which have been aliased. Naively, these
418 * demand a fmov output; instead, we alias them in a later pass to
419 * avoid the wasted op.
421 * A note on encoding: to avoid dynamic memory management here, rather
422 * than ampping to a pointer, we map to the source index; the key
423 * itself is just the destination index. */
425 struct hash_table_u64
*ssa_to_alias
;
426 struct set
*leftover_ssa_to_alias
;
428 /* Actual SSA-to-register for RA */
429 struct hash_table_u64
*ssa_to_register
;
431 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
432 struct hash_table_u64
*hash_to_temp
;
436 /* Just the count of the max register used. Higher count => higher
437 * register pressure */
440 /* Used for cont/last hinting. Increase when a tex op is added.
441 * Decrease when a tex op is removed. */
442 int texture_op_count
;
444 /* Mapping of texture register -> SSA index for unaliasing */
445 int texture_index
[2];
447 /* If any path hits a discard instruction */
450 /* The number of uniforms allowable for the fast path */
453 /* Count of instructions emitted from NIR overall, across all blocks */
454 int instruction_count
;
456 /* Alpha ref value passed in */
459 /* The index corresponding to the fragment output */
460 unsigned fragment_output
;
462 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
463 unsigned sysvals
[MAX_SYSVAL_COUNT
];
464 unsigned sysval_count
;
465 struct hash_table_u64
*sysval_to_id
;
468 /* Append instruction to end of current block */
470 static midgard_instruction
*
471 mir_upload_ins(struct midgard_instruction ins
)
473 midgard_instruction
*heap
= malloc(sizeof(ins
));
474 memcpy(heap
, &ins
, sizeof(ins
));
479 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
481 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
485 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
487 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
491 mir_remove_instruction(struct midgard_instruction
*ins
)
493 list_del(&ins
->link
);
496 static midgard_instruction
*
497 mir_prev_op(struct midgard_instruction
*ins
)
499 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
502 static midgard_instruction
*
503 mir_next_op(struct midgard_instruction
*ins
)
505 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
508 static midgard_block
*
509 mir_next_block(struct midgard_block
*blk
)
511 return list_first_entry(&(blk
->link
), midgard_block
, link
);
515 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
516 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
518 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
519 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
520 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
521 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
522 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
523 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
526 static midgard_instruction
*
527 mir_last_in_block(struct midgard_block
*block
)
529 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
532 static midgard_block
*
533 mir_get_block(compiler_context
*ctx
, int idx
)
535 struct list_head
*lst
= &ctx
->blocks
;
540 return (struct midgard_block
*) lst
;
543 /* Pretty printer for internal Midgard IR */
546 print_mir_source(int source
)
548 if (source
>= SSA_FIXED_MINIMUM
) {
549 /* Specific register */
550 int reg
= SSA_REG_FROM_FIXED(source
);
552 /* TODO: Moving threshold */
553 if (reg
> 16 && reg
< 24)
554 printf("u%d", 23 - reg
);
558 printf("%d", source
);
563 print_mir_instruction(midgard_instruction
*ins
)
569 midgard_alu_op op
= ins
->alu
.op
;
570 const char *name
= alu_opcode_names
[op
];
573 printf("%d.", ins
->unit
);
575 printf("%s", name
? name
: "??");
579 case TAG_LOAD_STORE_4
: {
580 midgard_load_store_op op
= ins
->load_store
.op
;
581 const char *name
= load_store_opcode_names
[op
];
588 case TAG_TEXTURE_4
: {
597 ssa_args
*args
= &ins
->ssa_args
;
599 printf(" %d, ", args
->dest
);
601 print_mir_source(args
->src0
);
604 if (args
->inline_constant
)
605 printf("#%d", ins
->inline_constant
);
607 print_mir_source(args
->src1
);
609 if (ins
->has_constants
)
610 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
616 print_mir_block(midgard_block
*block
)
620 mir_foreach_instr_in_block(block
, ins
) {
621 print_mir_instruction(ins
);
630 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
632 ins
->has_constants
= true;
633 memcpy(&ins
->constants
, constants
, 16);
635 /* If this is the special blend constant, mark this instruction */
637 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
638 ins
->has_blend_constant
= true;
642 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
644 return glsl_count_attribute_slots(type
, false);
647 /* Lower fdot2 to a vector multiplication followed by channel addition */
649 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
651 if (alu
->op
!= nir_op_fdot2
)
654 b
->cursor
= nir_before_instr(&alu
->instr
);
656 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
657 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
659 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
661 nir_ssa_def
*sum
= nir_fadd(b
,
662 nir_channel(b
, product
, 0),
663 nir_channel(b
, product
, 1));
665 /* Replace the fdot2 with this sum */
666 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
670 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
672 switch (instr
->intrinsic
) {
673 case nir_intrinsic_load_viewport_scale
:
674 return PAN_SYSVAL_VIEWPORT_SCALE
;
675 case nir_intrinsic_load_viewport_offset
:
676 return PAN_SYSVAL_VIEWPORT_OFFSET
;
683 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
687 if (instr
->type
== nir_instr_type_intrinsic
) {
688 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
689 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
695 /* We have a sysval load; check if it's already been assigned */
697 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
700 /* It hasn't -- so assign it now! */
702 unsigned id
= ctx
->sysval_count
++;
703 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
704 ctx
->sysvals
[id
] = sysval
;
708 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
710 ctx
->sysval_count
= 0;
712 nir_foreach_function(function
, shader
) {
713 if (!function
->impl
) continue;
715 nir_foreach_block(block
, function
->impl
) {
716 nir_foreach_instr_safe(instr
, block
) {
717 midgard_nir_assign_sysval_body(ctx
, instr
);
724 midgard_nir_lower_fdot2(nir_shader
*shader
)
726 bool progress
= false;
728 nir_foreach_function(function
, shader
) {
729 if (!function
->impl
) continue;
732 nir_builder
*b
= &_b
;
733 nir_builder_init(b
, function
->impl
);
735 nir_foreach_block(block
, function
->impl
) {
736 nir_foreach_instr_safe(instr
, block
) {
737 if (instr
->type
!= nir_instr_type_alu
) continue;
739 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
740 midgard_nir_lower_fdot2_body(b
, alu
);
746 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
754 optimise_nir(nir_shader
*nir
)
758 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
759 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
761 nir_lower_tex_options lower_tex_options
= {
765 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
770 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
771 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
772 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
774 NIR_PASS(progress
, nir
, nir_copy_prop
);
775 NIR_PASS(progress
, nir
, nir_opt_dce
);
776 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
777 NIR_PASS(progress
, nir
, nir_opt_cse
);
778 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
779 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
780 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
781 NIR_PASS(progress
, nir
, nir_opt_undef
);
782 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
785 nir_var_function_temp
);
787 /* TODO: Enable vectorize when merged upstream */
788 // NIR_PASS(progress, nir, nir_opt_vectorize);
791 /* Must be run at the end to prevent creation of fsin/fcos ops */
792 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
797 NIR_PASS(progress
, nir
, nir_opt_dce
);
798 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
799 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
800 NIR_PASS(progress
, nir
, nir_copy_prop
);
803 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
804 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
806 /* Lower mods for float ops only. Integer ops don't support modifiers
807 * (saturate doesn't make sense on integers, neg/abs require dedicated
810 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
811 NIR_PASS(progress
, nir
, nir_copy_prop
);
812 NIR_PASS(progress
, nir
, nir_opt_dce
);
814 /* We implement booleans as 32-bit 0/~0 */
815 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
817 /* Take us out of SSA */
818 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
819 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
821 /* We are a vector architecture; write combine where possible */
822 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
823 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
825 NIR_PASS(progress
, nir
, nir_opt_dce
);
828 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
829 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
830 * r0. See the comments in compiler_context */
833 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
835 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
836 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
839 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
842 unalias_ssa(compiler_context
*ctx
, int dest
)
844 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
845 /* TODO: Remove from leftover or no? */
849 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
851 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
855 midgard_is_pinned(compiler_context
*ctx
, int index
)
857 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
860 /* Do not actually emit a load; instead, cache the constant for inlining */
863 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
865 nir_ssa_def def
= instr
->def
;
867 float *v
= ralloc_array(NULL
, float, 4);
868 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
869 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
872 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
876 expand_writemask(unsigned mask
)
880 for (int i
= 0; i
< 4; ++i
)
888 squeeze_writemask(unsigned mask
)
892 for (int i
= 0; i
< 4; ++i
)
893 if (mask
& (3 << (2 * i
)))
900 /* Determines effective writemask, taking quirks and expansion into account */
902 effective_writemask(midgard_vector_alu
*alu
)
904 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
907 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
909 /* If there is a fixed channel count, construct the appropriate mask */
912 return (1 << channel_count
) - 1;
914 /* Otherwise, just squeeze the existing mask */
915 return squeeze_writemask(alu
->mask
);
919 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
921 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
924 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
929 /* If no temp is find, allocate one */
930 temp
= ctx
->temp_count
++;
931 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
933 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
939 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
942 return src
->ssa
->index
;
944 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
948 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
951 return dst
->ssa
.index
;
953 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
957 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
959 return nir_src_index(ctx
, &src
->src
);
962 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
963 * a conditional test) into that register */
966 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
968 /* XXX: Force component correct */
969 int condition
= nir_src_index(ctx
, src
);
971 /* There is no boolean move instruction. Instead, we simulate a move by
972 * ANDing the condition with itself to get it into r31.w */
974 midgard_instruction ins
= {
976 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
980 .dest
= SSA_FIXED_REGISTER(31),
983 .op
= midgard_alu_op_iand
,
984 .reg_mode
= midgard_reg_mode_full
,
985 .dest_override
= midgard_dest_override_none
,
986 .mask
= (0x3 << 6), /* w */
987 .src1
= vector_alu_srco_unsigned(blank_alu_src_xxxx
),
988 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
992 emit_mir_instruction(ctx
, ins
);
995 #define ALU_CASE(nir, _op) \
997 op = midgard_alu_op_##_op; \
1001 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1003 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1005 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1006 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1007 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1009 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1010 * supported. A few do not and are commented for now. Also, there are a
1011 * number of NIR ops which Midgard does not support and need to be
1012 * lowered, also TODO. This switch block emits the opcode and calling
1013 * convention of the Midgard instruction; actual packing is done in
1018 switch (instr
->op
) {
1019 ALU_CASE(fadd
, fadd
);
1020 ALU_CASE(fmul
, fmul
);
1021 ALU_CASE(fmin
, fmin
);
1022 ALU_CASE(fmax
, fmax
);
1023 ALU_CASE(imin
, imin
);
1024 ALU_CASE(imax
, imax
);
1025 ALU_CASE(umin
, umin
);
1026 ALU_CASE(umax
, umax
);
1027 ALU_CASE(fmov
, fmov
);
1028 ALU_CASE(ffloor
, ffloor
);
1029 ALU_CASE(fround_even
, froundeven
);
1030 ALU_CASE(ftrunc
, ftrunc
);
1031 ALU_CASE(fceil
, fceil
);
1032 ALU_CASE(fdot3
, fdot3
);
1033 ALU_CASE(fdot4
, fdot4
);
1034 ALU_CASE(iadd
, iadd
);
1035 ALU_CASE(isub
, isub
);
1036 ALU_CASE(imul
, imul
);
1037 ALU_CASE(iabs
, iabs
);
1039 /* XXX: Use fmov, not imov, since imov was causing major
1040 * issues with texture precision? XXX research */
1041 ALU_CASE(imov
, fmov
);
1043 ALU_CASE(feq32
, feq
);
1044 ALU_CASE(fne32
, fne
);
1045 ALU_CASE(flt32
, flt
);
1046 ALU_CASE(ieq32
, ieq
);
1047 ALU_CASE(ine32
, ine
);
1048 ALU_CASE(ilt32
, ilt
);
1049 ALU_CASE(ult32
, ult
);
1051 /* We don't have a native b2f32 instruction. Instead, like many
1052 * GPUs, we exploit booleans as 0/~0 for false/true, and
1053 * correspondingly AND
1054 * by 1.0 to do the type conversion. For the moment, prime us
1057 * iand [whatever], #0
1059 * At the end of emit_alu (as MIR), we'll fix-up the constant
1062 ALU_CASE(b2f32
, iand
);
1063 ALU_CASE(b2i32
, iand
);
1065 /* Likewise, we don't have a dedicated f2b32 instruction, but
1066 * we can do a "not equal to 0.0" test. */
1068 ALU_CASE(f2b32
, fne
);
1069 ALU_CASE(i2b32
, ine
);
1071 ALU_CASE(frcp
, frcp
);
1072 ALU_CASE(frsq
, frsqrt
);
1073 ALU_CASE(fsqrt
, fsqrt
);
1074 ALU_CASE(fexp2
, fexp2
);
1075 ALU_CASE(flog2
, flog2
);
1077 ALU_CASE(f2i32
, f2i
);
1078 ALU_CASE(f2u32
, f2u
);
1079 ALU_CASE(i2f32
, i2f
);
1080 ALU_CASE(u2f32
, u2f
);
1082 ALU_CASE(fsin
, fsin
);
1083 ALU_CASE(fcos
, fcos
);
1085 ALU_CASE(iand
, iand
);
1087 ALU_CASE(ixor
, ixor
);
1088 ALU_CASE(inot
, inot
);
1089 ALU_CASE(ishl
, ishl
);
1090 ALU_CASE(ishr
, iasr
);
1091 ALU_CASE(ushr
, ilsr
);
1093 ALU_CASE(b32all_fequal2
, fball_eq
);
1094 ALU_CASE(b32all_fequal3
, fball_eq
);
1095 ALU_CASE(b32all_fequal4
, fball_eq
);
1097 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1098 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1099 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1101 ALU_CASE(b32all_iequal2
, iball_eq
);
1102 ALU_CASE(b32all_iequal3
, iball_eq
);
1103 ALU_CASE(b32all_iequal4
, iball_eq
);
1105 ALU_CASE(b32any_inequal2
, ibany_neq
);
1106 ALU_CASE(b32any_inequal3
, ibany_neq
);
1107 ALU_CASE(b32any_inequal4
, ibany_neq
);
1109 /* For greater-or-equal, we lower to less-or-equal and flip the
1115 case nir_op_uge32
: {
1117 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1118 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1119 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1120 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1123 /* Swap via temporary */
1124 nir_alu_src temp
= instr
->src
[1];
1125 instr
->src
[1] = instr
->src
[0];
1126 instr
->src
[0] = temp
;
1131 case nir_op_b32csel
: {
1132 op
= midgard_alu_op_fcsel
;
1134 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1137 emit_condition(ctx
, &instr
->src
[0].src
, false);
1139 /* The condition is the first argument; move the other
1140 * arguments up one to be a binary instruction for
1143 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1148 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1153 /* Fetch unit, quirks, etc information */
1154 unsigned opcode_props
= alu_opcode_props
[op
];
1155 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1157 /* Initialise fields common between scalar/vector instructions */
1158 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1160 /* src0 will always exist afaik, but src1 will not for 1-argument
1161 * instructions. The latter can only be fetched if the instruction
1162 * needs it, or else we may segfault. */
1164 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1165 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1167 /* Rather than use the instruction generation helpers, we do it
1168 * ourselves here to avoid the mess */
1170 midgard_instruction ins
= {
1173 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1174 .src1
= quirk_flipped_r24
? src0
: src1
,
1179 nir_alu_src
*nirmods
[2] = { NULL
};
1181 if (nr_inputs
== 2) {
1182 nirmods
[0] = &instr
->src
[0];
1183 nirmods
[1] = &instr
->src
[1];
1184 } else if (nr_inputs
== 1) {
1185 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1190 midgard_vector_alu alu
= {
1192 .reg_mode
= midgard_reg_mode_full
,
1193 .dest_override
= midgard_dest_override_none
,
1196 /* Writemask only valid for non-SSA NIR */
1197 .mask
= expand_writemask((1 << nr_components
) - 1),
1199 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1200 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1203 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1206 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1210 /* Late fixup for emulated instructions */
1212 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1213 /* Presently, our second argument is an inline #0 constant.
1214 * Switch over to an embedded 1.0 constant (that can't fit
1215 * inline, since we're 32-bit, not 16-bit like the inline
1218 ins
.ssa_args
.inline_constant
= false;
1219 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1220 ins
.has_constants
= true;
1222 if (instr
->op
== nir_op_b2f32
) {
1223 ins
.constants
[0] = 1.0f
;
1225 /* Type pun it into place */
1227 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1230 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1231 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1232 ins
.ssa_args
.inline_constant
= false;
1233 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1234 ins
.has_constants
= true;
1235 ins
.constants
[0] = 0.0f
;
1236 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1239 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1240 /* To avoid duplicating the lookup tables (probably), true LUT
1241 * instructions can only operate as if they were scalars. Lower
1242 * them here by changing the component. */
1244 uint8_t original_swizzle
[4];
1245 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1247 for (int i
= 0; i
< nr_components
; ++i
) {
1248 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1250 for (int j
= 0; j
< 4; ++j
)
1251 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1253 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1254 emit_mir_instruction(ctx
, ins
);
1257 emit_mir_instruction(ctx
, ins
);
1264 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
)
1266 /* TODO: half-floats */
1268 if (offset
< ctx
->uniform_cutoff
) {
1269 /* Fast path: For the first 16 uniform,
1270 * accesses are 0-cycle, since they're
1271 * just a register fetch in the usual
1272 * case. So, we alias the registers
1273 * while we're still in SSA-space */
1275 int reg_slot
= 23 - offset
;
1276 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1278 /* Otherwise, read from the 'special'
1279 * UBO to access higher-indexed
1280 * uniforms, at a performance cost */
1282 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1284 /* TODO: Don't split */
1285 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1286 ins
.load_store
.address
= offset
>> 3;
1288 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1289 emit_mir_instruction(ctx
, ins
);
1294 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1296 /* First, pull out the destination */
1297 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1299 /* Now, figure out which uniform this is */
1300 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1301 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1303 /* Sysvals are prefix uniforms */
1304 unsigned uniform
= ((uintptr_t) val
) - 1;
1306 emit_uniform_read(ctx
, dest
, uniform
);
1310 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1312 unsigned offset
, reg
;
1314 switch (instr
->intrinsic
) {
1315 case nir_intrinsic_discard_if
:
1316 emit_condition(ctx
, &instr
->src
[0], true);
1320 case nir_intrinsic_discard
: {
1321 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1322 struct midgard_instruction discard
= v_branch(conditional
, false);
1323 discard
.branch
.target_type
= TARGET_DISCARD
;
1324 emit_mir_instruction(ctx
, discard
);
1326 ctx
->can_discard
= true;
1330 case nir_intrinsic_load_uniform
:
1331 case nir_intrinsic_load_input
:
1332 assert(nir_src_is_const(instr
->src
[0]) && "no indirect inputs");
1334 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[0]);
1336 reg
= nir_dest_index(ctx
, &instr
->dest
);
1338 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1339 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
);
1340 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1341 /* XXX: Half-floats? */
1342 /* TODO: swizzle, mask */
1344 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1346 midgard_varying_parameter p
= {
1348 .interpolation
= midgard_interp_default
,
1349 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1353 memcpy(&u
, &p
, sizeof(p
));
1354 ins
.load_store
.varying_parameters
= u
;
1356 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1357 emit_mir_instruction(ctx
, ins
);
1358 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1359 /* Constant encoded as a pinned constant */
1361 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1362 ins
.has_constants
= true;
1363 ins
.has_blend_constant
= true;
1364 emit_mir_instruction(ctx
, ins
);
1365 } else if (ctx
->is_blend
) {
1366 /* For blend shaders, a load might be
1367 * translated various ways depending on what
1368 * we're loading. Figure out how this is used */
1370 nir_variable
*out
= NULL
;
1372 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1373 int drvloc
= var
->data
.driver_location
;
1375 if (nir_intrinsic_base(instr
) == drvloc
) {
1383 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1384 /* Source color preloaded to r0 */
1386 midgard_pin_output(ctx
, reg
, 0);
1387 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1388 /* Destination color must be read from framebuffer */
1390 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1391 ins
.load_store
.swizzle
= 0; /* xxxx */
1393 /* Read each component sequentially */
1395 for (int c
= 0; c
< 4; ++c
) {
1396 ins
.load_store
.mask
= (1 << c
);
1397 ins
.load_store
.unknown
= c
;
1398 emit_mir_instruction(ctx
, ins
);
1401 /* vadd.u2f hr2, abs(hr2), #0 */
1403 midgard_vector_alu_src alu_src
= blank_alu_src
;
1405 alu_src
.half
= true;
1407 midgard_instruction u2f
= {
1411 .src1
= SSA_UNUSED_0
,
1413 .inline_constant
= true
1416 .op
= midgard_alu_op_u2f
,
1417 .reg_mode
= midgard_reg_mode_half
,
1418 .dest_override
= midgard_dest_override_none
,
1420 .src1
= vector_alu_srco_unsigned(alu_src
),
1421 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1425 emit_mir_instruction(ctx
, u2f
);
1427 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1429 alu_src
.abs
= false;
1431 midgard_instruction fmul
= {
1433 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1437 .src1
= SSA_UNUSED_0
,
1438 .inline_constant
= true
1441 .op
= midgard_alu_op_fmul
,
1442 .reg_mode
= midgard_reg_mode_full
,
1443 .dest_override
= midgard_dest_override_none
,
1444 .outmod
= midgard_outmod_sat
,
1446 .src1
= vector_alu_srco_unsigned(alu_src
),
1447 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1451 emit_mir_instruction(ctx
, fmul
);
1453 DBG("Unknown input in blend shader\n");
1456 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1457 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1458 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1459 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1460 emit_mir_instruction(ctx
, ins
);
1462 DBG("Unknown load\n");
1468 case nir_intrinsic_store_output
:
1469 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1471 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1473 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1475 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1476 /* gl_FragColor is not emitted with load/store
1477 * instructions. Instead, it gets plonked into
1478 * r0 at the end of the shader and we do the
1479 * framebuffer writeout dance. TODO: Defer
1482 midgard_pin_output(ctx
, reg
, 0);
1484 /* Save the index we're writing to for later reference
1485 * in the epilogue */
1487 ctx
->fragment_output
= reg
;
1488 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1489 /* Varyings are written into one of two special
1490 * varying register, r26 or r27. The register itself is selected as the register
1491 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1493 * Normally emitting fmov's is frowned upon,
1494 * but due to unique constraints of
1495 * REGISTER_VARYING, fmov emission + a
1496 * dedicated cleanup pass is the only way to
1497 * guarantee correctness when considering some
1498 * (common) edge cases XXX: FIXME */
1500 /* If this varying corresponds to a constant (why?!),
1501 * emit that now since it won't get picked up by
1502 * hoisting (since there is no corresponding move
1503 * emitted otherwise) */
1505 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1507 if (constant_value
) {
1508 /* Special case: emit the varying write
1509 * directly to r26 (looks funny in asm but it's
1510 * fine) and emit the store _now_. Possibly
1511 * slightly slower, but this is a really stupid
1512 * special case anyway (why on earth would you
1513 * have a constant varying? Your own fault for
1514 * slightly worse perf :P) */
1516 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1517 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1518 emit_mir_instruction(ctx
, ins
);
1520 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1521 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1522 emit_mir_instruction(ctx
, st
);
1524 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1526 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1529 DBG("Unknown store\n");
1535 case nir_intrinsic_load_alpha_ref_float
:
1536 assert(instr
->dest
.is_ssa
);
1538 float ref_value
= ctx
->alpha_ref
;
1540 float *v
= ralloc_array(NULL
, float, 4);
1541 memcpy(v
, &ref_value
, sizeof(float));
1542 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1545 case nir_intrinsic_load_viewport_scale
:
1546 case nir_intrinsic_load_viewport_offset
:
1547 emit_sysval_read(ctx
, instr
);
1551 printf ("Unhandled intrinsic\n");
1558 midgard_tex_format(enum glsl_sampler_dim dim
)
1561 case GLSL_SAMPLER_DIM_2D
:
1562 case GLSL_SAMPLER_DIM_EXTERNAL
:
1565 case GLSL_SAMPLER_DIM_3D
:
1568 case GLSL_SAMPLER_DIM_CUBE
:
1569 return TEXTURE_CUBE
;
1572 DBG("Unknown sampler dim type\n");
1579 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1582 //assert (!instr->sampler);
1583 //assert (!instr->texture_array_size);
1584 assert (instr
->op
== nir_texop_tex
);
1586 /* Allocate registers via a round robin scheme to alternate between the two registers */
1587 int reg
= ctx
->texture_op_count
& 1;
1588 int in_reg
= reg
, out_reg
= reg
;
1590 /* Make room for the reg */
1592 if (ctx
->texture_index
[reg
] > -1)
1593 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1595 int texture_index
= instr
->texture_index
;
1596 int sampler_index
= texture_index
;
1598 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1599 switch (instr
->src
[i
].src_type
) {
1600 case nir_tex_src_coord
: {
1601 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1603 midgard_vector_alu_src alu_src
= blank_alu_src
;
1605 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1607 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1608 /* For cubemaps, we need to load coords into
1609 * special r27, and then use a special ld/st op
1610 * to copy into the texture register */
1612 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1614 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1615 emit_mir_instruction(ctx
, move
);
1617 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1618 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1619 st
.load_store
.mask
= 0x3; /* xy? */
1620 st
.load_store
.swizzle
= alu_src
.swizzle
;
1621 emit_mir_instruction(ctx
, st
);
1624 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1626 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1627 emit_mir_instruction(ctx
, ins
);
1630 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1636 DBG("Unknown source type\n");
1643 /* No helper to build texture words -- we do it all here */
1644 midgard_instruction ins
= {
1645 .type
= TAG_TEXTURE_4
,
1647 .op
= TEXTURE_OP_NORMAL
,
1648 .format
= midgard_tex_format(instr
->sampler_dim
),
1649 .texture_handle
= texture_index
,
1650 .sampler_handle
= sampler_index
,
1652 /* TODO: Don't force xyzw */
1653 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1665 /* Assume we can continue; hint it out later */
1670 /* Set registers to read and write from the same place */
1671 ins
.texture
.in_reg_select
= in_reg
;
1672 ins
.texture
.out_reg_select
= out_reg
;
1674 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1675 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1676 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1677 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1678 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1680 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1681 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1682 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1685 emit_mir_instruction(ctx
, ins
);
1687 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1689 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1690 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1691 ctx
->texture_index
[reg
] = o_index
;
1693 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1694 emit_mir_instruction(ctx
, ins2
);
1696 /* Used for .cont and .last hinting */
1697 ctx
->texture_op_count
++;
1701 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1703 switch (instr
->type
) {
1704 case nir_jump_break
: {
1705 /* Emit a branch out of the loop */
1706 struct midgard_instruction br
= v_branch(false, false);
1707 br
.branch
.target_type
= TARGET_BREAK
;
1708 br
.branch
.target_break
= ctx
->current_loop
;
1709 emit_mir_instruction(ctx
, br
);
1716 DBG("Unknown jump type %d\n", instr
->type
);
1722 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1724 switch (instr
->type
) {
1725 case nir_instr_type_load_const
:
1726 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1729 case nir_instr_type_intrinsic
:
1730 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1733 case nir_instr_type_alu
:
1734 emit_alu(ctx
, nir_instr_as_alu(instr
));
1737 case nir_instr_type_tex
:
1738 emit_tex(ctx
, nir_instr_as_tex(instr
));
1741 case nir_instr_type_jump
:
1742 emit_jump(ctx
, nir_instr_as_jump(instr
));
1745 case nir_instr_type_ssa_undef
:
1750 DBG("Unhandled instruction type\n");
1755 /* Determine the actual hardware from the index based on the RA results or special values */
1758 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1760 if (reg
>= SSA_FIXED_MINIMUM
)
1761 return SSA_REG_FROM_FIXED(reg
);
1764 assert(reg
< maxreg
);
1765 int r
= ra_get_node_reg(g
, reg
);
1766 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1771 /* fmov style unused */
1773 return REGISTER_UNUSED
;
1775 /* lut style unused */
1777 return REGISTER_UNUSED
;
1780 DBG("Unknown SSA register alias %d\n", reg
);
1787 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1789 /* Choose the first available register to minimise reported register pressure */
1791 for (int i
= 0; i
< 16; ++i
) {
1792 if (BITSET_TEST(regs
, i
)) {
1802 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1804 if (ins
->ssa_args
.src0
== src
) return true;
1805 if (ins
->ssa_args
.src1
== src
) return true;
1811 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1813 /* Check the rest of the block for liveness */
1814 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1815 if (midgard_is_live_in_instr(ins
, src
))
1819 /* Check the rest of the blocks for liveness */
1820 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1821 mir_foreach_instr_in_block(b
, ins
) {
1822 if (midgard_is_live_in_instr(ins
, src
))
1827 /* TODO: How does control flow interact in complex shaders? */
1833 allocate_registers(compiler_context
*ctx
)
1835 /* First, initialize the RA */
1836 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1838 /* Create a primary (general purpose) class, as well as special purpose
1839 * pipeline register classes */
1841 int primary_class
= ra_alloc_reg_class(regs
);
1842 int varying_class
= ra_alloc_reg_class(regs
);
1844 /* Add the full set of work registers */
1845 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1846 for (int i
= 0; i
< work_count
; ++i
)
1847 ra_class_add_reg(regs
, primary_class
, i
);
1849 /* Add special registers */
1850 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1851 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1853 /* We're done setting up */
1854 ra_set_finalize(regs
, NULL
);
1856 /* Transform the MIR into squeezed index form */
1857 mir_foreach_block(ctx
, block
) {
1858 mir_foreach_instr_in_block(block
, ins
) {
1859 if (ins
->compact_branch
) continue;
1861 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1862 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1863 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1865 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1866 print_mir_block(block
);
1869 /* Let's actually do register allocation */
1870 int nodes
= ctx
->temp_count
;
1871 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1873 /* Set everything to the work register class, unless it has somewhere
1876 mir_foreach_block(ctx
, block
) {
1877 mir_foreach_instr_in_block(block
, ins
) {
1878 if (ins
->compact_branch
) continue;
1880 if (ins
->ssa_args
.dest
< 0) continue;
1882 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1884 int class = primary_class
;
1886 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1890 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1891 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1894 unsigned reg
= temp
- 1;
1895 int t
= find_or_allocate_temp(ctx
, index
);
1896 ra_set_node_reg(g
, t
, reg
);
1900 /* Determine liveness */
1902 int *live_start
= malloc(nodes
* sizeof(int));
1903 int *live_end
= malloc(nodes
* sizeof(int));
1905 /* Initialize as non-existent */
1907 for (int i
= 0; i
< nodes
; ++i
) {
1908 live_start
[i
] = live_end
[i
] = -1;
1913 mir_foreach_block(ctx
, block
) {
1914 mir_foreach_instr_in_block(block
, ins
) {
1915 if (ins
->compact_branch
) continue;
1917 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1918 /* If this destination is not yet live, it is now since we just wrote it */
1920 int dest
= ins
->ssa_args
.dest
;
1922 if (live_start
[dest
] == -1)
1923 live_start
[dest
] = d
;
1926 /* Since we just used a source, the source might be
1927 * dead now. Scan the rest of the block for
1928 * invocations, and if there are none, the source dies
1931 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1933 for (int src
= 0; src
< 2; ++src
) {
1934 int s
= sources
[src
];
1936 if (s
< 0) continue;
1938 if (s
>= SSA_FIXED_MINIMUM
) continue;
1940 if (!is_live_after(ctx
, block
, ins
, s
)) {
1949 /* If a node still hasn't been killed, kill it now */
1951 for (int i
= 0; i
< nodes
; ++i
) {
1952 /* live_start == -1 most likely indicates a pinned output */
1954 if (live_end
[i
] == -1)
1958 /* Setup interference between nodes that are live at the same time */
1960 for (int i
= 0; i
< nodes
; ++i
) {
1961 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1962 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1963 ra_add_node_interference(g
, i
, j
);
1967 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1969 if (!ra_allocate(g
)) {
1970 DBG("Error allocating registers\n");
1978 mir_foreach_block(ctx
, block
) {
1979 mir_foreach_instr_in_block(block
, ins
) {
1980 if (ins
->compact_branch
) continue;
1982 ssa_args args
= ins
->ssa_args
;
1984 switch (ins
->type
) {
1986 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1988 ins
->registers
.src2_imm
= args
.inline_constant
;
1990 if (args
.inline_constant
) {
1991 /* Encode inline 16-bit constant as a vector by default */
1993 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1995 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1997 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1998 ins
->alu
.src2
= imm
<< 2;
2000 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2003 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2007 case TAG_LOAD_STORE_4
: {
2008 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2009 /* TODO: use ssa_args for store_vary */
2010 ins
->load_store
.reg
= 0;
2012 bool has_dest
= args
.dest
>= 0;
2013 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2015 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2028 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2029 * use scalar ALU instructions, for functional or performance reasons. To do
2030 * this, we just demote vector ALU payloads to scalar. */
2033 component_from_mask(unsigned mask
)
2035 for (int c
= 0; c
< 4; ++c
) {
2036 if (mask
& (3 << (2 * c
)))
2045 is_single_component_mask(unsigned mask
)
2049 for (int c
= 0; c
< 4; ++c
)
2050 if (mask
& (3 << (2 * c
)))
2053 return components
== 1;
2056 /* Create a mask of accessed components from a swizzle to figure out vector
2060 swizzle_to_access_mask(unsigned swizzle
)
2062 unsigned component_mask
= 0;
2064 for (int i
= 0; i
< 4; ++i
) {
2065 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2066 component_mask
|= (1 << c
);
2069 return component_mask
;
2073 vector_to_scalar_source(unsigned u
)
2075 midgard_vector_alu_src v
;
2076 memcpy(&v
, &u
, sizeof(v
));
2078 midgard_scalar_alu_src s
= {
2082 .component
= (v
.swizzle
& 3) << 1
2086 memcpy(&o
, &s
, sizeof(s
));
2088 return o
& ((1 << 6) - 1);
2091 static midgard_scalar_alu
2092 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2094 /* The output component is from the mask */
2095 midgard_scalar_alu s
= {
2097 .src1
= vector_to_scalar_source(v
.src1
),
2098 .src2
= vector_to_scalar_source(v
.src2
),
2101 .output_full
= 1, /* TODO: Half */
2102 .output_component
= component_from_mask(v
.mask
) << 1,
2105 /* Inline constant is passed along rather than trying to extract it
2108 if (ins
->ssa_args
.inline_constant
) {
2110 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2111 imm
|= (lower_11
>> 9) & 3;
2112 imm
|= (lower_11
>> 6) & 4;
2113 imm
|= (lower_11
>> 2) & 0x38;
2114 imm
|= (lower_11
& 63) << 6;
2122 /* Midgard prefetches instruction types, so during emission we need to
2123 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2124 * if this is the second to last and the last is an ALU, then it's also 1... */
2126 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2127 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2129 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2130 bytes_emitted += sizeof(type)
2133 emit_binary_vector_instruction(midgard_instruction
*ains
,
2134 uint16_t *register_words
, int *register_words_count
,
2135 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2136 size_t *bytes_emitted
)
2138 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2139 *bytes_emitted
+= sizeof(midgard_reg_info
);
2141 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2142 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2143 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2146 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2147 * mind that we are a vector architecture and we can write to different
2148 * components simultaneously */
2151 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2153 /* Each instruction reads some registers and writes to a register. See
2154 * where the first writes */
2156 /* Figure out where exactly we wrote to */
2157 int source
= first
->ssa_args
.dest
;
2158 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2160 /* As long as the second doesn't read from the first, we're okay */
2161 if (second
->ssa_args
.src0
== source
) {
2162 if (first
->type
== TAG_ALU_4
) {
2163 /* Figure out which components we just read from */
2165 int q
= second
->alu
.src1
;
2166 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2168 /* Check if there are components in common, and fail if so */
2169 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2176 if (second
->ssa_args
.src1
== source
)
2179 /* Otherwise, it's safe in that regard. Another data hazard is both
2180 * writing to the same place, of course */
2182 if (second
->ssa_args
.dest
== source
) {
2183 /* ...but only if the components overlap */
2184 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2186 if (dest_mask
& source_mask
)
2196 midgard_instruction
**segment
, unsigned segment_size
,
2197 midgard_instruction
*ains
)
2199 for (int s
= 0; s
< segment_size
; ++s
)
2200 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2208 /* Schedules, but does not emit, a single basic block. After scheduling, the
2209 * final tag and size of the block are known, which are necessary for branching
2212 static midgard_bundle
2213 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2215 int instructions_emitted
= 0, instructions_consumed
= -1;
2216 midgard_bundle bundle
= { 0 };
2218 uint8_t tag
= ins
->type
;
2220 /* Default to the instruction's tag */
2223 switch (ins
->type
) {
2225 uint32_t control
= 0;
2226 size_t bytes_emitted
= sizeof(control
);
2228 /* TODO: Constant combining */
2229 int index
= 0, last_unit
= 0;
2231 /* Previous instructions, for the purpose of parallelism */
2232 midgard_instruction
*segment
[4] = {0};
2233 int segment_size
= 0;
2235 instructions_emitted
= -1;
2236 midgard_instruction
*pins
= ins
;
2239 midgard_instruction
*ains
= pins
;
2241 /* Advance instruction pointer */
2243 ains
= mir_next_op(pins
);
2247 /* Out-of-work condition */
2248 if ((struct list_head
*) ains
== &block
->instructions
)
2251 /* Ensure that the chain can continue */
2252 if (ains
->type
!= TAG_ALU_4
) break;
2254 /* According to the presentation "The ARM
2255 * Mali-T880 Mobile GPU" from HotChips 27,
2256 * there are two pipeline stages. Branching
2257 * position determined experimentally. Lines
2258 * are executed in parallel:
2261 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2263 * Verify that there are no ordering dependencies here.
2265 * TODO: Allow for parallelism!!!
2268 /* Pick a unit for it if it doesn't force a particular unit */
2270 int unit
= ains
->unit
;
2273 int op
= ains
->alu
.op
;
2274 int units
= alu_opcode_props
[op
];
2276 /* TODO: Promotion of scalars to vectors */
2277 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2280 assert(units
& UNITS_SCALAR
);
2283 if (last_unit
>= UNIT_VADD
) {
2284 if (units
& UNIT_VLUT
)
2289 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2291 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2293 else if (units
& UNIT_VLUT
)
2299 if (last_unit
>= UNIT_VADD
) {
2300 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2302 else if (units
& UNIT_VLUT
)
2307 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2309 else if (units
& UNIT_SMUL
)
2310 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2311 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2318 assert(unit
& units
);
2321 /* Late unit check, this time for encoding (not parallelism) */
2322 if (unit
<= last_unit
) break;
2324 /* Clear the segment */
2325 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2328 if (midgard_has_hazard(segment
, segment_size
, ains
))
2331 /* We're good to go -- emit the instruction */
2334 segment
[segment_size
++] = ains
;
2336 /* Only one set of embedded constants per
2337 * bundle possible; if we have more, we must
2338 * break the chain early, unfortunately */
2340 if (ains
->has_constants
) {
2341 if (bundle
.has_embedded_constants
) {
2342 /* ...but if there are already
2343 * constants but these are the
2344 * *same* constants, we let it
2347 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2350 bundle
.has_embedded_constants
= true;
2351 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2353 /* If this is a blend shader special constant, track it for patching */
2354 if (ains
->has_blend_constant
)
2355 bundle
.has_blend_constant
= true;
2359 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2360 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2361 &bundle
.register_words_count
, bundle
.body_words
,
2362 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2363 } else if (ains
->compact_branch
) {
2364 /* All of r0 has to be written out
2365 * along with the branch writeout.
2368 if (ains
->writeout
) {
2370 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2371 ins
.unit
= UNIT_VMUL
;
2373 control
|= ins
.unit
;
2375 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2376 &bundle
.register_words_count
, bundle
.body_words
,
2377 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2379 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2380 bool written_late
= false;
2381 bool components
[4] = { 0 };
2382 uint16_t register_dep_mask
= 0;
2383 uint16_t written_mask
= 0;
2385 midgard_instruction
*qins
= ins
;
2386 for (int t
= 0; t
< index
; ++t
) {
2387 if (qins
->registers
.out_reg
!= 0) {
2388 /* Mark down writes */
2390 written_mask
|= (1 << qins
->registers
.out_reg
);
2392 /* Mark down the register dependencies for errata check */
2394 if (qins
->registers
.src1_reg
< 16)
2395 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2397 if (qins
->registers
.src2_reg
< 16)
2398 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2400 int mask
= qins
->alu
.mask
;
2402 for (int c
= 0; c
< 4; ++c
)
2403 if (mask
& (0x3 << (2 * c
)))
2404 components
[c
] = true;
2406 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2408 if (qins
->unit
== UNIT_VLUT
)
2409 written_late
= true;
2412 /* Advance instruction pointer */
2413 qins
= mir_next_op(qins
);
2417 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2418 if (register_dep_mask
& written_mask
) {
2419 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2426 /* If even a single component is not written, break it up (conservative check). */
2427 bool breakup
= false;
2429 for (int c
= 0; c
< 4; ++c
)
2436 /* Otherwise, we're free to proceed */
2440 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2441 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2442 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2443 bytes_emitted
+= sizeof(midgard_branch_extended
);
2445 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2446 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2447 bytes_emitted
+= sizeof(ains
->br_compact
);
2450 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2451 bytes_emitted
+= sizeof(midgard_reg_info
);
2453 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2454 bundle
.body_words_count
++;
2455 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2458 /* Defer marking until after writing to allow for break */
2459 control
|= ains
->unit
;
2460 last_unit
= ains
->unit
;
2461 ++instructions_emitted
;
2465 /* Bubble up the number of instructions for skipping */
2466 instructions_consumed
= index
- 1;
2470 /* Pad ALU op to nearest word */
2472 if (bytes_emitted
& 15) {
2473 padding
= 16 - (bytes_emitted
& 15);
2474 bytes_emitted
+= padding
;
2477 /* Constants must always be quadwords */
2478 if (bundle
.has_embedded_constants
)
2479 bytes_emitted
+= 16;
2481 /* Size ALU instruction for tag */
2482 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2483 bundle
.padding
= padding
;
2484 bundle
.control
= bundle
.tag
| control
;
2489 case TAG_LOAD_STORE_4
: {
2490 /* Load store instructions have two words at once. If
2491 * we only have one queued up, we need to NOP pad.
2492 * Otherwise, we store both in succession to save space
2493 * and cycles -- letting them go in parallel -- skip
2494 * the next. The usefulness of this optimisation is
2495 * greatly dependent on the quality of the instruction
2499 midgard_instruction
*next_op
= mir_next_op(ins
);
2501 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2502 /* As the two operate concurrently, make sure
2503 * they are not dependent */
2505 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2506 /* Skip ahead, since it's redundant with the pair */
2507 instructions_consumed
= 1 + (instructions_emitted
++);
2515 /* Texture ops default to single-op-per-bundle scheduling */
2519 /* Copy the instructions into the bundle */
2520 bundle
.instruction_count
= instructions_emitted
+ 1;
2524 midgard_instruction
*uins
= ins
;
2525 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2526 bundle
.instructions
[used_idx
++] = *uins
;
2527 uins
= mir_next_op(uins
);
2530 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2536 quadword_size(int tag
)
2551 case TAG_LOAD_STORE_4
:
2563 /* Schedule a single block by iterating its instruction to create bundles.
2564 * While we go, tally about the bundle sizes to compute the block size. */
2567 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2569 util_dynarray_init(&block
->bundles
, NULL
);
2571 block
->quadword_count
= 0;
2573 mir_foreach_instr_in_block(block
, ins
) {
2575 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2576 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2578 if (bundle
.has_blend_constant
) {
2579 /* TODO: Multiblock? */
2580 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2581 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2585 ins
= mir_next_op(ins
);
2587 block
->quadword_count
+= quadword_size(bundle
.tag
);
2590 block
->is_scheduled
= true;
2594 schedule_program(compiler_context
*ctx
)
2596 allocate_registers(ctx
);
2598 mir_foreach_block(ctx
, block
) {
2599 schedule_block(ctx
, block
);
2603 /* After everything is scheduled, emit whole bundles at a time */
2606 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2608 int lookahead
= next_tag
<< 4;
2610 switch (bundle
->tag
) {
2615 /* Actually emit each component */
2616 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2618 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2619 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2621 /* Emit body words based on the instructions bundled */
2622 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2623 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2625 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2626 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2627 } else if (ins
->compact_branch
) {
2628 /* Dummy move, XXX DRY */
2629 if ((i
== 0) && ins
->writeout
) {
2630 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2631 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2634 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2635 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2637 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2641 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2642 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2646 /* Emit padding (all zero) */
2647 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2649 /* Tack on constants */
2651 if (bundle
->has_embedded_constants
) {
2652 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2653 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2654 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2655 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2661 case TAG_LOAD_STORE_4
: {
2662 /* One or two composing instructions */
2664 uint64_t current64
, next64
= LDST_NOP
;
2666 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2668 if (bundle
->instruction_count
== 2)
2669 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2671 midgard_load_store instruction
= {
2672 .type
= bundle
->tag
,
2673 .next_type
= next_tag
,
2678 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2683 case TAG_TEXTURE_4
: {
2684 /* Texture instructions are easy, since there is no
2685 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2687 midgard_instruction
*ins
= &bundle
->instructions
[0];
2689 ins
->texture
.type
= TAG_TEXTURE_4
;
2690 ins
->texture
.next_type
= next_tag
;
2692 ctx
->texture_op_count
--;
2694 if (!ctx
->texture_op_count
) {
2695 ins
->texture
.cont
= 0;
2696 ins
->texture
.last
= 1;
2699 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2704 DBG("Unknown midgard instruction type\n");
2711 /* ALU instructions can inline or embed constants, which decreases register
2712 * pressure and saves space. */
2714 #define CONDITIONAL_ATTACH(src) { \
2715 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2718 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2719 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2724 inline_alu_constants(compiler_context
*ctx
)
2726 mir_foreach_instr(ctx
, alu
) {
2727 /* Other instructions cannot inline constants */
2728 if (alu
->type
!= TAG_ALU_4
) continue;
2730 /* If there is already a constant here, we can do nothing */
2731 if (alu
->has_constants
) continue;
2733 CONDITIONAL_ATTACH(src0
);
2735 if (!alu
->has_constants
) {
2736 CONDITIONAL_ATTACH(src1
)
2737 } else if (!alu
->inline_constant
) {
2738 /* Corner case: _two_ vec4 constants, for instance with a
2739 * csel. For this case, we can only use a constant
2740 * register for one, we'll have to emit a move for the
2741 * other. Note, if both arguments are constants, then
2742 * necessarily neither argument depends on the value of
2743 * any particular register. As the destination register
2744 * will be wiped, that means we can spill the constant
2745 * to the destination register.
2748 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2749 unsigned scratch
= alu
->ssa_args
.dest
;
2752 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2753 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2755 /* Force a break XXX Defer r31 writes */
2756 ins
.unit
= UNIT_VLUT
;
2758 /* Set the source */
2759 alu
->ssa_args
.src1
= scratch
;
2761 /* Inject us -before- the last instruction which set r31 */
2762 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2768 /* Midgard supports two types of constants, embedded constants (128-bit) and
2769 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2770 * constants can be demoted to inline constants, for space savings and
2771 * sometimes a performance boost */
2774 embedded_to_inline_constant(compiler_context
*ctx
)
2776 mir_foreach_instr(ctx
, ins
) {
2777 if (!ins
->has_constants
) continue;
2779 if (ins
->ssa_args
.inline_constant
) continue;
2781 /* Blend constants must not be inlined by definition */
2782 if (ins
->has_blend_constant
) continue;
2784 /* src1 cannot be an inline constant due to encoding
2785 * restrictions. So, if possible we try to flip the arguments
2788 int op
= ins
->alu
.op
;
2790 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2791 /* Flip based on op. Fallthrough intentional */
2794 /* These ops require an operational change to flip their arguments TODO */
2795 case midgard_alu_op_flt
:
2796 case midgard_alu_op_fle
:
2797 case midgard_alu_op_ilt
:
2798 case midgard_alu_op_ile
:
2799 case midgard_alu_op_fcsel
:
2800 case midgard_alu_op_icsel
:
2801 case midgard_alu_op_isub
:
2802 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2805 /* These ops are commutative and Just Flip */
2806 case midgard_alu_op_fne
:
2807 case midgard_alu_op_fadd
:
2808 case midgard_alu_op_fmul
:
2809 case midgard_alu_op_fmin
:
2810 case midgard_alu_op_fmax
:
2811 case midgard_alu_op_iadd
:
2812 case midgard_alu_op_imul
:
2813 case midgard_alu_op_feq
:
2814 case midgard_alu_op_ieq
:
2815 case midgard_alu_op_ine
:
2816 case midgard_alu_op_iand
:
2817 case midgard_alu_op_ior
:
2818 case midgard_alu_op_ixor
:
2819 /* Flip the SSA numbers */
2820 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2821 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2823 /* And flip the modifiers */
2827 src_temp
= ins
->alu
.src2
;
2828 ins
->alu
.src2
= ins
->alu
.src1
;
2829 ins
->alu
.src1
= src_temp
;
2836 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2837 /* Extract the source information */
2839 midgard_vector_alu_src
*src
;
2840 int q
= ins
->alu
.src2
;
2841 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2844 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2845 int component
= src
->swizzle
& 3;
2847 /* Scale constant appropriately, if we can legally */
2848 uint16_t scaled_constant
= 0;
2850 /* XXX: Check legality */
2851 if (midgard_is_integer_op(op
)) {
2852 /* TODO: Inline integer */
2855 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2856 scaled_constant
= (uint16_t) iconstants
[component
];
2858 /* Constant overflow after resize */
2859 if (scaled_constant
!= iconstants
[component
])
2862 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2865 /* We don't know how to handle these with a constant */
2867 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2868 DBG("Bailing inline constant...\n");
2872 /* Make sure that the constant is not itself a
2873 * vector by checking if all accessed values
2874 * (by the swizzle) are the same. */
2876 uint32_t *cons
= (uint32_t *) ins
->constants
;
2877 uint32_t value
= cons
[component
];
2879 bool is_vector
= false;
2880 unsigned mask
= effective_writemask(&ins
->alu
);
2882 for (int c
= 1; c
< 4; ++c
) {
2883 /* We only care if this component is actually used */
2884 if (!(mask
& (1 << c
)))
2887 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2889 if (test
!= value
) {
2898 /* Get rid of the embedded constant */
2899 ins
->has_constants
= false;
2900 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2901 ins
->ssa_args
.inline_constant
= true;
2902 ins
->inline_constant
= scaled_constant
;
2907 /* Map normal SSA sources to other SSA sources / fixed registers (like
2911 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2913 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2916 /* Remove entry in leftovers to avoid a redunant fmov */
2918 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2921 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2923 /* Assign the alias map */
2929 #define AS_SRC(to, u) \
2930 int q##to = ins->alu.src2; \
2931 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2933 /* Removing unused moves is necessary to clean up the texture pipeline results.
2935 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2938 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2940 mir_foreach_instr_in_block_safe(block
, ins
) {
2941 if (ins
->type
!= TAG_ALU_4
) continue;
2943 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2945 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2947 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2949 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2951 mir_remove_instruction(ins
);
2955 /* The following passes reorder MIR instructions to enable better scheduling */
2958 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2960 mir_foreach_instr_in_block_safe(block
, ins
) {
2961 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2963 /* We've found a load/store op. Check if next is also load/store. */
2964 midgard_instruction
*next_op
= mir_next_op(ins
);
2965 if (&next_op
->link
!= &block
->instructions
) {
2966 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2967 /* If so, we're done since we're a pair */
2968 ins
= mir_next_op(ins
);
2972 /* Maximum search distance to pair, to avoid register pressure disasters */
2973 int search_distance
= 8;
2975 /* Otherwise, we have an orphaned load/store -- search for another load */
2976 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2977 /* Terminate search if necessary */
2978 if (!(search_distance
--)) break;
2980 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2982 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2984 /* We found one! Move it up to pair and remove it from the old location */
2986 mir_insert_instruction_before(ins
, *c
);
2987 mir_remove_instruction(c
);
2995 /* Emit varying stores late */
2998 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2999 /* Iterate in reverse to get the final write, rather than the first */
3001 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3002 /* Check if what we just wrote needs a store */
3003 int idx
= ins
->ssa_args
.dest
;
3004 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3006 if (!varying
) continue;
3010 /* We need to store to the appropriate varying, so emit the
3013 /* TODO: Integrate with special purpose RA (and scheduler?) */
3014 bool high_varying_register
= false;
3016 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3018 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3019 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3021 mir_insert_instruction_before(mir_next_op(ins
), st
);
3022 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3024 /* We no longer need to store this varying */
3025 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3029 /* If there are leftovers after the below pass, emit actual fmov
3030 * instructions for the slow-but-correct path */
3033 emit_leftover_move(compiler_context
*ctx
)
3035 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3036 int base
= ((uintptr_t) leftover
->key
) - 1;
3039 map_ssa_to_alias(ctx
, &mapped
);
3040 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3045 actualise_ssa_to_alias(compiler_context
*ctx
)
3047 mir_foreach_instr(ctx
, ins
) {
3048 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3049 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3052 emit_leftover_move(ctx
);
3055 /* Vertex shaders do not write gl_Position as is; instead, they write a
3056 * transformed screen space position as a varying. See section 12.5 "Coordinate
3057 * Transformation" of the ES 3.2 full specification for details.
3059 * This transformation occurs early on, as NIR and prior to optimisation, in
3060 * order to take advantage of NIR optimisation passes of the transform itself.
3064 write_transformed_position(nir_builder
*b
, nir_src input_point_src
)
3066 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
3067 nir_ssa_def
*scale
= nir_load_viewport_scale(b
);
3068 nir_ssa_def
*offset
= nir_load_viewport_offset(b
);
3070 /* World space to normalised device coordinates to screen space */
3072 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
3073 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
3074 nir_ssa_def
*screen
= nir_fadd(b
, nir_fmul(b
, ndc_point
, scale
), offset
);
3076 /* gl_Position will be written out in screenspace xyz, with w set to
3077 * the reciprocal we computed earlier. The transformed w component is
3078 * then used for perspective-correct varying interpolation. The
3079 * transformed w component must preserve its original sign; this is
3080 * used in depth clipping computations */
3082 nir_ssa_def
*screen_space
= nir_vec4(b
,
3083 nir_channel(b
, screen
, 0),
3084 nir_channel(b
, screen
, 1),
3085 nir_channel(b
, screen
, 2),
3088 /* Finally, write out the transformed values to the varying */
3090 nir_intrinsic_instr
*store
;
3091 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
3092 store
->num_components
= 4;
3093 nir_intrinsic_set_base(store
, 0);
3094 nir_intrinsic_set_write_mask(store
, 0xf);
3095 store
->src
[0].ssa
= screen_space
;
3096 store
->src
[0].is_ssa
= true;
3097 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
3098 nir_builder_instr_insert(b
, &store
->instr
);
3102 transform_position_writes(nir_shader
*shader
)
3104 nir_foreach_function(func
, shader
) {
3105 nir_foreach_block(block
, func
->impl
) {
3106 nir_foreach_instr_safe(instr
, block
) {
3107 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
3109 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
3110 nir_variable
*out
= NULL
;
3112 switch (intr
->intrinsic
) {
3113 case nir_intrinsic_store_output
:
3114 /* already had i/o lowered.. lookup the matching output var: */
3115 nir_foreach_variable(var
, &shader
->outputs
) {
3116 int drvloc
= var
->data
.driver_location
;
3118 if (nir_intrinsic_base(intr
) == drvloc
) {
3132 if (out
->data
.mode
!= nir_var_shader_out
)
3135 if (out
->data
.location
!= VARYING_SLOT_POS
)
3139 nir_builder_init(&b
, func
->impl
);
3140 b
.cursor
= nir_before_instr(instr
);
3142 write_transformed_position(&b
, intr
->src
[0]);
3143 nir_instr_remove(instr
);
3150 emit_fragment_epilogue(compiler_context
*ctx
)
3152 /* Special case: writing out constants requires us to include the move
3153 * explicitly now, so shove it into r0 */
3155 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3157 if (constant_value
) {
3158 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3159 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3160 emit_mir_instruction(ctx
, ins
);
3163 /* Perform the actual fragment writeout. We have two writeout/branch
3164 * instructions, forming a loop until writeout is successful as per the
3165 * docs. TODO: gl_FragDepth */
3167 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3168 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3171 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3172 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3173 * with the int8 analogue to the fragment epilogue */
3176 emit_blend_epilogue(compiler_context
*ctx
)
3178 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3180 midgard_instruction scale
= {
3183 .inline_constant
= _mesa_float_to_half(255.0),
3185 .src0
= SSA_FIXED_REGISTER(0),
3186 .src1
= SSA_UNUSED_0
,
3187 .dest
= SSA_FIXED_REGISTER(24),
3188 .inline_constant
= true
3191 .op
= midgard_alu_op_fmul
,
3192 .reg_mode
= midgard_reg_mode_full
,
3193 .dest_override
= midgard_dest_override_lower
,
3195 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3196 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3200 emit_mir_instruction(ctx
, scale
);
3202 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3204 midgard_vector_alu_src alu_src
= blank_alu_src
;
3205 alu_src
.half
= true;
3207 midgard_instruction f2u8
= {
3210 .src0
= SSA_FIXED_REGISTER(24),
3211 .src1
= SSA_UNUSED_0
,
3212 .dest
= SSA_FIXED_REGISTER(0),
3213 .inline_constant
= true
3216 .op
= midgard_alu_op_f2u8
,
3217 .reg_mode
= midgard_reg_mode_half
,
3218 .dest_override
= midgard_dest_override_lower
,
3219 .outmod
= midgard_outmod_pos
,
3221 .src1
= vector_alu_srco_unsigned(alu_src
),
3222 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3226 emit_mir_instruction(ctx
, f2u8
);
3228 /* vmul.imov.quarter r0, r0, r0 */
3230 midgard_instruction imov_8
= {
3233 .src0
= SSA_UNUSED_1
,
3234 .src1
= SSA_FIXED_REGISTER(0),
3235 .dest
= SSA_FIXED_REGISTER(0),
3238 .op
= midgard_alu_op_imov
,
3239 .reg_mode
= midgard_reg_mode_quarter
,
3240 .dest_override
= midgard_dest_override_none
,
3242 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3243 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3247 /* Emit branch epilogue with the 8-bit move as the source */
3249 emit_mir_instruction(ctx
, imov_8
);
3250 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3252 emit_mir_instruction(ctx
, imov_8
);
3253 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3256 static midgard_block
*
3257 emit_block(compiler_context
*ctx
, nir_block
*block
)
3259 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3260 list_addtail(&this_block
->link
, &ctx
->blocks
);
3262 this_block
->is_scheduled
= false;
3265 ctx
->texture_index
[0] = -1;
3266 ctx
->texture_index
[1] = -1;
3268 /* Set up current block */
3269 list_inithead(&this_block
->instructions
);
3270 ctx
->current_block
= this_block
;
3272 nir_foreach_instr(instr
, block
) {
3273 emit_instr(ctx
, instr
);
3274 ++ctx
->instruction_count
;
3277 inline_alu_constants(ctx
);
3278 embedded_to_inline_constant(ctx
);
3280 /* Perform heavylifting for aliasing */
3281 actualise_ssa_to_alias(ctx
);
3283 midgard_emit_store(ctx
, this_block
);
3284 midgard_eliminate_orphan_moves(ctx
, this_block
);
3285 midgard_pair_load_store(ctx
, this_block
);
3287 /* Append fragment shader epilogue (value writeout) */
3288 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3289 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3291 emit_blend_epilogue(ctx
);
3293 emit_fragment_epilogue(ctx
);
3297 /* Fallthrough save */
3298 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3300 if (block
== nir_start_block(ctx
->func
->impl
))
3301 ctx
->initial_block
= this_block
;
3303 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3304 ctx
->final_block
= this_block
;
3306 /* Allow the next control flow to access us retroactively, for
3308 ctx
->current_block
= this_block
;
3310 /* Document the fallthrough chain */
3311 ctx
->previous_source_block
= this_block
;
3316 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3319 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3321 /* Conditional branches expect the condition in r31.w; emit a move for
3322 * that in the _previous_ block (which is the current block). */
3323 emit_condition(ctx
, &nif
->condition
, true);
3325 /* Speculatively emit the branch, but we can't fill it in until later */
3326 EMIT(branch
, true, true);
3327 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3329 /* Emit the two subblocks */
3330 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3332 /* Emit a jump from the end of the then block to the end of the else */
3333 EMIT(branch
, false, false);
3334 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3336 /* Emit second block, and check if it's empty */
3338 int else_idx
= ctx
->block_count
;
3339 int count_in
= ctx
->instruction_count
;
3340 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3341 int after_else_idx
= ctx
->block_count
;
3343 /* Now that we have the subblocks emitted, fix up the branches */
3348 if (ctx
->instruction_count
== count_in
) {
3349 /* The else block is empty, so don't emit an exit jump */
3350 mir_remove_instruction(then_exit
);
3351 then_branch
->branch
.target_block
= after_else_idx
;
3353 then_branch
->branch
.target_block
= else_idx
;
3354 then_exit
->branch
.target_block
= after_else_idx
;
3359 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3361 /* Remember where we are */
3362 midgard_block
*start_block
= ctx
->current_block
;
3364 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3365 * single current_loop variable, maybe we need a stack */
3367 int loop_idx
= ++ctx
->current_loop
;
3369 /* Get index from before the body so we can loop back later */
3370 int start_idx
= ctx
->block_count
;
3372 /* Emit the body itself */
3373 emit_cf_list(ctx
, &nloop
->body
);
3375 /* Branch back to loop back */
3376 struct midgard_instruction br_back
= v_branch(false, false);
3377 br_back
.branch
.target_block
= start_idx
;
3378 emit_mir_instruction(ctx
, br_back
);
3380 /* Find the index of the block about to follow us (note: we don't add
3381 * one; blocks are 0-indexed so we get a fencepost problem) */
3382 int break_block_idx
= ctx
->block_count
;
3384 /* Fix up the break statements we emitted to point to the right place,
3385 * now that we can allocate a block number for them */
3387 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3388 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3389 print_mir_block(block
);
3390 mir_foreach_instr_in_block(block
, ins
) {
3391 if (ins
->type
!= TAG_ALU_4
) continue;
3392 if (!ins
->compact_branch
) continue;
3393 if (ins
->prepacked_branch
) continue;
3395 /* We found a branch -- check the type to see if we need to do anything */
3396 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3398 /* It's a break! Check if it's our break */
3399 if (ins
->branch
.target_break
!= loop_idx
) continue;
3401 /* Okay, cool, we're breaking out of this loop.
3402 * Rewrite from a break to a goto */
3404 ins
->branch
.target_type
= TARGET_GOTO
;
3405 ins
->branch
.target_block
= break_block_idx
;
3410 static midgard_block
*
3411 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3413 midgard_block
*start_block
= NULL
;
3415 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3416 switch (node
->type
) {
3417 case nir_cf_node_block
: {
3418 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3421 start_block
= block
;
3426 case nir_cf_node_if
:
3427 emit_if(ctx
, nir_cf_node_as_if(node
));
3430 case nir_cf_node_loop
:
3431 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3434 case nir_cf_node_function
:
3443 /* Due to lookahead, we need to report the first tag executed in the command
3444 * stream and in branch targets. An initial block might be empty, so iterate
3445 * until we find one that 'works' */
3448 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3450 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3452 unsigned first_tag
= 0;
3455 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3457 if (initial_bundle
) {
3458 first_tag
= initial_bundle
->tag
;
3462 /* Initial block is empty, try the next block */
3463 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3464 } while(initial_block
!= NULL
);
3471 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3473 struct util_dynarray
*compiled
= &program
->compiled
;
3475 midgard_debug
= debug_get_option_midgard_debug();
3477 compiler_context ictx
= {
3479 .stage
= nir
->info
.stage
,
3481 .is_blend
= is_blend
,
3482 .blend_constant_offset
= -1,
3484 .alpha_ref
= program
->alpha_ref
3487 compiler_context
*ctx
= &ictx
;
3489 /* TODO: Decide this at runtime */
3490 ctx
->uniform_cutoff
= 8;
3492 /* Assign var locations early, so the epilogue can use them if necessary */
3494 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3495 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3496 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3498 /* Initialize at a global (not block) level hash tables */
3500 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3501 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3502 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3503 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3504 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3505 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3506 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3508 /* Record the varying mapping for the command stream's bookkeeping */
3510 struct exec_list
*varyings
=
3511 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3513 nir_foreach_variable(var
, varyings
) {
3514 unsigned loc
= var
->data
.driver_location
;
3515 program
->varyings
[loc
] = var
->data
.location
;
3518 /* Lower vars -- not I/O -- before epilogue */
3520 NIR_PASS_V(nir
, nir_lower_var_copies
);
3521 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3522 NIR_PASS_V(nir
, nir_split_var_copies
);
3523 NIR_PASS_V(nir
, nir_lower_var_copies
);
3524 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3525 NIR_PASS_V(nir
, nir_lower_var_copies
);
3526 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3528 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3530 /* Append vertex epilogue before optimisation, so the epilogue itself
3533 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3534 transform_position_writes(nir
);
3536 /* Optimisation passes */
3540 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3541 nir_print_shader(nir
, stdout
);
3544 /* Assign sysvals and counts, now that we're sure
3545 * (post-optimisation) */
3547 midgard_nir_assign_sysvals(ctx
, nir
);
3549 program
->uniform_count
= nir
->num_uniforms
;
3550 program
->sysval_count
= ctx
->sysval_count
;
3551 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3553 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3554 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3556 nir_foreach_function(func
, nir
) {
3560 list_inithead(&ctx
->blocks
);
3561 ctx
->block_count
= 0;
3564 emit_cf_list(ctx
, &func
->impl
->body
);
3565 emit_block(ctx
, func
->impl
->end_block
);
3567 break; /* TODO: Multi-function shaders */
3570 util_dynarray_init(compiled
, NULL
);
3573 schedule_program(ctx
);
3575 /* Now that all the bundles are scheduled and we can calculate block
3576 * sizes, emit actual branch instructions rather than placeholders */
3578 int br_block_idx
= 0;
3580 mir_foreach_block(ctx
, block
) {
3581 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3582 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3583 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3585 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3587 if (ins
->prepacked_branch
) continue;
3589 /* Parse some basic branch info */
3590 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3591 bool is_conditional
= ins
->branch
.conditional
;
3592 bool is_inverted
= ins
->branch
.invert_conditional
;
3593 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3595 /* Determine the block we're jumping to */
3596 int target_number
= ins
->branch
.target_block
;
3598 /* Report the destination tag. Discards don't need this */
3599 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3601 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3602 int quadword_offset
= 0;
3605 /* Jump to the end of the shader. We
3606 * need to include not only the
3607 * following blocks, but also the
3608 * contents of our current block (since
3609 * discard can come in the middle of
3612 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3614 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3615 quadword_offset
+= quadword_size(bun
->tag
);
3618 mir_foreach_block_from(ctx
, blk
, b
) {
3619 quadword_offset
+= b
->quadword_count
;
3622 } else if (target_number
> br_block_idx
) {
3625 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3626 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3629 quadword_offset
+= blk
->quadword_count
;
3632 /* Jump backwards */
3634 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3635 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3638 quadword_offset
-= blk
->quadword_count
;
3642 /* Unconditional extended branches (far jumps)
3643 * have issues, so we always use a conditional
3644 * branch, setting the condition to always for
3645 * unconditional. For compact unconditional
3646 * branches, cond isn't used so it doesn't
3647 * matter what we pick. */
3649 midgard_condition cond
=
3650 !is_conditional
? midgard_condition_always
:
3651 is_inverted
? midgard_condition_false
:
3652 midgard_condition_true
;
3654 midgard_jmp_writeout_op op
=
3655 is_discard
? midgard_jmp_writeout_op_discard
:
3656 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3657 midgard_jmp_writeout_op_branch_cond
;
3660 midgard_branch_extended branch
=
3661 midgard_create_branch_extended(
3666 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3667 } else if (is_conditional
|| is_discard
) {
3668 midgard_branch_cond branch
= {
3670 .dest_tag
= dest_tag
,
3671 .offset
= quadword_offset
,
3675 assert(branch
.offset
== quadword_offset
);
3677 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3679 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3681 midgard_branch_uncond branch
= {
3683 .dest_tag
= dest_tag
,
3684 .offset
= quadword_offset
,
3688 assert(branch
.offset
== quadword_offset
);
3690 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3698 /* Emit flat binary from the instruction arrays. Iterate each block in
3699 * sequence. Save instruction boundaries such that lookahead tags can
3700 * be assigned easily */
3702 /* Cache _all_ bundles in source order for lookahead across failed branches */
3704 int bundle_count
= 0;
3705 mir_foreach_block(ctx
, block
) {
3706 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3708 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3710 mir_foreach_block(ctx
, block
) {
3711 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3712 source_order_bundles
[bundle_idx
++] = bundle
;
3716 int current_bundle
= 0;
3718 mir_foreach_block(ctx
, block
) {
3719 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3722 if (current_bundle
+ 1 < bundle_count
) {
3723 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3725 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3732 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3736 /* TODO: Free deeper */
3737 //util_dynarray_fini(&block->instructions);
3740 free(source_order_bundles
);
3742 /* Report the very first tag executed */
3743 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3745 /* Deal with off-by-one related to the fencepost problem */
3746 program
->work_register_count
= ctx
->work_registers
+ 1;
3748 program
->can_discard
= ctx
->can_discard
;
3749 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3751 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3753 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3754 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);