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panfrost/midgard: Lower inot to inor with 0
[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value debug_options[] = {
54 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
56 DEBUG_NAMED_VALUE_END
57 };
58
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
60
61 int midgard_debug = 0;
62
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67
68 static bool
69 midgard_is_branch_unit(unsigned unit)
70 {
71 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
72 }
73
74 static void
75 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
76 {
77 block->successors[block->nr_successors++] = successor;
78 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
79 }
80
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
83
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
91 .ssa_args = { \
92 .rname = ssa, \
93 .uname = -1, \
94 .src1 = -1 \
95 }, \
96 .load_store = { \
97 .op = midgard_op_##name, \
98 .mask = 0xF, \
99 .swizzle = SWIZZLE_XYZW, \
100 .address = address \
101 } \
102 }; \
103 \
104 return i; \
105 }
106
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
109
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
112
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src *src, bool is_int)
115 {
116 if (!src) return blank_alu_src;
117
118 midgard_vector_alu_src alu_src = {
119 .rep_low = 0,
120 .rep_high = 0,
121 .half = 0, /* TODO */
122 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
123 };
124
125 if (is_int) {
126 /* TODO: sign-extend/zero-extend */
127 alu_src.mod = midgard_int_normal;
128
129 /* These should have been lowered away */
130 assert(!(src->abs || src->negate));
131 } else {
132 alu_src.mod = (src->abs << 0) | (src->negate << 1);
133 }
134
135 return alu_src;
136 }
137
138 /* load/store instructions have both 32-bit and 16-bit variants, depending on
139 * whether we are using vectors composed of highp or mediump. At the moment, we
140 * don't support half-floats -- this requires changes in other parts of the
141 * compiler -- therefore the 16-bit versions are commented out. */
142
143 //M_LOAD(ld_attr_16);
144 M_LOAD(ld_attr_32);
145 //M_LOAD(ld_vary_16);
146 M_LOAD(ld_vary_32);
147 //M_LOAD(ld_uniform_16);
148 M_LOAD(ld_uniform_32);
149 M_LOAD(ld_color_buffer_8);
150 //M_STORE(st_vary_16);
151 M_STORE(st_vary_32);
152 M_STORE(st_cubemap_coords);
153
154 static midgard_instruction
155 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
156 {
157 midgard_branch_cond branch = {
158 .op = op,
159 .dest_tag = tag,
160 .offset = offset,
161 .cond = cond
162 };
163
164 uint16_t compact;
165 memcpy(&compact, &branch, sizeof(branch));
166
167 midgard_instruction ins = {
168 .type = TAG_ALU_4,
169 .unit = ALU_ENAB_BR_COMPACT,
170 .prepacked_branch = true,
171 .compact_branch = true,
172 .br_compact = compact
173 };
174
175 if (op == midgard_jmp_writeout_op_writeout)
176 ins.writeout = true;
177
178 return ins;
179 }
180
181 static midgard_instruction
182 v_branch(bool conditional, bool invert)
183 {
184 midgard_instruction ins = {
185 .type = TAG_ALU_4,
186 .unit = ALU_ENAB_BRANCH,
187 .compact_branch = true,
188 .branch = {
189 .conditional = conditional,
190 .invert_conditional = invert
191 }
192 };
193
194 return ins;
195 }
196
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond,
199 midgard_jmp_writeout_op op,
200 unsigned dest_tag,
201 signed quadword_offset)
202 {
203 /* For unclear reasons, the condition code is repeated 8 times */
204 uint16_t duplicated_cond =
205 (cond << 14) |
206 (cond << 12) |
207 (cond << 10) |
208 (cond << 8) |
209 (cond << 6) |
210 (cond << 4) |
211 (cond << 2) |
212 (cond << 0);
213
214 midgard_branch_extended branch = {
215 .op = op,
216 .dest_tag = dest_tag,
217 .offset = quadword_offset,
218 .cond = duplicated_cond
219 };
220
221 return branch;
222 }
223
224 static void
225 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
226 {
227 ins->has_constants = true;
228 memcpy(&ins->constants, constants, 16);
229 }
230
231 static int
232 glsl_type_size(const struct glsl_type *type, bool bindless)
233 {
234 return glsl_count_attribute_slots(type, false);
235 }
236
237 /* Lower fdot2 to a vector multiplication followed by channel addition */
238 static void
239 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
240 {
241 if (alu->op != nir_op_fdot2)
242 return;
243
244 b->cursor = nir_before_instr(&alu->instr);
245
246 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
247 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
248
249 nir_ssa_def *product = nir_fmul(b, src0, src1);
250
251 nir_ssa_def *sum = nir_fadd(b,
252 nir_channel(b, product, 0),
253 nir_channel(b, product, 1));
254
255 /* Replace the fdot2 with this sum */
256 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
257 }
258
259 static int
260 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
261 {
262 switch (instr->intrinsic) {
263 case nir_intrinsic_load_viewport_scale:
264 return PAN_SYSVAL_VIEWPORT_SCALE;
265 case nir_intrinsic_load_viewport_offset:
266 return PAN_SYSVAL_VIEWPORT_OFFSET;
267 default:
268 return -1;
269 }
270 }
271
272 static void
273 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
274 {
275 int sysval = -1;
276
277 if (instr->type == nir_instr_type_intrinsic) {
278 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
279 sysval = midgard_nir_sysval_for_intrinsic(intr);
280 }
281
282 if (sysval < 0)
283 return;
284
285 /* We have a sysval load; check if it's already been assigned */
286
287 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
288 return;
289
290 /* It hasn't -- so assign it now! */
291
292 unsigned id = ctx->sysval_count++;
293 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
294 ctx->sysvals[id] = sysval;
295 }
296
297 static void
298 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
299 {
300 ctx->sysval_count = 0;
301
302 nir_foreach_function(function, shader) {
303 if (!function->impl) continue;
304
305 nir_foreach_block(block, function->impl) {
306 nir_foreach_instr_safe(instr, block) {
307 midgard_nir_assign_sysval_body(ctx, instr);
308 }
309 }
310 }
311 }
312
313 static bool
314 midgard_nir_lower_fdot2(nir_shader *shader)
315 {
316 bool progress = false;
317
318 nir_foreach_function(function, shader) {
319 if (!function->impl) continue;
320
321 nir_builder _b;
322 nir_builder *b = &_b;
323 nir_builder_init(b, function->impl);
324
325 nir_foreach_block(block, function->impl) {
326 nir_foreach_instr_safe(instr, block) {
327 if (instr->type != nir_instr_type_alu) continue;
328
329 nir_alu_instr *alu = nir_instr_as_alu(instr);
330 midgard_nir_lower_fdot2_body(b, alu);
331
332 progress |= true;
333 }
334 }
335
336 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
337
338 }
339
340 return progress;
341 }
342
343 static void
344 optimise_nir(nir_shader *nir)
345 {
346 bool progress;
347 unsigned lower_flrp =
348 (nir->options->lower_flrp16 ? 16 : 0) |
349 (nir->options->lower_flrp32 ? 32 : 0) |
350 (nir->options->lower_flrp64 ? 64 : 0);
351
352 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
353 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
354 NIR_PASS(progress, nir, nir_lower_idiv);
355
356 nir_lower_tex_options lower_tex_options = {
357 .lower_rect = true
358 };
359
360 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
361
362 do {
363 progress = false;
364
365 NIR_PASS(progress, nir, nir_lower_var_copies);
366 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
367
368 NIR_PASS(progress, nir, nir_copy_prop);
369 NIR_PASS(progress, nir, nir_opt_dce);
370 NIR_PASS(progress, nir, nir_opt_dead_cf);
371 NIR_PASS(progress, nir, nir_opt_cse);
372 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
373 NIR_PASS(progress, nir, nir_opt_algebraic);
374 NIR_PASS(progress, nir, nir_opt_constant_folding);
375
376 if (lower_flrp != 0) {
377 bool lower_flrp_progress = false;
378 NIR_PASS(lower_flrp_progress,
379 nir,
380 nir_lower_flrp,
381 lower_flrp,
382 false /* always_precise */,
383 nir->options->lower_ffma);
384 if (lower_flrp_progress) {
385 NIR_PASS(progress, nir,
386 nir_opt_constant_folding);
387 progress = true;
388 }
389
390 /* Nothing should rematerialize any flrps, so we only
391 * need to do this lowering once.
392 */
393 lower_flrp = 0;
394 }
395
396 NIR_PASS(progress, nir, nir_opt_undef);
397 NIR_PASS(progress, nir, nir_opt_loop_unroll,
398 nir_var_shader_in |
399 nir_var_shader_out |
400 nir_var_function_temp);
401
402 /* TODO: Enable vectorize when merged upstream */
403 // NIR_PASS(progress, nir, nir_opt_vectorize);
404 } while (progress);
405
406 /* Must be run at the end to prevent creation of fsin/fcos ops */
407 NIR_PASS(progress, nir, midgard_nir_scale_trig);
408
409 do {
410 progress = false;
411
412 NIR_PASS(progress, nir, nir_opt_dce);
413 NIR_PASS(progress, nir, nir_opt_algebraic);
414 NIR_PASS(progress, nir, nir_opt_constant_folding);
415 NIR_PASS(progress, nir, nir_copy_prop);
416 } while (progress);
417
418 NIR_PASS(progress, nir, nir_opt_algebraic_late);
419
420 /* We implement booleans as 32-bit 0/~0 */
421 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
422
423 /* Now that booleans are lowered, we can run out late opts */
424 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
425
426 /* Lower mods for float ops only. Integer ops don't support modifiers
427 * (saturate doesn't make sense on integers, neg/abs require dedicated
428 * instructions) */
429
430 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
431 NIR_PASS(progress, nir, nir_copy_prop);
432 NIR_PASS(progress, nir, nir_opt_dce);
433
434 /* Take us out of SSA */
435 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
436 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
437
438 /* We are a vector architecture; write combine where possible */
439 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
440 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
441
442 NIR_PASS(progress, nir, nir_opt_dce);
443 }
444
445 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
446 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
447 * r0. See the comments in compiler_context */
448
449 static void
450 alias_ssa(compiler_context *ctx, int dest, int src)
451 {
452 _mesa_hash_table_u64_insert(ctx->ssa_to_alias, dest + 1, (void *) ((uintptr_t) src + 1));
453 _mesa_set_add(ctx->leftover_ssa_to_alias, (void *) (uintptr_t) (dest + 1));
454 }
455
456 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
457
458 static void
459 unalias_ssa(compiler_context *ctx, int dest)
460 {
461 _mesa_hash_table_u64_remove(ctx->ssa_to_alias, dest + 1);
462 /* TODO: Remove from leftover or no? */
463 }
464
465 /* Do not actually emit a load; instead, cache the constant for inlining */
466
467 static void
468 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
469 {
470 nir_ssa_def def = instr->def;
471
472 float *v = rzalloc_array(NULL, float, 4);
473 nir_const_load_to_arr(v, instr, f32);
474 _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
475 }
476
477 static unsigned
478 nir_src_index(compiler_context *ctx, nir_src *src)
479 {
480 if (src->is_ssa)
481 return src->ssa->index;
482 else {
483 assert(!src->reg.indirect);
484 return ctx->func->impl->ssa_alloc + src->reg.reg->index;
485 }
486 }
487
488 static unsigned
489 nir_dest_index(compiler_context *ctx, nir_dest *dst)
490 {
491 if (dst->is_ssa)
492 return dst->ssa.index;
493 else {
494 assert(!dst->reg.indirect);
495 return ctx->func->impl->ssa_alloc + dst->reg.reg->index;
496 }
497 }
498
499 static unsigned
500 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
501 {
502 return nir_src_index(ctx, &src->src);
503 }
504
505 static bool
506 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
507 {
508 unsigned comp = src->swizzle[0];
509
510 for (unsigned c = 1; c < nr_components; ++c) {
511 if (src->swizzle[c] != comp)
512 return true;
513 }
514
515 return false;
516 }
517
518 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
519 * output of a conditional test) into that register */
520
521 static void
522 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
523 {
524 int condition = nir_src_index(ctx, src);
525
526 /* Source to swizzle the desired component into w */
527
528 const midgard_vector_alu_src alu_src = {
529 .swizzle = SWIZZLE(component, component, component, component),
530 };
531
532 /* There is no boolean move instruction. Instead, we simulate a move by
533 * ANDing the condition with itself to get it into r31.w */
534
535 midgard_instruction ins = {
536 .type = TAG_ALU_4,
537
538 /* We need to set the conditional as close as possible */
539 .precede_break = true,
540 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
541
542 .ssa_args = {
543
544 .src0 = condition,
545 .src1 = condition,
546 .dest = SSA_FIXED_REGISTER(31),
547 },
548 .alu = {
549 .op = midgard_alu_op_iand,
550 .outmod = midgard_outmod_int,
551 .reg_mode = midgard_reg_mode_32,
552 .dest_override = midgard_dest_override_none,
553 .mask = (0x3 << 6), /* w */
554 .src1 = vector_alu_srco_unsigned(alu_src),
555 .src2 = vector_alu_srco_unsigned(alu_src)
556 },
557 };
558
559 emit_mir_instruction(ctx, ins);
560 }
561
562 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
563 * r31 instead */
564
565 static void
566 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
567 {
568 int condition = nir_src_index(ctx, &src->src);
569
570 /* Source to swizzle the desired component into w */
571
572 const midgard_vector_alu_src alu_src = {
573 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
574 };
575
576 /* There is no boolean move instruction. Instead, we simulate a move by
577 * ANDing the condition with itself to get it into r31.w */
578
579 midgard_instruction ins = {
580 .type = TAG_ALU_4,
581 .precede_break = true,
582 .ssa_args = {
583 .src0 = condition,
584 .src1 = condition,
585 .dest = SSA_FIXED_REGISTER(31),
586 },
587 .alu = {
588 .op = midgard_alu_op_iand,
589 .outmod = midgard_outmod_int,
590 .reg_mode = midgard_reg_mode_32,
591 .dest_override = midgard_dest_override_none,
592 .mask = expand_writemask((1 << nr_comp) - 1),
593 .src1 = vector_alu_srco_unsigned(alu_src),
594 .src2 = vector_alu_srco_unsigned(alu_src)
595 },
596 };
597
598 emit_mir_instruction(ctx, ins);
599 }
600
601
602
603 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
604 * pinning to eliminate this move in all known cases */
605
606 static void
607 emit_indirect_offset(compiler_context *ctx, nir_src *src)
608 {
609 int offset = nir_src_index(ctx, src);
610
611 midgard_instruction ins = {
612 .type = TAG_ALU_4,
613 .ssa_args = {
614 .src0 = SSA_UNUSED_1,
615 .src1 = offset,
616 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
617 },
618 .alu = {
619 .op = midgard_alu_op_imov,
620 .outmod = midgard_outmod_int,
621 .reg_mode = midgard_reg_mode_32,
622 .dest_override = midgard_dest_override_none,
623 .mask = (0x3 << 6), /* w */
624 .src1 = vector_alu_srco_unsigned(zero_alu_src),
625 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
626 },
627 };
628
629 emit_mir_instruction(ctx, ins);
630 }
631
632 #define ALU_CASE(nir, _op) \
633 case nir_op_##nir: \
634 op = midgard_alu_op_##_op; \
635 break;
636 static bool
637 nir_is_fzero_constant(nir_src src)
638 {
639 if (!nir_src_is_const(src))
640 return false;
641
642 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
643 if (nir_src_comp_as_float(src, c) != 0.0)
644 return false;
645 }
646
647 return true;
648 }
649
650 static void
651 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
652 {
653 bool is_ssa = instr->dest.dest.is_ssa;
654
655 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
656 unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components;
657 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
658
659 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
660 * supported. A few do not and are commented for now. Also, there are a
661 * number of NIR ops which Midgard does not support and need to be
662 * lowered, also TODO. This switch block emits the opcode and calling
663 * convention of the Midgard instruction; actual packing is done in
664 * emit_alu below */
665
666 unsigned op;
667
668 switch (instr->op) {
669 ALU_CASE(fadd, fadd);
670 ALU_CASE(fmul, fmul);
671 ALU_CASE(fmin, fmin);
672 ALU_CASE(fmax, fmax);
673 ALU_CASE(imin, imin);
674 ALU_CASE(imax, imax);
675 ALU_CASE(umin, umin);
676 ALU_CASE(umax, umax);
677 ALU_CASE(ffloor, ffloor);
678 ALU_CASE(fround_even, froundeven);
679 ALU_CASE(ftrunc, ftrunc);
680 ALU_CASE(fceil, fceil);
681 ALU_CASE(fdot3, fdot3);
682 ALU_CASE(fdot4, fdot4);
683 ALU_CASE(iadd, iadd);
684 ALU_CASE(isub, isub);
685 ALU_CASE(imul, imul);
686
687 /* Zero shoved as second-arg */
688 ALU_CASE(iabs, iabsdiff);
689
690 ALU_CASE(mov, imov);
691
692 ALU_CASE(feq32, feq);
693 ALU_CASE(fne32, fne);
694 ALU_CASE(flt32, flt);
695 ALU_CASE(ieq32, ieq);
696 ALU_CASE(ine32, ine);
697 ALU_CASE(ilt32, ilt);
698 ALU_CASE(ult32, ult);
699
700 /* We don't have a native b2f32 instruction. Instead, like many
701 * GPUs, we exploit booleans as 0/~0 for false/true, and
702 * correspondingly AND
703 * by 1.0 to do the type conversion. For the moment, prime us
704 * to emit:
705 *
706 * iand [whatever], #0
707 *
708 * At the end of emit_alu (as MIR), we'll fix-up the constant
709 */
710
711 ALU_CASE(b2f32, iand);
712 ALU_CASE(b2i32, iand);
713
714 /* Likewise, we don't have a dedicated f2b32 instruction, but
715 * we can do a "not equal to 0.0" test. */
716
717 ALU_CASE(f2b32, fne);
718 ALU_CASE(i2b32, ine);
719
720 ALU_CASE(frcp, frcp);
721 ALU_CASE(frsq, frsqrt);
722 ALU_CASE(fsqrt, fsqrt);
723 ALU_CASE(fexp2, fexp2);
724 ALU_CASE(flog2, flog2);
725
726 ALU_CASE(f2i32, f2i);
727 ALU_CASE(f2u32, f2u);
728 ALU_CASE(i2f32, i2f);
729 ALU_CASE(u2f32, u2f);
730
731 ALU_CASE(fsin, fsin);
732 ALU_CASE(fcos, fcos);
733
734 /* Second op implicit #0 */
735 ALU_CASE(inot, inor);
736 ALU_CASE(iand, iand);
737 ALU_CASE(ior, ior);
738 ALU_CASE(ixor, ixor);
739 ALU_CASE(ishl, ishl);
740 ALU_CASE(ishr, iasr);
741 ALU_CASE(ushr, ilsr);
742
743 ALU_CASE(b32all_fequal2, fball_eq);
744 ALU_CASE(b32all_fequal3, fball_eq);
745 ALU_CASE(b32all_fequal4, fball_eq);
746
747 ALU_CASE(b32any_fnequal2, fbany_neq);
748 ALU_CASE(b32any_fnequal3, fbany_neq);
749 ALU_CASE(b32any_fnequal4, fbany_neq);
750
751 ALU_CASE(b32all_iequal2, iball_eq);
752 ALU_CASE(b32all_iequal3, iball_eq);
753 ALU_CASE(b32all_iequal4, iball_eq);
754
755 ALU_CASE(b32any_inequal2, ibany_neq);
756 ALU_CASE(b32any_inequal3, ibany_neq);
757 ALU_CASE(b32any_inequal4, ibany_neq);
758
759 /* Source mods will be shoved in later */
760 ALU_CASE(fabs, fmov);
761 ALU_CASE(fneg, fmov);
762 ALU_CASE(fsat, fmov);
763
764 /* For greater-or-equal, we lower to less-or-equal and flip the
765 * arguments */
766
767 case nir_op_fge:
768 case nir_op_fge32:
769 case nir_op_ige32:
770 case nir_op_uge32: {
771 op =
772 instr->op == nir_op_fge ? midgard_alu_op_fle :
773 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
774 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
775 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
776 0;
777
778 /* Swap via temporary */
779 nir_alu_src temp = instr->src[1];
780 instr->src[1] = instr->src[0];
781 instr->src[0] = temp;
782
783 break;
784 }
785
786 case nir_op_b32csel: {
787 /* Midgard features both fcsel and icsel, depending on
788 * the type of the arguments/output. However, as long
789 * as we're careful we can _always_ use icsel and
790 * _never_ need fcsel, since the latter does additional
791 * floating-point-specific processing whereas the
792 * former just moves bits on the wire. It's not obvious
793 * why these are separate opcodes, save for the ability
794 * to do things like sat/pos/abs/neg for free */
795
796 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
797 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
798
799 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
800 nr_inputs = 2;
801
802 /* Emit the condition into r31 */
803
804 if (mixed)
805 emit_condition_mixed(ctx, &instr->src[0], nr_components);
806 else
807 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
808
809 /* The condition is the first argument; move the other
810 * arguments up one to be a binary instruction for
811 * Midgard */
812
813 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
814 break;
815 }
816
817 default:
818 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
819 assert(0);
820 return;
821 }
822
823 /* Midgard can perform certain modifiers on output of an ALU op */
824 midgard_outmod outmod =
825 midgard_is_integer_out_op(op) ? midgard_outmod_int :
826 instr->dest.saturate ? midgard_outmod_sat : midgard_outmod_none;
827
828 if (instr->op == nir_op_fsat)
829 outmod = midgard_outmod_sat;
830
831 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
832
833 if (instr->op == nir_op_fmax) {
834 if (nir_is_fzero_constant(instr->src[0].src)) {
835 op = midgard_alu_op_fmov;
836 nr_inputs = 1;
837 outmod = midgard_outmod_pos;
838 instr->src[0] = instr->src[1];
839 } else if (nir_is_fzero_constant(instr->src[1].src)) {
840 op = midgard_alu_op_fmov;
841 nr_inputs = 1;
842 outmod = midgard_outmod_pos;
843 }
844 }
845
846 /* Fetch unit, quirks, etc information */
847 unsigned opcode_props = alu_opcode_props[op].props;
848 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
849
850 /* src0 will always exist afaik, but src1 will not for 1-argument
851 * instructions. The latter can only be fetched if the instruction
852 * needs it, or else we may segfault. */
853
854 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
855 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
856
857 /* Rather than use the instruction generation helpers, we do it
858 * ourselves here to avoid the mess */
859
860 midgard_instruction ins = {
861 .type = TAG_ALU_4,
862 .ssa_args = {
863 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
864 .src1 = quirk_flipped_r24 ? src0 : src1,
865 .dest = dest,
866 }
867 };
868
869 nir_alu_src *nirmods[2] = { NULL };
870
871 if (nr_inputs == 2) {
872 nirmods[0] = &instr->src[0];
873 nirmods[1] = &instr->src[1];
874 } else if (nr_inputs == 1) {
875 nirmods[quirk_flipped_r24] = &instr->src[0];
876 } else {
877 assert(0);
878 }
879
880 /* These were lowered to a move, so apply the corresponding mod */
881
882 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
883 nir_alu_src *s = nirmods[quirk_flipped_r24];
884
885 if (instr->op == nir_op_fneg)
886 s->negate = !s->negate;
887
888 if (instr->op == nir_op_fabs)
889 s->abs = !s->abs;
890 }
891
892 bool is_int = midgard_is_integer_op(op);
893
894 midgard_vector_alu alu = {
895 .op = op,
896 .reg_mode = midgard_reg_mode_32,
897 .dest_override = midgard_dest_override_none,
898 .outmod = outmod,
899
900 /* Writemask only valid for non-SSA NIR */
901 .mask = expand_writemask((1 << nr_components) - 1),
902
903 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int)),
904 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int)),
905 };
906
907 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
908
909 if (!is_ssa)
910 alu.mask &= expand_writemask(instr->dest.write_mask);
911
912 ins.alu = alu;
913
914 /* Late fixup for emulated instructions */
915
916 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
917 /* Presently, our second argument is an inline #0 constant.
918 * Switch over to an embedded 1.0 constant (that can't fit
919 * inline, since we're 32-bit, not 16-bit like the inline
920 * constants) */
921
922 ins.ssa_args.inline_constant = false;
923 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
924 ins.has_constants = true;
925
926 if (instr->op == nir_op_b2f32) {
927 ins.constants[0] = 1.0f;
928 } else {
929 /* Type pun it into place */
930 uint32_t one = 0x1;
931 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
932 }
933
934 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
935 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
936 /* Lots of instructions need a 0 plonked in */
937 ins.ssa_args.inline_constant = false;
938 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
939 ins.has_constants = true;
940 ins.constants[0] = 0.0f;
941 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
942 } else if (instr->op == nir_op_inot) {
943 /* ~b = ~(b & b), so duplicate the source */
944 ins.ssa_args.src1 = ins.ssa_args.src0;
945 ins.alu.src2 = ins.alu.src1;
946 }
947
948 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
949 /* To avoid duplicating the lookup tables (probably), true LUT
950 * instructions can only operate as if they were scalars. Lower
951 * them here by changing the component. */
952
953 uint8_t original_swizzle[4];
954 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
955
956 for (int i = 0; i < nr_components; ++i) {
957 ins.alu.mask = (0x3) << (2 * i); /* Mask the associated component */
958
959 for (int j = 0; j < 4; ++j)
960 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
961
962 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int));
963 emit_mir_instruction(ctx, ins);
964 }
965 } else {
966 emit_mir_instruction(ctx, ins);
967 }
968 }
969
970 #undef ALU_CASE
971
972 static void
973 emit_uniform_read(compiler_context *ctx, unsigned dest, unsigned offset, nir_src *indirect_offset)
974 {
975 /* TODO: half-floats */
976
977 if (!indirect_offset && offset < ctx->uniform_cutoff) {
978 /* Fast path: For the first 16 uniforms, direct accesses are
979 * 0-cycle, since they're just a register fetch in the usual
980 * case. So, we alias the registers while we're still in
981 * SSA-space */
982
983 int reg_slot = 23 - offset;
984 alias_ssa(ctx, dest, SSA_FIXED_REGISTER(reg_slot));
985 } else {
986 /* Otherwise, read from the 'special' UBO to access
987 * higher-indexed uniforms, at a performance cost. More
988 * generally, we're emitting a UBO read instruction. */
989
990 midgard_instruction ins = m_ld_uniform_32(dest, offset);
991
992 /* TODO: Don't split */
993 ins.load_store.varying_parameters = (offset & 7) << 7;
994 ins.load_store.address = offset >> 3;
995
996 if (indirect_offset) {
997 emit_indirect_offset(ctx, indirect_offset);
998 ins.load_store.unknown = 0x8700; /* xxx: what is this? */
999 } else {
1000 ins.load_store.unknown = 0x1E00; /* xxx: what is this? */
1001 }
1002
1003 emit_mir_instruction(ctx, ins);
1004 }
1005 }
1006
1007 static void
1008 emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
1009 {
1010 /* First, pull out the destination */
1011 unsigned dest = nir_dest_index(ctx, &instr->dest);
1012
1013 /* Now, figure out which uniform this is */
1014 int sysval = midgard_nir_sysval_for_intrinsic(instr);
1015 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1016
1017 /* Sysvals are prefix uniforms */
1018 unsigned uniform = ((uintptr_t) val) - 1;
1019
1020 /* Emit the read itself -- this is never indirect */
1021 emit_uniform_read(ctx, dest, uniform, NULL);
1022 }
1023
1024 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1025 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1026 * generations have faster vectorized reads. This operation is for blend
1027 * shaders in particular; reading the tilebuffer from the fragment shader
1028 * remains an open problem. */
1029
1030 static void
1031 emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
1032 {
1033 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1034 ins.load_store.swizzle = 0; /* xxxx */
1035
1036 /* Read each component sequentially */
1037
1038 for (unsigned c = 0; c < 4; ++c) {
1039 ins.load_store.mask = (1 << c);
1040 ins.load_store.unknown = c;
1041 emit_mir_instruction(ctx, ins);
1042 }
1043
1044 /* vadd.u2f hr2, zext(hr2), #0 */
1045
1046 midgard_vector_alu_src alu_src = blank_alu_src;
1047 alu_src.mod = midgard_int_zero_extend;
1048 alu_src.half = true;
1049
1050 midgard_instruction u2f = {
1051 .type = TAG_ALU_4,
1052 .ssa_args = {
1053 .src0 = reg,
1054 .src1 = SSA_UNUSED_0,
1055 .dest = reg,
1056 .inline_constant = true
1057 },
1058 .alu = {
1059 .op = midgard_alu_op_u2f,
1060 .reg_mode = midgard_reg_mode_16,
1061 .dest_override = midgard_dest_override_none,
1062 .mask = 0xF,
1063 .src1 = vector_alu_srco_unsigned(alu_src),
1064 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1065 }
1066 };
1067
1068 emit_mir_instruction(ctx, u2f);
1069
1070 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1071
1072 alu_src.mod = 0;
1073
1074 midgard_instruction fmul = {
1075 .type = TAG_ALU_4,
1076 .inline_constant = _mesa_float_to_half(1.0 / 255.0),
1077 .ssa_args = {
1078 .src0 = reg,
1079 .dest = reg,
1080 .src1 = SSA_UNUSED_0,
1081 .inline_constant = true
1082 },
1083 .alu = {
1084 .op = midgard_alu_op_fmul,
1085 .reg_mode = midgard_reg_mode_32,
1086 .dest_override = midgard_dest_override_none,
1087 .outmod = midgard_outmod_sat,
1088 .mask = 0xFF,
1089 .src1 = vector_alu_srco_unsigned(alu_src),
1090 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1091 }
1092 };
1093
1094 emit_mir_instruction(ctx, fmul);
1095 }
1096
1097 static void
1098 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1099 {
1100 unsigned offset, reg;
1101
1102 switch (instr->intrinsic) {
1103 case nir_intrinsic_discard_if:
1104 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1105
1106 /* fallthrough */
1107
1108 case nir_intrinsic_discard: {
1109 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1110 struct midgard_instruction discard = v_branch(conditional, false);
1111 discard.branch.target_type = TARGET_DISCARD;
1112 emit_mir_instruction(ctx, discard);
1113
1114 ctx->can_discard = true;
1115 break;
1116 }
1117
1118 case nir_intrinsic_load_uniform:
1119 case nir_intrinsic_load_input:
1120 offset = nir_intrinsic_base(instr);
1121
1122 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1123 bool direct = nir_src_is_const(instr->src[0]);
1124
1125 if (direct) {
1126 offset += nir_src_as_uint(instr->src[0]);
1127 }
1128
1129 /* We may need to apply a fractional offset */
1130 int component = instr->intrinsic == nir_intrinsic_load_input ?
1131 nir_intrinsic_component(instr) : 0;
1132 reg = nir_dest_index(ctx, &instr->dest);
1133
1134 if (instr->intrinsic == nir_intrinsic_load_uniform && !ctx->is_blend) {
1135 emit_uniform_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL);
1136 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1137 /* XXX: Half-floats? */
1138 /* TODO: swizzle, mask */
1139
1140 midgard_instruction ins = m_ld_vary_32(reg, offset);
1141 ins.load_store.mask = (1 << nr_comp) - 1;
1142 ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component);
1143
1144 midgard_varying_parameter p = {
1145 .is_varying = 1,
1146 .interpolation = midgard_interp_default,
1147 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1148 };
1149
1150 unsigned u;
1151 memcpy(&u, &p, sizeof(p));
1152 ins.load_store.varying_parameters = u;
1153
1154 if (direct) {
1155 /* We have the offset totally ready */
1156 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1157 } else {
1158 /* We have it partially ready, but we need to
1159 * add in the dynamic index, moved to r27.w */
1160 emit_indirect_offset(ctx, &instr->src[0]);
1161 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1162 }
1163
1164 emit_mir_instruction(ctx, ins);
1165 } else if (ctx->is_blend) {
1166 /* For blend shaders, load the input color, which is
1167 * preloaded to r0 */
1168
1169 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1170 emit_mir_instruction(ctx, move);
1171 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1172 midgard_instruction ins = m_ld_attr_32(reg, offset);
1173 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1174 ins.load_store.mask = (1 << nr_comp) - 1;
1175 emit_mir_instruction(ctx, ins);
1176 } else {
1177 DBG("Unknown load\n");
1178 assert(0);
1179 }
1180
1181 break;
1182
1183 case nir_intrinsic_load_output:
1184 assert(nir_src_is_const(instr->src[0]));
1185 reg = nir_dest_index(ctx, &instr->dest);
1186
1187 if (ctx->is_blend) {
1188 /* TODO: MRT */
1189 emit_fb_read_blend_scalar(ctx, reg);
1190 } else {
1191 DBG("Unknown output load\n");
1192 assert(0);
1193 }
1194
1195 break;
1196
1197 case nir_intrinsic_load_blend_const_color_rgba: {
1198 assert(ctx->is_blend);
1199 reg = nir_dest_index(ctx, &instr->dest);
1200
1201 /* Blend constants are embedded directly in the shader and
1202 * patched in, so we use some magic routing */
1203
1204 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1205 ins.has_constants = true;
1206 ins.has_blend_constant = true;
1207 emit_mir_instruction(ctx, ins);
1208 break;
1209 }
1210
1211 case nir_intrinsic_store_output:
1212 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1213
1214 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1215
1216 reg = nir_src_index(ctx, &instr->src[0]);
1217
1218 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1219 /* gl_FragColor is not emitted with load/store
1220 * instructions. Instead, it gets plonked into
1221 * r0 at the end of the shader and we do the
1222 * framebuffer writeout dance. TODO: Defer
1223 * writes */
1224
1225 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1226 emit_mir_instruction(ctx, move);
1227
1228 /* Save the index we're writing to for later reference
1229 * in the epilogue */
1230
1231 ctx->fragment_output = reg;
1232 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1233 /* Varyings are written into one of two special
1234 * varying register, r26 or r27. The register itself is
1235 * selected as the register in the st_vary instruction,
1236 * minus the base of 26. E.g. write into r27 and then
1237 * call st_vary(1) */
1238
1239 midgard_instruction ins = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(26));
1240 emit_mir_instruction(ctx, ins);
1241
1242 /* We should have been vectorized. That also lets us
1243 * ignore the mask. because the mask component on
1244 * st_vary is (as far as I can tell) ignored [the blob
1245 * sets it to zero] */
1246 assert(nir_intrinsic_component(instr) == 0);
1247
1248 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset);
1249 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1250 emit_mir_instruction(ctx, st);
1251 } else {
1252 DBG("Unknown store\n");
1253 assert(0);
1254 }
1255
1256 break;
1257
1258 case nir_intrinsic_load_alpha_ref_float:
1259 assert(instr->dest.is_ssa);
1260
1261 float ref_value = ctx->alpha_ref;
1262
1263 float *v = ralloc_array(NULL, float, 4);
1264 memcpy(v, &ref_value, sizeof(float));
1265 _mesa_hash_table_u64_insert(ctx->ssa_constants, instr->dest.ssa.index + 1, v);
1266 break;
1267
1268 case nir_intrinsic_load_viewport_scale:
1269 case nir_intrinsic_load_viewport_offset:
1270 emit_sysval_read(ctx, instr);
1271 break;
1272
1273 default:
1274 printf ("Unhandled intrinsic\n");
1275 assert(0);
1276 break;
1277 }
1278 }
1279
1280 static unsigned
1281 midgard_tex_format(enum glsl_sampler_dim dim)
1282 {
1283 switch (dim) {
1284 case GLSL_SAMPLER_DIM_2D:
1285 case GLSL_SAMPLER_DIM_EXTERNAL:
1286 return TEXTURE_2D;
1287
1288 case GLSL_SAMPLER_DIM_3D:
1289 return TEXTURE_3D;
1290
1291 case GLSL_SAMPLER_DIM_CUBE:
1292 return TEXTURE_CUBE;
1293
1294 default:
1295 DBG("Unknown sampler dim type\n");
1296 assert(0);
1297 return 0;
1298 }
1299 }
1300
1301 static void
1302 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1303 {
1304 /* TODO */
1305 //assert (!instr->sampler);
1306 //assert (!instr->texture_array_size);
1307 assert (instr->op == nir_texop_tex);
1308
1309 /* Allocate registers via a round robin scheme to alternate between the two registers */
1310 int reg = ctx->texture_op_count & 1;
1311 int in_reg = reg, out_reg = reg;
1312
1313 /* Make room for the reg */
1314
1315 if (ctx->texture_index[reg] > -1)
1316 unalias_ssa(ctx, ctx->texture_index[reg]);
1317
1318 int texture_index = instr->texture_index;
1319 int sampler_index = texture_index;
1320
1321 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1322 switch (instr->src[i].src_type) {
1323 case nir_tex_src_coord: {
1324 int index = nir_src_index(ctx, &instr->src[i].src);
1325
1326 midgard_vector_alu_src alu_src = blank_alu_src;
1327
1328 int reg = SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + in_reg);
1329
1330 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1331 /* For cubemaps, we need to load coords into
1332 * special r27, and then use a special ld/st op
1333 * to copy into the texture register */
1334
1335 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X);
1336
1337 midgard_instruction move = v_fmov(index, alu_src, SSA_FIXED_REGISTER(27));
1338 emit_mir_instruction(ctx, move);
1339
1340 midgard_instruction st = m_st_cubemap_coords(reg, 0);
1341 st.load_store.unknown = 0x24; /* XXX: What is this? */
1342 st.load_store.mask = 0x3; /* xy? */
1343 st.load_store.swizzle = alu_src.swizzle;
1344 emit_mir_instruction(ctx, st);
1345
1346 } else {
1347 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X);
1348
1349 midgard_instruction ins = v_fmov(index, alu_src, reg);
1350 emit_mir_instruction(ctx, ins);
1351 }
1352
1353 break;
1354 }
1355
1356 default: {
1357 DBG("Unknown source type\n");
1358 //assert(0);
1359 break;
1360 }
1361 }
1362 }
1363
1364 /* No helper to build texture words -- we do it all here */
1365 midgard_instruction ins = {
1366 .type = TAG_TEXTURE_4,
1367 .texture = {
1368 .op = TEXTURE_OP_NORMAL,
1369 .format = midgard_tex_format(instr->sampler_dim),
1370 .texture_handle = texture_index,
1371 .sampler_handle = sampler_index,
1372
1373 /* TODO: Don't force xyzw */
1374 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
1375 .mask = 0xF,
1376
1377 /* TODO: half */
1378 //.in_reg_full = 1,
1379 .out_full = 1,
1380
1381 .filter = 1,
1382
1383 /* Always 1 */
1384 .unknown7 = 1,
1385
1386 /* Assume we can continue; hint it out later */
1387 .cont = 1,
1388 }
1389 };
1390
1391 /* Set registers to read and write from the same place */
1392 ins.texture.in_reg_select = in_reg;
1393 ins.texture.out_reg_select = out_reg;
1394
1395 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1396 if (instr->sampler_dim == GLSL_SAMPLER_DIM_3D) {
1397 ins.texture.in_reg_swizzle_right = COMPONENT_X;
1398 ins.texture.in_reg_swizzle_left = COMPONENT_Y;
1399 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1400 } else {
1401 ins.texture.in_reg_swizzle_left = COMPONENT_X;
1402 ins.texture.in_reg_swizzle_right = COMPONENT_Y;
1403 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1404 }
1405
1406 emit_mir_instruction(ctx, ins);
1407
1408 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1409
1410 int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest);
1411 alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg));
1412 ctx->texture_index[reg] = o_index;
1413
1414 midgard_instruction ins2 = v_fmov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index);
1415 emit_mir_instruction(ctx, ins2);
1416
1417 /* Used for .cont and .last hinting */
1418 ctx->texture_op_count++;
1419 }
1420
1421 static void
1422 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1423 {
1424 switch (instr->type) {
1425 case nir_jump_break: {
1426 /* Emit a branch out of the loop */
1427 struct midgard_instruction br = v_branch(false, false);
1428 br.branch.target_type = TARGET_BREAK;
1429 br.branch.target_break = ctx->current_loop_depth;
1430 emit_mir_instruction(ctx, br);
1431
1432 DBG("break..\n");
1433 break;
1434 }
1435
1436 default:
1437 DBG("Unknown jump type %d\n", instr->type);
1438 break;
1439 }
1440 }
1441
1442 static void
1443 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1444 {
1445 switch (instr->type) {
1446 case nir_instr_type_load_const:
1447 emit_load_const(ctx, nir_instr_as_load_const(instr));
1448 break;
1449
1450 case nir_instr_type_intrinsic:
1451 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1452 break;
1453
1454 case nir_instr_type_alu:
1455 emit_alu(ctx, nir_instr_as_alu(instr));
1456 break;
1457
1458 case nir_instr_type_tex:
1459 emit_tex(ctx, nir_instr_as_tex(instr));
1460 break;
1461
1462 case nir_instr_type_jump:
1463 emit_jump(ctx, nir_instr_as_jump(instr));
1464 break;
1465
1466 case nir_instr_type_ssa_undef:
1467 /* Spurious */
1468 break;
1469
1470 default:
1471 DBG("Unhandled instruction type\n");
1472 break;
1473 }
1474 }
1475
1476
1477 /* ALU instructions can inline or embed constants, which decreases register
1478 * pressure and saves space. */
1479
1480 #define CONDITIONAL_ATTACH(src) { \
1481 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1482 \
1483 if (entry) { \
1484 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1485 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1486 } \
1487 }
1488
1489 static void
1490 inline_alu_constants(compiler_context *ctx)
1491 {
1492 mir_foreach_instr(ctx, alu) {
1493 /* Other instructions cannot inline constants */
1494 if (alu->type != TAG_ALU_4) continue;
1495
1496 /* If there is already a constant here, we can do nothing */
1497 if (alu->has_constants) continue;
1498
1499 /* It makes no sense to inline constants on a branch */
1500 if (alu->compact_branch || alu->prepacked_branch) continue;
1501
1502 CONDITIONAL_ATTACH(src0);
1503
1504 if (!alu->has_constants) {
1505 CONDITIONAL_ATTACH(src1)
1506 } else if (!alu->inline_constant) {
1507 /* Corner case: _two_ vec4 constants, for instance with a
1508 * csel. For this case, we can only use a constant
1509 * register for one, we'll have to emit a move for the
1510 * other. Note, if both arguments are constants, then
1511 * necessarily neither argument depends on the value of
1512 * any particular register. As the destination register
1513 * will be wiped, that means we can spill the constant
1514 * to the destination register.
1515 */
1516
1517 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
1518 unsigned scratch = alu->ssa_args.dest;
1519
1520 if (entry) {
1521 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
1522 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
1523
1524 /* Force a break XXX Defer r31 writes */
1525 ins.unit = UNIT_VLUT;
1526
1527 /* Set the source */
1528 alu->ssa_args.src1 = scratch;
1529
1530 /* Inject us -before- the last instruction which set r31 */
1531 mir_insert_instruction_before(mir_prev_op(alu), ins);
1532 }
1533 }
1534 }
1535 }
1536
1537 /* Midgard supports two types of constants, embedded constants (128-bit) and
1538 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1539 * constants can be demoted to inline constants, for space savings and
1540 * sometimes a performance boost */
1541
1542 static void
1543 embedded_to_inline_constant(compiler_context *ctx)
1544 {
1545 mir_foreach_instr(ctx, ins) {
1546 if (!ins->has_constants) continue;
1547
1548 if (ins->ssa_args.inline_constant) continue;
1549
1550 /* Blend constants must not be inlined by definition */
1551 if (ins->has_blend_constant) continue;
1552
1553 /* src1 cannot be an inline constant due to encoding
1554 * restrictions. So, if possible we try to flip the arguments
1555 * in that case */
1556
1557 int op = ins->alu.op;
1558
1559 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1560 switch (op) {
1561 /* These ops require an operational change to flip
1562 * their arguments TODO */
1563 case midgard_alu_op_flt:
1564 case midgard_alu_op_fle:
1565 case midgard_alu_op_ilt:
1566 case midgard_alu_op_ile:
1567 case midgard_alu_op_fcsel:
1568 case midgard_alu_op_icsel:
1569 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
1570 default:
1571 break;
1572 }
1573
1574 if (alu_opcode_props[op].props & OP_COMMUTES) {
1575 /* Flip the SSA numbers */
1576 ins->ssa_args.src0 = ins->ssa_args.src1;
1577 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1578
1579 /* And flip the modifiers */
1580
1581 unsigned src_temp;
1582
1583 src_temp = ins->alu.src2;
1584 ins->alu.src2 = ins->alu.src1;
1585 ins->alu.src1 = src_temp;
1586 }
1587 }
1588
1589 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1590 /* Extract the source information */
1591
1592 midgard_vector_alu_src *src;
1593 int q = ins->alu.src2;
1594 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1595 src = m;
1596
1597 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1598 int component = src->swizzle & 3;
1599
1600 /* Scale constant appropriately, if we can legally */
1601 uint16_t scaled_constant = 0;
1602
1603 if (midgard_is_integer_op(op)) {
1604 unsigned int *iconstants = (unsigned int *) ins->constants;
1605 scaled_constant = (uint16_t) iconstants[component];
1606
1607 /* Constant overflow after resize */
1608 if (scaled_constant != iconstants[component])
1609 continue;
1610 } else {
1611 float original = (float) ins->constants[component];
1612 scaled_constant = _mesa_float_to_half(original);
1613
1614 /* Check for loss of precision. If this is
1615 * mediump, we don't care, but for a highp
1616 * shader, we need to pay attention. NIR
1617 * doesn't yet tell us which mode we're in!
1618 * Practically this prevents most constants
1619 * from being inlined, sadly. */
1620
1621 float fp32 = _mesa_half_to_float(scaled_constant);
1622
1623 if (fp32 != original)
1624 continue;
1625 }
1626
1627 /* We don't know how to handle these with a constant */
1628
1629 if (src->mod || src->half || src->rep_low || src->rep_high) {
1630 DBG("Bailing inline constant...\n");
1631 continue;
1632 }
1633
1634 /* Make sure that the constant is not itself a
1635 * vector by checking if all accessed values
1636 * (by the swizzle) are the same. */
1637
1638 uint32_t *cons = (uint32_t *) ins->constants;
1639 uint32_t value = cons[component];
1640
1641 bool is_vector = false;
1642 unsigned mask = effective_writemask(&ins->alu);
1643
1644 for (int c = 1; c < 4; ++c) {
1645 /* We only care if this component is actually used */
1646 if (!(mask & (1 << c)))
1647 continue;
1648
1649 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
1650
1651 if (test != value) {
1652 is_vector = true;
1653 break;
1654 }
1655 }
1656
1657 if (is_vector)
1658 continue;
1659
1660 /* Get rid of the embedded constant */
1661 ins->has_constants = false;
1662 ins->ssa_args.src1 = SSA_UNUSED_0;
1663 ins->ssa_args.inline_constant = true;
1664 ins->inline_constant = scaled_constant;
1665 }
1666 }
1667 }
1668
1669 /* Map normal SSA sources to other SSA sources / fixed registers (like
1670 * uniforms) */
1671
1672 static void
1673 map_ssa_to_alias(compiler_context *ctx, int *ref)
1674 {
1675 /* Sign is used quite deliberately for unused */
1676 if (*ref < 0)
1677 return;
1678
1679 unsigned int alias = (uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_to_alias, *ref + 1);
1680
1681 if (alias) {
1682 /* Remove entry in leftovers to avoid a redunant fmov */
1683
1684 struct set_entry *leftover = _mesa_set_search(ctx->leftover_ssa_to_alias, ((void *) (uintptr_t) (*ref + 1)));
1685
1686 if (leftover)
1687 _mesa_set_remove(ctx->leftover_ssa_to_alias, leftover);
1688
1689 /* Assign the alias map */
1690 *ref = alias - 1;
1691 return;
1692 }
1693 }
1694
1695 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1696 * texture pipeline */
1697
1698 static bool
1699 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
1700 {
1701 bool progress = false;
1702
1703 mir_foreach_instr_in_block_safe(block, ins) {
1704 if (ins->type != TAG_ALU_4) continue;
1705 if (ins->compact_branch) continue;
1706
1707 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
1708 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
1709
1710 mir_remove_instruction(ins);
1711 progress = true;
1712 }
1713
1714 return progress;
1715 }
1716
1717 /* Dead code elimination for branches at the end of a block - only one branch
1718 * per block is legal semantically */
1719
1720 static void
1721 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
1722 {
1723 bool branched = false;
1724
1725 mir_foreach_instr_in_block_safe(block, ins) {
1726 if (!midgard_is_branch_unit(ins->unit)) continue;
1727
1728 /* We ignore prepacked branches since the fragment epilogue is
1729 * just generally special */
1730 if (ins->prepacked_branch) continue;
1731
1732 if (branched) {
1733 /* We already branched, so this is dead */
1734 mir_remove_instruction(ins);
1735 }
1736
1737 branched = true;
1738 }
1739 }
1740
1741 static bool
1742 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
1743 {
1744 /* abs or neg */
1745 if (!is_int && src.mod) return true;
1746
1747 /* swizzle */
1748 for (unsigned c = 0; c < 4; ++c) {
1749 if (!(mask & (1 << c))) continue;
1750 if (((src.swizzle >> (2*c)) & 3) != c) return true;
1751 }
1752
1753 return false;
1754 }
1755
1756 static bool
1757 mir_nontrivial_source2_mod(midgard_instruction *ins)
1758 {
1759 unsigned mask = squeeze_writemask(ins->alu.mask);
1760 bool is_int = midgard_is_integer_op(ins->alu.op);
1761
1762 midgard_vector_alu_src src2 =
1763 vector_alu_from_unsigned(ins->alu.src2);
1764
1765 return mir_nontrivial_mod(src2, is_int, mask);
1766 }
1767
1768 static bool
1769 midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
1770 {
1771 bool progress = false;
1772
1773 mir_foreach_instr_in_block_safe(block, ins) {
1774 if (ins->type != TAG_ALU_4) continue;
1775 if (!OP_IS_MOVE(ins->alu.op)) continue;
1776
1777 unsigned from = ins->ssa_args.src1;
1778 unsigned to = ins->ssa_args.dest;
1779
1780 /* We only work on pure SSA */
1781
1782 if (to >= SSA_FIXED_MINIMUM) continue;
1783 if (from >= SSA_FIXED_MINIMUM) continue;
1784 if (to >= ctx->func->impl->ssa_alloc) continue;
1785 if (from >= ctx->func->impl->ssa_alloc) continue;
1786
1787 /* Constant propagation is not handled here, either */
1788 if (ins->ssa_args.inline_constant) continue;
1789 if (ins->has_constants) continue;
1790
1791 if (mir_nontrivial_source2_mod(ins)) continue;
1792 if (ins->alu.outmod != midgard_outmod_none) continue;
1793
1794 /* We're clear -- rewrite */
1795 mir_rewrite_index_src(ctx, to, from);
1796 mir_remove_instruction(ins);
1797 progress |= true;
1798 }
1799
1800 return progress;
1801 }
1802
1803 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1804 * the move can be propagated away entirely */
1805
1806 static bool
1807 mir_compose_outmod(midgard_outmod *outmod, midgard_outmod comp)
1808 {
1809 /* Nothing to do */
1810 if (comp == midgard_outmod_none)
1811 return true;
1812
1813 if (*outmod == midgard_outmod_none) {
1814 *outmod = comp;
1815 return true;
1816 }
1817
1818 /* TODO: Compose rules */
1819 return false;
1820 }
1821
1822 static bool
1823 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
1824 {
1825 bool progress = false;
1826
1827 mir_foreach_instr_in_block_safe(block, ins) {
1828 if (ins->type != TAG_ALU_4) continue;
1829 if (ins->alu.op != midgard_alu_op_fmov) continue;
1830 if (ins->alu.outmod != midgard_outmod_pos) continue;
1831
1832 /* TODO: Registers? */
1833 unsigned src = ins->ssa_args.src1;
1834 if (src >= ctx->func->impl->ssa_alloc) continue;
1835
1836 /* There might be a source modifier, too */
1837 if (mir_nontrivial_source2_mod(ins)) continue;
1838
1839 /* Backpropagate the modifier */
1840 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1841 if (v->type != TAG_ALU_4) continue;
1842 if (v->ssa_args.dest != src) continue;
1843
1844 midgard_outmod temp = v->alu.outmod;
1845 progress |= mir_compose_outmod(&temp, ins->alu.outmod);
1846
1847 /* Throw in the towel.. */
1848 if (!progress) break;
1849
1850 /* Otherwise, transfer the modifier */
1851 v->alu.outmod = temp;
1852 ins->alu.outmod = midgard_outmod_none;
1853
1854 break;
1855 }
1856 }
1857
1858 return progress;
1859 }
1860
1861 static bool
1862 midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
1863 {
1864 bool progress = false;
1865
1866 mir_foreach_instr_in_block_safe(block, ins) {
1867 if (ins->type != TAG_ALU_4) continue;
1868 if (!OP_IS_MOVE(ins->alu.op)) continue;
1869
1870 unsigned from = ins->ssa_args.src1;
1871 unsigned to = ins->ssa_args.dest;
1872
1873 /* Make sure it's simple enough for us to handle */
1874
1875 if (from >= SSA_FIXED_MINIMUM) continue;
1876 if (from >= ctx->func->impl->ssa_alloc) continue;
1877 if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
1878 if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
1879
1880 bool eliminated = false;
1881
1882 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1883 /* The texture registers are not SSA so be careful.
1884 * Conservatively, just stop if we hit a texture op
1885 * (even if it may not write) to where we are */
1886
1887 if (v->type != TAG_ALU_4)
1888 break;
1889
1890 if (v->ssa_args.dest == from) {
1891 /* We don't want to track partial writes ... */
1892 if (v->alu.mask == 0xF) {
1893 v->ssa_args.dest = to;
1894 eliminated = true;
1895 }
1896
1897 break;
1898 }
1899 }
1900
1901 if (eliminated)
1902 mir_remove_instruction(ins);
1903
1904 progress |= eliminated;
1905 }
1906
1907 return progress;
1908 }
1909
1910 /* The following passes reorder MIR instructions to enable better scheduling */
1911
1912 static void
1913 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
1914 {
1915 mir_foreach_instr_in_block_safe(block, ins) {
1916 if (ins->type != TAG_LOAD_STORE_4) continue;
1917
1918 /* We've found a load/store op. Check if next is also load/store. */
1919 midgard_instruction *next_op = mir_next_op(ins);
1920 if (&next_op->link != &block->instructions) {
1921 if (next_op->type == TAG_LOAD_STORE_4) {
1922 /* If so, we're done since we're a pair */
1923 ins = mir_next_op(ins);
1924 continue;
1925 }
1926
1927 /* Maximum search distance to pair, to avoid register pressure disasters */
1928 int search_distance = 8;
1929
1930 /* Otherwise, we have an orphaned load/store -- search for another load */
1931 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
1932 /* Terminate search if necessary */
1933 if (!(search_distance--)) break;
1934
1935 if (c->type != TAG_LOAD_STORE_4) continue;
1936
1937 /* Stores cannot be reordered, since they have
1938 * dependencies. For the same reason, indirect
1939 * loads cannot be reordered as their index is
1940 * loaded in r27.w */
1941
1942 if (OP_IS_STORE(c->load_store.op)) continue;
1943
1944 /* It appears the 0x800 bit is set whenever a
1945 * load is direct, unset when it is indirect.
1946 * Skip indirect loads. */
1947
1948 if (!(c->load_store.unknown & 0x800)) continue;
1949
1950 /* We found one! Move it up to pair and remove it from the old location */
1951
1952 mir_insert_instruction_before(ins, *c);
1953 mir_remove_instruction(c);
1954
1955 break;
1956 }
1957 }
1958 }
1959 }
1960
1961 /* If there are leftovers after the below pass, emit actual fmov
1962 * instructions for the slow-but-correct path */
1963
1964 static void
1965 emit_leftover_move(compiler_context *ctx)
1966 {
1967 set_foreach(ctx->leftover_ssa_to_alias, leftover) {
1968 int base = ((uintptr_t) leftover->key) - 1;
1969 int mapped = base;
1970
1971 map_ssa_to_alias(ctx, &mapped);
1972 EMIT(fmov, mapped, blank_alu_src, base);
1973 }
1974 }
1975
1976 static void
1977 actualise_ssa_to_alias(compiler_context *ctx)
1978 {
1979 mir_foreach_instr(ctx, ins) {
1980 map_ssa_to_alias(ctx, &ins->ssa_args.src0);
1981 map_ssa_to_alias(ctx, &ins->ssa_args.src1);
1982 }
1983
1984 emit_leftover_move(ctx);
1985 }
1986
1987 static void
1988 emit_fragment_epilogue(compiler_context *ctx)
1989 {
1990 /* Special case: writing out constants requires us to include the move
1991 * explicitly now, so shove it into r0 */
1992
1993 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, ctx->fragment_output + 1);
1994
1995 if (constant_value) {
1996 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(0));
1997 attach_constants(ctx, &ins, constant_value, ctx->fragment_output + 1);
1998 emit_mir_instruction(ctx, ins);
1999 }
2000
2001 /* Perform the actual fragment writeout. We have two writeout/branch
2002 * instructions, forming a loop until writeout is successful as per the
2003 * docs. TODO: gl_FragDepth */
2004
2005 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2006 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2007 }
2008
2009 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2010 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2011 * with the int8 analogue to the fragment epilogue */
2012
2013 static void
2014 emit_blend_epilogue(compiler_context *ctx)
2015 {
2016 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2017
2018 midgard_instruction scale = {
2019 .type = TAG_ALU_4,
2020 .unit = UNIT_VMUL,
2021 .inline_constant = _mesa_float_to_half(255.0),
2022 .ssa_args = {
2023 .src0 = SSA_FIXED_REGISTER(0),
2024 .src1 = SSA_UNUSED_0,
2025 .dest = SSA_FIXED_REGISTER(24),
2026 .inline_constant = true
2027 },
2028 .alu = {
2029 .op = midgard_alu_op_fmul,
2030 .reg_mode = midgard_reg_mode_32,
2031 .dest_override = midgard_dest_override_lower,
2032 .mask = 0xFF,
2033 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2034 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2035 }
2036 };
2037
2038 emit_mir_instruction(ctx, scale);
2039
2040 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2041
2042 midgard_vector_alu_src alu_src = blank_alu_src;
2043 alu_src.half = true;
2044
2045 midgard_instruction f2u8 = {
2046 .type = TAG_ALU_4,
2047 .ssa_args = {
2048 .src0 = SSA_FIXED_REGISTER(24),
2049 .src1 = SSA_UNUSED_0,
2050 .dest = SSA_FIXED_REGISTER(0),
2051 .inline_constant = true
2052 },
2053 .alu = {
2054 .op = midgard_alu_op_f2u8,
2055 .reg_mode = midgard_reg_mode_16,
2056 .dest_override = midgard_dest_override_lower,
2057 .outmod = midgard_outmod_pos,
2058 .mask = 0xF,
2059 .src1 = vector_alu_srco_unsigned(alu_src),
2060 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2061 }
2062 };
2063
2064 emit_mir_instruction(ctx, f2u8);
2065
2066 /* vmul.imov.quarter r0, r0, r0 */
2067
2068 midgard_instruction imov_8 = {
2069 .type = TAG_ALU_4,
2070 .ssa_args = {
2071 .src0 = SSA_UNUSED_1,
2072 .src1 = SSA_FIXED_REGISTER(0),
2073 .dest = SSA_FIXED_REGISTER(0),
2074 },
2075 .alu = {
2076 .op = midgard_alu_op_imov,
2077 .reg_mode = midgard_reg_mode_8,
2078 .dest_override = midgard_dest_override_none,
2079 .outmod = midgard_outmod_int,
2080 .mask = 0xFF,
2081 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2082 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2083 }
2084 };
2085
2086 /* Emit branch epilogue with the 8-bit move as the source */
2087
2088 emit_mir_instruction(ctx, imov_8);
2089 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2090
2091 emit_mir_instruction(ctx, imov_8);
2092 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2093 }
2094
2095 static midgard_block *
2096 emit_block(compiler_context *ctx, nir_block *block)
2097 {
2098 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2099 list_addtail(&this_block->link, &ctx->blocks);
2100
2101 this_block->is_scheduled = false;
2102 ++ctx->block_count;
2103
2104 ctx->texture_index[0] = -1;
2105 ctx->texture_index[1] = -1;
2106
2107 /* Add us as a successor to the block we are following */
2108 if (ctx->current_block)
2109 midgard_block_add_successor(ctx->current_block, this_block);
2110
2111 /* Set up current block */
2112 list_inithead(&this_block->instructions);
2113 ctx->current_block = this_block;
2114
2115 nir_foreach_instr(instr, block) {
2116 emit_instr(ctx, instr);
2117 ++ctx->instruction_count;
2118 }
2119
2120 inline_alu_constants(ctx);
2121 embedded_to_inline_constant(ctx);
2122
2123 /* Perform heavylifting for aliasing */
2124 actualise_ssa_to_alias(ctx);
2125
2126 midgard_pair_load_store(ctx, this_block);
2127
2128 /* Append fragment shader epilogue (value writeout) */
2129 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2130 if (block == nir_impl_last_block(ctx->func->impl)) {
2131 if (ctx->is_blend)
2132 emit_blend_epilogue(ctx);
2133 else
2134 emit_fragment_epilogue(ctx);
2135 }
2136 }
2137
2138 if (block == nir_start_block(ctx->func->impl))
2139 ctx->initial_block = this_block;
2140
2141 if (block == nir_impl_last_block(ctx->func->impl))
2142 ctx->final_block = this_block;
2143
2144 /* Allow the next control flow to access us retroactively, for
2145 * branching etc */
2146 ctx->current_block = this_block;
2147
2148 /* Document the fallthrough chain */
2149 ctx->previous_source_block = this_block;
2150
2151 return this_block;
2152 }
2153
2154 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2155
2156 static void
2157 emit_if(struct compiler_context *ctx, nir_if *nif)
2158 {
2159 /* Conditional branches expect the condition in r31.w; emit a move for
2160 * that in the _previous_ block (which is the current block). */
2161 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2162
2163 /* Speculatively emit the branch, but we can't fill it in until later */
2164 EMIT(branch, true, true);
2165 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2166
2167 /* Emit the two subblocks */
2168 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2169
2170 /* Emit a jump from the end of the then block to the end of the else */
2171 EMIT(branch, false, false);
2172 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2173
2174 /* Emit second block, and check if it's empty */
2175
2176 int else_idx = ctx->block_count;
2177 int count_in = ctx->instruction_count;
2178 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2179 int after_else_idx = ctx->block_count;
2180
2181 /* Now that we have the subblocks emitted, fix up the branches */
2182
2183 assert(then_block);
2184 assert(else_block);
2185
2186 if (ctx->instruction_count == count_in) {
2187 /* The else block is empty, so don't emit an exit jump */
2188 mir_remove_instruction(then_exit);
2189 then_branch->branch.target_block = after_else_idx;
2190 } else {
2191 then_branch->branch.target_block = else_idx;
2192 then_exit->branch.target_block = after_else_idx;
2193 }
2194 }
2195
2196 static void
2197 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2198 {
2199 /* Remember where we are */
2200 midgard_block *start_block = ctx->current_block;
2201
2202 /* Allocate a loop number, growing the current inner loop depth */
2203 int loop_idx = ++ctx->current_loop_depth;
2204
2205 /* Get index from before the body so we can loop back later */
2206 int start_idx = ctx->block_count;
2207
2208 /* Emit the body itself */
2209 emit_cf_list(ctx, &nloop->body);
2210
2211 /* Branch back to loop back */
2212 struct midgard_instruction br_back = v_branch(false, false);
2213 br_back.branch.target_block = start_idx;
2214 emit_mir_instruction(ctx, br_back);
2215
2216 /* Mark down that branch in the graph. Note that we're really branching
2217 * to the block *after* we started in. TODO: Why doesn't the branch
2218 * itself have an off-by-one then...? */
2219 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2220
2221 /* Find the index of the block about to follow us (note: we don't add
2222 * one; blocks are 0-indexed so we get a fencepost problem) */
2223 int break_block_idx = ctx->block_count;
2224
2225 /* Fix up the break statements we emitted to point to the right place,
2226 * now that we can allocate a block number for them */
2227
2228 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2229 mir_foreach_instr_in_block(block, ins) {
2230 if (ins->type != TAG_ALU_4) continue;
2231 if (!ins->compact_branch) continue;
2232 if (ins->prepacked_branch) continue;
2233
2234 /* We found a branch -- check the type to see if we need to do anything */
2235 if (ins->branch.target_type != TARGET_BREAK) continue;
2236
2237 /* It's a break! Check if it's our break */
2238 if (ins->branch.target_break != loop_idx) continue;
2239
2240 /* Okay, cool, we're breaking out of this loop.
2241 * Rewrite from a break to a goto */
2242
2243 ins->branch.target_type = TARGET_GOTO;
2244 ins->branch.target_block = break_block_idx;
2245 }
2246 }
2247
2248 /* Now that we've finished emitting the loop, free up the depth again
2249 * so we play nice with recursion amid nested loops */
2250 --ctx->current_loop_depth;
2251 }
2252
2253 static midgard_block *
2254 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2255 {
2256 midgard_block *start_block = NULL;
2257
2258 foreach_list_typed(nir_cf_node, node, node, list) {
2259 switch (node->type) {
2260 case nir_cf_node_block: {
2261 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2262
2263 if (!start_block)
2264 start_block = block;
2265
2266 break;
2267 }
2268
2269 case nir_cf_node_if:
2270 emit_if(ctx, nir_cf_node_as_if(node));
2271 break;
2272
2273 case nir_cf_node_loop:
2274 emit_loop(ctx, nir_cf_node_as_loop(node));
2275 break;
2276
2277 case nir_cf_node_function:
2278 assert(0);
2279 break;
2280 }
2281 }
2282
2283 return start_block;
2284 }
2285
2286 /* Due to lookahead, we need to report the first tag executed in the command
2287 * stream and in branch targets. An initial block might be empty, so iterate
2288 * until we find one that 'works' */
2289
2290 static unsigned
2291 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2292 {
2293 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2294
2295 unsigned first_tag = 0;
2296
2297 do {
2298 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
2299
2300 if (initial_bundle) {
2301 first_tag = initial_bundle->tag;
2302 break;
2303 }
2304
2305 /* Initial block is empty, try the next block */
2306 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
2307 } while(initial_block != NULL);
2308
2309 assert(first_tag);
2310 return first_tag;
2311 }
2312
2313 int
2314 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend)
2315 {
2316 struct util_dynarray *compiled = &program->compiled;
2317
2318 midgard_debug = debug_get_option_midgard_debug();
2319
2320 compiler_context ictx = {
2321 .nir = nir,
2322 .stage = nir->info.stage,
2323
2324 .is_blend = is_blend,
2325 .blend_constant_offset = -1,
2326
2327 .alpha_ref = program->alpha_ref
2328 };
2329
2330 compiler_context *ctx = &ictx;
2331
2332 /* TODO: Decide this at runtime */
2333 ctx->uniform_cutoff = 8;
2334
2335 /* Initialize at a global (not block) level hash tables */
2336
2337 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2338 ctx->ssa_to_alias = _mesa_hash_table_u64_create(NULL);
2339 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2340 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2341 ctx->leftover_ssa_to_alias = _mesa_set_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
2342
2343 /* Record the varying mapping for the command stream's bookkeeping */
2344
2345 struct exec_list *varyings =
2346 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2347
2348 unsigned max_varying = 0;
2349 nir_foreach_variable(var, varyings) {
2350 unsigned loc = var->data.driver_location;
2351 unsigned sz = glsl_type_size(var->type, FALSE);
2352
2353 for (int c = loc; c < (loc + sz); ++c) {
2354 program->varyings[c] = var->data.location;
2355 max_varying = MAX2(max_varying, c);
2356 }
2357 }
2358
2359 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2360 * (so we don't accidentally duplicate the epilogue since mesa/st has
2361 * messed with our I/O quite a bit already) */
2362
2363 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2364
2365 if (ctx->stage == MESA_SHADER_VERTEX)
2366 NIR_PASS_V(nir, nir_lower_viewport_transform);
2367
2368 NIR_PASS_V(nir, nir_lower_var_copies);
2369 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2370 NIR_PASS_V(nir, nir_split_var_copies);
2371 NIR_PASS_V(nir, nir_lower_var_copies);
2372 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2373 NIR_PASS_V(nir, nir_lower_var_copies);
2374 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2375
2376 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2377
2378 /* Optimisation passes */
2379
2380 optimise_nir(nir);
2381
2382 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2383 nir_print_shader(nir, stdout);
2384 }
2385
2386 /* Assign sysvals and counts, now that we're sure
2387 * (post-optimisation) */
2388
2389 midgard_nir_assign_sysvals(ctx, nir);
2390
2391 program->uniform_count = nir->num_uniforms;
2392 program->sysval_count = ctx->sysval_count;
2393 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2394
2395 program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_inputs : 0;
2396 program->varying_count = max_varying + 1; /* Fencepost off-by-one */
2397
2398 nir_foreach_function(func, nir) {
2399 if (!func->impl)
2400 continue;
2401
2402 list_inithead(&ctx->blocks);
2403 ctx->block_count = 0;
2404 ctx->func = func;
2405
2406 emit_cf_list(ctx, &func->impl->body);
2407 emit_block(ctx, func->impl->end_block);
2408
2409 break; /* TODO: Multi-function shaders */
2410 }
2411
2412 util_dynarray_init(compiled, NULL);
2413
2414 /* MIR-level optimizations */
2415
2416 bool progress = false;
2417
2418 do {
2419 progress = false;
2420
2421 mir_foreach_block(ctx, block) {
2422 progress |= midgard_opt_pos_propagate(ctx, block);
2423 progress |= midgard_opt_copy_prop(ctx, block);
2424 progress |= midgard_opt_copy_prop_tex(ctx, block);
2425 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2426 }
2427 } while (progress);
2428
2429 /* Nested control-flow can result in dead branches at the end of the
2430 * block. This messes with our analysis and is just dead code, so cull
2431 * them */
2432 mir_foreach_block(ctx, block) {
2433 midgard_opt_cull_dead_branch(ctx, block);
2434 }
2435
2436 /* Schedule! */
2437 schedule_program(ctx);
2438
2439 /* Now that all the bundles are scheduled and we can calculate block
2440 * sizes, emit actual branch instructions rather than placeholders */
2441
2442 int br_block_idx = 0;
2443
2444 mir_foreach_block(ctx, block) {
2445 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2446 for (int c = 0; c < bundle->instruction_count; ++c) {
2447 midgard_instruction *ins = bundle->instructions[c];
2448
2449 if (!midgard_is_branch_unit(ins->unit)) continue;
2450
2451 if (ins->prepacked_branch) continue;
2452
2453 /* Parse some basic branch info */
2454 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2455 bool is_conditional = ins->branch.conditional;
2456 bool is_inverted = ins->branch.invert_conditional;
2457 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2458
2459 /* Determine the block we're jumping to */
2460 int target_number = ins->branch.target_block;
2461
2462 /* Report the destination tag */
2463 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2464
2465 /* Count up the number of quadwords we're
2466 * jumping over = number of quadwords until
2467 * (br_block_idx, target_number) */
2468
2469 int quadword_offset = 0;
2470
2471 if (is_discard) {
2472 /* Jump to the end of the shader. We
2473 * need to include not only the
2474 * following blocks, but also the
2475 * contents of our current block (since
2476 * discard can come in the middle of
2477 * the block) */
2478
2479 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
2480
2481 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
2482 quadword_offset += quadword_size(bun->tag);
2483 }
2484
2485 mir_foreach_block_from(ctx, blk, b) {
2486 quadword_offset += b->quadword_count;
2487 }
2488
2489 } else if (target_number > br_block_idx) {
2490 /* Jump forward */
2491
2492 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2493 midgard_block *blk = mir_get_block(ctx, idx);
2494 assert(blk);
2495
2496 quadword_offset += blk->quadword_count;
2497 }
2498 } else {
2499 /* Jump backwards */
2500
2501 for (int idx = br_block_idx; idx >= target_number; --idx) {
2502 midgard_block *blk = mir_get_block(ctx, idx);
2503 assert(blk);
2504
2505 quadword_offset -= blk->quadword_count;
2506 }
2507 }
2508
2509 /* Unconditional extended branches (far jumps)
2510 * have issues, so we always use a conditional
2511 * branch, setting the condition to always for
2512 * unconditional. For compact unconditional
2513 * branches, cond isn't used so it doesn't
2514 * matter what we pick. */
2515
2516 midgard_condition cond =
2517 !is_conditional ? midgard_condition_always :
2518 is_inverted ? midgard_condition_false :
2519 midgard_condition_true;
2520
2521 midgard_jmp_writeout_op op =
2522 is_discard ? midgard_jmp_writeout_op_discard :
2523 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2524 midgard_jmp_writeout_op_branch_cond;
2525
2526 if (!is_compact) {
2527 midgard_branch_extended branch =
2528 midgard_create_branch_extended(
2529 cond, op,
2530 dest_tag,
2531 quadword_offset);
2532
2533 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2534 } else if (is_conditional || is_discard) {
2535 midgard_branch_cond branch = {
2536 .op = op,
2537 .dest_tag = dest_tag,
2538 .offset = quadword_offset,
2539 .cond = cond
2540 };
2541
2542 assert(branch.offset == quadword_offset);
2543
2544 memcpy(&ins->br_compact, &branch, sizeof(branch));
2545 } else {
2546 assert(op == midgard_jmp_writeout_op_branch_uncond);
2547
2548 midgard_branch_uncond branch = {
2549 .op = op,
2550 .dest_tag = dest_tag,
2551 .offset = quadword_offset,
2552 .unknown = 1
2553 };
2554
2555 assert(branch.offset == quadword_offset);
2556
2557 memcpy(&ins->br_compact, &branch, sizeof(branch));
2558 }
2559 }
2560 }
2561
2562 ++br_block_idx;
2563 }
2564
2565 /* Emit flat binary from the instruction arrays. Iterate each block in
2566 * sequence. Save instruction boundaries such that lookahead tags can
2567 * be assigned easily */
2568
2569 /* Cache _all_ bundles in source order for lookahead across failed branches */
2570
2571 int bundle_count = 0;
2572 mir_foreach_block(ctx, block) {
2573 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2574 }
2575 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2576 int bundle_idx = 0;
2577 mir_foreach_block(ctx, block) {
2578 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2579 source_order_bundles[bundle_idx++] = bundle;
2580 }
2581 }
2582
2583 int current_bundle = 0;
2584
2585 /* Midgard prefetches instruction types, so during emission we
2586 * need to lookahead. Unless this is the last instruction, in
2587 * which we return 1. Or if this is the second to last and the
2588 * last is an ALU, then it's also 1... */
2589
2590 mir_foreach_block(ctx, block) {
2591 mir_foreach_bundle_in_block(block, bundle) {
2592 int lookahead = 1;
2593
2594 if (current_bundle + 1 < bundle_count) {
2595 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2596
2597 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2598 lookahead = 1;
2599 } else {
2600 lookahead = next;
2601 }
2602 }
2603
2604 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2605 ++current_bundle;
2606 }
2607
2608 /* TODO: Free deeper */
2609 //util_dynarray_fini(&block->instructions);
2610 }
2611
2612 free(source_order_bundles);
2613
2614 /* Report the very first tag executed */
2615 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2616
2617 /* Deal with off-by-one related to the fencepost problem */
2618 program->work_register_count = ctx->work_registers + 1;
2619
2620 program->can_discard = ctx->can_discard;
2621 program->uniform_cutoff = ctx->uniform_cutoff;
2622
2623 program->blend_patch_offset = ctx->blend_constant_offset;
2624
2625 if (midgard_debug & MIDGARD_DBG_SHADERS)
2626 disassemble_midgard(program->compiled.data, program->compiled.size);
2627
2628 return 0;
2629 }