2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 /* Successors: always one forward (the block after us), maybe
173 * one backwards (for a backward branch). No need for a second
174 * forward, since graph traversal would get there eventually
176 struct midgard_block
*successors
[2];
177 unsigned nr_successors
;
179 /* The successors pointer form a graph, and in the case of
180 * complex control flow, this graph has a cycles. To aid
181 * traversal during liveness analysis, we have a visited?
182 * boolean for passes to use as they see fit, provided they
188 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
190 block
->successors
[block
->nr_successors
++] = successor
;
191 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
194 /* Helpers to generate midgard_instruction's using macro magic, since every
195 * driver seems to do it that way */
197 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
198 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
200 #define M_LOAD_STORE(name, rname, uname) \
201 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
202 midgard_instruction i = { \
203 .type = TAG_LOAD_STORE_4, \
210 .op = midgard_op_##name, \
212 .swizzle = SWIZZLE_XYZW, \
220 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
221 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
223 const midgard_vector_alu_src blank_alu_src
= {
224 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
227 const midgard_vector_alu_src blank_alu_src_xxxx
= {
228 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
231 const midgard_scalar_alu_src blank_scalar_alu_src
= {
235 /* Used for encoding the unused source of 1-op instructions */
236 const midgard_vector_alu_src zero_alu_src
= { 0 };
238 /* Coerce structs to integer */
241 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
244 memcpy(&u
, &src
, sizeof(src
));
248 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
249 * the corresponding Midgard source */
251 static midgard_vector_alu_src
252 vector_alu_modifiers(nir_alu_src
*src
)
254 if (!src
) return blank_alu_src
;
256 midgard_vector_alu_src alu_src
= {
258 .negate
= src
->negate
,
261 .half
= 0, /* TODO */
262 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
268 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
270 static midgard_instruction
271 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
273 midgard_instruction ins
= {
276 .src0
= SSA_UNUSED_1
,
281 .op
= midgard_alu_op_fmov
,
282 .reg_mode
= midgard_reg_mode_full
,
283 .dest_override
= midgard_dest_override_none
,
285 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
286 .src2
= vector_alu_srco_unsigned(mod
)
293 /* load/store instructions have both 32-bit and 16-bit variants, depending on
294 * whether we are using vectors composed of highp or mediump. At the moment, we
295 * don't support half-floats -- this requires changes in other parts of the
296 * compiler -- therefore the 16-bit versions are commented out. */
298 //M_LOAD(load_attr_16);
299 M_LOAD(load_attr_32
);
300 //M_LOAD(load_vary_16);
301 M_LOAD(load_vary_32
);
302 //M_LOAD(load_uniform_16);
303 M_LOAD(load_uniform_32
);
304 M_LOAD(load_color_buffer_8
);
305 //M_STORE(store_vary_16);
306 M_STORE(store_vary_32
);
307 M_STORE(store_cubemap_coords
);
309 static midgard_instruction
310 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
312 midgard_branch_cond branch
= {
320 memcpy(&compact
, &branch
, sizeof(branch
));
322 midgard_instruction ins
= {
324 .unit
= ALU_ENAB_BR_COMPACT
,
325 .prepacked_branch
= true,
326 .compact_branch
= true,
327 .br_compact
= compact
330 if (op
== midgard_jmp_writeout_op_writeout
)
336 static midgard_instruction
337 v_branch(bool conditional
, bool invert
)
339 midgard_instruction ins
= {
341 .unit
= ALU_ENAB_BRANCH
,
342 .compact_branch
= true,
344 .conditional
= conditional
,
345 .invert_conditional
= invert
352 static midgard_branch_extended
353 midgard_create_branch_extended( midgard_condition cond
,
354 midgard_jmp_writeout_op op
,
356 signed quadword_offset
)
358 /* For unclear reasons, the condition code is repeated 8 times */
359 uint16_t duplicated_cond
=
369 midgard_branch_extended branch
= {
371 .dest_tag
= dest_tag
,
372 .offset
= quadword_offset
,
373 .cond
= duplicated_cond
379 typedef struct midgard_bundle
{
380 /* Tag for the overall bundle */
383 /* Instructions contained by the bundle */
384 int instruction_count
;
385 midgard_instruction instructions
[5];
387 /* Bundle-wide ALU configuration */
390 bool has_embedded_constants
;
392 bool has_blend_constant
;
394 uint16_t register_words
[8];
395 int register_words_count
;
397 uint64_t body_words
[8];
399 int body_words_count
;
402 typedef struct compiler_context
{
404 gl_shader_stage stage
;
406 /* Is internally a blend shader? Depends on stage == FRAGMENT */
409 /* Tracking for blend constant patching */
410 int blend_constant_number
;
411 int blend_constant_offset
;
413 /* Current NIR function */
416 /* Unordered list of midgard_blocks */
418 struct list_head blocks
;
420 midgard_block
*initial_block
;
421 midgard_block
*previous_source_block
;
422 midgard_block
*final_block
;
424 /* List of midgard_instructions emitted for the current block */
425 midgard_block
*current_block
;
427 /* The index corresponding to the current loop, e.g. for breaks/contineus */
430 /* Constants which have been loaded, for later inlining */
431 struct hash_table_u64
*ssa_constants
;
433 /* SSA indices to be outputted to corresponding varying offset */
434 struct hash_table_u64
*ssa_varyings
;
436 /* SSA values / registers which have been aliased. Naively, these
437 * demand a fmov output; instead, we alias them in a later pass to
438 * avoid the wasted op.
440 * A note on encoding: to avoid dynamic memory management here, rather
441 * than ampping to a pointer, we map to the source index; the key
442 * itself is just the destination index. */
444 struct hash_table_u64
*ssa_to_alias
;
445 struct set
*leftover_ssa_to_alias
;
447 /* Actual SSA-to-register for RA */
448 struct hash_table_u64
*ssa_to_register
;
450 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
451 struct hash_table_u64
*hash_to_temp
;
455 /* Just the count of the max register used. Higher count => higher
456 * register pressure */
459 /* Used for cont/last hinting. Increase when a tex op is added.
460 * Decrease when a tex op is removed. */
461 int texture_op_count
;
463 /* Mapping of texture register -> SSA index for unaliasing */
464 int texture_index
[2];
466 /* If any path hits a discard instruction */
469 /* The number of uniforms allowable for the fast path */
472 /* Count of instructions emitted from NIR overall, across all blocks */
473 int instruction_count
;
475 /* Alpha ref value passed in */
478 /* The index corresponding to the fragment output */
479 unsigned fragment_output
;
481 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
482 unsigned sysvals
[MAX_SYSVAL_COUNT
];
483 unsigned sysval_count
;
484 struct hash_table_u64
*sysval_to_id
;
487 /* Append instruction to end of current block */
489 static midgard_instruction
*
490 mir_upload_ins(struct midgard_instruction ins
)
492 midgard_instruction
*heap
= malloc(sizeof(ins
));
493 memcpy(heap
, &ins
, sizeof(ins
));
498 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
500 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
504 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
506 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
510 mir_remove_instruction(struct midgard_instruction
*ins
)
512 list_del(&ins
->link
);
515 static midgard_instruction
*
516 mir_prev_op(struct midgard_instruction
*ins
)
518 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
521 static midgard_instruction
*
522 mir_next_op(struct midgard_instruction
*ins
)
524 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
527 static midgard_block
*
528 mir_next_block(struct midgard_block
*blk
)
530 return list_first_entry(&(blk
->link
), midgard_block
, link
);
534 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
535 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
537 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
538 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
539 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
540 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
541 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
542 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
545 static midgard_instruction
*
546 mir_last_in_block(struct midgard_block
*block
)
548 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
551 static midgard_block
*
552 mir_get_block(compiler_context
*ctx
, int idx
)
554 struct list_head
*lst
= &ctx
->blocks
;
559 return (struct midgard_block
*) lst
;
562 /* Pretty printer for internal Midgard IR */
565 print_mir_source(int source
)
567 if (source
>= SSA_FIXED_MINIMUM
) {
568 /* Specific register */
569 int reg
= SSA_REG_FROM_FIXED(source
);
571 /* TODO: Moving threshold */
572 if (reg
> 16 && reg
< 24)
573 printf("u%d", 23 - reg
);
577 printf("%d", source
);
582 print_mir_instruction(midgard_instruction
*ins
)
588 midgard_alu_op op
= ins
->alu
.op
;
589 const char *name
= alu_opcode_names
[op
];
592 printf("%d.", ins
->unit
);
594 printf("%s", name
? name
: "??");
598 case TAG_LOAD_STORE_4
: {
599 midgard_load_store_op op
= ins
->load_store
.op
;
600 const char *name
= load_store_opcode_names
[op
];
607 case TAG_TEXTURE_4
: {
616 ssa_args
*args
= &ins
->ssa_args
;
618 printf(" %d, ", args
->dest
);
620 print_mir_source(args
->src0
);
623 if (args
->inline_constant
)
624 printf("#%d", ins
->inline_constant
);
626 print_mir_source(args
->src1
);
628 if (ins
->has_constants
)
629 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
635 print_mir_block(midgard_block
*block
)
639 mir_foreach_instr_in_block(block
, ins
) {
640 print_mir_instruction(ins
);
647 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
649 ins
->has_constants
= true;
650 memcpy(&ins
->constants
, constants
, 16);
652 /* If this is the special blend constant, mark this instruction */
654 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
655 ins
->has_blend_constant
= true;
659 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
661 return glsl_count_attribute_slots(type
, false);
664 /* Lower fdot2 to a vector multiplication followed by channel addition */
666 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
668 if (alu
->op
!= nir_op_fdot2
)
671 b
->cursor
= nir_before_instr(&alu
->instr
);
673 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
674 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
676 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
678 nir_ssa_def
*sum
= nir_fadd(b
,
679 nir_channel(b
, product
, 0),
680 nir_channel(b
, product
, 1));
682 /* Replace the fdot2 with this sum */
683 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
687 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
689 switch (instr
->intrinsic
) {
690 case nir_intrinsic_load_viewport_scale
:
691 return PAN_SYSVAL_VIEWPORT_SCALE
;
692 case nir_intrinsic_load_viewport_offset
:
693 return PAN_SYSVAL_VIEWPORT_OFFSET
;
700 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
704 if (instr
->type
== nir_instr_type_intrinsic
) {
705 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
706 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
712 /* We have a sysval load; check if it's already been assigned */
714 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
717 /* It hasn't -- so assign it now! */
719 unsigned id
= ctx
->sysval_count
++;
720 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
721 ctx
->sysvals
[id
] = sysval
;
725 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
727 ctx
->sysval_count
= 0;
729 nir_foreach_function(function
, shader
) {
730 if (!function
->impl
) continue;
732 nir_foreach_block(block
, function
->impl
) {
733 nir_foreach_instr_safe(instr
, block
) {
734 midgard_nir_assign_sysval_body(ctx
, instr
);
741 midgard_nir_lower_fdot2(nir_shader
*shader
)
743 bool progress
= false;
745 nir_foreach_function(function
, shader
) {
746 if (!function
->impl
) continue;
749 nir_builder
*b
= &_b
;
750 nir_builder_init(b
, function
->impl
);
752 nir_foreach_block(block
, function
->impl
) {
753 nir_foreach_instr_safe(instr
, block
) {
754 if (instr
->type
!= nir_instr_type_alu
) continue;
756 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
757 midgard_nir_lower_fdot2_body(b
, alu
);
763 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
771 optimise_nir(nir_shader
*nir
)
775 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
776 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
778 nir_lower_tex_options lower_tex_options
= {
782 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
787 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
788 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
790 NIR_PASS(progress
, nir
, nir_copy_prop
);
791 NIR_PASS(progress
, nir
, nir_opt_dce
);
792 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
793 NIR_PASS(progress
, nir
, nir_opt_cse
);
794 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
795 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
796 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
797 NIR_PASS(progress
, nir
, nir_opt_undef
);
798 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
801 nir_var_function_temp
);
803 /* TODO: Enable vectorize when merged upstream */
804 // NIR_PASS(progress, nir, nir_opt_vectorize);
807 /* Must be run at the end to prevent creation of fsin/fcos ops */
808 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
813 NIR_PASS(progress
, nir
, nir_opt_dce
);
814 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
815 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
816 NIR_PASS(progress
, nir
, nir_copy_prop
);
819 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
820 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
822 /* Lower mods for float ops only. Integer ops don't support modifiers
823 * (saturate doesn't make sense on integers, neg/abs require dedicated
826 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
827 NIR_PASS(progress
, nir
, nir_copy_prop
);
828 NIR_PASS(progress
, nir
, nir_opt_dce
);
830 /* We implement booleans as 32-bit 0/~0 */
831 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
833 /* Take us out of SSA */
834 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
835 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
837 /* We are a vector architecture; write combine where possible */
838 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
839 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
841 NIR_PASS(progress
, nir
, nir_opt_dce
);
844 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
845 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
846 * r0. See the comments in compiler_context */
849 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
851 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
852 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
855 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
858 unalias_ssa(compiler_context
*ctx
, int dest
)
860 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
861 /* TODO: Remove from leftover or no? */
865 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
867 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
871 midgard_is_pinned(compiler_context
*ctx
, int index
)
873 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
876 /* Do not actually emit a load; instead, cache the constant for inlining */
879 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
881 nir_ssa_def def
= instr
->def
;
883 float *v
= ralloc_array(NULL
, float, 4);
884 nir_const_load_to_arr(v
, instr
, f32
);
885 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
888 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
892 expand_writemask(unsigned mask
)
896 for (int i
= 0; i
< 4; ++i
)
904 squeeze_writemask(unsigned mask
)
908 for (int i
= 0; i
< 4; ++i
)
909 if (mask
& (3 << (2 * i
)))
916 /* Determines effective writemask, taking quirks and expansion into account */
918 effective_writemask(midgard_vector_alu
*alu
)
920 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
923 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
925 /* If there is a fixed channel count, construct the appropriate mask */
928 return (1 << channel_count
) - 1;
930 /* Otherwise, just squeeze the existing mask */
931 return squeeze_writemask(alu
->mask
);
935 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
937 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
940 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
945 /* If no temp is find, allocate one */
946 temp
= ctx
->temp_count
++;
947 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
949 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
955 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
958 return src
->ssa
->index
;
960 assert(!src
->reg
.indirect
);
961 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
966 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
969 return dst
->ssa
.index
;
971 assert(!dst
->reg
.indirect
);
972 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
977 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
979 return nir_src_index(ctx
, &src
->src
);
982 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
983 * a conditional test) into that register */
986 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
988 int condition
= nir_src_index(ctx
, src
);
990 /* Source to swizzle the desired component into w */
992 const midgard_vector_alu_src alu_src
= {
993 .swizzle
= SWIZZLE(component
, component
, component
, component
),
996 /* There is no boolean move instruction. Instead, we simulate a move by
997 * ANDing the condition with itself to get it into r31.w */
999 midgard_instruction ins
= {
1001 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
1005 .dest
= SSA_FIXED_REGISTER(31),
1008 .op
= midgard_alu_op_iand
,
1009 .reg_mode
= midgard_reg_mode_full
,
1010 .dest_override
= midgard_dest_override_none
,
1011 .mask
= (0x3 << 6), /* w */
1012 .src1
= vector_alu_srco_unsigned(alu_src
),
1013 .src2
= vector_alu_srco_unsigned(alu_src
)
1017 emit_mir_instruction(ctx
, ins
);
1020 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1021 * pinning to eliminate this move in all known cases */
1024 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1026 int offset
= nir_src_index(ctx
, src
);
1028 midgard_instruction ins
= {
1031 .src0
= SSA_UNUSED_1
,
1033 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1036 .op
= midgard_alu_op_imov
,
1037 .reg_mode
= midgard_reg_mode_full
,
1038 .dest_override
= midgard_dest_override_none
,
1039 .mask
= (0x3 << 6), /* w */
1040 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1041 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1045 emit_mir_instruction(ctx
, ins
);
1048 #define ALU_CASE(nir, _op) \
1049 case nir_op_##nir: \
1050 op = midgard_alu_op_##_op; \
1054 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1056 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1058 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1059 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1060 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1062 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1063 * supported. A few do not and are commented for now. Also, there are a
1064 * number of NIR ops which Midgard does not support and need to be
1065 * lowered, also TODO. This switch block emits the opcode and calling
1066 * convention of the Midgard instruction; actual packing is done in
1071 switch (instr
->op
) {
1072 ALU_CASE(fadd
, fadd
);
1073 ALU_CASE(fmul
, fmul
);
1074 ALU_CASE(fmin
, fmin
);
1075 ALU_CASE(fmax
, fmax
);
1076 ALU_CASE(imin
, imin
);
1077 ALU_CASE(imax
, imax
);
1078 ALU_CASE(umin
, umin
);
1079 ALU_CASE(umax
, umax
);
1080 ALU_CASE(fmov
, fmov
);
1081 ALU_CASE(ffloor
, ffloor
);
1082 ALU_CASE(fround_even
, froundeven
);
1083 ALU_CASE(ftrunc
, ftrunc
);
1084 ALU_CASE(fceil
, fceil
);
1085 ALU_CASE(fdot3
, fdot3
);
1086 ALU_CASE(fdot4
, fdot4
);
1087 ALU_CASE(iadd
, iadd
);
1088 ALU_CASE(isub
, isub
);
1089 ALU_CASE(imul
, imul
);
1090 ALU_CASE(iabs
, iabs
);
1092 /* XXX: Use fmov, not imov, since imov was causing major
1093 * issues with texture precision? XXX research */
1094 ALU_CASE(imov
, imov
);
1096 ALU_CASE(feq32
, feq
);
1097 ALU_CASE(fne32
, fne
);
1098 ALU_CASE(flt32
, flt
);
1099 ALU_CASE(ieq32
, ieq
);
1100 ALU_CASE(ine32
, ine
);
1101 ALU_CASE(ilt32
, ilt
);
1102 ALU_CASE(ult32
, ult
);
1104 /* We don't have a native b2f32 instruction. Instead, like many
1105 * GPUs, we exploit booleans as 0/~0 for false/true, and
1106 * correspondingly AND
1107 * by 1.0 to do the type conversion. For the moment, prime us
1110 * iand [whatever], #0
1112 * At the end of emit_alu (as MIR), we'll fix-up the constant
1115 ALU_CASE(b2f32
, iand
);
1116 ALU_CASE(b2i32
, iand
);
1118 /* Likewise, we don't have a dedicated f2b32 instruction, but
1119 * we can do a "not equal to 0.0" test. */
1121 ALU_CASE(f2b32
, fne
);
1122 ALU_CASE(i2b32
, ine
);
1124 ALU_CASE(frcp
, frcp
);
1125 ALU_CASE(frsq
, frsqrt
);
1126 ALU_CASE(fsqrt
, fsqrt
);
1127 ALU_CASE(fexp2
, fexp2
);
1128 ALU_CASE(flog2
, flog2
);
1130 ALU_CASE(f2i32
, f2i
);
1131 ALU_CASE(f2u32
, f2u
);
1132 ALU_CASE(i2f32
, i2f
);
1133 ALU_CASE(u2f32
, u2f
);
1135 ALU_CASE(fsin
, fsin
);
1136 ALU_CASE(fcos
, fcos
);
1138 ALU_CASE(iand
, iand
);
1140 ALU_CASE(ixor
, ixor
);
1141 ALU_CASE(inot
, inot
);
1142 ALU_CASE(ishl
, ishl
);
1143 ALU_CASE(ishr
, iasr
);
1144 ALU_CASE(ushr
, ilsr
);
1146 ALU_CASE(b32all_fequal2
, fball_eq
);
1147 ALU_CASE(b32all_fequal3
, fball_eq
);
1148 ALU_CASE(b32all_fequal4
, fball_eq
);
1150 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1151 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1152 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1154 ALU_CASE(b32all_iequal2
, iball_eq
);
1155 ALU_CASE(b32all_iequal3
, iball_eq
);
1156 ALU_CASE(b32all_iequal4
, iball_eq
);
1158 ALU_CASE(b32any_inequal2
, ibany_neq
);
1159 ALU_CASE(b32any_inequal3
, ibany_neq
);
1160 ALU_CASE(b32any_inequal4
, ibany_neq
);
1162 /* For greater-or-equal, we lower to less-or-equal and flip the
1168 case nir_op_uge32
: {
1170 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1171 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1172 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1173 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1176 /* Swap via temporary */
1177 nir_alu_src temp
= instr
->src
[1];
1178 instr
->src
[1] = instr
->src
[0];
1179 instr
->src
[0] = temp
;
1184 case nir_op_b32csel
: {
1185 op
= midgard_alu_op_fcsel
;
1187 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1190 /* Figure out which component the condition is in */
1192 unsigned comp
= instr
->src
[0].swizzle
[0];
1194 /* Make sure NIR isn't throwing a mixed condition at us */
1196 for (unsigned c
= 1; c
< nr_components
; ++c
)
1197 assert(instr
->src
[0].swizzle
[c
] == comp
);
1199 /* Emit the condition into r31.w */
1200 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1202 /* The condition is the first argument; move the other
1203 * arguments up one to be a binary instruction for
1206 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1211 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1216 /* Fetch unit, quirks, etc information */
1217 unsigned opcode_props
= alu_opcode_props
[op
];
1218 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1220 /* Initialise fields common between scalar/vector instructions */
1221 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1223 /* src0 will always exist afaik, but src1 will not for 1-argument
1224 * instructions. The latter can only be fetched if the instruction
1225 * needs it, or else we may segfault. */
1227 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1228 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1230 /* Rather than use the instruction generation helpers, we do it
1231 * ourselves here to avoid the mess */
1233 midgard_instruction ins
= {
1236 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1237 .src1
= quirk_flipped_r24
? src0
: src1
,
1242 nir_alu_src
*nirmods
[2] = { NULL
};
1244 if (nr_inputs
== 2) {
1245 nirmods
[0] = &instr
->src
[0];
1246 nirmods
[1] = &instr
->src
[1];
1247 } else if (nr_inputs
== 1) {
1248 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1253 midgard_vector_alu alu
= {
1255 .reg_mode
= midgard_reg_mode_full
,
1256 .dest_override
= midgard_dest_override_none
,
1259 /* Writemask only valid for non-SSA NIR */
1260 .mask
= expand_writemask((1 << nr_components
) - 1),
1262 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1263 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1266 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1269 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1273 /* Late fixup for emulated instructions */
1275 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1276 /* Presently, our second argument is an inline #0 constant.
1277 * Switch over to an embedded 1.0 constant (that can't fit
1278 * inline, since we're 32-bit, not 16-bit like the inline
1281 ins
.ssa_args
.inline_constant
= false;
1282 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1283 ins
.has_constants
= true;
1285 if (instr
->op
== nir_op_b2f32
) {
1286 ins
.constants
[0] = 1.0f
;
1288 /* Type pun it into place */
1290 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1293 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1294 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1295 ins
.ssa_args
.inline_constant
= false;
1296 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1297 ins
.has_constants
= true;
1298 ins
.constants
[0] = 0.0f
;
1299 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1302 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1303 /* To avoid duplicating the lookup tables (probably), true LUT
1304 * instructions can only operate as if they were scalars. Lower
1305 * them here by changing the component. */
1307 uint8_t original_swizzle
[4];
1308 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1310 for (int i
= 0; i
< nr_components
; ++i
) {
1311 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1313 for (int j
= 0; j
< 4; ++j
)
1314 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1316 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1317 emit_mir_instruction(ctx
, ins
);
1320 emit_mir_instruction(ctx
, ins
);
1327 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1329 /* TODO: half-floats */
1331 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1332 /* Fast path: For the first 16 uniforms, direct accesses are
1333 * 0-cycle, since they're just a register fetch in the usual
1334 * case. So, we alias the registers while we're still in
1337 int reg_slot
= 23 - offset
;
1338 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1340 /* Otherwise, read from the 'special' UBO to access
1341 * higher-indexed uniforms, at a performance cost. More
1342 * generally, we're emitting a UBO read instruction. */
1344 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1346 /* TODO: Don't split */
1347 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1348 ins
.load_store
.address
= offset
>> 3;
1350 if (indirect_offset
) {
1351 emit_indirect_offset(ctx
, indirect_offset
);
1352 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1354 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1357 emit_mir_instruction(ctx
, ins
);
1362 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1364 /* First, pull out the destination */
1365 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1367 /* Now, figure out which uniform this is */
1368 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1369 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1371 /* Sysvals are prefix uniforms */
1372 unsigned uniform
= ((uintptr_t) val
) - 1;
1374 /* Emit the read itself -- this is never indirect */
1375 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1379 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1381 unsigned offset
, reg
;
1383 switch (instr
->intrinsic
) {
1384 case nir_intrinsic_discard_if
:
1385 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1389 case nir_intrinsic_discard
: {
1390 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1391 struct midgard_instruction discard
= v_branch(conditional
, false);
1392 discard
.branch
.target_type
= TARGET_DISCARD
;
1393 emit_mir_instruction(ctx
, discard
);
1395 ctx
->can_discard
= true;
1399 case nir_intrinsic_load_uniform
:
1400 case nir_intrinsic_load_input
:
1401 offset
= nir_intrinsic_base(instr
);
1403 bool direct
= nir_src_is_const(instr
->src
[0]);
1406 offset
+= nir_src_as_uint(instr
->src
[0]);
1409 reg
= nir_dest_index(ctx
, &instr
->dest
);
1411 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1412 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1413 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1414 /* XXX: Half-floats? */
1415 /* TODO: swizzle, mask */
1417 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1419 midgard_varying_parameter p
= {
1421 .interpolation
= midgard_interp_default
,
1422 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1426 memcpy(&u
, &p
, sizeof(p
));
1427 ins
.load_store
.varying_parameters
= u
;
1430 /* We have the offset totally ready */
1431 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1433 /* We have it partially ready, but we need to
1434 * add in the dynamic index, moved to r27.w */
1435 emit_indirect_offset(ctx
, &instr
->src
[0]);
1436 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1439 emit_mir_instruction(ctx
, ins
);
1440 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1441 /* Constant encoded as a pinned constant */
1443 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1444 ins
.has_constants
= true;
1445 ins
.has_blend_constant
= true;
1446 emit_mir_instruction(ctx
, ins
);
1447 } else if (ctx
->is_blend
) {
1448 /* For blend shaders, a load might be
1449 * translated various ways depending on what
1450 * we're loading. Figure out how this is used */
1452 nir_variable
*out
= NULL
;
1454 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1455 int drvloc
= var
->data
.driver_location
;
1457 if (nir_intrinsic_base(instr
) == drvloc
) {
1465 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1466 /* Source color preloaded to r0 */
1468 midgard_pin_output(ctx
, reg
, 0);
1469 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1470 /* Destination color must be read from framebuffer */
1472 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1473 ins
.load_store
.swizzle
= 0; /* xxxx */
1475 /* Read each component sequentially */
1477 for (int c
= 0; c
< 4; ++c
) {
1478 ins
.load_store
.mask
= (1 << c
);
1479 ins
.load_store
.unknown
= c
;
1480 emit_mir_instruction(ctx
, ins
);
1483 /* vadd.u2f hr2, abs(hr2), #0 */
1485 midgard_vector_alu_src alu_src
= blank_alu_src
;
1487 alu_src
.half
= true;
1489 midgard_instruction u2f
= {
1493 .src1
= SSA_UNUSED_0
,
1495 .inline_constant
= true
1498 .op
= midgard_alu_op_u2f
,
1499 .reg_mode
= midgard_reg_mode_half
,
1500 .dest_override
= midgard_dest_override_none
,
1502 .src1
= vector_alu_srco_unsigned(alu_src
),
1503 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1507 emit_mir_instruction(ctx
, u2f
);
1509 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1511 alu_src
.abs
= false;
1513 midgard_instruction fmul
= {
1515 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1519 .src1
= SSA_UNUSED_0
,
1520 .inline_constant
= true
1523 .op
= midgard_alu_op_fmul
,
1524 .reg_mode
= midgard_reg_mode_full
,
1525 .dest_override
= midgard_dest_override_none
,
1526 .outmod
= midgard_outmod_sat
,
1528 .src1
= vector_alu_srco_unsigned(alu_src
),
1529 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1533 emit_mir_instruction(ctx
, fmul
);
1535 DBG("Unknown input in blend shader\n");
1538 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1539 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1540 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1541 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1542 emit_mir_instruction(ctx
, ins
);
1544 DBG("Unknown load\n");
1550 case nir_intrinsic_store_output
:
1551 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1553 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1555 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1557 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1558 /* gl_FragColor is not emitted with load/store
1559 * instructions. Instead, it gets plonked into
1560 * r0 at the end of the shader and we do the
1561 * framebuffer writeout dance. TODO: Defer
1564 midgard_pin_output(ctx
, reg
, 0);
1566 /* Save the index we're writing to for later reference
1567 * in the epilogue */
1569 ctx
->fragment_output
= reg
;
1570 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1571 /* Varyings are written into one of two special
1572 * varying register, r26 or r27. The register itself is selected as the register
1573 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1575 * Normally emitting fmov's is frowned upon,
1576 * but due to unique constraints of
1577 * REGISTER_VARYING, fmov emission + a
1578 * dedicated cleanup pass is the only way to
1579 * guarantee correctness when considering some
1580 * (common) edge cases XXX: FIXME */
1582 /* If this varying corresponds to a constant (why?!),
1583 * emit that now since it won't get picked up by
1584 * hoisting (since there is no corresponding move
1585 * emitted otherwise) */
1587 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1589 if (constant_value
) {
1590 /* Special case: emit the varying write
1591 * directly to r26 (looks funny in asm but it's
1592 * fine) and emit the store _now_. Possibly
1593 * slightly slower, but this is a really stupid
1594 * special case anyway (why on earth would you
1595 * have a constant varying? Your own fault for
1596 * slightly worse perf :P) */
1598 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1599 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1600 emit_mir_instruction(ctx
, ins
);
1602 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1603 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1604 emit_mir_instruction(ctx
, st
);
1606 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1608 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1611 DBG("Unknown store\n");
1617 case nir_intrinsic_load_alpha_ref_float
:
1618 assert(instr
->dest
.is_ssa
);
1620 float ref_value
= ctx
->alpha_ref
;
1622 float *v
= ralloc_array(NULL
, float, 4);
1623 memcpy(v
, &ref_value
, sizeof(float));
1624 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1627 case nir_intrinsic_load_viewport_scale
:
1628 case nir_intrinsic_load_viewport_offset
:
1629 emit_sysval_read(ctx
, instr
);
1633 printf ("Unhandled intrinsic\n");
1640 midgard_tex_format(enum glsl_sampler_dim dim
)
1643 case GLSL_SAMPLER_DIM_2D
:
1644 case GLSL_SAMPLER_DIM_EXTERNAL
:
1647 case GLSL_SAMPLER_DIM_3D
:
1650 case GLSL_SAMPLER_DIM_CUBE
:
1651 return TEXTURE_CUBE
;
1654 DBG("Unknown sampler dim type\n");
1661 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1664 //assert (!instr->sampler);
1665 //assert (!instr->texture_array_size);
1666 assert (instr
->op
== nir_texop_tex
);
1668 /* Allocate registers via a round robin scheme to alternate between the two registers */
1669 int reg
= ctx
->texture_op_count
& 1;
1670 int in_reg
= reg
, out_reg
= reg
;
1672 /* Make room for the reg */
1674 if (ctx
->texture_index
[reg
] > -1)
1675 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1677 int texture_index
= instr
->texture_index
;
1678 int sampler_index
= texture_index
;
1680 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1681 switch (instr
->src
[i
].src_type
) {
1682 case nir_tex_src_coord
: {
1683 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1685 midgard_vector_alu_src alu_src
= blank_alu_src
;
1687 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1689 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1690 /* For cubemaps, we need to load coords into
1691 * special r27, and then use a special ld/st op
1692 * to copy into the texture register */
1694 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1696 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1697 emit_mir_instruction(ctx
, move
);
1699 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1700 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1701 st
.load_store
.mask
= 0x3; /* xy? */
1702 st
.load_store
.swizzle
= alu_src
.swizzle
;
1703 emit_mir_instruction(ctx
, st
);
1706 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1708 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1709 emit_mir_instruction(ctx
, ins
);
1712 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1718 DBG("Unknown source type\n");
1725 /* No helper to build texture words -- we do it all here */
1726 midgard_instruction ins
= {
1727 .type
= TAG_TEXTURE_4
,
1729 .op
= TEXTURE_OP_NORMAL
,
1730 .format
= midgard_tex_format(instr
->sampler_dim
),
1731 .texture_handle
= texture_index
,
1732 .sampler_handle
= sampler_index
,
1734 /* TODO: Don't force xyzw */
1735 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1747 /* Assume we can continue; hint it out later */
1752 /* Set registers to read and write from the same place */
1753 ins
.texture
.in_reg_select
= in_reg
;
1754 ins
.texture
.out_reg_select
= out_reg
;
1756 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1757 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1758 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1759 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1760 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1762 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1763 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1764 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1767 emit_mir_instruction(ctx
, ins
);
1769 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1771 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1772 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1773 ctx
->texture_index
[reg
] = o_index
;
1775 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1776 emit_mir_instruction(ctx
, ins2
);
1778 /* Used for .cont and .last hinting */
1779 ctx
->texture_op_count
++;
1783 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1785 switch (instr
->type
) {
1786 case nir_jump_break
: {
1787 /* Emit a branch out of the loop */
1788 struct midgard_instruction br
= v_branch(false, false);
1789 br
.branch
.target_type
= TARGET_BREAK
;
1790 br
.branch
.target_break
= ctx
->current_loop
;
1791 emit_mir_instruction(ctx
, br
);
1798 DBG("Unknown jump type %d\n", instr
->type
);
1804 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1806 switch (instr
->type
) {
1807 case nir_instr_type_load_const
:
1808 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1811 case nir_instr_type_intrinsic
:
1812 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1815 case nir_instr_type_alu
:
1816 emit_alu(ctx
, nir_instr_as_alu(instr
));
1819 case nir_instr_type_tex
:
1820 emit_tex(ctx
, nir_instr_as_tex(instr
));
1823 case nir_instr_type_jump
:
1824 emit_jump(ctx
, nir_instr_as_jump(instr
));
1827 case nir_instr_type_ssa_undef
:
1832 DBG("Unhandled instruction type\n");
1837 /* Determine the actual hardware from the index based on the RA results or special values */
1840 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1842 if (reg
>= SSA_FIXED_MINIMUM
)
1843 return SSA_REG_FROM_FIXED(reg
);
1846 assert(reg
< maxreg
);
1847 int r
= ra_get_node_reg(g
, reg
);
1848 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1853 /* fmov style unused */
1855 return REGISTER_UNUSED
;
1857 /* lut style unused */
1859 return REGISTER_UNUSED
;
1862 DBG("Unknown SSA register alias %d\n", reg
);
1869 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1871 /* Choose the first available register to minimise reported register pressure */
1873 for (int i
= 0; i
< 16; ++i
) {
1874 if (BITSET_TEST(regs
, i
)) {
1884 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1886 if (ins
->ssa_args
.src0
== src
) return true;
1887 if (ins
->ssa_args
.src1
== src
) return true;
1892 /* Determine if a variable is live in the successors of a block */
1894 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
1896 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
1897 midgard_block
*succ
= bl
->successors
[i
];
1899 /* If we already visited, the value we're seeking
1900 * isn't down this path (or we would have short
1903 if (succ
->visited
) continue;
1905 /* Otherwise (it's visited *now*), check the block */
1907 succ
->visited
= true;
1909 mir_foreach_instr_in_block(succ
, ins
) {
1910 if (midgard_is_live_in_instr(ins
, src
))
1914 /* ...and also, check *its* successors */
1915 if (is_live_after_successors(ctx
, succ
, src
))
1920 /* Welp. We're really not live. */
1926 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1928 /* Check the rest of the block for liveness */
1930 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1931 if (midgard_is_live_in_instr(ins
, src
))
1935 /* Check the rest of the blocks for liveness recursively */
1937 bool succ
= is_live_after_successors(ctx
, block
, src
);
1939 mir_foreach_block(ctx
, block
) {
1940 block
->visited
= false;
1947 allocate_registers(compiler_context
*ctx
)
1949 /* First, initialize the RA */
1950 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1952 /* Create a primary (general purpose) class, as well as special purpose
1953 * pipeline register classes */
1955 int primary_class
= ra_alloc_reg_class(regs
);
1956 int varying_class
= ra_alloc_reg_class(regs
);
1958 /* Add the full set of work registers */
1959 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1960 for (int i
= 0; i
< work_count
; ++i
)
1961 ra_class_add_reg(regs
, primary_class
, i
);
1963 /* Add special registers */
1964 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1965 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1967 /* We're done setting up */
1968 ra_set_finalize(regs
, NULL
);
1970 /* Transform the MIR into squeezed index form */
1971 mir_foreach_block(ctx
, block
) {
1972 mir_foreach_instr_in_block(block
, ins
) {
1973 if (ins
->compact_branch
) continue;
1975 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1976 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1977 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1979 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1980 print_mir_block(block
);
1983 /* Let's actually do register allocation */
1984 int nodes
= ctx
->temp_count
;
1985 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1987 /* Set everything to the work register class, unless it has somewhere
1990 mir_foreach_block(ctx
, block
) {
1991 mir_foreach_instr_in_block(block
, ins
) {
1992 if (ins
->compact_branch
) continue;
1994 if (ins
->ssa_args
.dest
< 0) continue;
1996 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1998 int class = primary_class
;
2000 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2004 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2005 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2008 unsigned reg
= temp
- 1;
2009 int t
= find_or_allocate_temp(ctx
, index
);
2010 ra_set_node_reg(g
, t
, reg
);
2014 /* Determine liveness */
2016 int *live_start
= malloc(nodes
* sizeof(int));
2017 int *live_end
= malloc(nodes
* sizeof(int));
2019 /* Initialize as non-existent */
2021 for (int i
= 0; i
< nodes
; ++i
) {
2022 live_start
[i
] = live_end
[i
] = -1;
2027 mir_foreach_block(ctx
, block
) {
2028 mir_foreach_instr_in_block(block
, ins
) {
2029 if (ins
->compact_branch
) continue;
2031 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2032 /* If this destination is not yet live, it is now since we just wrote it */
2034 int dest
= ins
->ssa_args
.dest
;
2036 if (live_start
[dest
] == -1)
2037 live_start
[dest
] = d
;
2040 /* Since we just used a source, the source might be
2041 * dead now. Scan the rest of the block for
2042 * invocations, and if there are none, the source dies
2045 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2047 for (int src
= 0; src
< 2; ++src
) {
2048 int s
= sources
[src
];
2050 if (s
< 0) continue;
2052 if (s
>= SSA_FIXED_MINIMUM
) continue;
2054 if (!is_live_after(ctx
, block
, ins
, s
)) {
2063 /* If a node still hasn't been killed, kill it now */
2065 for (int i
= 0; i
< nodes
; ++i
) {
2066 /* live_start == -1 most likely indicates a pinned output */
2068 if (live_end
[i
] == -1)
2072 /* Setup interference between nodes that are live at the same time */
2074 for (int i
= 0; i
< nodes
; ++i
) {
2075 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2076 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2077 ra_add_node_interference(g
, i
, j
);
2081 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2083 if (!ra_allocate(g
)) {
2084 DBG("Error allocating registers\n");
2092 mir_foreach_block(ctx
, block
) {
2093 mir_foreach_instr_in_block(block
, ins
) {
2094 if (ins
->compact_branch
) continue;
2096 ssa_args args
= ins
->ssa_args
;
2098 switch (ins
->type
) {
2100 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2102 ins
->registers
.src2_imm
= args
.inline_constant
;
2104 if (args
.inline_constant
) {
2105 /* Encode inline 16-bit constant as a vector by default */
2107 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2109 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2111 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2112 ins
->alu
.src2
= imm
<< 2;
2114 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2117 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2121 case TAG_LOAD_STORE_4
: {
2122 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2123 /* TODO: use ssa_args for store_vary */
2124 ins
->load_store
.reg
= 0;
2126 bool has_dest
= args
.dest
>= 0;
2127 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2129 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2142 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2143 * use scalar ALU instructions, for functional or performance reasons. To do
2144 * this, we just demote vector ALU payloads to scalar. */
2147 component_from_mask(unsigned mask
)
2149 for (int c
= 0; c
< 4; ++c
) {
2150 if (mask
& (3 << (2 * c
)))
2159 is_single_component_mask(unsigned mask
)
2163 for (int c
= 0; c
< 4; ++c
)
2164 if (mask
& (3 << (2 * c
)))
2167 return components
== 1;
2170 /* Create a mask of accessed components from a swizzle to figure out vector
2174 swizzle_to_access_mask(unsigned swizzle
)
2176 unsigned component_mask
= 0;
2178 for (int i
= 0; i
< 4; ++i
) {
2179 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2180 component_mask
|= (1 << c
);
2183 return component_mask
;
2187 vector_to_scalar_source(unsigned u
)
2189 midgard_vector_alu_src v
;
2190 memcpy(&v
, &u
, sizeof(v
));
2192 midgard_scalar_alu_src s
= {
2196 .component
= (v
.swizzle
& 3) << 1
2200 memcpy(&o
, &s
, sizeof(s
));
2202 return o
& ((1 << 6) - 1);
2205 static midgard_scalar_alu
2206 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2208 /* The output component is from the mask */
2209 midgard_scalar_alu s
= {
2211 .src1
= vector_to_scalar_source(v
.src1
),
2212 .src2
= vector_to_scalar_source(v
.src2
),
2215 .output_full
= 1, /* TODO: Half */
2216 .output_component
= component_from_mask(v
.mask
) << 1,
2219 /* Inline constant is passed along rather than trying to extract it
2222 if (ins
->ssa_args
.inline_constant
) {
2224 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2225 imm
|= (lower_11
>> 9) & 3;
2226 imm
|= (lower_11
>> 6) & 4;
2227 imm
|= (lower_11
>> 2) & 0x38;
2228 imm
|= (lower_11
& 63) << 6;
2236 /* Midgard prefetches instruction types, so during emission we need to
2237 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2238 * if this is the second to last and the last is an ALU, then it's also 1... */
2240 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2241 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2243 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2244 bytes_emitted += sizeof(type)
2247 emit_binary_vector_instruction(midgard_instruction
*ains
,
2248 uint16_t *register_words
, int *register_words_count
,
2249 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2250 size_t *bytes_emitted
)
2252 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2253 *bytes_emitted
+= sizeof(midgard_reg_info
);
2255 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2256 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2257 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2260 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2261 * mind that we are a vector architecture and we can write to different
2262 * components simultaneously */
2265 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2267 /* Each instruction reads some registers and writes to a register. See
2268 * where the first writes */
2270 /* Figure out where exactly we wrote to */
2271 int source
= first
->ssa_args
.dest
;
2272 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2274 /* As long as the second doesn't read from the first, we're okay */
2275 if (second
->ssa_args
.src0
== source
) {
2276 if (first
->type
== TAG_ALU_4
) {
2277 /* Figure out which components we just read from */
2279 int q
= second
->alu
.src1
;
2280 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2282 /* Check if there are components in common, and fail if so */
2283 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2290 if (second
->ssa_args
.src1
== source
)
2293 /* Otherwise, it's safe in that regard. Another data hazard is both
2294 * writing to the same place, of course */
2296 if (second
->ssa_args
.dest
== source
) {
2297 /* ...but only if the components overlap */
2298 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2300 if (dest_mask
& source_mask
)
2310 midgard_instruction
**segment
, unsigned segment_size
,
2311 midgard_instruction
*ains
)
2313 for (int s
= 0; s
< segment_size
; ++s
)
2314 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2322 /* Schedules, but does not emit, a single basic block. After scheduling, the
2323 * final tag and size of the block are known, which are necessary for branching
2326 static midgard_bundle
2327 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2329 int instructions_emitted
= 0, instructions_consumed
= -1;
2330 midgard_bundle bundle
= { 0 };
2332 uint8_t tag
= ins
->type
;
2334 /* Default to the instruction's tag */
2337 switch (ins
->type
) {
2339 uint32_t control
= 0;
2340 size_t bytes_emitted
= sizeof(control
);
2342 /* TODO: Constant combining */
2343 int index
= 0, last_unit
= 0;
2345 /* Previous instructions, for the purpose of parallelism */
2346 midgard_instruction
*segment
[4] = {0};
2347 int segment_size
= 0;
2349 instructions_emitted
= -1;
2350 midgard_instruction
*pins
= ins
;
2353 midgard_instruction
*ains
= pins
;
2355 /* Advance instruction pointer */
2357 ains
= mir_next_op(pins
);
2361 /* Out-of-work condition */
2362 if ((struct list_head
*) ains
== &block
->instructions
)
2365 /* Ensure that the chain can continue */
2366 if (ains
->type
!= TAG_ALU_4
) break;
2368 /* According to the presentation "The ARM
2369 * Mali-T880 Mobile GPU" from HotChips 27,
2370 * there are two pipeline stages. Branching
2371 * position determined experimentally. Lines
2372 * are executed in parallel:
2375 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2377 * Verify that there are no ordering dependencies here.
2379 * TODO: Allow for parallelism!!!
2382 /* Pick a unit for it if it doesn't force a particular unit */
2384 int unit
= ains
->unit
;
2387 int op
= ains
->alu
.op
;
2388 int units
= alu_opcode_props
[op
];
2390 /* TODO: Promotion of scalars to vectors */
2391 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2394 assert(units
& UNITS_SCALAR
);
2397 if (last_unit
>= UNIT_VADD
) {
2398 if (units
& UNIT_VLUT
)
2403 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2405 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2407 else if (units
& UNIT_VLUT
)
2413 if (last_unit
>= UNIT_VADD
) {
2414 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2416 else if (units
& UNIT_VLUT
)
2421 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2423 else if (units
& UNIT_SMUL
)
2424 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2425 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2432 assert(unit
& units
);
2435 /* Late unit check, this time for encoding (not parallelism) */
2436 if (unit
<= last_unit
) break;
2438 /* Clear the segment */
2439 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2442 if (midgard_has_hazard(segment
, segment_size
, ains
))
2445 /* We're good to go -- emit the instruction */
2448 segment
[segment_size
++] = ains
;
2450 /* Only one set of embedded constants per
2451 * bundle possible; if we have more, we must
2452 * break the chain early, unfortunately */
2454 if (ains
->has_constants
) {
2455 if (bundle
.has_embedded_constants
) {
2456 /* ...but if there are already
2457 * constants but these are the
2458 * *same* constants, we let it
2461 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2464 bundle
.has_embedded_constants
= true;
2465 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2467 /* If this is a blend shader special constant, track it for patching */
2468 if (ains
->has_blend_constant
)
2469 bundle
.has_blend_constant
= true;
2473 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2474 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2475 &bundle
.register_words_count
, bundle
.body_words
,
2476 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2477 } else if (ains
->compact_branch
) {
2478 /* All of r0 has to be written out
2479 * along with the branch writeout.
2482 if (ains
->writeout
) {
2484 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2485 ins
.unit
= UNIT_VMUL
;
2487 control
|= ins
.unit
;
2489 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2490 &bundle
.register_words_count
, bundle
.body_words
,
2491 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2493 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2494 bool written_late
= false;
2495 bool components
[4] = { 0 };
2496 uint16_t register_dep_mask
= 0;
2497 uint16_t written_mask
= 0;
2499 midgard_instruction
*qins
= ins
;
2500 for (int t
= 0; t
< index
; ++t
) {
2501 if (qins
->registers
.out_reg
!= 0) {
2502 /* Mark down writes */
2504 written_mask
|= (1 << qins
->registers
.out_reg
);
2506 /* Mark down the register dependencies for errata check */
2508 if (qins
->registers
.src1_reg
< 16)
2509 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2511 if (qins
->registers
.src2_reg
< 16)
2512 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2514 int mask
= qins
->alu
.mask
;
2516 for (int c
= 0; c
< 4; ++c
)
2517 if (mask
& (0x3 << (2 * c
)))
2518 components
[c
] = true;
2520 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2522 if (qins
->unit
== UNIT_VLUT
)
2523 written_late
= true;
2526 /* Advance instruction pointer */
2527 qins
= mir_next_op(qins
);
2531 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2532 if (register_dep_mask
& written_mask
) {
2533 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2540 /* If even a single component is not written, break it up (conservative check). */
2541 bool breakup
= false;
2543 for (int c
= 0; c
< 4; ++c
)
2550 /* Otherwise, we're free to proceed */
2554 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2555 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2556 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2557 bytes_emitted
+= sizeof(midgard_branch_extended
);
2559 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2560 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2561 bytes_emitted
+= sizeof(ains
->br_compact
);
2564 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2565 bytes_emitted
+= sizeof(midgard_reg_info
);
2567 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2568 bundle
.body_words_count
++;
2569 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2572 /* Defer marking until after writing to allow for break */
2573 control
|= ains
->unit
;
2574 last_unit
= ains
->unit
;
2575 ++instructions_emitted
;
2579 /* Bubble up the number of instructions for skipping */
2580 instructions_consumed
= index
- 1;
2584 /* Pad ALU op to nearest word */
2586 if (bytes_emitted
& 15) {
2587 padding
= 16 - (bytes_emitted
& 15);
2588 bytes_emitted
+= padding
;
2591 /* Constants must always be quadwords */
2592 if (bundle
.has_embedded_constants
)
2593 bytes_emitted
+= 16;
2595 /* Size ALU instruction for tag */
2596 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2597 bundle
.padding
= padding
;
2598 bundle
.control
= bundle
.tag
| control
;
2603 case TAG_LOAD_STORE_4
: {
2604 /* Load store instructions have two words at once. If
2605 * we only have one queued up, we need to NOP pad.
2606 * Otherwise, we store both in succession to save space
2607 * and cycles -- letting them go in parallel -- skip
2608 * the next. The usefulness of this optimisation is
2609 * greatly dependent on the quality of the instruction
2613 midgard_instruction
*next_op
= mir_next_op(ins
);
2615 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2616 /* As the two operate concurrently, make sure
2617 * they are not dependent */
2619 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2620 /* Skip ahead, since it's redundant with the pair */
2621 instructions_consumed
= 1 + (instructions_emitted
++);
2629 /* Texture ops default to single-op-per-bundle scheduling */
2633 /* Copy the instructions into the bundle */
2634 bundle
.instruction_count
= instructions_emitted
+ 1;
2638 midgard_instruction
*uins
= ins
;
2639 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2640 bundle
.instructions
[used_idx
++] = *uins
;
2641 uins
= mir_next_op(uins
);
2644 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2650 quadword_size(int tag
)
2665 case TAG_LOAD_STORE_4
:
2677 /* Schedule a single block by iterating its instruction to create bundles.
2678 * While we go, tally about the bundle sizes to compute the block size. */
2681 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2683 util_dynarray_init(&block
->bundles
, NULL
);
2685 block
->quadword_count
= 0;
2687 mir_foreach_instr_in_block(block
, ins
) {
2689 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2690 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2692 if (bundle
.has_blend_constant
) {
2693 /* TODO: Multiblock? */
2694 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2695 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2699 ins
= mir_next_op(ins
);
2701 block
->quadword_count
+= quadword_size(bundle
.tag
);
2704 block
->is_scheduled
= true;
2708 schedule_program(compiler_context
*ctx
)
2710 allocate_registers(ctx
);
2712 mir_foreach_block(ctx
, block
) {
2713 schedule_block(ctx
, block
);
2717 /* After everything is scheduled, emit whole bundles at a time */
2720 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2722 int lookahead
= next_tag
<< 4;
2724 switch (bundle
->tag
) {
2729 /* Actually emit each component */
2730 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2732 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2733 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2735 /* Emit body words based on the instructions bundled */
2736 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2737 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2739 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2740 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2741 } else if (ins
->compact_branch
) {
2742 /* Dummy move, XXX DRY */
2743 if ((i
== 0) && ins
->writeout
) {
2744 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2745 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2748 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2749 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2751 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2755 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2756 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2760 /* Emit padding (all zero) */
2761 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2763 /* Tack on constants */
2765 if (bundle
->has_embedded_constants
) {
2766 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2767 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2768 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2769 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2775 case TAG_LOAD_STORE_4
: {
2776 /* One or two composing instructions */
2778 uint64_t current64
, next64
= LDST_NOP
;
2780 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2782 if (bundle
->instruction_count
== 2)
2783 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2785 midgard_load_store instruction
= {
2786 .type
= bundle
->tag
,
2787 .next_type
= next_tag
,
2792 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2797 case TAG_TEXTURE_4
: {
2798 /* Texture instructions are easy, since there is no
2799 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2801 midgard_instruction
*ins
= &bundle
->instructions
[0];
2803 ins
->texture
.type
= TAG_TEXTURE_4
;
2804 ins
->texture
.next_type
= next_tag
;
2806 ctx
->texture_op_count
--;
2808 if (!ctx
->texture_op_count
) {
2809 ins
->texture
.cont
= 0;
2810 ins
->texture
.last
= 1;
2813 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2818 DBG("Unknown midgard instruction type\n");
2825 /* ALU instructions can inline or embed constants, which decreases register
2826 * pressure and saves space. */
2828 #define CONDITIONAL_ATTACH(src) { \
2829 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2832 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2833 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2838 inline_alu_constants(compiler_context
*ctx
)
2840 mir_foreach_instr(ctx
, alu
) {
2841 /* Other instructions cannot inline constants */
2842 if (alu
->type
!= TAG_ALU_4
) continue;
2844 /* If there is already a constant here, we can do nothing */
2845 if (alu
->has_constants
) continue;
2847 /* It makes no sense to inline constants on a branch */
2848 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2850 CONDITIONAL_ATTACH(src0
);
2852 if (!alu
->has_constants
) {
2853 CONDITIONAL_ATTACH(src1
)
2854 } else if (!alu
->inline_constant
) {
2855 /* Corner case: _two_ vec4 constants, for instance with a
2856 * csel. For this case, we can only use a constant
2857 * register for one, we'll have to emit a move for the
2858 * other. Note, if both arguments are constants, then
2859 * necessarily neither argument depends on the value of
2860 * any particular register. As the destination register
2861 * will be wiped, that means we can spill the constant
2862 * to the destination register.
2865 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2866 unsigned scratch
= alu
->ssa_args
.dest
;
2869 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2870 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2872 /* Force a break XXX Defer r31 writes */
2873 ins
.unit
= UNIT_VLUT
;
2875 /* Set the source */
2876 alu
->ssa_args
.src1
= scratch
;
2878 /* Inject us -before- the last instruction which set r31 */
2879 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2885 /* Midgard supports two types of constants, embedded constants (128-bit) and
2886 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2887 * constants can be demoted to inline constants, for space savings and
2888 * sometimes a performance boost */
2891 embedded_to_inline_constant(compiler_context
*ctx
)
2893 mir_foreach_instr(ctx
, ins
) {
2894 if (!ins
->has_constants
) continue;
2896 if (ins
->ssa_args
.inline_constant
) continue;
2898 /* Blend constants must not be inlined by definition */
2899 if (ins
->has_blend_constant
) continue;
2901 /* src1 cannot be an inline constant due to encoding
2902 * restrictions. So, if possible we try to flip the arguments
2905 int op
= ins
->alu
.op
;
2907 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2908 /* Flip based on op. Fallthrough intentional */
2911 /* These ops require an operational change to flip their arguments TODO */
2912 case midgard_alu_op_flt
:
2913 case midgard_alu_op_fle
:
2914 case midgard_alu_op_ilt
:
2915 case midgard_alu_op_ile
:
2916 case midgard_alu_op_fcsel
:
2917 case midgard_alu_op_icsel
:
2918 case midgard_alu_op_isub
:
2919 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2922 /* These ops are commutative and Just Flip */
2923 case midgard_alu_op_fne
:
2924 case midgard_alu_op_fadd
:
2925 case midgard_alu_op_fmul
:
2926 case midgard_alu_op_fmin
:
2927 case midgard_alu_op_fmax
:
2928 case midgard_alu_op_iadd
:
2929 case midgard_alu_op_imul
:
2930 case midgard_alu_op_feq
:
2931 case midgard_alu_op_ieq
:
2932 case midgard_alu_op_ine
:
2933 case midgard_alu_op_iand
:
2934 case midgard_alu_op_ior
:
2935 case midgard_alu_op_ixor
:
2936 /* Flip the SSA numbers */
2937 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2938 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2940 /* And flip the modifiers */
2944 src_temp
= ins
->alu
.src2
;
2945 ins
->alu
.src2
= ins
->alu
.src1
;
2946 ins
->alu
.src1
= src_temp
;
2953 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2954 /* Extract the source information */
2956 midgard_vector_alu_src
*src
;
2957 int q
= ins
->alu
.src2
;
2958 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2961 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2962 int component
= src
->swizzle
& 3;
2964 /* Scale constant appropriately, if we can legally */
2965 uint16_t scaled_constant
= 0;
2967 /* XXX: Check legality */
2968 if (midgard_is_integer_op(op
)) {
2969 /* TODO: Inline integer */
2972 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2973 scaled_constant
= (uint16_t) iconstants
[component
];
2975 /* Constant overflow after resize */
2976 if (scaled_constant
!= iconstants
[component
])
2979 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2982 /* We don't know how to handle these with a constant */
2984 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2985 DBG("Bailing inline constant...\n");
2989 /* Make sure that the constant is not itself a
2990 * vector by checking if all accessed values
2991 * (by the swizzle) are the same. */
2993 uint32_t *cons
= (uint32_t *) ins
->constants
;
2994 uint32_t value
= cons
[component
];
2996 bool is_vector
= false;
2997 unsigned mask
= effective_writemask(&ins
->alu
);
2999 for (int c
= 1; c
< 4; ++c
) {
3000 /* We only care if this component is actually used */
3001 if (!(mask
& (1 << c
)))
3004 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3006 if (test
!= value
) {
3015 /* Get rid of the embedded constant */
3016 ins
->has_constants
= false;
3017 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3018 ins
->ssa_args
.inline_constant
= true;
3019 ins
->inline_constant
= scaled_constant
;
3024 /* Map normal SSA sources to other SSA sources / fixed registers (like
3028 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3030 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3033 /* Remove entry in leftovers to avoid a redunant fmov */
3035 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3038 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3040 /* Assign the alias map */
3046 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3047 * texture pipeline */
3050 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3052 mir_foreach_instr_in_block_safe(block
, ins
) {
3053 if (ins
->type
!= TAG_ALU_4
) continue;
3054 if (ins
->compact_branch
) continue;
3056 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3057 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3058 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3060 mir_remove_instruction(ins
);
3064 /* The following passes reorder MIR instructions to enable better scheduling */
3067 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3069 mir_foreach_instr_in_block_safe(block
, ins
) {
3070 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3072 /* We've found a load/store op. Check if next is also load/store. */
3073 midgard_instruction
*next_op
= mir_next_op(ins
);
3074 if (&next_op
->link
!= &block
->instructions
) {
3075 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3076 /* If so, we're done since we're a pair */
3077 ins
= mir_next_op(ins
);
3081 /* Maximum search distance to pair, to avoid register pressure disasters */
3082 int search_distance
= 8;
3084 /* Otherwise, we have an orphaned load/store -- search for another load */
3085 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3086 /* Terminate search if necessary */
3087 if (!(search_distance
--)) break;
3089 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3091 /* Stores cannot be reordered, since they have
3092 * dependencies. For the same reason, indirect
3093 * loads cannot be reordered as their index is
3094 * loaded in r27.w */
3096 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3098 /* It appears the 0x800 bit is set whenever a
3099 * load is direct, unset when it is indirect.
3100 * Skip indirect loads. */
3102 if (!(c
->load_store
.unknown
& 0x800)) continue;
3104 /* We found one! Move it up to pair and remove it from the old location */
3106 mir_insert_instruction_before(ins
, *c
);
3107 mir_remove_instruction(c
);
3115 /* Emit varying stores late */
3118 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3119 /* Iterate in reverse to get the final write, rather than the first */
3121 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3122 /* Check if what we just wrote needs a store */
3123 int idx
= ins
->ssa_args
.dest
;
3124 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3126 if (!varying
) continue;
3130 /* We need to store to the appropriate varying, so emit the
3133 /* TODO: Integrate with special purpose RA (and scheduler?) */
3134 bool high_varying_register
= false;
3136 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3138 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3139 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3141 mir_insert_instruction_before(mir_next_op(ins
), st
);
3142 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3144 /* We no longer need to store this varying */
3145 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3149 /* If there are leftovers after the below pass, emit actual fmov
3150 * instructions for the slow-but-correct path */
3153 emit_leftover_move(compiler_context
*ctx
)
3155 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3156 int base
= ((uintptr_t) leftover
->key
) - 1;
3159 map_ssa_to_alias(ctx
, &mapped
);
3160 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3165 actualise_ssa_to_alias(compiler_context
*ctx
)
3167 mir_foreach_instr(ctx
, ins
) {
3168 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3169 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3172 emit_leftover_move(ctx
);
3176 emit_fragment_epilogue(compiler_context
*ctx
)
3178 /* Special case: writing out constants requires us to include the move
3179 * explicitly now, so shove it into r0 */
3181 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3183 if (constant_value
) {
3184 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3185 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3186 emit_mir_instruction(ctx
, ins
);
3189 /* Perform the actual fragment writeout. We have two writeout/branch
3190 * instructions, forming a loop until writeout is successful as per the
3191 * docs. TODO: gl_FragDepth */
3193 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3194 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3197 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3198 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3199 * with the int8 analogue to the fragment epilogue */
3202 emit_blend_epilogue(compiler_context
*ctx
)
3204 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3206 midgard_instruction scale
= {
3209 .inline_constant
= _mesa_float_to_half(255.0),
3211 .src0
= SSA_FIXED_REGISTER(0),
3212 .src1
= SSA_UNUSED_0
,
3213 .dest
= SSA_FIXED_REGISTER(24),
3214 .inline_constant
= true
3217 .op
= midgard_alu_op_fmul
,
3218 .reg_mode
= midgard_reg_mode_full
,
3219 .dest_override
= midgard_dest_override_lower
,
3221 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3222 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3226 emit_mir_instruction(ctx
, scale
);
3228 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3230 midgard_vector_alu_src alu_src
= blank_alu_src
;
3231 alu_src
.half
= true;
3233 midgard_instruction f2u8
= {
3236 .src0
= SSA_FIXED_REGISTER(24),
3237 .src1
= SSA_UNUSED_0
,
3238 .dest
= SSA_FIXED_REGISTER(0),
3239 .inline_constant
= true
3242 .op
= midgard_alu_op_f2u8
,
3243 .reg_mode
= midgard_reg_mode_half
,
3244 .dest_override
= midgard_dest_override_lower
,
3245 .outmod
= midgard_outmod_pos
,
3247 .src1
= vector_alu_srco_unsigned(alu_src
),
3248 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3252 emit_mir_instruction(ctx
, f2u8
);
3254 /* vmul.imov.quarter r0, r0, r0 */
3256 midgard_instruction imov_8
= {
3259 .src0
= SSA_UNUSED_1
,
3260 .src1
= SSA_FIXED_REGISTER(0),
3261 .dest
= SSA_FIXED_REGISTER(0),
3264 .op
= midgard_alu_op_imov
,
3265 .reg_mode
= midgard_reg_mode_quarter
,
3266 .dest_override
= midgard_dest_override_none
,
3268 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3269 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3273 /* Emit branch epilogue with the 8-bit move as the source */
3275 emit_mir_instruction(ctx
, imov_8
);
3276 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3278 emit_mir_instruction(ctx
, imov_8
);
3279 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3282 static midgard_block
*
3283 emit_block(compiler_context
*ctx
, nir_block
*block
)
3285 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3286 list_addtail(&this_block
->link
, &ctx
->blocks
);
3288 this_block
->is_scheduled
= false;
3291 ctx
->texture_index
[0] = -1;
3292 ctx
->texture_index
[1] = -1;
3294 /* Add us as a successor to the block we are following */
3295 if (ctx
->current_block
)
3296 midgard_block_add_successor(ctx
->current_block
, this_block
);
3298 /* Set up current block */
3299 list_inithead(&this_block
->instructions
);
3300 ctx
->current_block
= this_block
;
3302 nir_foreach_instr(instr
, block
) {
3303 emit_instr(ctx
, instr
);
3304 ++ctx
->instruction_count
;
3307 inline_alu_constants(ctx
);
3308 embedded_to_inline_constant(ctx
);
3310 /* Perform heavylifting for aliasing */
3311 actualise_ssa_to_alias(ctx
);
3313 midgard_emit_store(ctx
, this_block
);
3314 midgard_pair_load_store(ctx
, this_block
);
3316 /* Append fragment shader epilogue (value writeout) */
3317 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3318 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3320 emit_blend_epilogue(ctx
);
3322 emit_fragment_epilogue(ctx
);
3326 if (block
== nir_start_block(ctx
->func
->impl
))
3327 ctx
->initial_block
= this_block
;
3329 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3330 ctx
->final_block
= this_block
;
3332 /* Allow the next control flow to access us retroactively, for
3334 ctx
->current_block
= this_block
;
3336 /* Document the fallthrough chain */
3337 ctx
->previous_source_block
= this_block
;
3342 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3345 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3347 /* Conditional branches expect the condition in r31.w; emit a move for
3348 * that in the _previous_ block (which is the current block). */
3349 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3351 /* Speculatively emit the branch, but we can't fill it in until later */
3352 EMIT(branch
, true, true);
3353 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3355 /* Emit the two subblocks */
3356 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3358 /* Emit a jump from the end of the then block to the end of the else */
3359 EMIT(branch
, false, false);
3360 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3362 /* Emit second block, and check if it's empty */
3364 int else_idx
= ctx
->block_count
;
3365 int count_in
= ctx
->instruction_count
;
3366 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3367 int after_else_idx
= ctx
->block_count
;
3369 /* Now that we have the subblocks emitted, fix up the branches */
3374 if (ctx
->instruction_count
== count_in
) {
3375 /* The else block is empty, so don't emit an exit jump */
3376 mir_remove_instruction(then_exit
);
3377 then_branch
->branch
.target_block
= after_else_idx
;
3379 then_branch
->branch
.target_block
= else_idx
;
3380 then_exit
->branch
.target_block
= after_else_idx
;
3385 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3387 /* Remember where we are */
3388 midgard_block
*start_block
= ctx
->current_block
;
3390 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3391 * single current_loop variable, maybe we need a stack */
3393 int loop_idx
= ++ctx
->current_loop
;
3395 /* Get index from before the body so we can loop back later */
3396 int start_idx
= ctx
->block_count
;
3398 /* Emit the body itself */
3399 emit_cf_list(ctx
, &nloop
->body
);
3401 /* Branch back to loop back */
3402 struct midgard_instruction br_back
= v_branch(false, false);
3403 br_back
.branch
.target_block
= start_idx
;
3404 emit_mir_instruction(ctx
, br_back
);
3406 /* Mark down that branch in the graph */
3407 midgard_block_add_successor(ctx
->current_block
, start_block
);
3409 /* Find the index of the block about to follow us (note: we don't add
3410 * one; blocks are 0-indexed so we get a fencepost problem) */
3411 int break_block_idx
= ctx
->block_count
;
3413 /* Fix up the break statements we emitted to point to the right place,
3414 * now that we can allocate a block number for them */
3416 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3417 mir_foreach_instr_in_block(block
, ins
) {
3418 if (ins
->type
!= TAG_ALU_4
) continue;
3419 if (!ins
->compact_branch
) continue;
3420 if (ins
->prepacked_branch
) continue;
3422 /* We found a branch -- check the type to see if we need to do anything */
3423 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3425 /* It's a break! Check if it's our break */
3426 if (ins
->branch
.target_break
!= loop_idx
) continue;
3428 /* Okay, cool, we're breaking out of this loop.
3429 * Rewrite from a break to a goto */
3431 ins
->branch
.target_type
= TARGET_GOTO
;
3432 ins
->branch
.target_block
= break_block_idx
;
3437 static midgard_block
*
3438 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3440 midgard_block
*start_block
= NULL
;
3442 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3443 switch (node
->type
) {
3444 case nir_cf_node_block
: {
3445 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3448 start_block
= block
;
3453 case nir_cf_node_if
:
3454 emit_if(ctx
, nir_cf_node_as_if(node
));
3457 case nir_cf_node_loop
:
3458 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3461 case nir_cf_node_function
:
3470 /* Due to lookahead, we need to report the first tag executed in the command
3471 * stream and in branch targets. An initial block might be empty, so iterate
3472 * until we find one that 'works' */
3475 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3477 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3479 unsigned first_tag
= 0;
3482 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3484 if (initial_bundle
) {
3485 first_tag
= initial_bundle
->tag
;
3489 /* Initial block is empty, try the next block */
3490 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3491 } while(initial_block
!= NULL
);
3498 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3500 struct util_dynarray
*compiled
= &program
->compiled
;
3502 midgard_debug
= debug_get_option_midgard_debug();
3504 compiler_context ictx
= {
3506 .stage
= nir
->info
.stage
,
3508 .is_blend
= is_blend
,
3509 .blend_constant_offset
= -1,
3511 .alpha_ref
= program
->alpha_ref
3514 compiler_context
*ctx
= &ictx
;
3516 /* TODO: Decide this at runtime */
3517 ctx
->uniform_cutoff
= 8;
3519 /* Assign var locations early, so the epilogue can use them if necessary */
3521 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3522 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3523 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3525 /* Initialize at a global (not block) level hash tables */
3527 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3528 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3529 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3530 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3531 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3532 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3533 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3535 /* Record the varying mapping for the command stream's bookkeeping */
3537 struct exec_list
*varyings
=
3538 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3540 nir_foreach_variable(var
, varyings
) {
3541 unsigned loc
= var
->data
.driver_location
;
3542 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3544 for (int c
= 0; c
< sz
; ++c
) {
3545 program
->varyings
[loc
+ c
] = var
->data
.location
;
3549 /* Lower gl_Position pre-optimisation */
3551 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3552 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3554 NIR_PASS_V(nir
, nir_lower_var_copies
);
3555 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3556 NIR_PASS_V(nir
, nir_split_var_copies
);
3557 NIR_PASS_V(nir
, nir_lower_var_copies
);
3558 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3559 NIR_PASS_V(nir
, nir_lower_var_copies
);
3560 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3562 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3564 /* Optimisation passes */
3568 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3569 nir_print_shader(nir
, stdout
);
3572 /* Assign sysvals and counts, now that we're sure
3573 * (post-optimisation) */
3575 midgard_nir_assign_sysvals(ctx
, nir
);
3577 program
->uniform_count
= nir
->num_uniforms
;
3578 program
->sysval_count
= ctx
->sysval_count
;
3579 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3581 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3582 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3584 nir_foreach_function(func
, nir
) {
3588 list_inithead(&ctx
->blocks
);
3589 ctx
->block_count
= 0;
3592 emit_cf_list(ctx
, &func
->impl
->body
);
3593 emit_block(ctx
, func
->impl
->end_block
);
3595 break; /* TODO: Multi-function shaders */
3598 util_dynarray_init(compiled
, NULL
);
3600 /* Peephole optimizations */
3602 mir_foreach_block(ctx
, block
) {
3603 midgard_opt_dead_code_eliminate(ctx
, block
);
3607 schedule_program(ctx
);
3609 /* Now that all the bundles are scheduled and we can calculate block
3610 * sizes, emit actual branch instructions rather than placeholders */
3612 int br_block_idx
= 0;
3614 mir_foreach_block(ctx
, block
) {
3615 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3616 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3617 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3619 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3621 if (ins
->prepacked_branch
) continue;
3623 /* Parse some basic branch info */
3624 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3625 bool is_conditional
= ins
->branch
.conditional
;
3626 bool is_inverted
= ins
->branch
.invert_conditional
;
3627 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3629 /* Determine the block we're jumping to */
3630 int target_number
= ins
->branch
.target_block
;
3632 /* Report the destination tag. Discards don't need this */
3633 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3635 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3636 int quadword_offset
= 0;
3639 /* Jump to the end of the shader. We
3640 * need to include not only the
3641 * following blocks, but also the
3642 * contents of our current block (since
3643 * discard can come in the middle of
3646 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3648 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3649 quadword_offset
+= quadword_size(bun
->tag
);
3652 mir_foreach_block_from(ctx
, blk
, b
) {
3653 quadword_offset
+= b
->quadword_count
;
3656 } else if (target_number
> br_block_idx
) {
3659 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3660 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3663 quadword_offset
+= blk
->quadword_count
;
3666 /* Jump backwards */
3668 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3669 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3672 quadword_offset
-= blk
->quadword_count
;
3676 /* Unconditional extended branches (far jumps)
3677 * have issues, so we always use a conditional
3678 * branch, setting the condition to always for
3679 * unconditional. For compact unconditional
3680 * branches, cond isn't used so it doesn't
3681 * matter what we pick. */
3683 midgard_condition cond
=
3684 !is_conditional
? midgard_condition_always
:
3685 is_inverted
? midgard_condition_false
:
3686 midgard_condition_true
;
3688 midgard_jmp_writeout_op op
=
3689 is_discard
? midgard_jmp_writeout_op_discard
:
3690 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3691 midgard_jmp_writeout_op_branch_cond
;
3694 midgard_branch_extended branch
=
3695 midgard_create_branch_extended(
3700 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3701 } else if (is_conditional
|| is_discard
) {
3702 midgard_branch_cond branch
= {
3704 .dest_tag
= dest_tag
,
3705 .offset
= quadword_offset
,
3709 assert(branch
.offset
== quadword_offset
);
3711 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3713 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3715 midgard_branch_uncond branch
= {
3717 .dest_tag
= dest_tag
,
3718 .offset
= quadword_offset
,
3722 assert(branch
.offset
== quadword_offset
);
3724 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3732 /* Emit flat binary from the instruction arrays. Iterate each block in
3733 * sequence. Save instruction boundaries such that lookahead tags can
3734 * be assigned easily */
3736 /* Cache _all_ bundles in source order for lookahead across failed branches */
3738 int bundle_count
= 0;
3739 mir_foreach_block(ctx
, block
) {
3740 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3742 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3744 mir_foreach_block(ctx
, block
) {
3745 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3746 source_order_bundles
[bundle_idx
++] = bundle
;
3750 int current_bundle
= 0;
3752 mir_foreach_block(ctx
, block
) {
3753 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3756 if (current_bundle
+ 1 < bundle_count
) {
3757 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3759 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3766 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3770 /* TODO: Free deeper */
3771 //util_dynarray_fini(&block->instructions);
3774 free(source_order_bundles
);
3776 /* Report the very first tag executed */
3777 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3779 /* Deal with off-by-one related to the fencepost problem */
3780 program
->work_register_count
= ctx
->work_registers
+ 1;
3782 program
->can_discard
= ctx
->can_discard
;
3783 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3785 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3787 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3788 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);