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panfrost/midgard: Fix 1-arg ALU memory corruption
[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value debug_options[] = {
54 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
56 DEBUG_NAMED_VALUE_END
57 };
58
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
60
61 int midgard_debug = 0;
62
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67
68 static bool
69 midgard_is_branch_unit(unsigned unit)
70 {
71 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
72 }
73
74 static void
75 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
76 {
77 block->successors[block->nr_successors++] = successor;
78 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
79 }
80
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
83
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
91 .ssa_args = { \
92 .rname = ssa, \
93 .uname = -1, \
94 .src1 = -1 \
95 }, \
96 .load_store = { \
97 .op = midgard_op_##name, \
98 .mask = 0xF, \
99 .swizzle = SWIZZLE_XYZW, \
100 .address = address \
101 } \
102 }; \
103 \
104 return i; \
105 }
106
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
109
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
112
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src *src, bool is_int)
115 {
116 if (!src) return blank_alu_src;
117
118 midgard_vector_alu_src alu_src = {
119 .rep_low = 0,
120 .rep_high = 0,
121 .half = 0, /* TODO */
122 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
123 };
124
125 if (is_int) {
126 /* TODO: sign-extend/zero-extend */
127 alu_src.mod = midgard_int_normal;
128
129 /* These should have been lowered away */
130 assert(!(src->abs || src->negate));
131 } else {
132 alu_src.mod = (src->abs << 0) | (src->negate << 1);
133 }
134
135 return alu_src;
136 }
137
138 /* load/store instructions have both 32-bit and 16-bit variants, depending on
139 * whether we are using vectors composed of highp or mediump. At the moment, we
140 * don't support half-floats -- this requires changes in other parts of the
141 * compiler -- therefore the 16-bit versions are commented out. */
142
143 //M_LOAD(ld_attr_16);
144 M_LOAD(ld_attr_32);
145 //M_LOAD(ld_vary_16);
146 M_LOAD(ld_vary_32);
147 //M_LOAD(ld_uniform_16);
148 M_LOAD(ld_uniform_32);
149 M_LOAD(ld_color_buffer_8);
150 //M_STORE(st_vary_16);
151 M_STORE(st_vary_32);
152 M_STORE(st_cubemap_coords);
153
154 static midgard_instruction
155 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
156 {
157 midgard_branch_cond branch = {
158 .op = op,
159 .dest_tag = tag,
160 .offset = offset,
161 .cond = cond
162 };
163
164 uint16_t compact;
165 memcpy(&compact, &branch, sizeof(branch));
166
167 midgard_instruction ins = {
168 .type = TAG_ALU_4,
169 .unit = ALU_ENAB_BR_COMPACT,
170 .prepacked_branch = true,
171 .compact_branch = true,
172 .br_compact = compact
173 };
174
175 if (op == midgard_jmp_writeout_op_writeout)
176 ins.writeout = true;
177
178 return ins;
179 }
180
181 static midgard_instruction
182 v_branch(bool conditional, bool invert)
183 {
184 midgard_instruction ins = {
185 .type = TAG_ALU_4,
186 .unit = ALU_ENAB_BRANCH,
187 .compact_branch = true,
188 .branch = {
189 .conditional = conditional,
190 .invert_conditional = invert
191 }
192 };
193
194 return ins;
195 }
196
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond,
199 midgard_jmp_writeout_op op,
200 unsigned dest_tag,
201 signed quadword_offset)
202 {
203 /* For unclear reasons, the condition code is repeated 8 times */
204 uint16_t duplicated_cond =
205 (cond << 14) |
206 (cond << 12) |
207 (cond << 10) |
208 (cond << 8) |
209 (cond << 6) |
210 (cond << 4) |
211 (cond << 2) |
212 (cond << 0);
213
214 midgard_branch_extended branch = {
215 .op = op,
216 .dest_tag = dest_tag,
217 .offset = quadword_offset,
218 .cond = duplicated_cond
219 };
220
221 return branch;
222 }
223
224 static void
225 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
226 {
227 ins->has_constants = true;
228 memcpy(&ins->constants, constants, 16);
229 }
230
231 static int
232 glsl_type_size(const struct glsl_type *type, bool bindless)
233 {
234 return glsl_count_attribute_slots(type, false);
235 }
236
237 /* Lower fdot2 to a vector multiplication followed by channel addition */
238 static void
239 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
240 {
241 if (alu->op != nir_op_fdot2)
242 return;
243
244 b->cursor = nir_before_instr(&alu->instr);
245
246 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
247 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
248
249 nir_ssa_def *product = nir_fmul(b, src0, src1);
250
251 nir_ssa_def *sum = nir_fadd(b,
252 nir_channel(b, product, 0),
253 nir_channel(b, product, 1));
254
255 /* Replace the fdot2 with this sum */
256 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
257 }
258
259 static int
260 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
261 {
262 switch (instr->intrinsic) {
263 case nir_intrinsic_load_viewport_scale:
264 return PAN_SYSVAL_VIEWPORT_SCALE;
265 case nir_intrinsic_load_viewport_offset:
266 return PAN_SYSVAL_VIEWPORT_OFFSET;
267 default:
268 return -1;
269 }
270 }
271
272 static void
273 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
274 {
275 int sysval = -1;
276
277 if (instr->type == nir_instr_type_intrinsic) {
278 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
279 sysval = midgard_nir_sysval_for_intrinsic(intr);
280 }
281
282 if (sysval < 0)
283 return;
284
285 /* We have a sysval load; check if it's already been assigned */
286
287 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
288 return;
289
290 /* It hasn't -- so assign it now! */
291
292 unsigned id = ctx->sysval_count++;
293 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
294 ctx->sysvals[id] = sysval;
295 }
296
297 static void
298 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
299 {
300 ctx->sysval_count = 0;
301
302 nir_foreach_function(function, shader) {
303 if (!function->impl) continue;
304
305 nir_foreach_block(block, function->impl) {
306 nir_foreach_instr_safe(instr, block) {
307 midgard_nir_assign_sysval_body(ctx, instr);
308 }
309 }
310 }
311 }
312
313 static bool
314 midgard_nir_lower_fdot2(nir_shader *shader)
315 {
316 bool progress = false;
317
318 nir_foreach_function(function, shader) {
319 if (!function->impl) continue;
320
321 nir_builder _b;
322 nir_builder *b = &_b;
323 nir_builder_init(b, function->impl);
324
325 nir_foreach_block(block, function->impl) {
326 nir_foreach_instr_safe(instr, block) {
327 if (instr->type != nir_instr_type_alu) continue;
328
329 nir_alu_instr *alu = nir_instr_as_alu(instr);
330 midgard_nir_lower_fdot2_body(b, alu);
331
332 progress |= true;
333 }
334 }
335
336 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
337
338 }
339
340 return progress;
341 }
342
343 static void
344 optimise_nir(nir_shader *nir)
345 {
346 bool progress;
347 unsigned lower_flrp =
348 (nir->options->lower_flrp16 ? 16 : 0) |
349 (nir->options->lower_flrp32 ? 32 : 0) |
350 (nir->options->lower_flrp64 ? 64 : 0);
351
352 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
353 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
354
355 nir_lower_tex_options lower_tex_options = {
356 .lower_rect = true
357 };
358
359 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
360
361 do {
362 progress = false;
363
364 NIR_PASS(progress, nir, nir_lower_var_copies);
365 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
366
367 NIR_PASS(progress, nir, nir_copy_prop);
368 NIR_PASS(progress, nir, nir_opt_dce);
369 NIR_PASS(progress, nir, nir_opt_dead_cf);
370 NIR_PASS(progress, nir, nir_opt_cse);
371 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
372 NIR_PASS(progress, nir, nir_opt_algebraic);
373 NIR_PASS(progress, nir, nir_opt_constant_folding);
374
375 if (lower_flrp != 0) {
376 bool lower_flrp_progress = false;
377 NIR_PASS(lower_flrp_progress,
378 nir,
379 nir_lower_flrp,
380 lower_flrp,
381 false /* always_precise */,
382 nir->options->lower_ffma);
383 if (lower_flrp_progress) {
384 NIR_PASS(progress, nir,
385 nir_opt_constant_folding);
386 progress = true;
387 }
388
389 /* Nothing should rematerialize any flrps, so we only
390 * need to do this lowering once.
391 */
392 lower_flrp = 0;
393 }
394
395 NIR_PASS(progress, nir, nir_opt_undef);
396 NIR_PASS(progress, nir, nir_opt_loop_unroll,
397 nir_var_shader_in |
398 nir_var_shader_out |
399 nir_var_function_temp);
400
401 /* TODO: Enable vectorize when merged upstream */
402 // NIR_PASS(progress, nir, nir_opt_vectorize);
403 } while (progress);
404
405 /* Must be run at the end to prevent creation of fsin/fcos ops */
406 NIR_PASS(progress, nir, midgard_nir_scale_trig);
407
408 do {
409 progress = false;
410
411 NIR_PASS(progress, nir, nir_opt_dce);
412 NIR_PASS(progress, nir, nir_opt_algebraic);
413 NIR_PASS(progress, nir, nir_opt_constant_folding);
414 NIR_PASS(progress, nir, nir_copy_prop);
415 } while (progress);
416
417 NIR_PASS(progress, nir, nir_opt_algebraic_late);
418
419 /* We implement booleans as 32-bit 0/~0 */
420 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
421
422 /* Now that booleans are lowered, we can run out late opts */
423 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
424
425 /* Lower mods for float ops only. Integer ops don't support modifiers
426 * (saturate doesn't make sense on integers, neg/abs require dedicated
427 * instructions) */
428
429 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
430 NIR_PASS(progress, nir, nir_copy_prop);
431 NIR_PASS(progress, nir, nir_opt_dce);
432
433 /* Take us out of SSA */
434 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
435 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
436
437 /* We are a vector architecture; write combine where possible */
438 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
439 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
440
441 NIR_PASS(progress, nir, nir_opt_dce);
442 }
443
444 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
445 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
446 * r0. See the comments in compiler_context */
447
448 static void
449 alias_ssa(compiler_context *ctx, int dest, int src)
450 {
451 _mesa_hash_table_u64_insert(ctx->ssa_to_alias, dest + 1, (void *) ((uintptr_t) src + 1));
452 _mesa_set_add(ctx->leftover_ssa_to_alias, (void *) (uintptr_t) (dest + 1));
453 }
454
455 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
456
457 static void
458 unalias_ssa(compiler_context *ctx, int dest)
459 {
460 _mesa_hash_table_u64_remove(ctx->ssa_to_alias, dest + 1);
461 /* TODO: Remove from leftover or no? */
462 }
463
464 /* Do not actually emit a load; instead, cache the constant for inlining */
465
466 static void
467 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
468 {
469 nir_ssa_def def = instr->def;
470
471 float *v = rzalloc_array(NULL, float, 4);
472 nir_const_load_to_arr(v, instr, f32);
473 _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
474 }
475
476 static unsigned
477 nir_src_index(compiler_context *ctx, nir_src *src)
478 {
479 if (src->is_ssa)
480 return src->ssa->index;
481 else {
482 assert(!src->reg.indirect);
483 return ctx->func->impl->ssa_alloc + src->reg.reg->index;
484 }
485 }
486
487 static unsigned
488 nir_dest_index(compiler_context *ctx, nir_dest *dst)
489 {
490 if (dst->is_ssa)
491 return dst->ssa.index;
492 else {
493 assert(!dst->reg.indirect);
494 return ctx->func->impl->ssa_alloc + dst->reg.reg->index;
495 }
496 }
497
498 static unsigned
499 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
500 {
501 return nir_src_index(ctx, &src->src);
502 }
503
504 static bool
505 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
506 {
507 unsigned comp = src->swizzle[0];
508
509 for (unsigned c = 1; c < nr_components; ++c) {
510 if (src->swizzle[c] != comp)
511 return true;
512 }
513
514 return false;
515 }
516
517 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
518 * output of a conditional test) into that register */
519
520 static void
521 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
522 {
523 int condition = nir_src_index(ctx, src);
524
525 /* Source to swizzle the desired component into w */
526
527 const midgard_vector_alu_src alu_src = {
528 .swizzle = SWIZZLE(component, component, component, component),
529 };
530
531 /* There is no boolean move instruction. Instead, we simulate a move by
532 * ANDing the condition with itself to get it into r31.w */
533
534 midgard_instruction ins = {
535 .type = TAG_ALU_4,
536
537 /* We need to set the conditional as close as possible */
538 .precede_break = true,
539 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
540
541 .ssa_args = {
542
543 .src0 = condition,
544 .src1 = condition,
545 .dest = SSA_FIXED_REGISTER(31),
546 },
547 .alu = {
548 .op = midgard_alu_op_iand,
549 .outmod = midgard_outmod_int,
550 .reg_mode = midgard_reg_mode_32,
551 .dest_override = midgard_dest_override_none,
552 .mask = (0x3 << 6), /* w */
553 .src1 = vector_alu_srco_unsigned(alu_src),
554 .src2 = vector_alu_srco_unsigned(alu_src)
555 },
556 };
557
558 emit_mir_instruction(ctx, ins);
559 }
560
561 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
562 * r31 instead */
563
564 static void
565 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
566 {
567 int condition = nir_src_index(ctx, &src->src);
568
569 /* Source to swizzle the desired component into w */
570
571 const midgard_vector_alu_src alu_src = {
572 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
573 };
574
575 /* There is no boolean move instruction. Instead, we simulate a move by
576 * ANDing the condition with itself to get it into r31.w */
577
578 midgard_instruction ins = {
579 .type = TAG_ALU_4,
580 .precede_break = true,
581 .ssa_args = {
582 .src0 = condition,
583 .src1 = condition,
584 .dest = SSA_FIXED_REGISTER(31),
585 },
586 .alu = {
587 .op = midgard_alu_op_iand,
588 .outmod = midgard_outmod_int,
589 .reg_mode = midgard_reg_mode_32,
590 .dest_override = midgard_dest_override_none,
591 .mask = expand_writemask((1 << nr_comp) - 1),
592 .src1 = vector_alu_srco_unsigned(alu_src),
593 .src2 = vector_alu_srco_unsigned(alu_src)
594 },
595 };
596
597 emit_mir_instruction(ctx, ins);
598 }
599
600
601
602 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
603 * pinning to eliminate this move in all known cases */
604
605 static void
606 emit_indirect_offset(compiler_context *ctx, nir_src *src)
607 {
608 int offset = nir_src_index(ctx, src);
609
610 midgard_instruction ins = {
611 .type = TAG_ALU_4,
612 .ssa_args = {
613 .src0 = SSA_UNUSED_1,
614 .src1 = offset,
615 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
616 },
617 .alu = {
618 .op = midgard_alu_op_imov,
619 .outmod = midgard_outmod_int,
620 .reg_mode = midgard_reg_mode_32,
621 .dest_override = midgard_dest_override_none,
622 .mask = (0x3 << 6), /* w */
623 .src1 = vector_alu_srco_unsigned(zero_alu_src),
624 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
625 },
626 };
627
628 emit_mir_instruction(ctx, ins);
629 }
630
631 #define ALU_CASE(nir, _op) \
632 case nir_op_##nir: \
633 op = midgard_alu_op_##_op; \
634 break;
635 static bool
636 nir_is_fzero_constant(nir_src src)
637 {
638 if (!nir_src_is_const(src))
639 return false;
640
641 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
642 if (nir_src_comp_as_float(src, c) != 0.0)
643 return false;
644 }
645
646 return true;
647 }
648
649 static void
650 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
651 {
652 bool is_ssa = instr->dest.dest.is_ssa;
653
654 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
655 unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components;
656 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
657
658 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
659 * supported. A few do not and are commented for now. Also, there are a
660 * number of NIR ops which Midgard does not support and need to be
661 * lowered, also TODO. This switch block emits the opcode and calling
662 * convention of the Midgard instruction; actual packing is done in
663 * emit_alu below */
664
665 unsigned op;
666
667 switch (instr->op) {
668 ALU_CASE(fadd, fadd);
669 ALU_CASE(fmul, fmul);
670 ALU_CASE(fmin, fmin);
671 ALU_CASE(fmax, fmax);
672 ALU_CASE(imin, imin);
673 ALU_CASE(imax, imax);
674 ALU_CASE(umin, umin);
675 ALU_CASE(umax, umax);
676 ALU_CASE(ffloor, ffloor);
677 ALU_CASE(fround_even, froundeven);
678 ALU_CASE(ftrunc, ftrunc);
679 ALU_CASE(fceil, fceil);
680 ALU_CASE(fdot3, fdot3);
681 ALU_CASE(fdot4, fdot4);
682 ALU_CASE(iadd, iadd);
683 ALU_CASE(isub, isub);
684 ALU_CASE(imul, imul);
685
686 /* Zero shoved as second-arg */
687 ALU_CASE(iabs, iabsdiff);
688
689 ALU_CASE(mov, imov);
690
691 ALU_CASE(feq32, feq);
692 ALU_CASE(fne32, fne);
693 ALU_CASE(flt32, flt);
694 ALU_CASE(ieq32, ieq);
695 ALU_CASE(ine32, ine);
696 ALU_CASE(ilt32, ilt);
697 ALU_CASE(ult32, ult);
698
699 /* We don't have a native b2f32 instruction. Instead, like many
700 * GPUs, we exploit booleans as 0/~0 for false/true, and
701 * correspondingly AND
702 * by 1.0 to do the type conversion. For the moment, prime us
703 * to emit:
704 *
705 * iand [whatever], #0
706 *
707 * At the end of emit_alu (as MIR), we'll fix-up the constant
708 */
709
710 ALU_CASE(b2f32, iand);
711 ALU_CASE(b2i32, iand);
712
713 /* Likewise, we don't have a dedicated f2b32 instruction, but
714 * we can do a "not equal to 0.0" test. */
715
716 ALU_CASE(f2b32, fne);
717 ALU_CASE(i2b32, ine);
718
719 ALU_CASE(frcp, frcp);
720 ALU_CASE(frsq, frsqrt);
721 ALU_CASE(fsqrt, fsqrt);
722 ALU_CASE(fexp2, fexp2);
723 ALU_CASE(flog2, flog2);
724
725 ALU_CASE(f2i32, f2i);
726 ALU_CASE(f2u32, f2u);
727 ALU_CASE(i2f32, i2f);
728 ALU_CASE(u2f32, u2f);
729
730 ALU_CASE(fsin, fsin);
731 ALU_CASE(fcos, fcos);
732
733 ALU_CASE(iand, iand);
734 ALU_CASE(ior, ior);
735 ALU_CASE(ixor, ixor);
736 ALU_CASE(inot, inand);
737 ALU_CASE(ishl, ishl);
738 ALU_CASE(ishr, iasr);
739 ALU_CASE(ushr, ilsr);
740
741 ALU_CASE(b32all_fequal2, fball_eq);
742 ALU_CASE(b32all_fequal3, fball_eq);
743 ALU_CASE(b32all_fequal4, fball_eq);
744
745 ALU_CASE(b32any_fnequal2, fbany_neq);
746 ALU_CASE(b32any_fnequal3, fbany_neq);
747 ALU_CASE(b32any_fnequal4, fbany_neq);
748
749 ALU_CASE(b32all_iequal2, iball_eq);
750 ALU_CASE(b32all_iequal3, iball_eq);
751 ALU_CASE(b32all_iequal4, iball_eq);
752
753 ALU_CASE(b32any_inequal2, ibany_neq);
754 ALU_CASE(b32any_inequal3, ibany_neq);
755 ALU_CASE(b32any_inequal4, ibany_neq);
756
757 /* Source mods will be shoved in later */
758 ALU_CASE(fabs, fmov);
759 ALU_CASE(fneg, fmov);
760 ALU_CASE(fsat, fmov);
761
762 /* For greater-or-equal, we lower to less-or-equal and flip the
763 * arguments */
764
765 case nir_op_fge:
766 case nir_op_fge32:
767 case nir_op_ige32:
768 case nir_op_uge32: {
769 op =
770 instr->op == nir_op_fge ? midgard_alu_op_fle :
771 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
772 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
773 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
774 0;
775
776 /* Swap via temporary */
777 nir_alu_src temp = instr->src[1];
778 instr->src[1] = instr->src[0];
779 instr->src[0] = temp;
780
781 break;
782 }
783
784 case nir_op_b32csel: {
785 /* Midgard features both fcsel and icsel, depending on
786 * the type of the arguments/output. However, as long
787 * as we're careful we can _always_ use icsel and
788 * _never_ need fcsel, since the latter does additional
789 * floating-point-specific processing whereas the
790 * former just moves bits on the wire. It's not obvious
791 * why these are separate opcodes, save for the ability
792 * to do things like sat/pos/abs/neg for free */
793
794 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
795 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
796
797 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
798 nr_inputs = 2;
799
800 /* Emit the condition into r31 */
801
802 if (mixed)
803 emit_condition_mixed(ctx, &instr->src[0], nr_components);
804 else
805 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
806
807 /* The condition is the first argument; move the other
808 * arguments up one to be a binary instruction for
809 * Midgard */
810
811 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
812 break;
813 }
814
815 default:
816 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
817 assert(0);
818 return;
819 }
820
821 /* Midgard can perform certain modifiers on output of an ALU op */
822 midgard_outmod outmod =
823 midgard_is_integer_out_op(op) ? midgard_outmod_int :
824 instr->dest.saturate ? midgard_outmod_sat : midgard_outmod_none;
825
826 if (instr->op == nir_op_fsat)
827 outmod = midgard_outmod_sat;
828
829 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
830
831 if (instr->op == nir_op_fmax) {
832 if (nir_is_fzero_constant(instr->src[0].src)) {
833 op = midgard_alu_op_fmov;
834 nr_inputs = 1;
835 outmod = midgard_outmod_pos;
836 instr->src[0] = instr->src[1];
837 } else if (nir_is_fzero_constant(instr->src[1].src)) {
838 op = midgard_alu_op_fmov;
839 nr_inputs = 1;
840 outmod = midgard_outmod_pos;
841 }
842 }
843
844 /* Fetch unit, quirks, etc information */
845 unsigned opcode_props = alu_opcode_props[op].props;
846 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
847
848 /* src0 will always exist afaik, but src1 will not for 1-argument
849 * instructions. The latter can only be fetched if the instruction
850 * needs it, or else we may segfault. */
851
852 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
853 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
854
855 /* Rather than use the instruction generation helpers, we do it
856 * ourselves here to avoid the mess */
857
858 midgard_instruction ins = {
859 .type = TAG_ALU_4,
860 .ssa_args = {
861 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
862 .src1 = quirk_flipped_r24 ? src0 : src1,
863 .dest = dest,
864 }
865 };
866
867 nir_alu_src *nirmods[2] = { NULL };
868
869 if (nr_inputs == 2) {
870 nirmods[0] = &instr->src[0];
871 nirmods[1] = &instr->src[1];
872 } else if (nr_inputs == 1) {
873 nirmods[quirk_flipped_r24] = &instr->src[0];
874 } else {
875 assert(0);
876 }
877
878 /* These were lowered to a move, so apply the corresponding mod */
879
880 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
881 nir_alu_src *s = nirmods[quirk_flipped_r24];
882
883 if (instr->op == nir_op_fneg)
884 s->negate = !s->negate;
885
886 if (instr->op == nir_op_fabs)
887 s->abs = !s->abs;
888 }
889
890 bool is_int = midgard_is_integer_op(op);
891
892 midgard_vector_alu alu = {
893 .op = op,
894 .reg_mode = midgard_reg_mode_32,
895 .dest_override = midgard_dest_override_none,
896 .outmod = outmod,
897
898 /* Writemask only valid for non-SSA NIR */
899 .mask = expand_writemask((1 << nr_components) - 1),
900
901 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int)),
902 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int)),
903 };
904
905 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
906
907 if (!is_ssa)
908 alu.mask &= expand_writemask(instr->dest.write_mask);
909
910 ins.alu = alu;
911
912 /* Late fixup for emulated instructions */
913
914 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
915 /* Presently, our second argument is an inline #0 constant.
916 * Switch over to an embedded 1.0 constant (that can't fit
917 * inline, since we're 32-bit, not 16-bit like the inline
918 * constants) */
919
920 ins.ssa_args.inline_constant = false;
921 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
922 ins.has_constants = true;
923
924 if (instr->op == nir_op_b2f32) {
925 ins.constants[0] = 1.0f;
926 } else {
927 /* Type pun it into place */
928 uint32_t one = 0x1;
929 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
930 }
931
932 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
933 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
934 /* Lots of instructions need a 0 plonked in */
935 ins.ssa_args.inline_constant = false;
936 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
937 ins.has_constants = true;
938 ins.constants[0] = 0.0f;
939 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
940 } else if (instr->op == nir_op_inot) {
941 /* ~b = ~(b & b), so duplicate the source */
942 ins.ssa_args.src1 = ins.ssa_args.src0;
943 ins.alu.src2 = ins.alu.src1;
944 }
945
946 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
947 /* To avoid duplicating the lookup tables (probably), true LUT
948 * instructions can only operate as if they were scalars. Lower
949 * them here by changing the component. */
950
951 uint8_t original_swizzle[4];
952 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
953
954 for (int i = 0; i < nr_components; ++i) {
955 ins.alu.mask = (0x3) << (2 * i); /* Mask the associated component */
956
957 for (int j = 0; j < 4; ++j)
958 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
959
960 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int));
961 emit_mir_instruction(ctx, ins);
962 }
963 } else {
964 emit_mir_instruction(ctx, ins);
965 }
966 }
967
968 #undef ALU_CASE
969
970 static void
971 emit_uniform_read(compiler_context *ctx, unsigned dest, unsigned offset, nir_src *indirect_offset)
972 {
973 /* TODO: half-floats */
974
975 if (!indirect_offset && offset < ctx->uniform_cutoff) {
976 /* Fast path: For the first 16 uniforms, direct accesses are
977 * 0-cycle, since they're just a register fetch in the usual
978 * case. So, we alias the registers while we're still in
979 * SSA-space */
980
981 int reg_slot = 23 - offset;
982 alias_ssa(ctx, dest, SSA_FIXED_REGISTER(reg_slot));
983 } else {
984 /* Otherwise, read from the 'special' UBO to access
985 * higher-indexed uniforms, at a performance cost. More
986 * generally, we're emitting a UBO read instruction. */
987
988 midgard_instruction ins = m_ld_uniform_32(dest, offset);
989
990 /* TODO: Don't split */
991 ins.load_store.varying_parameters = (offset & 7) << 7;
992 ins.load_store.address = offset >> 3;
993
994 if (indirect_offset) {
995 emit_indirect_offset(ctx, indirect_offset);
996 ins.load_store.unknown = 0x8700; /* xxx: what is this? */
997 } else {
998 ins.load_store.unknown = 0x1E00; /* xxx: what is this? */
999 }
1000
1001 emit_mir_instruction(ctx, ins);
1002 }
1003 }
1004
1005 static void
1006 emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
1007 {
1008 /* First, pull out the destination */
1009 unsigned dest = nir_dest_index(ctx, &instr->dest);
1010
1011 /* Now, figure out which uniform this is */
1012 int sysval = midgard_nir_sysval_for_intrinsic(instr);
1013 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1014
1015 /* Sysvals are prefix uniforms */
1016 unsigned uniform = ((uintptr_t) val) - 1;
1017
1018 /* Emit the read itself -- this is never indirect */
1019 emit_uniform_read(ctx, dest, uniform, NULL);
1020 }
1021
1022 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1023 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1024 * generations have faster vectorized reads. This operation is for blend
1025 * shaders in particular; reading the tilebuffer from the fragment shader
1026 * remains an open problem. */
1027
1028 static void
1029 emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
1030 {
1031 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1032 ins.load_store.swizzle = 0; /* xxxx */
1033
1034 /* Read each component sequentially */
1035
1036 for (unsigned c = 0; c < 4; ++c) {
1037 ins.load_store.mask = (1 << c);
1038 ins.load_store.unknown = c;
1039 emit_mir_instruction(ctx, ins);
1040 }
1041
1042 /* vadd.u2f hr2, zext(hr2), #0 */
1043
1044 midgard_vector_alu_src alu_src = blank_alu_src;
1045 alu_src.mod = midgard_int_zero_extend;
1046 alu_src.half = true;
1047
1048 midgard_instruction u2f = {
1049 .type = TAG_ALU_4,
1050 .ssa_args = {
1051 .src0 = reg,
1052 .src1 = SSA_UNUSED_0,
1053 .dest = reg,
1054 .inline_constant = true
1055 },
1056 .alu = {
1057 .op = midgard_alu_op_u2f,
1058 .reg_mode = midgard_reg_mode_16,
1059 .dest_override = midgard_dest_override_none,
1060 .mask = 0xF,
1061 .src1 = vector_alu_srco_unsigned(alu_src),
1062 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1063 }
1064 };
1065
1066 emit_mir_instruction(ctx, u2f);
1067
1068 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1069
1070 alu_src.mod = 0;
1071
1072 midgard_instruction fmul = {
1073 .type = TAG_ALU_4,
1074 .inline_constant = _mesa_float_to_half(1.0 / 255.0),
1075 .ssa_args = {
1076 .src0 = reg,
1077 .dest = reg,
1078 .src1 = SSA_UNUSED_0,
1079 .inline_constant = true
1080 },
1081 .alu = {
1082 .op = midgard_alu_op_fmul,
1083 .reg_mode = midgard_reg_mode_32,
1084 .dest_override = midgard_dest_override_none,
1085 .outmod = midgard_outmod_sat,
1086 .mask = 0xFF,
1087 .src1 = vector_alu_srco_unsigned(alu_src),
1088 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1089 }
1090 };
1091
1092 emit_mir_instruction(ctx, fmul);
1093 }
1094
1095 static void
1096 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1097 {
1098 unsigned offset, reg;
1099
1100 switch (instr->intrinsic) {
1101 case nir_intrinsic_discard_if:
1102 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1103
1104 /* fallthrough */
1105
1106 case nir_intrinsic_discard: {
1107 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1108 struct midgard_instruction discard = v_branch(conditional, false);
1109 discard.branch.target_type = TARGET_DISCARD;
1110 emit_mir_instruction(ctx, discard);
1111
1112 ctx->can_discard = true;
1113 break;
1114 }
1115
1116 case nir_intrinsic_load_uniform:
1117 case nir_intrinsic_load_input:
1118 offset = nir_intrinsic_base(instr);
1119
1120 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1121 bool direct = nir_src_is_const(instr->src[0]);
1122
1123 if (direct) {
1124 offset += nir_src_as_uint(instr->src[0]);
1125 }
1126
1127 reg = nir_dest_index(ctx, &instr->dest);
1128
1129 if (instr->intrinsic == nir_intrinsic_load_uniform && !ctx->is_blend) {
1130 emit_uniform_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL);
1131 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1132 /* XXX: Half-floats? */
1133 /* TODO: swizzle, mask */
1134
1135 midgard_instruction ins = m_ld_vary_32(reg, offset);
1136 ins.load_store.mask = (1 << nr_comp) - 1;
1137
1138 midgard_varying_parameter p = {
1139 .is_varying = 1,
1140 .interpolation = midgard_interp_default,
1141 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1142 };
1143
1144 unsigned u;
1145 memcpy(&u, &p, sizeof(p));
1146 ins.load_store.varying_parameters = u;
1147
1148 if (direct) {
1149 /* We have the offset totally ready */
1150 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1151 } else {
1152 /* We have it partially ready, but we need to
1153 * add in the dynamic index, moved to r27.w */
1154 emit_indirect_offset(ctx, &instr->src[0]);
1155 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1156 }
1157
1158 emit_mir_instruction(ctx, ins);
1159 } else if (ctx->is_blend) {
1160 /* For blend shaders, load the input color, which is
1161 * preloaded to r0 */
1162
1163 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1164 emit_mir_instruction(ctx, move);
1165 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1166 midgard_instruction ins = m_ld_attr_32(reg, offset);
1167 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1168 ins.load_store.mask = (1 << nr_comp) - 1;
1169 emit_mir_instruction(ctx, ins);
1170 } else {
1171 DBG("Unknown load\n");
1172 assert(0);
1173 }
1174
1175 break;
1176
1177 case nir_intrinsic_load_output:
1178 assert(nir_src_is_const(instr->src[0]));
1179 reg = nir_dest_index(ctx, &instr->dest);
1180
1181 if (ctx->is_blend) {
1182 /* TODO: MRT */
1183 emit_fb_read_blend_scalar(ctx, reg);
1184 } else {
1185 DBG("Unknown output load\n");
1186 assert(0);
1187 }
1188
1189 break;
1190
1191 case nir_intrinsic_load_blend_const_color_rgba: {
1192 assert(ctx->is_blend);
1193 reg = nir_dest_index(ctx, &instr->dest);
1194
1195 /* Blend constants are embedded directly in the shader and
1196 * patched in, so we use some magic routing */
1197
1198 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1199 ins.has_constants = true;
1200 ins.has_blend_constant = true;
1201 emit_mir_instruction(ctx, ins);
1202 break;
1203 }
1204
1205 case nir_intrinsic_store_output:
1206 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1207
1208 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1209
1210 reg = nir_src_index(ctx, &instr->src[0]);
1211
1212 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1213 /* gl_FragColor is not emitted with load/store
1214 * instructions. Instead, it gets plonked into
1215 * r0 at the end of the shader and we do the
1216 * framebuffer writeout dance. TODO: Defer
1217 * writes */
1218
1219 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1220 emit_mir_instruction(ctx, move);
1221
1222 /* Save the index we're writing to for later reference
1223 * in the epilogue */
1224
1225 ctx->fragment_output = reg;
1226 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1227 /* Varyings are written into one of two special
1228 * varying register, r26 or r27. The register itself is selected as the register
1229 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1230 *
1231 * Normally emitting fmov's is frowned upon,
1232 * but due to unique constraints of
1233 * REGISTER_VARYING, fmov emission + a
1234 * dedicated cleanup pass is the only way to
1235 * guarantee correctness when considering some
1236 * (common) edge cases XXX: FIXME */
1237
1238 /* If this varying corresponds to a constant (why?!),
1239 * emit that now since it won't get picked up by
1240 * hoisting (since there is no corresponding move
1241 * emitted otherwise) */
1242
1243 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, reg + 1);
1244
1245 if (constant_value) {
1246 /* Special case: emit the varying write
1247 * directly to r26 (looks funny in asm but it's
1248 * fine) and emit the store _now_. Possibly
1249 * slightly slower, but this is a really stupid
1250 * special case anyway (why on earth would you
1251 * have a constant varying? Your own fault for
1252 * slightly worse perf :P) */
1253
1254 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(26));
1255 attach_constants(ctx, &ins, constant_value, reg + 1);
1256 emit_mir_instruction(ctx, ins);
1257
1258 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset);
1259 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1260 emit_mir_instruction(ctx, st);
1261 } else {
1262 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1263
1264 _mesa_hash_table_u64_insert(ctx->ssa_varyings, reg + 1, (void *) ((uintptr_t) (offset + 1)));
1265 }
1266 } else {
1267 DBG("Unknown store\n");
1268 assert(0);
1269 }
1270
1271 break;
1272
1273 case nir_intrinsic_load_alpha_ref_float:
1274 assert(instr->dest.is_ssa);
1275
1276 float ref_value = ctx->alpha_ref;
1277
1278 float *v = ralloc_array(NULL, float, 4);
1279 memcpy(v, &ref_value, sizeof(float));
1280 _mesa_hash_table_u64_insert(ctx->ssa_constants, instr->dest.ssa.index + 1, v);
1281 break;
1282
1283 case nir_intrinsic_load_viewport_scale:
1284 case nir_intrinsic_load_viewport_offset:
1285 emit_sysval_read(ctx, instr);
1286 break;
1287
1288 default:
1289 printf ("Unhandled intrinsic\n");
1290 assert(0);
1291 break;
1292 }
1293 }
1294
1295 static unsigned
1296 midgard_tex_format(enum glsl_sampler_dim dim)
1297 {
1298 switch (dim) {
1299 case GLSL_SAMPLER_DIM_2D:
1300 case GLSL_SAMPLER_DIM_EXTERNAL:
1301 return TEXTURE_2D;
1302
1303 case GLSL_SAMPLER_DIM_3D:
1304 return TEXTURE_3D;
1305
1306 case GLSL_SAMPLER_DIM_CUBE:
1307 return TEXTURE_CUBE;
1308
1309 default:
1310 DBG("Unknown sampler dim type\n");
1311 assert(0);
1312 return 0;
1313 }
1314 }
1315
1316 static void
1317 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1318 {
1319 /* TODO */
1320 //assert (!instr->sampler);
1321 //assert (!instr->texture_array_size);
1322 assert (instr->op == nir_texop_tex);
1323
1324 /* Allocate registers via a round robin scheme to alternate between the two registers */
1325 int reg = ctx->texture_op_count & 1;
1326 int in_reg = reg, out_reg = reg;
1327
1328 /* Make room for the reg */
1329
1330 if (ctx->texture_index[reg] > -1)
1331 unalias_ssa(ctx, ctx->texture_index[reg]);
1332
1333 int texture_index = instr->texture_index;
1334 int sampler_index = texture_index;
1335
1336 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1337 switch (instr->src[i].src_type) {
1338 case nir_tex_src_coord: {
1339 int index = nir_src_index(ctx, &instr->src[i].src);
1340
1341 midgard_vector_alu_src alu_src = blank_alu_src;
1342
1343 int reg = SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + in_reg);
1344
1345 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1346 /* For cubemaps, we need to load coords into
1347 * special r27, and then use a special ld/st op
1348 * to copy into the texture register */
1349
1350 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X);
1351
1352 midgard_instruction move = v_fmov(index, alu_src, SSA_FIXED_REGISTER(27));
1353 emit_mir_instruction(ctx, move);
1354
1355 midgard_instruction st = m_st_cubemap_coords(reg, 0);
1356 st.load_store.unknown = 0x24; /* XXX: What is this? */
1357 st.load_store.mask = 0x3; /* xy? */
1358 st.load_store.swizzle = alu_src.swizzle;
1359 emit_mir_instruction(ctx, st);
1360
1361 } else {
1362 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X);
1363
1364 midgard_instruction ins = v_fmov(index, alu_src, reg);
1365 emit_mir_instruction(ctx, ins);
1366 }
1367
1368 break;
1369 }
1370
1371 default: {
1372 DBG("Unknown source type\n");
1373 //assert(0);
1374 break;
1375 }
1376 }
1377 }
1378
1379 /* No helper to build texture words -- we do it all here */
1380 midgard_instruction ins = {
1381 .type = TAG_TEXTURE_4,
1382 .texture = {
1383 .op = TEXTURE_OP_NORMAL,
1384 .format = midgard_tex_format(instr->sampler_dim),
1385 .texture_handle = texture_index,
1386 .sampler_handle = sampler_index,
1387
1388 /* TODO: Don't force xyzw */
1389 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
1390 .mask = 0xF,
1391
1392 /* TODO: half */
1393 //.in_reg_full = 1,
1394 .out_full = 1,
1395
1396 .filter = 1,
1397
1398 /* Always 1 */
1399 .unknown7 = 1,
1400
1401 /* Assume we can continue; hint it out later */
1402 .cont = 1,
1403 }
1404 };
1405
1406 /* Set registers to read and write from the same place */
1407 ins.texture.in_reg_select = in_reg;
1408 ins.texture.out_reg_select = out_reg;
1409
1410 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1411 if (instr->sampler_dim == GLSL_SAMPLER_DIM_3D) {
1412 ins.texture.in_reg_swizzle_right = COMPONENT_X;
1413 ins.texture.in_reg_swizzle_left = COMPONENT_Y;
1414 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1415 } else {
1416 ins.texture.in_reg_swizzle_left = COMPONENT_X;
1417 ins.texture.in_reg_swizzle_right = COMPONENT_Y;
1418 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1419 }
1420
1421 emit_mir_instruction(ctx, ins);
1422
1423 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1424
1425 int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest);
1426 alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg));
1427 ctx->texture_index[reg] = o_index;
1428
1429 midgard_instruction ins2 = v_fmov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index);
1430 emit_mir_instruction(ctx, ins2);
1431
1432 /* Used for .cont and .last hinting */
1433 ctx->texture_op_count++;
1434 }
1435
1436 static void
1437 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1438 {
1439 switch (instr->type) {
1440 case nir_jump_break: {
1441 /* Emit a branch out of the loop */
1442 struct midgard_instruction br = v_branch(false, false);
1443 br.branch.target_type = TARGET_BREAK;
1444 br.branch.target_break = ctx->current_loop_depth;
1445 emit_mir_instruction(ctx, br);
1446
1447 DBG("break..\n");
1448 break;
1449 }
1450
1451 default:
1452 DBG("Unknown jump type %d\n", instr->type);
1453 break;
1454 }
1455 }
1456
1457 static void
1458 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1459 {
1460 switch (instr->type) {
1461 case nir_instr_type_load_const:
1462 emit_load_const(ctx, nir_instr_as_load_const(instr));
1463 break;
1464
1465 case nir_instr_type_intrinsic:
1466 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1467 break;
1468
1469 case nir_instr_type_alu:
1470 emit_alu(ctx, nir_instr_as_alu(instr));
1471 break;
1472
1473 case nir_instr_type_tex:
1474 emit_tex(ctx, nir_instr_as_tex(instr));
1475 break;
1476
1477 case nir_instr_type_jump:
1478 emit_jump(ctx, nir_instr_as_jump(instr));
1479 break;
1480
1481 case nir_instr_type_ssa_undef:
1482 /* Spurious */
1483 break;
1484
1485 default:
1486 DBG("Unhandled instruction type\n");
1487 break;
1488 }
1489 }
1490
1491
1492 /* ALU instructions can inline or embed constants, which decreases register
1493 * pressure and saves space. */
1494
1495 #define CONDITIONAL_ATTACH(src) { \
1496 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1497 \
1498 if (entry) { \
1499 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1500 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1501 } \
1502 }
1503
1504 static void
1505 inline_alu_constants(compiler_context *ctx)
1506 {
1507 mir_foreach_instr(ctx, alu) {
1508 /* Other instructions cannot inline constants */
1509 if (alu->type != TAG_ALU_4) continue;
1510
1511 /* If there is already a constant here, we can do nothing */
1512 if (alu->has_constants) continue;
1513
1514 /* It makes no sense to inline constants on a branch */
1515 if (alu->compact_branch || alu->prepacked_branch) continue;
1516
1517 CONDITIONAL_ATTACH(src0);
1518
1519 if (!alu->has_constants) {
1520 CONDITIONAL_ATTACH(src1)
1521 } else if (!alu->inline_constant) {
1522 /* Corner case: _two_ vec4 constants, for instance with a
1523 * csel. For this case, we can only use a constant
1524 * register for one, we'll have to emit a move for the
1525 * other. Note, if both arguments are constants, then
1526 * necessarily neither argument depends on the value of
1527 * any particular register. As the destination register
1528 * will be wiped, that means we can spill the constant
1529 * to the destination register.
1530 */
1531
1532 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
1533 unsigned scratch = alu->ssa_args.dest;
1534
1535 if (entry) {
1536 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
1537 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
1538
1539 /* Force a break XXX Defer r31 writes */
1540 ins.unit = UNIT_VLUT;
1541
1542 /* Set the source */
1543 alu->ssa_args.src1 = scratch;
1544
1545 /* Inject us -before- the last instruction which set r31 */
1546 mir_insert_instruction_before(mir_prev_op(alu), ins);
1547 }
1548 }
1549 }
1550 }
1551
1552 /* Midgard supports two types of constants, embedded constants (128-bit) and
1553 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1554 * constants can be demoted to inline constants, for space savings and
1555 * sometimes a performance boost */
1556
1557 static void
1558 embedded_to_inline_constant(compiler_context *ctx)
1559 {
1560 mir_foreach_instr(ctx, ins) {
1561 if (!ins->has_constants) continue;
1562
1563 if (ins->ssa_args.inline_constant) continue;
1564
1565 /* Blend constants must not be inlined by definition */
1566 if (ins->has_blend_constant) continue;
1567
1568 /* src1 cannot be an inline constant due to encoding
1569 * restrictions. So, if possible we try to flip the arguments
1570 * in that case */
1571
1572 int op = ins->alu.op;
1573
1574 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1575 switch (op) {
1576 /* These ops require an operational change to flip
1577 * their arguments TODO */
1578 case midgard_alu_op_flt:
1579 case midgard_alu_op_fle:
1580 case midgard_alu_op_ilt:
1581 case midgard_alu_op_ile:
1582 case midgard_alu_op_fcsel:
1583 case midgard_alu_op_icsel:
1584 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
1585 default:
1586 break;
1587 }
1588
1589 if (alu_opcode_props[op].props & OP_COMMUTES) {
1590 /* Flip the SSA numbers */
1591 ins->ssa_args.src0 = ins->ssa_args.src1;
1592 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1593
1594 /* And flip the modifiers */
1595
1596 unsigned src_temp;
1597
1598 src_temp = ins->alu.src2;
1599 ins->alu.src2 = ins->alu.src1;
1600 ins->alu.src1 = src_temp;
1601 }
1602 }
1603
1604 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1605 /* Extract the source information */
1606
1607 midgard_vector_alu_src *src;
1608 int q = ins->alu.src2;
1609 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1610 src = m;
1611
1612 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1613 int component = src->swizzle & 3;
1614
1615 /* Scale constant appropriately, if we can legally */
1616 uint16_t scaled_constant = 0;
1617
1618 if (midgard_is_integer_op(op)) {
1619 unsigned int *iconstants = (unsigned int *) ins->constants;
1620 scaled_constant = (uint16_t) iconstants[component];
1621
1622 /* Constant overflow after resize */
1623 if (scaled_constant != iconstants[component])
1624 continue;
1625 } else {
1626 float original = (float) ins->constants[component];
1627 scaled_constant = _mesa_float_to_half(original);
1628
1629 /* Check for loss of precision. If this is
1630 * mediump, we don't care, but for a highp
1631 * shader, we need to pay attention. NIR
1632 * doesn't yet tell us which mode we're in!
1633 * Practically this prevents most constants
1634 * from being inlined, sadly. */
1635
1636 float fp32 = _mesa_half_to_float(scaled_constant);
1637
1638 if (fp32 != original)
1639 continue;
1640 }
1641
1642 /* We don't know how to handle these with a constant */
1643
1644 if (src->mod || src->half || src->rep_low || src->rep_high) {
1645 DBG("Bailing inline constant...\n");
1646 continue;
1647 }
1648
1649 /* Make sure that the constant is not itself a
1650 * vector by checking if all accessed values
1651 * (by the swizzle) are the same. */
1652
1653 uint32_t *cons = (uint32_t *) ins->constants;
1654 uint32_t value = cons[component];
1655
1656 bool is_vector = false;
1657 unsigned mask = effective_writemask(&ins->alu);
1658
1659 for (int c = 1; c < 4; ++c) {
1660 /* We only care if this component is actually used */
1661 if (!(mask & (1 << c)))
1662 continue;
1663
1664 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
1665
1666 if (test != value) {
1667 is_vector = true;
1668 break;
1669 }
1670 }
1671
1672 if (is_vector)
1673 continue;
1674
1675 /* Get rid of the embedded constant */
1676 ins->has_constants = false;
1677 ins->ssa_args.src1 = SSA_UNUSED_0;
1678 ins->ssa_args.inline_constant = true;
1679 ins->inline_constant = scaled_constant;
1680 }
1681 }
1682 }
1683
1684 /* Map normal SSA sources to other SSA sources / fixed registers (like
1685 * uniforms) */
1686
1687 static void
1688 map_ssa_to_alias(compiler_context *ctx, int *ref)
1689 {
1690 unsigned int alias = (uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_to_alias, *ref + 1);
1691
1692 if (alias) {
1693 /* Remove entry in leftovers to avoid a redunant fmov */
1694
1695 struct set_entry *leftover = _mesa_set_search(ctx->leftover_ssa_to_alias, ((void *) (uintptr_t) (*ref + 1)));
1696
1697 if (leftover)
1698 _mesa_set_remove(ctx->leftover_ssa_to_alias, leftover);
1699
1700 /* Assign the alias map */
1701 *ref = alias - 1;
1702 return;
1703 }
1704 }
1705
1706 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1707 * texture pipeline */
1708
1709 static bool
1710 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
1711 {
1712 bool progress = false;
1713
1714 mir_foreach_instr_in_block_safe(block, ins) {
1715 if (ins->type != TAG_ALU_4) continue;
1716 if (ins->compact_branch) continue;
1717
1718 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
1719 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
1720
1721 mir_remove_instruction(ins);
1722 progress = true;
1723 }
1724
1725 return progress;
1726 }
1727
1728 static bool
1729 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
1730 {
1731 /* abs or neg */
1732 if (!is_int && src.mod) return true;
1733
1734 /* swizzle */
1735 for (unsigned c = 0; c < 4; ++c) {
1736 if (!(mask & (1 << c))) continue;
1737 if (((src.swizzle >> (2*c)) & 3) != c) return true;
1738 }
1739
1740 return false;
1741 }
1742
1743 static bool
1744 mir_nontrivial_source2_mod(midgard_instruction *ins)
1745 {
1746 unsigned mask = squeeze_writemask(ins->alu.mask);
1747 bool is_int = midgard_is_integer_op(ins->alu.op);
1748
1749 midgard_vector_alu_src src2 =
1750 vector_alu_from_unsigned(ins->alu.src2);
1751
1752 return mir_nontrivial_mod(src2, is_int, mask);
1753 }
1754
1755 static bool
1756 midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
1757 {
1758 bool progress = false;
1759
1760 mir_foreach_instr_in_block_safe(block, ins) {
1761 if (ins->type != TAG_ALU_4) continue;
1762 if (!OP_IS_MOVE(ins->alu.op)) continue;
1763
1764 unsigned from = ins->ssa_args.src1;
1765 unsigned to = ins->ssa_args.dest;
1766
1767 /* We only work on pure SSA */
1768
1769 if (to >= SSA_FIXED_MINIMUM) continue;
1770 if (from >= SSA_FIXED_MINIMUM) continue;
1771 if (to >= ctx->func->impl->ssa_alloc) continue;
1772 if (from >= ctx->func->impl->ssa_alloc) continue;
1773
1774 /* Constant propagation is not handled here, either */
1775 if (ins->ssa_args.inline_constant) continue;
1776 if (ins->has_constants) continue;
1777
1778 if (mir_nontrivial_source2_mod(ins)) continue;
1779 if (ins->alu.outmod != midgard_outmod_none) continue;
1780
1781 /* We're clear -- rewrite */
1782 mir_rewrite_index_src(ctx, to, from);
1783 mir_remove_instruction(ins);
1784 progress |= true;
1785 }
1786
1787 return progress;
1788 }
1789
1790 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1791 * the move can be propagated away entirely */
1792
1793 static bool
1794 mir_compose_outmod(midgard_outmod *outmod, midgard_outmod comp)
1795 {
1796 /* Nothing to do */
1797 if (comp == midgard_outmod_none)
1798 return true;
1799
1800 if (*outmod == midgard_outmod_none) {
1801 *outmod = comp;
1802 return true;
1803 }
1804
1805 /* TODO: Compose rules */
1806 return false;
1807 }
1808
1809 static bool
1810 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
1811 {
1812 bool progress = false;
1813
1814 mir_foreach_instr_in_block_safe(block, ins) {
1815 if (ins->type != TAG_ALU_4) continue;
1816 if (ins->alu.op != midgard_alu_op_fmov) continue;
1817 if (ins->alu.outmod != midgard_outmod_pos) continue;
1818
1819 /* TODO: Registers? */
1820 unsigned src = ins->ssa_args.src1;
1821 if (src >= ctx->func->impl->ssa_alloc) continue;
1822
1823 /* There might be a source modifier, too */
1824 if (mir_nontrivial_source2_mod(ins)) continue;
1825
1826 /* Backpropagate the modifier */
1827 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1828 if (v->type != TAG_ALU_4) continue;
1829 if (v->ssa_args.dest != src) continue;
1830
1831 midgard_outmod temp = v->alu.outmod;
1832 progress |= mir_compose_outmod(&temp, ins->alu.outmod);
1833
1834 /* Throw in the towel.. */
1835 if (!progress) break;
1836
1837 /* Otherwise, transfer the modifier */
1838 v->alu.outmod = temp;
1839 ins->alu.outmod = midgard_outmod_none;
1840
1841 break;
1842 }
1843 }
1844
1845 return progress;
1846 }
1847
1848 static bool
1849 midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
1850 {
1851 bool progress = false;
1852
1853 mir_foreach_instr_in_block_safe(block, ins) {
1854 if (ins->type != TAG_ALU_4) continue;
1855 if (!OP_IS_MOVE(ins->alu.op)) continue;
1856
1857 unsigned from = ins->ssa_args.src1;
1858 unsigned to = ins->ssa_args.dest;
1859
1860 /* Make sure it's simple enough for us to handle */
1861
1862 if (from >= SSA_FIXED_MINIMUM) continue;
1863 if (from >= ctx->func->impl->ssa_alloc) continue;
1864 if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
1865 if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
1866
1867 bool eliminated = false;
1868
1869 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1870 /* The texture registers are not SSA so be careful.
1871 * Conservatively, just stop if we hit a texture op
1872 * (even if it may not write) to where we are */
1873
1874 if (v->type != TAG_ALU_4)
1875 break;
1876
1877 if (v->ssa_args.dest == from) {
1878 /* We don't want to track partial writes ... */
1879 if (v->alu.mask == 0xF) {
1880 v->ssa_args.dest = to;
1881 eliminated = true;
1882 }
1883
1884 break;
1885 }
1886 }
1887
1888 if (eliminated)
1889 mir_remove_instruction(ins);
1890
1891 progress |= eliminated;
1892 }
1893
1894 return progress;
1895 }
1896
1897 /* The following passes reorder MIR instructions to enable better scheduling */
1898
1899 static void
1900 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
1901 {
1902 mir_foreach_instr_in_block_safe(block, ins) {
1903 if (ins->type != TAG_LOAD_STORE_4) continue;
1904
1905 /* We've found a load/store op. Check if next is also load/store. */
1906 midgard_instruction *next_op = mir_next_op(ins);
1907 if (&next_op->link != &block->instructions) {
1908 if (next_op->type == TAG_LOAD_STORE_4) {
1909 /* If so, we're done since we're a pair */
1910 ins = mir_next_op(ins);
1911 continue;
1912 }
1913
1914 /* Maximum search distance to pair, to avoid register pressure disasters */
1915 int search_distance = 8;
1916
1917 /* Otherwise, we have an orphaned load/store -- search for another load */
1918 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
1919 /* Terminate search if necessary */
1920 if (!(search_distance--)) break;
1921
1922 if (c->type != TAG_LOAD_STORE_4) continue;
1923
1924 /* Stores cannot be reordered, since they have
1925 * dependencies. For the same reason, indirect
1926 * loads cannot be reordered as their index is
1927 * loaded in r27.w */
1928
1929 if (OP_IS_STORE(c->load_store.op)) continue;
1930
1931 /* It appears the 0x800 bit is set whenever a
1932 * load is direct, unset when it is indirect.
1933 * Skip indirect loads. */
1934
1935 if (!(c->load_store.unknown & 0x800)) continue;
1936
1937 /* We found one! Move it up to pair and remove it from the old location */
1938
1939 mir_insert_instruction_before(ins, *c);
1940 mir_remove_instruction(c);
1941
1942 break;
1943 }
1944 }
1945 }
1946 }
1947
1948 /* Emit varying stores late */
1949
1950 static void
1951 midgard_emit_store(compiler_context *ctx, midgard_block *block) {
1952 /* Iterate in reverse to get the final write, rather than the first */
1953
1954 mir_foreach_instr_in_block_safe_rev(block, ins) {
1955 /* Check if what we just wrote needs a store */
1956 int idx = ins->ssa_args.dest;
1957 uintptr_t varying = ((uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_varyings, idx + 1));
1958
1959 if (!varying) continue;
1960
1961 varying -= 1;
1962
1963 /* We need to store to the appropriate varying, so emit the
1964 * move/store */
1965
1966 /* TODO: Integrate with special purpose RA (and scheduler?) */
1967 bool high_varying_register = false;
1968
1969 midgard_instruction mov = v_fmov(idx, blank_alu_src, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE + high_varying_register));
1970
1971 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(high_varying_register), varying);
1972 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1973
1974 mir_insert_instruction_before(mir_next_op(ins), st);
1975 mir_insert_instruction_before(mir_next_op(ins), mov);
1976
1977 /* We no longer need to store this varying */
1978 _mesa_hash_table_u64_remove(ctx->ssa_varyings, idx + 1);
1979 }
1980 }
1981
1982 /* If there are leftovers after the below pass, emit actual fmov
1983 * instructions for the slow-but-correct path */
1984
1985 static void
1986 emit_leftover_move(compiler_context *ctx)
1987 {
1988 set_foreach(ctx->leftover_ssa_to_alias, leftover) {
1989 int base = ((uintptr_t) leftover->key) - 1;
1990 int mapped = base;
1991
1992 map_ssa_to_alias(ctx, &mapped);
1993 EMIT(fmov, mapped, blank_alu_src, base);
1994 }
1995 }
1996
1997 static void
1998 actualise_ssa_to_alias(compiler_context *ctx)
1999 {
2000 mir_foreach_instr(ctx, ins) {
2001 map_ssa_to_alias(ctx, &ins->ssa_args.src0);
2002 map_ssa_to_alias(ctx, &ins->ssa_args.src1);
2003 }
2004
2005 emit_leftover_move(ctx);
2006 }
2007
2008 static void
2009 emit_fragment_epilogue(compiler_context *ctx)
2010 {
2011 /* Special case: writing out constants requires us to include the move
2012 * explicitly now, so shove it into r0 */
2013
2014 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, ctx->fragment_output + 1);
2015
2016 if (constant_value) {
2017 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(0));
2018 attach_constants(ctx, &ins, constant_value, ctx->fragment_output + 1);
2019 emit_mir_instruction(ctx, ins);
2020 }
2021
2022 /* Perform the actual fragment writeout. We have two writeout/branch
2023 * instructions, forming a loop until writeout is successful as per the
2024 * docs. TODO: gl_FragDepth */
2025
2026 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2027 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2028 }
2029
2030 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2031 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2032 * with the int8 analogue to the fragment epilogue */
2033
2034 static void
2035 emit_blend_epilogue(compiler_context *ctx)
2036 {
2037 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2038
2039 midgard_instruction scale = {
2040 .type = TAG_ALU_4,
2041 .unit = UNIT_VMUL,
2042 .inline_constant = _mesa_float_to_half(255.0),
2043 .ssa_args = {
2044 .src0 = SSA_FIXED_REGISTER(0),
2045 .src1 = SSA_UNUSED_0,
2046 .dest = SSA_FIXED_REGISTER(24),
2047 .inline_constant = true
2048 },
2049 .alu = {
2050 .op = midgard_alu_op_fmul,
2051 .reg_mode = midgard_reg_mode_32,
2052 .dest_override = midgard_dest_override_lower,
2053 .mask = 0xFF,
2054 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2055 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2056 }
2057 };
2058
2059 emit_mir_instruction(ctx, scale);
2060
2061 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2062
2063 midgard_vector_alu_src alu_src = blank_alu_src;
2064 alu_src.half = true;
2065
2066 midgard_instruction f2u8 = {
2067 .type = TAG_ALU_4,
2068 .ssa_args = {
2069 .src0 = SSA_FIXED_REGISTER(24),
2070 .src1 = SSA_UNUSED_0,
2071 .dest = SSA_FIXED_REGISTER(0),
2072 .inline_constant = true
2073 },
2074 .alu = {
2075 .op = midgard_alu_op_f2u8,
2076 .reg_mode = midgard_reg_mode_16,
2077 .dest_override = midgard_dest_override_lower,
2078 .outmod = midgard_outmod_pos,
2079 .mask = 0xF,
2080 .src1 = vector_alu_srco_unsigned(alu_src),
2081 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2082 }
2083 };
2084
2085 emit_mir_instruction(ctx, f2u8);
2086
2087 /* vmul.imov.quarter r0, r0, r0 */
2088
2089 midgard_instruction imov_8 = {
2090 .type = TAG_ALU_4,
2091 .ssa_args = {
2092 .src0 = SSA_UNUSED_1,
2093 .src1 = SSA_FIXED_REGISTER(0),
2094 .dest = SSA_FIXED_REGISTER(0),
2095 },
2096 .alu = {
2097 .op = midgard_alu_op_imov,
2098 .reg_mode = midgard_reg_mode_8,
2099 .dest_override = midgard_dest_override_none,
2100 .outmod = midgard_outmod_int,
2101 .mask = 0xFF,
2102 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2103 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2104 }
2105 };
2106
2107 /* Emit branch epilogue with the 8-bit move as the source */
2108
2109 emit_mir_instruction(ctx, imov_8);
2110 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2111
2112 emit_mir_instruction(ctx, imov_8);
2113 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2114 }
2115
2116 static midgard_block *
2117 emit_block(compiler_context *ctx, nir_block *block)
2118 {
2119 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2120 list_addtail(&this_block->link, &ctx->blocks);
2121
2122 this_block->is_scheduled = false;
2123 ++ctx->block_count;
2124
2125 ctx->texture_index[0] = -1;
2126 ctx->texture_index[1] = -1;
2127
2128 /* Add us as a successor to the block we are following */
2129 if (ctx->current_block)
2130 midgard_block_add_successor(ctx->current_block, this_block);
2131
2132 /* Set up current block */
2133 list_inithead(&this_block->instructions);
2134 ctx->current_block = this_block;
2135
2136 nir_foreach_instr(instr, block) {
2137 emit_instr(ctx, instr);
2138 ++ctx->instruction_count;
2139 }
2140
2141 inline_alu_constants(ctx);
2142 embedded_to_inline_constant(ctx);
2143
2144 /* Perform heavylifting for aliasing */
2145 actualise_ssa_to_alias(ctx);
2146
2147 midgard_emit_store(ctx, this_block);
2148 midgard_pair_load_store(ctx, this_block);
2149
2150 /* Append fragment shader epilogue (value writeout) */
2151 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2152 if (block == nir_impl_last_block(ctx->func->impl)) {
2153 if (ctx->is_blend)
2154 emit_blend_epilogue(ctx);
2155 else
2156 emit_fragment_epilogue(ctx);
2157 }
2158 }
2159
2160 if (block == nir_start_block(ctx->func->impl))
2161 ctx->initial_block = this_block;
2162
2163 if (block == nir_impl_last_block(ctx->func->impl))
2164 ctx->final_block = this_block;
2165
2166 /* Allow the next control flow to access us retroactively, for
2167 * branching etc */
2168 ctx->current_block = this_block;
2169
2170 /* Document the fallthrough chain */
2171 ctx->previous_source_block = this_block;
2172
2173 return this_block;
2174 }
2175
2176 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2177
2178 static void
2179 emit_if(struct compiler_context *ctx, nir_if *nif)
2180 {
2181 /* Conditional branches expect the condition in r31.w; emit a move for
2182 * that in the _previous_ block (which is the current block). */
2183 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2184
2185 /* Speculatively emit the branch, but we can't fill it in until later */
2186 EMIT(branch, true, true);
2187 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2188
2189 /* Emit the two subblocks */
2190 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2191
2192 /* Emit a jump from the end of the then block to the end of the else */
2193 EMIT(branch, false, false);
2194 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2195
2196 /* Emit second block, and check if it's empty */
2197
2198 int else_idx = ctx->block_count;
2199 int count_in = ctx->instruction_count;
2200 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2201 int after_else_idx = ctx->block_count;
2202
2203 /* Now that we have the subblocks emitted, fix up the branches */
2204
2205 assert(then_block);
2206 assert(else_block);
2207
2208 if (ctx->instruction_count == count_in) {
2209 /* The else block is empty, so don't emit an exit jump */
2210 mir_remove_instruction(then_exit);
2211 then_branch->branch.target_block = after_else_idx;
2212 } else {
2213 then_branch->branch.target_block = else_idx;
2214 then_exit->branch.target_block = after_else_idx;
2215 }
2216 }
2217
2218 static void
2219 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2220 {
2221 /* Remember where we are */
2222 midgard_block *start_block = ctx->current_block;
2223
2224 /* Allocate a loop number, growing the current inner loop depth */
2225 int loop_idx = ++ctx->current_loop_depth;
2226
2227 /* Get index from before the body so we can loop back later */
2228 int start_idx = ctx->block_count;
2229
2230 /* Emit the body itself */
2231 emit_cf_list(ctx, &nloop->body);
2232
2233 /* Branch back to loop back */
2234 struct midgard_instruction br_back = v_branch(false, false);
2235 br_back.branch.target_block = start_idx;
2236 emit_mir_instruction(ctx, br_back);
2237
2238 /* Mark down that branch in the graph. Note that we're really branching
2239 * to the block *after* we started in. TODO: Why doesn't the branch
2240 * itself have an off-by-one then...? */
2241 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2242
2243 /* Find the index of the block about to follow us (note: we don't add
2244 * one; blocks are 0-indexed so we get a fencepost problem) */
2245 int break_block_idx = ctx->block_count;
2246
2247 /* Fix up the break statements we emitted to point to the right place,
2248 * now that we can allocate a block number for them */
2249
2250 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2251 mir_foreach_instr_in_block(block, ins) {
2252 if (ins->type != TAG_ALU_4) continue;
2253 if (!ins->compact_branch) continue;
2254 if (ins->prepacked_branch) continue;
2255
2256 /* We found a branch -- check the type to see if we need to do anything */
2257 if (ins->branch.target_type != TARGET_BREAK) continue;
2258
2259 /* It's a break! Check if it's our break */
2260 if (ins->branch.target_break != loop_idx) continue;
2261
2262 /* Okay, cool, we're breaking out of this loop.
2263 * Rewrite from a break to a goto */
2264
2265 ins->branch.target_type = TARGET_GOTO;
2266 ins->branch.target_block = break_block_idx;
2267 }
2268 }
2269
2270 /* Now that we've finished emitting the loop, free up the depth again
2271 * so we play nice with recursion amid nested loops */
2272 --ctx->current_loop_depth;
2273 }
2274
2275 static midgard_block *
2276 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2277 {
2278 midgard_block *start_block = NULL;
2279
2280 foreach_list_typed(nir_cf_node, node, node, list) {
2281 switch (node->type) {
2282 case nir_cf_node_block: {
2283 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2284
2285 if (!start_block)
2286 start_block = block;
2287
2288 break;
2289 }
2290
2291 case nir_cf_node_if:
2292 emit_if(ctx, nir_cf_node_as_if(node));
2293 break;
2294
2295 case nir_cf_node_loop:
2296 emit_loop(ctx, nir_cf_node_as_loop(node));
2297 break;
2298
2299 case nir_cf_node_function:
2300 assert(0);
2301 break;
2302 }
2303 }
2304
2305 return start_block;
2306 }
2307
2308 /* Due to lookahead, we need to report the first tag executed in the command
2309 * stream and in branch targets. An initial block might be empty, so iterate
2310 * until we find one that 'works' */
2311
2312 static unsigned
2313 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2314 {
2315 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2316
2317 unsigned first_tag = 0;
2318
2319 do {
2320 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
2321
2322 if (initial_bundle) {
2323 first_tag = initial_bundle->tag;
2324 break;
2325 }
2326
2327 /* Initial block is empty, try the next block */
2328 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
2329 } while(initial_block != NULL);
2330
2331 assert(first_tag);
2332 return first_tag;
2333 }
2334
2335 int
2336 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend)
2337 {
2338 struct util_dynarray *compiled = &program->compiled;
2339
2340 midgard_debug = debug_get_option_midgard_debug();
2341
2342 compiler_context ictx = {
2343 .nir = nir,
2344 .stage = nir->info.stage,
2345
2346 .is_blend = is_blend,
2347 .blend_constant_offset = -1,
2348
2349 .alpha_ref = program->alpha_ref
2350 };
2351
2352 compiler_context *ctx = &ictx;
2353
2354 /* TODO: Decide this at runtime */
2355 ctx->uniform_cutoff = 8;
2356
2357 /* Assign var locations early, so the epilogue can use them if necessary */
2358
2359 nir_assign_var_locations(&nir->outputs, &nir->num_outputs, glsl_type_size);
2360 nir_assign_var_locations(&nir->inputs, &nir->num_inputs, glsl_type_size);
2361 nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms, glsl_type_size);
2362
2363 /* Initialize at a global (not block) level hash tables */
2364
2365 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2366 ctx->ssa_varyings = _mesa_hash_table_u64_create(NULL);
2367 ctx->ssa_to_alias = _mesa_hash_table_u64_create(NULL);
2368 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2369 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2370 ctx->leftover_ssa_to_alias = _mesa_set_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
2371
2372 /* Record the varying mapping for the command stream's bookkeeping */
2373
2374 struct exec_list *varyings =
2375 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2376
2377 nir_foreach_variable(var, varyings) {
2378 unsigned loc = var->data.driver_location;
2379 unsigned sz = glsl_type_size(var->type, FALSE);
2380
2381 for (int c = 0; c < sz; ++c) {
2382 program->varyings[loc + c] = var->data.location;
2383 }
2384 }
2385
2386 /* Lower gl_Position pre-optimisation */
2387
2388 if (ctx->stage == MESA_SHADER_VERTEX)
2389 NIR_PASS_V(nir, nir_lower_viewport_transform);
2390
2391 NIR_PASS_V(nir, nir_lower_var_copies);
2392 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2393 NIR_PASS_V(nir, nir_split_var_copies);
2394 NIR_PASS_V(nir, nir_lower_var_copies);
2395 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2396 NIR_PASS_V(nir, nir_lower_var_copies);
2397 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2398
2399 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2400
2401 /* Optimisation passes */
2402
2403 optimise_nir(nir);
2404
2405 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2406 nir_print_shader(nir, stdout);
2407 }
2408
2409 /* Assign sysvals and counts, now that we're sure
2410 * (post-optimisation) */
2411
2412 midgard_nir_assign_sysvals(ctx, nir);
2413
2414 program->uniform_count = nir->num_uniforms;
2415 program->sysval_count = ctx->sysval_count;
2416 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2417
2418 program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_inputs : 0;
2419 program->varying_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_outputs : ((ctx->stage == MESA_SHADER_FRAGMENT) ? nir->num_inputs : 0);
2420
2421 nir_foreach_function(func, nir) {
2422 if (!func->impl)
2423 continue;
2424
2425 list_inithead(&ctx->blocks);
2426 ctx->block_count = 0;
2427 ctx->func = func;
2428
2429 emit_cf_list(ctx, &func->impl->body);
2430 emit_block(ctx, func->impl->end_block);
2431
2432 break; /* TODO: Multi-function shaders */
2433 }
2434
2435 util_dynarray_init(compiled, NULL);
2436
2437 /* MIR-level optimizations */
2438
2439 bool progress = false;
2440
2441 do {
2442 progress = false;
2443
2444 mir_foreach_block(ctx, block) {
2445 progress |= midgard_opt_pos_propagate(ctx, block);
2446 progress |= midgard_opt_copy_prop(ctx, block);
2447 progress |= midgard_opt_copy_prop_tex(ctx, block);
2448 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2449 }
2450 } while (progress);
2451
2452 /* Schedule! */
2453 schedule_program(ctx);
2454
2455 /* Now that all the bundles are scheduled and we can calculate block
2456 * sizes, emit actual branch instructions rather than placeholders */
2457
2458 int br_block_idx = 0;
2459
2460 mir_foreach_block(ctx, block) {
2461 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2462 for (int c = 0; c < bundle->instruction_count; ++c) {
2463 midgard_instruction *ins = bundle->instructions[c];
2464
2465 if (!midgard_is_branch_unit(ins->unit)) continue;
2466
2467 if (ins->prepacked_branch) continue;
2468
2469 /* Parse some basic branch info */
2470 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2471 bool is_conditional = ins->branch.conditional;
2472 bool is_inverted = ins->branch.invert_conditional;
2473 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2474
2475 /* Determine the block we're jumping to */
2476 int target_number = ins->branch.target_block;
2477
2478 /* Report the destination tag */
2479 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2480
2481 /* Count up the number of quadwords we're
2482 * jumping over = number of quadwords until
2483 * (br_block_idx, target_number) */
2484
2485 int quadword_offset = 0;
2486
2487 if (is_discard) {
2488 /* Jump to the end of the shader. We
2489 * need to include not only the
2490 * following blocks, but also the
2491 * contents of our current block (since
2492 * discard can come in the middle of
2493 * the block) */
2494
2495 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
2496
2497 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
2498 quadword_offset += quadword_size(bun->tag);
2499 }
2500
2501 mir_foreach_block_from(ctx, blk, b) {
2502 quadword_offset += b->quadword_count;
2503 }
2504
2505 } else if (target_number > br_block_idx) {
2506 /* Jump forward */
2507
2508 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2509 midgard_block *blk = mir_get_block(ctx, idx);
2510 assert(blk);
2511
2512 quadword_offset += blk->quadword_count;
2513 }
2514 } else {
2515 /* Jump backwards */
2516
2517 for (int idx = br_block_idx; idx >= target_number; --idx) {
2518 midgard_block *blk = mir_get_block(ctx, idx);
2519 assert(blk);
2520
2521 quadword_offset -= blk->quadword_count;
2522 }
2523 }
2524
2525 /* Unconditional extended branches (far jumps)
2526 * have issues, so we always use a conditional
2527 * branch, setting the condition to always for
2528 * unconditional. For compact unconditional
2529 * branches, cond isn't used so it doesn't
2530 * matter what we pick. */
2531
2532 midgard_condition cond =
2533 !is_conditional ? midgard_condition_always :
2534 is_inverted ? midgard_condition_false :
2535 midgard_condition_true;
2536
2537 midgard_jmp_writeout_op op =
2538 is_discard ? midgard_jmp_writeout_op_discard :
2539 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2540 midgard_jmp_writeout_op_branch_cond;
2541
2542 if (!is_compact) {
2543 midgard_branch_extended branch =
2544 midgard_create_branch_extended(
2545 cond, op,
2546 dest_tag,
2547 quadword_offset);
2548
2549 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2550 } else if (is_conditional || is_discard) {
2551 midgard_branch_cond branch = {
2552 .op = op,
2553 .dest_tag = dest_tag,
2554 .offset = quadword_offset,
2555 .cond = cond
2556 };
2557
2558 assert(branch.offset == quadword_offset);
2559
2560 memcpy(&ins->br_compact, &branch, sizeof(branch));
2561 } else {
2562 assert(op == midgard_jmp_writeout_op_branch_uncond);
2563
2564 midgard_branch_uncond branch = {
2565 .op = op,
2566 .dest_tag = dest_tag,
2567 .offset = quadword_offset,
2568 .unknown = 1
2569 };
2570
2571 assert(branch.offset == quadword_offset);
2572
2573 memcpy(&ins->br_compact, &branch, sizeof(branch));
2574 }
2575 }
2576 }
2577
2578 ++br_block_idx;
2579 }
2580
2581 /* Emit flat binary from the instruction arrays. Iterate each block in
2582 * sequence. Save instruction boundaries such that lookahead tags can
2583 * be assigned easily */
2584
2585 /* Cache _all_ bundles in source order for lookahead across failed branches */
2586
2587 int bundle_count = 0;
2588 mir_foreach_block(ctx, block) {
2589 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2590 }
2591 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2592 int bundle_idx = 0;
2593 mir_foreach_block(ctx, block) {
2594 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2595 source_order_bundles[bundle_idx++] = bundle;
2596 }
2597 }
2598
2599 int current_bundle = 0;
2600
2601 /* Midgard prefetches instruction types, so during emission we
2602 * need to lookahead. Unless this is the last instruction, in
2603 * which we return 1. Or if this is the second to last and the
2604 * last is an ALU, then it's also 1... */
2605
2606 mir_foreach_block(ctx, block) {
2607 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2608 int lookahead = 1;
2609
2610 if (current_bundle + 1 < bundle_count) {
2611 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2612
2613 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2614 lookahead = 1;
2615 } else {
2616 lookahead = next;
2617 }
2618 }
2619
2620 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2621 ++current_bundle;
2622 }
2623
2624 /* TODO: Free deeper */
2625 //util_dynarray_fini(&block->instructions);
2626 }
2627
2628 free(source_order_bundles);
2629
2630 /* Report the very first tag executed */
2631 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2632
2633 /* Deal with off-by-one related to the fencepost problem */
2634 program->work_register_count = ctx->work_registers + 1;
2635
2636 program->can_discard = ctx->can_discard;
2637 program->uniform_cutoff = ctx->uniform_cutoff;
2638
2639 program->blend_patch_offset = ctx->blend_constant_offset;
2640
2641 if (midgard_debug & MIDGARD_DBG_SHADERS)
2642 disassemble_midgard(program->compiled.data, program->compiled.size);
2643
2644 return 0;
2645 }