2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
51 #include "disassemble.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
61 int midgard_debug
= 0;
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
69 midgard_is_branch_unit(unsigned unit
)
71 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
75 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
77 block
->successors
[block
->nr_successors
++] = successor
;
78 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
86 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
87 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
88 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
89 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
90 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
92 static inline unsigned
93 swizzle_of(unsigned comp
)
105 unreachable("Invalid component count");
109 static inline unsigned
110 mask_of(unsigned nr_comp
)
112 return (1 << nr_comp
) - 1;
115 #define M_LOAD_STORE(name, rname, uname) \
116 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
117 midgard_instruction i = { \
118 .type = TAG_LOAD_STORE_4, \
125 .op = midgard_op_##name, \
127 .swizzle = SWIZZLE_XYZW, \
135 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
136 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
138 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
139 * the corresponding Midgard source */
141 static midgard_vector_alu_src
142 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
144 if (!src
) return blank_alu_src
;
146 midgard_vector_alu_src alu_src
= {
149 .half
= 0, /* TODO */
150 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
154 /* TODO: sign-extend/zero-extend */
155 alu_src
.mod
= midgard_int_normal
;
157 /* These should have been lowered away */
158 assert(!(src
->abs
|| src
->negate
));
160 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
166 /* load/store instructions have both 32-bit and 16-bit variants, depending on
167 * whether we are using vectors composed of highp or mediump. At the moment, we
168 * don't support half-floats -- this requires changes in other parts of the
169 * compiler -- therefore the 16-bit versions are commented out. */
171 //M_LOAD(ld_attr_16);
173 //M_LOAD(ld_vary_16);
175 //M_LOAD(ld_uniform_16);
176 M_LOAD(ld_uniform_32
);
177 M_LOAD(ld_color_buffer_8
);
178 //M_STORE(st_vary_16);
180 M_STORE(st_cubemap_coords
);
182 static midgard_instruction
183 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
185 midgard_branch_cond branch
= {
193 memcpy(&compact
, &branch
, sizeof(branch
));
195 midgard_instruction ins
= {
197 .unit
= ALU_ENAB_BR_COMPACT
,
198 .prepacked_branch
= true,
199 .compact_branch
= true,
200 .br_compact
= compact
203 if (op
== midgard_jmp_writeout_op_writeout
)
209 static midgard_instruction
210 v_branch(bool conditional
, bool invert
)
212 midgard_instruction ins
= {
214 .unit
= ALU_ENAB_BRANCH
,
215 .compact_branch
= true,
217 .conditional
= conditional
,
218 .invert_conditional
= invert
225 static midgard_branch_extended
226 midgard_create_branch_extended( midgard_condition cond
,
227 midgard_jmp_writeout_op op
,
229 signed quadword_offset
)
231 /* For unclear reasons, the condition code is repeated 8 times */
232 uint16_t duplicated_cond
=
242 midgard_branch_extended branch
= {
244 .dest_tag
= dest_tag
,
245 .offset
= quadword_offset
,
246 .cond
= duplicated_cond
253 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
255 ins
->has_constants
= true;
256 memcpy(&ins
->constants
, constants
, 16);
260 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
262 return glsl_count_attribute_slots(type
, false);
265 /* Lower fdot2 to a vector multiplication followed by channel addition */
267 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
269 if (alu
->op
!= nir_op_fdot2
)
272 b
->cursor
= nir_before_instr(&alu
->instr
);
274 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
275 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
277 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
279 nir_ssa_def
*sum
= nir_fadd(b
,
280 nir_channel(b
, product
, 0),
281 nir_channel(b
, product
, 1));
283 /* Replace the fdot2 with this sum */
284 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
288 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
290 switch (instr
->intrinsic
) {
291 case nir_intrinsic_load_viewport_scale
:
292 return PAN_SYSVAL_VIEWPORT_SCALE
;
293 case nir_intrinsic_load_viewport_offset
:
294 return PAN_SYSVAL_VIEWPORT_OFFSET
;
301 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
304 return dst
->ssa
.index
;
306 assert(!dst
->reg
.indirect
);
307 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
311 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
314 nir_intrinsic_instr
*intr
;
315 nir_dest
*dst
= NULL
;
319 switch (instr
->type
) {
320 case nir_instr_type_intrinsic
:
321 intr
= nir_instr_as_intrinsic(instr
);
322 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
325 case nir_instr_type_tex
:
326 tex
= nir_instr_as_tex(instr
);
327 if (tex
->op
!= nir_texop_txs
)
330 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
331 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
332 nir_tex_instr_dest_size(tex
) -
333 (tex
->is_array
? 1 : 0),
342 *dest
= nir_dest_index(ctx
, dst
);
348 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
352 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
356 /* We have a sysval load; check if it's already been assigned */
358 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
361 /* It hasn't -- so assign it now! */
363 unsigned id
= ctx
->sysval_count
++;
364 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
365 ctx
->sysvals
[id
] = sysval
;
369 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
371 ctx
->sysval_count
= 0;
373 nir_foreach_function(function
, shader
) {
374 if (!function
->impl
) continue;
376 nir_foreach_block(block
, function
->impl
) {
377 nir_foreach_instr_safe(instr
, block
) {
378 midgard_nir_assign_sysval_body(ctx
, instr
);
385 midgard_nir_lower_fdot2(nir_shader
*shader
)
387 bool progress
= false;
389 nir_foreach_function(function
, shader
) {
390 if (!function
->impl
) continue;
393 nir_builder
*b
= &_b
;
394 nir_builder_init(b
, function
->impl
);
396 nir_foreach_block(block
, function
->impl
) {
397 nir_foreach_instr_safe(instr
, block
) {
398 if (instr
->type
!= nir_instr_type_alu
) continue;
400 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
401 midgard_nir_lower_fdot2_body(b
, alu
);
407 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
415 optimise_nir(nir_shader
*nir
)
418 unsigned lower_flrp
=
419 (nir
->options
->lower_flrp16
? 16 : 0) |
420 (nir
->options
->lower_flrp32
? 32 : 0) |
421 (nir
->options
->lower_flrp64
? 64 : 0);
423 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
424 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
425 NIR_PASS(progress
, nir
, nir_lower_idiv
);
427 nir_lower_tex_options lower_tex_1st_pass_options
= {
432 nir_lower_tex_options lower_tex_2nd_pass_options
= {
433 .lower_txs_lod
= true,
436 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
437 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
442 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
443 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
445 NIR_PASS(progress
, nir
, nir_copy_prop
);
446 NIR_PASS(progress
, nir
, nir_opt_dce
);
447 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
448 NIR_PASS(progress
, nir
, nir_opt_cse
);
449 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
450 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
451 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
453 if (lower_flrp
!= 0) {
454 bool lower_flrp_progress
= false;
455 NIR_PASS(lower_flrp_progress
,
459 false /* always_precise */,
460 nir
->options
->lower_ffma
);
461 if (lower_flrp_progress
) {
462 NIR_PASS(progress
, nir
,
463 nir_opt_constant_folding
);
467 /* Nothing should rematerialize any flrps, so we only
468 * need to do this lowering once.
473 NIR_PASS(progress
, nir
, nir_opt_undef
);
474 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
477 nir_var_function_temp
);
479 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
482 /* Must be run at the end to prevent creation of fsin/fcos ops */
483 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
488 NIR_PASS(progress
, nir
, nir_opt_dce
);
489 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
490 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
491 NIR_PASS(progress
, nir
, nir_copy_prop
);
494 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
496 /* We implement booleans as 32-bit 0/~0 */
497 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
499 /* Now that booleans are lowered, we can run out late opts */
500 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
502 /* Lower mods for float ops only. Integer ops don't support modifiers
503 * (saturate doesn't make sense on integers, neg/abs require dedicated
506 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
507 NIR_PASS(progress
, nir
, nir_copy_prop
);
508 NIR_PASS(progress
, nir
, nir_opt_dce
);
510 /* Take us out of SSA */
511 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
512 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
514 /* We are a vector architecture; write combine where possible */
515 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
516 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
518 NIR_PASS(progress
, nir
, nir_opt_dce
);
521 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
522 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
523 * r0. See the comments in compiler_context */
526 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
528 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
529 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
532 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
535 unalias_ssa(compiler_context
*ctx
, int dest
)
537 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
538 /* TODO: Remove from leftover or no? */
541 /* Do not actually emit a load; instead, cache the constant for inlining */
544 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
546 nir_ssa_def def
= instr
->def
;
548 float *v
= rzalloc_array(NULL
, float, 4);
549 nir_const_load_to_arr(v
, instr
, f32
);
550 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
554 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
557 return src
->ssa
->index
;
559 assert(!src
->reg
.indirect
);
560 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
565 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
567 return nir_src_index(ctx
, &src
->src
);
571 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
573 unsigned comp
= src
->swizzle
[0];
575 for (unsigned c
= 1; c
< nr_components
; ++c
) {
576 if (src
->swizzle
[c
] != comp
)
583 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
584 * output of a conditional test) into that register */
587 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
589 int condition
= nir_src_index(ctx
, src
);
591 /* Source to swizzle the desired component into w */
593 const midgard_vector_alu_src alu_src
= {
594 .swizzle
= SWIZZLE(component
, component
, component
, component
),
597 /* There is no boolean move instruction. Instead, we simulate a move by
598 * ANDing the condition with itself to get it into r31.w */
600 midgard_instruction ins
= {
603 /* We need to set the conditional as close as possible */
604 .precede_break
= true,
605 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
610 .dest
= SSA_FIXED_REGISTER(31),
614 .op
= midgard_alu_op_iand
,
615 .outmod
= midgard_outmod_int_wrap
,
616 .reg_mode
= midgard_reg_mode_32
,
617 .dest_override
= midgard_dest_override_none
,
618 .mask
= (0x3 << 6), /* w */
619 .src1
= vector_alu_srco_unsigned(alu_src
),
620 .src2
= vector_alu_srco_unsigned(alu_src
)
624 emit_mir_instruction(ctx
, ins
);
627 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
631 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
633 int condition
= nir_src_index(ctx
, &src
->src
);
635 /* Source to swizzle the desired component into w */
637 const midgard_vector_alu_src alu_src
= {
638 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
641 /* There is no boolean move instruction. Instead, we simulate a move by
642 * ANDing the condition with itself to get it into r31.w */
644 midgard_instruction ins
= {
646 .precede_break
= true,
650 .dest
= SSA_FIXED_REGISTER(31),
653 .op
= midgard_alu_op_iand
,
654 .outmod
= midgard_outmod_int_wrap
,
655 .reg_mode
= midgard_reg_mode_32
,
656 .dest_override
= midgard_dest_override_none
,
657 .mask
= expand_writemask(mask_of(nr_comp
)),
658 .src1
= vector_alu_srco_unsigned(alu_src
),
659 .src2
= vector_alu_srco_unsigned(alu_src
)
663 emit_mir_instruction(ctx
, ins
);
668 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
669 * pinning to eliminate this move in all known cases */
672 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
674 int offset
= nir_src_index(ctx
, src
);
676 midgard_instruction ins
= {
679 .src0
= SSA_UNUSED_1
,
681 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
684 .op
= midgard_alu_op_imov
,
685 .outmod
= midgard_outmod_int_wrap
,
686 .reg_mode
= midgard_reg_mode_32
,
687 .dest_override
= midgard_dest_override_none
,
688 .mask
= (0x3 << 6), /* w */
689 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
690 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
694 emit_mir_instruction(ctx
, ins
);
697 #define ALU_CASE(nir, _op) \
699 op = midgard_alu_op_##_op; \
702 nir_is_fzero_constant(nir_src src
)
704 if (!nir_src_is_const(src
))
707 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
708 if (nir_src_comp_as_float(src
, c
) != 0.0)
716 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
718 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
720 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
721 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
722 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
724 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
725 * supported. A few do not and are commented for now. Also, there are a
726 * number of NIR ops which Midgard does not support and need to be
727 * lowered, also TODO. This switch block emits the opcode and calling
728 * convention of the Midgard instruction; actual packing is done in
734 ALU_CASE(fadd
, fadd
);
735 ALU_CASE(fmul
, fmul
);
736 ALU_CASE(fmin
, fmin
);
737 ALU_CASE(fmax
, fmax
);
738 ALU_CASE(imin
, imin
);
739 ALU_CASE(imax
, imax
);
740 ALU_CASE(umin
, umin
);
741 ALU_CASE(umax
, umax
);
742 ALU_CASE(ffloor
, ffloor
);
743 ALU_CASE(fround_even
, froundeven
);
744 ALU_CASE(ftrunc
, ftrunc
);
745 ALU_CASE(fceil
, fceil
);
746 ALU_CASE(fdot3
, fdot3
);
747 ALU_CASE(fdot4
, fdot4
);
748 ALU_CASE(iadd
, iadd
);
749 ALU_CASE(isub
, isub
);
750 ALU_CASE(imul
, imul
);
752 /* Zero shoved as second-arg */
753 ALU_CASE(iabs
, iabsdiff
);
757 ALU_CASE(feq32
, feq
);
758 ALU_CASE(fne32
, fne
);
759 ALU_CASE(flt32
, flt
);
760 ALU_CASE(ieq32
, ieq
);
761 ALU_CASE(ine32
, ine
);
762 ALU_CASE(ilt32
, ilt
);
763 ALU_CASE(ult32
, ult
);
765 /* We don't have a native b2f32 instruction. Instead, like many
766 * GPUs, we exploit booleans as 0/~0 for false/true, and
767 * correspondingly AND
768 * by 1.0 to do the type conversion. For the moment, prime us
771 * iand [whatever], #0
773 * At the end of emit_alu (as MIR), we'll fix-up the constant
776 ALU_CASE(b2f32
, iand
);
777 ALU_CASE(b2i32
, iand
);
779 /* Likewise, we don't have a dedicated f2b32 instruction, but
780 * we can do a "not equal to 0.0" test. */
782 ALU_CASE(f2b32
, fne
);
783 ALU_CASE(i2b32
, ine
);
785 ALU_CASE(frcp
, frcp
);
786 ALU_CASE(frsq
, frsqrt
);
787 ALU_CASE(fsqrt
, fsqrt
);
788 ALU_CASE(fexp2
, fexp2
);
789 ALU_CASE(flog2
, flog2
);
791 ALU_CASE(f2i32
, f2i_rtz
);
792 ALU_CASE(f2u32
, f2u_rtz
);
793 ALU_CASE(i2f32
, i2f_rtz
);
794 ALU_CASE(u2f32
, u2f_rtz
);
796 ALU_CASE(fsin
, fsin
);
797 ALU_CASE(fcos
, fcos
);
799 /* Second op implicit #0 */
800 ALU_CASE(inot
, inor
);
801 ALU_CASE(iand
, iand
);
803 ALU_CASE(ixor
, ixor
);
804 ALU_CASE(ishl
, ishl
);
805 ALU_CASE(ishr
, iasr
);
806 ALU_CASE(ushr
, ilsr
);
808 ALU_CASE(b32all_fequal2
, fball_eq
);
809 ALU_CASE(b32all_fequal3
, fball_eq
);
810 ALU_CASE(b32all_fequal4
, fball_eq
);
812 ALU_CASE(b32any_fnequal2
, fbany_neq
);
813 ALU_CASE(b32any_fnequal3
, fbany_neq
);
814 ALU_CASE(b32any_fnequal4
, fbany_neq
);
816 ALU_CASE(b32all_iequal2
, iball_eq
);
817 ALU_CASE(b32all_iequal3
, iball_eq
);
818 ALU_CASE(b32all_iequal4
, iball_eq
);
820 ALU_CASE(b32any_inequal2
, ibany_neq
);
821 ALU_CASE(b32any_inequal3
, ibany_neq
);
822 ALU_CASE(b32any_inequal4
, ibany_neq
);
824 /* Source mods will be shoved in later */
825 ALU_CASE(fabs
, fmov
);
826 ALU_CASE(fneg
, fmov
);
827 ALU_CASE(fsat
, fmov
);
829 /* For greater-or-equal, we lower to less-or-equal and flip the
837 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
838 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
839 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
840 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
843 /* Swap via temporary */
844 nir_alu_src temp
= instr
->src
[1];
845 instr
->src
[1] = instr
->src
[0];
846 instr
->src
[0] = temp
;
851 case nir_op_b32csel
: {
852 /* Midgard features both fcsel and icsel, depending on
853 * the type of the arguments/output. However, as long
854 * as we're careful we can _always_ use icsel and
855 * _never_ need fcsel, since the latter does additional
856 * floating-point-specific processing whereas the
857 * former just moves bits on the wire. It's not obvious
858 * why these are separate opcodes, save for the ability
859 * to do things like sat/pos/abs/neg for free */
861 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
862 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
864 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
867 /* Emit the condition into r31 */
870 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
872 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
874 /* The condition is the first argument; move the other
875 * arguments up one to be a binary instruction for
878 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
883 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
888 /* Midgard can perform certain modifiers on output of an ALU op */
891 if (midgard_is_integer_out_op(op
)) {
892 outmod
= midgard_outmod_int_wrap
;
894 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
895 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
898 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
900 if (instr
->op
== nir_op_fmax
) {
901 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
902 op
= midgard_alu_op_fmov
;
904 outmod
= midgard_outmod_pos
;
905 instr
->src
[0] = instr
->src
[1];
906 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
907 op
= midgard_alu_op_fmov
;
909 outmod
= midgard_outmod_pos
;
913 /* Fetch unit, quirks, etc information */
914 unsigned opcode_props
= alu_opcode_props
[op
].props
;
915 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
917 /* src0 will always exist afaik, but src1 will not for 1-argument
918 * instructions. The latter can only be fetched if the instruction
919 * needs it, or else we may segfault. */
921 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
922 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
924 /* Rather than use the instruction generation helpers, we do it
925 * ourselves here to avoid the mess */
927 midgard_instruction ins
= {
930 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
931 .src1
= quirk_flipped_r24
? src0
: src1
,
936 nir_alu_src
*nirmods
[2] = { NULL
};
938 if (nr_inputs
== 2) {
939 nirmods
[0] = &instr
->src
[0];
940 nirmods
[1] = &instr
->src
[1];
941 } else if (nr_inputs
== 1) {
942 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
947 /* These were lowered to a move, so apply the corresponding mod */
949 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
950 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
952 if (instr
->op
== nir_op_fneg
)
953 s
->negate
= !s
->negate
;
955 if (instr
->op
== nir_op_fabs
)
959 bool is_int
= midgard_is_integer_op(op
);
961 midgard_vector_alu alu
= {
963 .reg_mode
= midgard_reg_mode_32
,
964 .dest_override
= midgard_dest_override_none
,
967 /* Writemask only valid for non-SSA NIR */
968 .mask
= expand_writemask(mask_of(nr_components
)),
970 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
971 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
974 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
977 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
981 /* Late fixup for emulated instructions */
983 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
984 /* Presently, our second argument is an inline #0 constant.
985 * Switch over to an embedded 1.0 constant (that can't fit
986 * inline, since we're 32-bit, not 16-bit like the inline
989 ins
.ssa_args
.inline_constant
= false;
990 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
991 ins
.has_constants
= true;
993 if (instr
->op
== nir_op_b2f32
) {
994 ins
.constants
[0] = 1.0f
;
996 /* Type pun it into place */
998 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1001 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1002 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1003 /* Lots of instructions need a 0 plonked in */
1004 ins
.ssa_args
.inline_constant
= false;
1005 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1006 ins
.has_constants
= true;
1007 ins
.constants
[0] = 0.0f
;
1008 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1009 } else if (instr
->op
== nir_op_inot
) {
1010 /* ~b = ~(b & b), so duplicate the source */
1011 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1012 ins
.alu
.src2
= ins
.alu
.src1
;
1015 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1016 /* To avoid duplicating the lookup tables (probably), true LUT
1017 * instructions can only operate as if they were scalars. Lower
1018 * them here by changing the component. */
1020 uint8_t original_swizzle
[4];
1021 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1023 for (int i
= 0; i
< nr_components
; ++i
) {
1024 /* Mask the associated component, dropping the
1025 * instruction if needed */
1027 ins
.alu
.mask
= (0x3) << (2 * i
);
1028 ins
.alu
.mask
&= alu
.mask
;
1033 for (int j
= 0; j
< 4; ++j
)
1034 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1036 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
1037 emit_mir_instruction(ctx
, ins
);
1040 emit_mir_instruction(ctx
, ins
);
1047 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1049 /* TODO: half-floats */
1051 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1052 /* Fast path: For the first 16 uniforms, direct accesses are
1053 * 0-cycle, since they're just a register fetch in the usual
1054 * case. So, we alias the registers while we're still in
1057 int reg_slot
= 23 - offset
;
1058 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1060 /* Otherwise, read from the 'special' UBO to access
1061 * higher-indexed uniforms, at a performance cost. More
1062 * generally, we're emitting a UBO read instruction. */
1064 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1066 /* TODO: Don't split */
1067 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1068 ins
.load_store
.address
= offset
>> 3;
1070 if (indirect_offset
) {
1071 emit_indirect_offset(ctx
, indirect_offset
);
1072 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1074 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1077 emit_mir_instruction(ctx
, ins
);
1083 compiler_context
*ctx
,
1084 unsigned dest
, unsigned offset
,
1085 unsigned nr_comp
, unsigned component
,
1086 nir_src
*indirect_offset
)
1088 /* XXX: Half-floats? */
1089 /* TODO: swizzle, mask */
1091 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1092 ins
.load_store
.mask
= mask_of(nr_comp
);
1093 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1095 midgard_varying_parameter p
= {
1097 .interpolation
= midgard_interp_default
,
1098 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1102 memcpy(&u
, &p
, sizeof(p
));
1103 ins
.load_store
.varying_parameters
= u
;
1105 if (indirect_offset
) {
1106 /* We need to add in the dynamic index, moved to r27.w */
1107 emit_indirect_offset(ctx
, indirect_offset
);
1108 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1110 /* Just a direct load */
1111 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1114 emit_mir_instruction(ctx
, ins
);
1118 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1121 /* Figure out which uniform this is */
1122 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1123 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1125 /* Sysvals are prefix uniforms */
1126 unsigned uniform
= ((uintptr_t) val
) - 1;
1128 /* Emit the read itself -- this is never indirect */
1129 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1132 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1133 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1134 * generations have faster vectorized reads. This operation is for blend
1135 * shaders in particular; reading the tilebuffer from the fragment shader
1136 * remains an open problem. */
1139 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1141 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1142 ins
.load_store
.swizzle
= 0; /* xxxx */
1144 /* Read each component sequentially */
1146 for (unsigned c
= 0; c
< 4; ++c
) {
1147 ins
.load_store
.mask
= (1 << c
);
1148 ins
.load_store
.unknown
= c
;
1149 emit_mir_instruction(ctx
, ins
);
1152 /* vadd.u2f hr2, zext(hr2), #0 */
1154 midgard_vector_alu_src alu_src
= blank_alu_src
;
1155 alu_src
.mod
= midgard_int_zero_extend
;
1156 alu_src
.half
= true;
1158 midgard_instruction u2f
= {
1162 .src1
= SSA_UNUSED_0
,
1164 .inline_constant
= true
1167 .op
= midgard_alu_op_u2f_rtz
,
1168 .reg_mode
= midgard_reg_mode_16
,
1169 .dest_override
= midgard_dest_override_none
,
1171 .src1
= vector_alu_srco_unsigned(alu_src
),
1172 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1176 emit_mir_instruction(ctx
, u2f
);
1178 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1182 midgard_instruction fmul
= {
1184 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1188 .src1
= SSA_UNUSED_0
,
1189 .inline_constant
= true
1192 .op
= midgard_alu_op_fmul
,
1193 .reg_mode
= midgard_reg_mode_32
,
1194 .dest_override
= midgard_dest_override_none
,
1195 .outmod
= midgard_outmod_sat
,
1197 .src1
= vector_alu_srco_unsigned(alu_src
),
1198 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1202 emit_mir_instruction(ctx
, fmul
);
1206 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1208 unsigned offset
, reg
;
1210 switch (instr
->intrinsic
) {
1211 case nir_intrinsic_discard_if
:
1212 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1216 case nir_intrinsic_discard
: {
1217 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1218 struct midgard_instruction discard
= v_branch(conditional
, false);
1219 discard
.branch
.target_type
= TARGET_DISCARD
;
1220 emit_mir_instruction(ctx
, discard
);
1222 ctx
->can_discard
= true;
1226 case nir_intrinsic_load_uniform
:
1227 case nir_intrinsic_load_input
:
1228 offset
= nir_intrinsic_base(instr
);
1230 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1231 bool direct
= nir_src_is_const(instr
->src
[0]);
1234 offset
+= nir_src_as_uint(instr
->src
[0]);
1237 /* We may need to apply a fractional offset */
1238 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1239 nir_intrinsic_component(instr
) : 0;
1240 reg
= nir_dest_index(ctx
, &instr
->dest
);
1242 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1243 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1244 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1245 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
);
1246 } else if (ctx
->is_blend
) {
1247 /* For blend shaders, load the input color, which is
1248 * preloaded to r0 */
1250 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1251 emit_mir_instruction(ctx
, move
);
1252 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1253 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1254 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1255 ins
.load_store
.mask
= mask_of(nr_comp
);
1256 emit_mir_instruction(ctx
, ins
);
1258 DBG("Unknown load\n");
1264 case nir_intrinsic_load_output
:
1265 assert(nir_src_is_const(instr
->src
[0]));
1266 reg
= nir_dest_index(ctx
, &instr
->dest
);
1268 if (ctx
->is_blend
) {
1270 emit_fb_read_blend_scalar(ctx
, reg
);
1272 DBG("Unknown output load\n");
1278 case nir_intrinsic_load_blend_const_color_rgba
: {
1279 assert(ctx
->is_blend
);
1280 reg
= nir_dest_index(ctx
, &instr
->dest
);
1282 /* Blend constants are embedded directly in the shader and
1283 * patched in, so we use some magic routing */
1285 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1286 ins
.has_constants
= true;
1287 ins
.has_blend_constant
= true;
1288 emit_mir_instruction(ctx
, ins
);
1292 case nir_intrinsic_store_output
:
1293 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1295 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1297 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1299 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1300 /* gl_FragColor is not emitted with load/store
1301 * instructions. Instead, it gets plonked into
1302 * r0 at the end of the shader and we do the
1303 * framebuffer writeout dance. TODO: Defer
1306 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1307 emit_mir_instruction(ctx
, move
);
1309 /* Save the index we're writing to for later reference
1310 * in the epilogue */
1312 ctx
->fragment_output
= reg
;
1313 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1314 /* Varyings are written into one of two special
1315 * varying register, r26 or r27. The register itself is
1316 * selected as the register in the st_vary instruction,
1317 * minus the base of 26. E.g. write into r27 and then
1318 * call st_vary(1) */
1320 midgard_instruction ins
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1321 emit_mir_instruction(ctx
, ins
);
1323 /* We should have been vectorized, though we don't
1324 * currently check that st_vary is emitted only once
1325 * per slot (this is relevant, since there's not a mask
1326 * parameter available on the store [set to 0 by the
1327 * blob]). We do respect the component by adjusting the
1330 unsigned component
= nir_intrinsic_component(instr
);
1332 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1333 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1334 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1335 emit_mir_instruction(ctx
, st
);
1337 DBG("Unknown store\n");
1343 case nir_intrinsic_load_alpha_ref_float
:
1344 assert(instr
->dest
.is_ssa
);
1346 float ref_value
= ctx
->alpha_ref
;
1348 float *v
= ralloc_array(NULL
, float, 4);
1349 memcpy(v
, &ref_value
, sizeof(float));
1350 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1353 case nir_intrinsic_load_viewport_scale
:
1354 case nir_intrinsic_load_viewport_offset
:
1355 emit_sysval_read(ctx
, &instr
->instr
);
1359 printf ("Unhandled intrinsic\n");
1366 midgard_tex_format(enum glsl_sampler_dim dim
)
1369 case GLSL_SAMPLER_DIM_2D
:
1370 case GLSL_SAMPLER_DIM_EXTERNAL
:
1373 case GLSL_SAMPLER_DIM_3D
:
1376 case GLSL_SAMPLER_DIM_CUBE
:
1377 return TEXTURE_CUBE
;
1380 DBG("Unknown sampler dim type\n");
1387 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1388 unsigned midgard_texop
)
1391 //assert (!instr->sampler);
1392 //assert (!instr->texture_array_size);
1394 /* Allocate registers via a round robin scheme to alternate between the two registers */
1395 int reg
= ctx
->texture_op_count
& 1;
1396 int in_reg
= reg
, out_reg
= reg
;
1398 /* Make room for the reg */
1400 if (ctx
->texture_index
[reg
] > -1)
1401 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1403 int texture_index
= instr
->texture_index
;
1404 int sampler_index
= texture_index
;
1406 unsigned position_swizzle
= 0;
1408 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1409 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1410 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1411 int nr_comp
= nir_src_num_components(instr
->src
[i
].src
);
1412 midgard_vector_alu_src alu_src
= blank_alu_src
;
1414 switch (instr
->src
[i
].src_type
) {
1415 case nir_tex_src_coord
: {
1416 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1417 /* For cubemaps, we need to load coords into
1418 * special r27, and then use a special ld/st op
1419 * to select the face and copy the xy into the
1420 * texture register */
1422 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1424 midgard_instruction move
= v_mov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1425 emit_mir_instruction(ctx
, move
);
1427 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1428 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1429 st
.load_store
.mask
= 0x3; /* xy */
1430 st
.load_store
.swizzle
= alu_src
.swizzle
;
1431 emit_mir_instruction(ctx
, st
);
1433 position_swizzle
= swizzle_of(2);
1435 position_swizzle
= alu_src
.swizzle
= swizzle_of(nr_comp
);
1437 midgard_instruction ins
= v_mov(index
, alu_src
, reg
);
1438 ins
.alu
.mask
= expand_writemask(mask_of(nr_comp
));
1439 emit_mir_instruction(ctx
, ins
);
1441 /* To the hardware, z is depth, w is array
1442 * layer. To NIR, z is array layer for a 2D
1445 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
)
1446 position_swizzle
= SWIZZLE_XYXZ
;
1452 case nir_tex_src_bias
:
1453 case nir_tex_src_lod
: {
1454 /* To keep RA simple, we put the bias/LOD into the w
1455 * component of the input source, which is otherwise in xy */
1457 alu_src
.swizzle
= SWIZZLE_XXXX
;
1459 midgard_instruction ins
= v_mov(index
, alu_src
, reg
);
1460 ins
.alu
.mask
= expand_writemask(1 << COMPONENT_W
);
1461 emit_mir_instruction(ctx
, ins
);
1466 unreachable("Unknown texture source type\n");
1470 /* No helper to build texture words -- we do it all here */
1471 midgard_instruction ins
= {
1472 .type
= TAG_TEXTURE_4
,
1474 .op
= midgard_texop
,
1475 .format
= midgard_tex_format(instr
->sampler_dim
),
1476 .texture_handle
= texture_index
,
1477 .sampler_handle
= sampler_index
,
1479 /* TODO: Regalloc it in */
1480 .swizzle
= SWIZZLE_XYZW
,
1485 .in_reg_swizzle
= position_swizzle
,
1493 /* Set registers to read and write from the same place */
1494 ins
.texture
.in_reg_select
= in_reg
;
1495 ins
.texture
.out_reg_select
= out_reg
;
1497 /* Setup bias/LOD if necessary. Only register mode support right now.
1498 * TODO: Immediate mode for performance gains */
1500 if (instr
->op
== nir_texop_txb
|| instr
->op
== nir_texop_txl
) {
1501 ins
.texture
.lod_register
= true;
1503 midgard_tex_register_select sel
= {
1513 memcpy(&packed
, &sel
, sizeof(packed
));
1514 ins
.texture
.bias
= packed
;
1517 emit_mir_instruction(ctx
, ins
);
1519 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1521 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1522 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1523 ctx
->texture_index
[reg
] = o_index
;
1525 midgard_instruction ins2
= v_mov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1526 emit_mir_instruction(ctx
, ins2
);
1528 /* Used for .cont and .last hinting */
1529 ctx
->texture_op_count
++;
1533 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1535 switch (instr
->op
) {
1538 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1541 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1544 emit_sysval_read(ctx
, &instr
->instr
);
1547 unreachable("Unhanlded texture op");
1552 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1554 switch (instr
->type
) {
1555 case nir_jump_break
: {
1556 /* Emit a branch out of the loop */
1557 struct midgard_instruction br
= v_branch(false, false);
1558 br
.branch
.target_type
= TARGET_BREAK
;
1559 br
.branch
.target_break
= ctx
->current_loop_depth
;
1560 emit_mir_instruction(ctx
, br
);
1567 DBG("Unknown jump type %d\n", instr
->type
);
1573 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1575 switch (instr
->type
) {
1576 case nir_instr_type_load_const
:
1577 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1580 case nir_instr_type_intrinsic
:
1581 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1584 case nir_instr_type_alu
:
1585 emit_alu(ctx
, nir_instr_as_alu(instr
));
1588 case nir_instr_type_tex
:
1589 emit_tex(ctx
, nir_instr_as_tex(instr
));
1592 case nir_instr_type_jump
:
1593 emit_jump(ctx
, nir_instr_as_jump(instr
));
1596 case nir_instr_type_ssa_undef
:
1601 DBG("Unhandled instruction type\n");
1607 /* ALU instructions can inline or embed constants, which decreases register
1608 * pressure and saves space. */
1610 #define CONDITIONAL_ATTACH(src) { \
1611 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1614 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1615 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1620 inline_alu_constants(compiler_context
*ctx
)
1622 mir_foreach_instr(ctx
, alu
) {
1623 /* Other instructions cannot inline constants */
1624 if (alu
->type
!= TAG_ALU_4
) continue;
1626 /* If there is already a constant here, we can do nothing */
1627 if (alu
->has_constants
) continue;
1629 /* It makes no sense to inline constants on a branch */
1630 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1632 CONDITIONAL_ATTACH(src0
);
1634 if (!alu
->has_constants
) {
1635 CONDITIONAL_ATTACH(src1
)
1636 } else if (!alu
->inline_constant
) {
1637 /* Corner case: _two_ vec4 constants, for instance with a
1638 * csel. For this case, we can only use a constant
1639 * register for one, we'll have to emit a move for the
1640 * other. Note, if both arguments are constants, then
1641 * necessarily neither argument depends on the value of
1642 * any particular register. As the destination register
1643 * will be wiped, that means we can spill the constant
1644 * to the destination register.
1647 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1648 unsigned scratch
= alu
->ssa_args
.dest
;
1651 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1652 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1654 /* Force a break XXX Defer r31 writes */
1655 ins
.unit
= UNIT_VLUT
;
1657 /* Set the source */
1658 alu
->ssa_args
.src1
= scratch
;
1660 /* Inject us -before- the last instruction which set r31 */
1661 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1667 /* Midgard supports two types of constants, embedded constants (128-bit) and
1668 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1669 * constants can be demoted to inline constants, for space savings and
1670 * sometimes a performance boost */
1673 embedded_to_inline_constant(compiler_context
*ctx
)
1675 mir_foreach_instr(ctx
, ins
) {
1676 if (!ins
->has_constants
) continue;
1678 if (ins
->ssa_args
.inline_constant
) continue;
1680 /* Blend constants must not be inlined by definition */
1681 if (ins
->has_blend_constant
) continue;
1683 /* src1 cannot be an inline constant due to encoding
1684 * restrictions. So, if possible we try to flip the arguments
1687 int op
= ins
->alu
.op
;
1689 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1691 /* These ops require an operational change to flip
1692 * their arguments TODO */
1693 case midgard_alu_op_flt
:
1694 case midgard_alu_op_fle
:
1695 case midgard_alu_op_ilt
:
1696 case midgard_alu_op_ile
:
1697 case midgard_alu_op_fcsel
:
1698 case midgard_alu_op_icsel
:
1699 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1704 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1705 /* Flip the SSA numbers */
1706 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1707 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1709 /* And flip the modifiers */
1713 src_temp
= ins
->alu
.src2
;
1714 ins
->alu
.src2
= ins
->alu
.src1
;
1715 ins
->alu
.src1
= src_temp
;
1719 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1720 /* Extract the source information */
1722 midgard_vector_alu_src
*src
;
1723 int q
= ins
->alu
.src2
;
1724 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1727 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1728 int component
= src
->swizzle
& 3;
1730 /* Scale constant appropriately, if we can legally */
1731 uint16_t scaled_constant
= 0;
1733 if (midgard_is_integer_op(op
)) {
1734 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1735 scaled_constant
= (uint16_t) iconstants
[component
];
1737 /* Constant overflow after resize */
1738 if (scaled_constant
!= iconstants
[component
])
1741 float original
= (float) ins
->constants
[component
];
1742 scaled_constant
= _mesa_float_to_half(original
);
1744 /* Check for loss of precision. If this is
1745 * mediump, we don't care, but for a highp
1746 * shader, we need to pay attention. NIR
1747 * doesn't yet tell us which mode we're in!
1748 * Practically this prevents most constants
1749 * from being inlined, sadly. */
1751 float fp32
= _mesa_half_to_float(scaled_constant
);
1753 if (fp32
!= original
)
1757 /* We don't know how to handle these with a constant */
1759 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1760 DBG("Bailing inline constant...\n");
1764 /* Make sure that the constant is not itself a
1765 * vector by checking if all accessed values
1766 * (by the swizzle) are the same. */
1768 uint32_t *cons
= (uint32_t *) ins
->constants
;
1769 uint32_t value
= cons
[component
];
1771 bool is_vector
= false;
1772 unsigned mask
= effective_writemask(&ins
->alu
);
1774 for (int c
= 1; c
< 4; ++c
) {
1775 /* We only care if this component is actually used */
1776 if (!(mask
& (1 << c
)))
1779 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1781 if (test
!= value
) {
1790 /* Get rid of the embedded constant */
1791 ins
->has_constants
= false;
1792 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1793 ins
->ssa_args
.inline_constant
= true;
1794 ins
->inline_constant
= scaled_constant
;
1799 /* Map normal SSA sources to other SSA sources / fixed registers (like
1803 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
1805 /* Sign is used quite deliberately for unused */
1809 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
1812 /* Remove entry in leftovers to avoid a redunant fmov */
1814 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
1817 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
1819 /* Assign the alias map */
1825 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1826 * texture pipeline */
1829 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
1831 bool progress
= false;
1833 mir_foreach_instr_in_block_safe(block
, ins
) {
1834 if (ins
->type
!= TAG_ALU_4
) continue;
1835 if (ins
->compact_branch
) continue;
1837 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1838 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
1840 mir_remove_instruction(ins
);
1847 /* Dead code elimination for branches at the end of a block - only one branch
1848 * per block is legal semantically */
1851 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1853 bool branched
= false;
1855 mir_foreach_instr_in_block_safe(block
, ins
) {
1856 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1858 /* We ignore prepacked branches since the fragment epilogue is
1859 * just generally special */
1860 if (ins
->prepacked_branch
) continue;
1862 /* Discards are similarly special and may not correspond to the
1865 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
1868 /* We already branched, so this is dead */
1869 mir_remove_instruction(ins
);
1877 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
1880 if (!is_int
&& src
.mod
) return true;
1883 for (unsigned c
= 0; c
< 4; ++c
) {
1884 if (!(mask
& (1 << c
))) continue;
1885 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
1892 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
1894 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
1895 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
1897 midgard_vector_alu_src src2
=
1898 vector_alu_from_unsigned(ins
->alu
.src2
);
1900 return mir_nontrivial_mod(src2
, is_int
, mask
);
1904 mir_nontrivial_outmod(midgard_instruction
*ins
)
1906 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
1907 unsigned mod
= ins
->alu
.outmod
;
1910 return mod
!= midgard_outmod_int_wrap
;
1912 return mod
!= midgard_outmod_none
;
1916 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
1918 bool progress
= false;
1920 mir_foreach_instr_in_block_safe(block
, ins
) {
1921 if (ins
->type
!= TAG_ALU_4
) continue;
1922 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
1924 unsigned from
= ins
->ssa_args
.src1
;
1925 unsigned to
= ins
->ssa_args
.dest
;
1927 /* We only work on pure SSA */
1929 if (to
>= SSA_FIXED_MINIMUM
) continue;
1930 if (from
>= SSA_FIXED_MINIMUM
) continue;
1931 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
1932 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
1934 /* Constant propagation is not handled here, either */
1935 if (ins
->ssa_args
.inline_constant
) continue;
1936 if (ins
->has_constants
) continue;
1938 if (mir_nontrivial_source2_mod(ins
)) continue;
1939 if (mir_nontrivial_outmod(ins
)) continue;
1941 /* We're clear -- rewrite */
1942 mir_rewrite_index_src(ctx
, to
, from
);
1943 mir_remove_instruction(ins
);
1950 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1951 * the move can be propagated away entirely */
1954 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
1957 if (comp
== midgard_outmod_none
)
1960 if (*outmod
== midgard_outmod_none
) {
1965 /* TODO: Compose rules */
1970 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
1972 bool progress
= false;
1974 mir_foreach_instr_in_block_safe(block
, ins
) {
1975 if (ins
->type
!= TAG_ALU_4
) continue;
1976 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
1977 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
1979 /* TODO: Registers? */
1980 unsigned src
= ins
->ssa_args
.src1
;
1981 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
1982 assert(!mir_has_multiple_writes(ctx
, src
));
1984 /* There might be a source modifier, too */
1985 if (mir_nontrivial_source2_mod(ins
)) continue;
1987 /* Backpropagate the modifier */
1988 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1989 if (v
->type
!= TAG_ALU_4
) continue;
1990 if (v
->ssa_args
.dest
!= src
) continue;
1992 /* Can we even take a float outmod? */
1993 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
1995 midgard_outmod_float temp
= v
->alu
.outmod
;
1996 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
1998 /* Throw in the towel.. */
1999 if (!progress
) break;
2001 /* Otherwise, transfer the modifier */
2002 v
->alu
.outmod
= temp
;
2003 ins
->alu
.outmod
= midgard_outmod_none
;
2013 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
2015 bool progress
= false;
2017 mir_foreach_instr_in_block_safe(block
, ins
) {
2018 if (ins
->type
!= TAG_ALU_4
) continue;
2019 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2021 unsigned from
= ins
->ssa_args
.src1
;
2022 unsigned to
= ins
->ssa_args
.dest
;
2024 /* Make sure it's simple enough for us to handle */
2026 if (from
>= SSA_FIXED_MINIMUM
) continue;
2027 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2028 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
2029 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
2031 bool eliminated
= false;
2033 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2034 /* The texture registers are not SSA so be careful.
2035 * Conservatively, just stop if we hit a texture op
2036 * (even if it may not write) to where we are */
2038 if (v
->type
!= TAG_ALU_4
)
2041 if (v
->ssa_args
.dest
== from
) {
2042 /* We don't want to track partial writes ... */
2043 if (v
->alu
.mask
== 0xF) {
2044 v
->ssa_args
.dest
= to
;
2053 mir_remove_instruction(ins
);
2055 progress
|= eliminated
;
2061 /* The following passes reorder MIR instructions to enable better scheduling */
2064 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2066 mir_foreach_instr_in_block_safe(block
, ins
) {
2067 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2069 /* We've found a load/store op. Check if next is also load/store. */
2070 midgard_instruction
*next_op
= mir_next_op(ins
);
2071 if (&next_op
->link
!= &block
->instructions
) {
2072 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2073 /* If so, we're done since we're a pair */
2074 ins
= mir_next_op(ins
);
2078 /* Maximum search distance to pair, to avoid register pressure disasters */
2079 int search_distance
= 8;
2081 /* Otherwise, we have an orphaned load/store -- search for another load */
2082 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2083 /* Terminate search if necessary */
2084 if (!(search_distance
--)) break;
2086 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2088 /* Stores cannot be reordered, since they have
2089 * dependencies. For the same reason, indirect
2090 * loads cannot be reordered as their index is
2091 * loaded in r27.w */
2093 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2095 /* It appears the 0x800 bit is set whenever a
2096 * load is direct, unset when it is indirect.
2097 * Skip indirect loads. */
2099 if (!(c
->load_store
.unknown
& 0x800)) continue;
2101 /* We found one! Move it up to pair and remove it from the old location */
2103 mir_insert_instruction_before(ins
, *c
);
2104 mir_remove_instruction(c
);
2112 /* If there are leftovers after the below pass, emit actual fmov
2113 * instructions for the slow-but-correct path */
2116 emit_leftover_move(compiler_context
*ctx
)
2118 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2119 int base
= ((uintptr_t) leftover
->key
) - 1;
2122 map_ssa_to_alias(ctx
, &mapped
);
2123 EMIT(mov
, mapped
, blank_alu_src
, base
);
2128 actualise_ssa_to_alias(compiler_context
*ctx
)
2130 mir_foreach_instr(ctx
, ins
) {
2131 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2132 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2135 emit_leftover_move(ctx
);
2139 emit_fragment_epilogue(compiler_context
*ctx
)
2141 /* Special case: writing out constants requires us to include the move
2142 * explicitly now, so shove it into r0 */
2144 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2146 if (constant_value
) {
2147 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2148 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2149 emit_mir_instruction(ctx
, ins
);
2152 /* Perform the actual fragment writeout. We have two writeout/branch
2153 * instructions, forming a loop until writeout is successful as per the
2154 * docs. TODO: gl_FragDepth */
2156 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2157 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2160 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2161 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2162 * with the int8 analogue to the fragment epilogue */
2165 emit_blend_epilogue(compiler_context
*ctx
)
2167 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2169 midgard_instruction scale
= {
2172 .inline_constant
= _mesa_float_to_half(255.0),
2174 .src0
= SSA_FIXED_REGISTER(0),
2175 .src1
= SSA_UNUSED_0
,
2176 .dest
= SSA_FIXED_REGISTER(24),
2177 .inline_constant
= true
2180 .op
= midgard_alu_op_fmul
,
2181 .reg_mode
= midgard_reg_mode_32
,
2182 .dest_override
= midgard_dest_override_lower
,
2184 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2185 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2189 emit_mir_instruction(ctx
, scale
);
2191 /* vadd.f2u_rte.pos.low hr0, hr48, #0 */
2193 midgard_vector_alu_src alu_src
= blank_alu_src
;
2194 alu_src
.half
= true;
2196 midgard_instruction f2u_rte
= {
2199 .src0
= SSA_FIXED_REGISTER(24),
2200 .src1
= SSA_UNUSED_0
,
2201 .dest
= SSA_FIXED_REGISTER(0),
2202 .inline_constant
= true
2205 .op
= midgard_alu_op_f2u_rte
,
2206 .reg_mode
= midgard_reg_mode_16
,
2207 .dest_override
= midgard_dest_override_lower
,
2208 .outmod
= midgard_outmod_pos
,
2210 .src1
= vector_alu_srco_unsigned(alu_src
),
2211 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2215 emit_mir_instruction(ctx
, f2u_rte
);
2217 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2218 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2221 static midgard_block
*
2222 emit_block(compiler_context
*ctx
, nir_block
*block
)
2224 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2225 list_addtail(&this_block
->link
, &ctx
->blocks
);
2227 this_block
->is_scheduled
= false;
2230 ctx
->texture_index
[0] = -1;
2231 ctx
->texture_index
[1] = -1;
2233 /* Add us as a successor to the block we are following */
2234 if (ctx
->current_block
)
2235 midgard_block_add_successor(ctx
->current_block
, this_block
);
2237 /* Set up current block */
2238 list_inithead(&this_block
->instructions
);
2239 ctx
->current_block
= this_block
;
2241 nir_foreach_instr(instr
, block
) {
2242 emit_instr(ctx
, instr
);
2243 ++ctx
->instruction_count
;
2246 inline_alu_constants(ctx
);
2247 embedded_to_inline_constant(ctx
);
2249 /* Perform heavylifting for aliasing */
2250 actualise_ssa_to_alias(ctx
);
2252 midgard_pair_load_store(ctx
, this_block
);
2254 /* Append fragment shader epilogue (value writeout) */
2255 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2256 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2258 emit_blend_epilogue(ctx
);
2260 emit_fragment_epilogue(ctx
);
2264 if (block
== nir_start_block(ctx
->func
->impl
))
2265 ctx
->initial_block
= this_block
;
2267 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2268 ctx
->final_block
= this_block
;
2270 /* Allow the next control flow to access us retroactively, for
2272 ctx
->current_block
= this_block
;
2274 /* Document the fallthrough chain */
2275 ctx
->previous_source_block
= this_block
;
2280 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2283 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2285 /* Conditional branches expect the condition in r31.w; emit a move for
2286 * that in the _previous_ block (which is the current block). */
2287 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2289 /* Speculatively emit the branch, but we can't fill it in until later */
2290 EMIT(branch
, true, true);
2291 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2293 /* Emit the two subblocks */
2294 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2296 /* Emit a jump from the end of the then block to the end of the else */
2297 EMIT(branch
, false, false);
2298 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2300 /* Emit second block, and check if it's empty */
2302 int else_idx
= ctx
->block_count
;
2303 int count_in
= ctx
->instruction_count
;
2304 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2305 int after_else_idx
= ctx
->block_count
;
2307 /* Now that we have the subblocks emitted, fix up the branches */
2312 if (ctx
->instruction_count
== count_in
) {
2313 /* The else block is empty, so don't emit an exit jump */
2314 mir_remove_instruction(then_exit
);
2315 then_branch
->branch
.target_block
= after_else_idx
;
2317 then_branch
->branch
.target_block
= else_idx
;
2318 then_exit
->branch
.target_block
= after_else_idx
;
2323 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2325 /* Remember where we are */
2326 midgard_block
*start_block
= ctx
->current_block
;
2328 /* Allocate a loop number, growing the current inner loop depth */
2329 int loop_idx
= ++ctx
->current_loop_depth
;
2331 /* Get index from before the body so we can loop back later */
2332 int start_idx
= ctx
->block_count
;
2334 /* Emit the body itself */
2335 emit_cf_list(ctx
, &nloop
->body
);
2337 /* Branch back to loop back */
2338 struct midgard_instruction br_back
= v_branch(false, false);
2339 br_back
.branch
.target_block
= start_idx
;
2340 emit_mir_instruction(ctx
, br_back
);
2342 /* Mark down that branch in the graph. Note that we're really branching
2343 * to the block *after* we started in. TODO: Why doesn't the branch
2344 * itself have an off-by-one then...? */
2345 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2347 /* Find the index of the block about to follow us (note: we don't add
2348 * one; blocks are 0-indexed so we get a fencepost problem) */
2349 int break_block_idx
= ctx
->block_count
;
2351 /* Fix up the break statements we emitted to point to the right place,
2352 * now that we can allocate a block number for them */
2354 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2355 mir_foreach_instr_in_block(block
, ins
) {
2356 if (ins
->type
!= TAG_ALU_4
) continue;
2357 if (!ins
->compact_branch
) continue;
2358 if (ins
->prepacked_branch
) continue;
2360 /* We found a branch -- check the type to see if we need to do anything */
2361 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2363 /* It's a break! Check if it's our break */
2364 if (ins
->branch
.target_break
!= loop_idx
) continue;
2366 /* Okay, cool, we're breaking out of this loop.
2367 * Rewrite from a break to a goto */
2369 ins
->branch
.target_type
= TARGET_GOTO
;
2370 ins
->branch
.target_block
= break_block_idx
;
2374 /* Now that we've finished emitting the loop, free up the depth again
2375 * so we play nice with recursion amid nested loops */
2376 --ctx
->current_loop_depth
;
2379 static midgard_block
*
2380 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2382 midgard_block
*start_block
= NULL
;
2384 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2385 switch (node
->type
) {
2386 case nir_cf_node_block
: {
2387 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2390 start_block
= block
;
2395 case nir_cf_node_if
:
2396 emit_if(ctx
, nir_cf_node_as_if(node
));
2399 case nir_cf_node_loop
:
2400 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2403 case nir_cf_node_function
:
2412 /* Due to lookahead, we need to report the first tag executed in the command
2413 * stream and in branch targets. An initial block might be empty, so iterate
2414 * until we find one that 'works' */
2417 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2419 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2421 unsigned first_tag
= 0;
2424 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2426 if (initial_bundle
) {
2427 first_tag
= initial_bundle
->tag
;
2431 /* Initial block is empty, try the next block */
2432 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2433 } while(initial_block
!= NULL
);
2440 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2442 struct util_dynarray
*compiled
= &program
->compiled
;
2444 midgard_debug
= debug_get_option_midgard_debug();
2446 compiler_context ictx
= {
2448 .stage
= nir
->info
.stage
,
2450 .is_blend
= is_blend
,
2451 .blend_constant_offset
= -1,
2453 .alpha_ref
= program
->alpha_ref
2456 compiler_context
*ctx
= &ictx
;
2458 /* TODO: Decide this at runtime */
2459 ctx
->uniform_cutoff
= 8;
2461 /* Initialize at a global (not block) level hash tables */
2463 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2464 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2465 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2466 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2467 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2469 /* Record the varying mapping for the command stream's bookkeeping */
2471 struct exec_list
*varyings
=
2472 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2474 unsigned max_varying
= 0;
2475 nir_foreach_variable(var
, varyings
) {
2476 unsigned loc
= var
->data
.driver_location
;
2477 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2479 for (int c
= 0; c
< sz
; ++c
) {
2480 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2481 max_varying
= MAX2(max_varying
, loc
+ c
);
2485 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2486 * (so we don't accidentally duplicate the epilogue since mesa/st has
2487 * messed with our I/O quite a bit already) */
2489 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2491 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2492 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2494 NIR_PASS_V(nir
, nir_lower_var_copies
);
2495 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2496 NIR_PASS_V(nir
, nir_split_var_copies
);
2497 NIR_PASS_V(nir
, nir_lower_var_copies
);
2498 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2499 NIR_PASS_V(nir
, nir_lower_var_copies
);
2500 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2502 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2504 /* Optimisation passes */
2508 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2509 nir_print_shader(nir
, stdout
);
2512 /* Assign sysvals and counts, now that we're sure
2513 * (post-optimisation) */
2515 midgard_nir_assign_sysvals(ctx
, nir
);
2517 program
->uniform_count
= nir
->num_uniforms
;
2518 program
->sysval_count
= ctx
->sysval_count
;
2519 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2521 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2522 program
->varying_count
= max_varying
+ 1; /* Fencepost off-by-one */
2524 nir_foreach_function(func
, nir
) {
2528 list_inithead(&ctx
->blocks
);
2529 ctx
->block_count
= 0;
2532 emit_cf_list(ctx
, &func
->impl
->body
);
2533 emit_block(ctx
, func
->impl
->end_block
);
2535 break; /* TODO: Multi-function shaders */
2538 util_dynarray_init(compiled
, NULL
);
2540 /* MIR-level optimizations */
2542 bool progress
= false;
2547 mir_foreach_block(ctx
, block
) {
2548 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2549 progress
|= midgard_opt_copy_prop(ctx
, block
);
2550 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
2551 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2555 /* Nested control-flow can result in dead branches at the end of the
2556 * block. This messes with our analysis and is just dead code, so cull
2558 mir_foreach_block(ctx
, block
) {
2559 midgard_opt_cull_dead_branch(ctx
, block
);
2563 schedule_program(ctx
);
2565 /* Now that all the bundles are scheduled and we can calculate block
2566 * sizes, emit actual branch instructions rather than placeholders */
2568 int br_block_idx
= 0;
2570 mir_foreach_block(ctx
, block
) {
2571 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2572 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2573 midgard_instruction
*ins
= bundle
->instructions
[c
];
2575 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2577 if (ins
->prepacked_branch
) continue;
2579 /* Parse some basic branch info */
2580 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2581 bool is_conditional
= ins
->branch
.conditional
;
2582 bool is_inverted
= ins
->branch
.invert_conditional
;
2583 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2585 /* Determine the block we're jumping to */
2586 int target_number
= ins
->branch
.target_block
;
2588 /* Report the destination tag */
2589 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2591 /* Count up the number of quadwords we're
2592 * jumping over = number of quadwords until
2593 * (br_block_idx, target_number) */
2595 int quadword_offset
= 0;
2598 /* Jump to the end of the shader. We
2599 * need to include not only the
2600 * following blocks, but also the
2601 * contents of our current block (since
2602 * discard can come in the middle of
2605 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2607 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2608 quadword_offset
+= quadword_size(bun
->tag
);
2611 mir_foreach_block_from(ctx
, blk
, b
) {
2612 quadword_offset
+= b
->quadword_count
;
2615 } else if (target_number
> br_block_idx
) {
2618 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2619 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2622 quadword_offset
+= blk
->quadword_count
;
2625 /* Jump backwards */
2627 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2628 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2631 quadword_offset
-= blk
->quadword_count
;
2635 /* Unconditional extended branches (far jumps)
2636 * have issues, so we always use a conditional
2637 * branch, setting the condition to always for
2638 * unconditional. For compact unconditional
2639 * branches, cond isn't used so it doesn't
2640 * matter what we pick. */
2642 midgard_condition cond
=
2643 !is_conditional
? midgard_condition_always
:
2644 is_inverted
? midgard_condition_false
:
2645 midgard_condition_true
;
2647 midgard_jmp_writeout_op op
=
2648 is_discard
? midgard_jmp_writeout_op_discard
:
2649 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2650 midgard_jmp_writeout_op_branch_cond
;
2653 midgard_branch_extended branch
=
2654 midgard_create_branch_extended(
2659 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2660 } else if (is_conditional
|| is_discard
) {
2661 midgard_branch_cond branch
= {
2663 .dest_tag
= dest_tag
,
2664 .offset
= quadword_offset
,
2668 assert(branch
.offset
== quadword_offset
);
2670 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2672 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2674 midgard_branch_uncond branch
= {
2676 .dest_tag
= dest_tag
,
2677 .offset
= quadword_offset
,
2681 assert(branch
.offset
== quadword_offset
);
2683 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2691 /* Emit flat binary from the instruction arrays. Iterate each block in
2692 * sequence. Save instruction boundaries such that lookahead tags can
2693 * be assigned easily */
2695 /* Cache _all_ bundles in source order for lookahead across failed branches */
2697 int bundle_count
= 0;
2698 mir_foreach_block(ctx
, block
) {
2699 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2701 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2703 mir_foreach_block(ctx
, block
) {
2704 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2705 source_order_bundles
[bundle_idx
++] = bundle
;
2709 int current_bundle
= 0;
2711 /* Midgard prefetches instruction types, so during emission we
2712 * need to lookahead. Unless this is the last instruction, in
2713 * which we return 1. Or if this is the second to last and the
2714 * last is an ALU, then it's also 1... */
2716 mir_foreach_block(ctx
, block
) {
2717 mir_foreach_bundle_in_block(block
, bundle
) {
2720 if (current_bundle
+ 1 < bundle_count
) {
2721 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2723 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2730 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2734 /* TODO: Free deeper */
2735 //util_dynarray_fini(&block->instructions);
2738 free(source_order_bundles
);
2740 /* Report the very first tag executed */
2741 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2743 /* Deal with off-by-one related to the fencepost problem */
2744 program
->work_register_count
= ctx
->work_registers
+ 1;
2746 program
->can_discard
= ctx
->can_discard
;
2747 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2749 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2751 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2752 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);