2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 struct midgard_block
*next_fallthrough
;
175 /* Helpers to generate midgard_instruction's using macro magic, since every
176 * driver seems to do it that way */
178 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
180 #define M_LOAD_STORE(name, rname, uname) \
181 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
182 midgard_instruction i = { \
183 .type = TAG_LOAD_STORE_4, \
190 .op = midgard_op_##name, \
192 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
200 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
201 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
203 const midgard_vector_alu_src blank_alu_src
= {
204 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
207 const midgard_vector_alu_src blank_alu_src_xxxx
= {
208 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
211 const midgard_scalar_alu_src blank_scalar_alu_src
= {
215 /* Used for encoding the unused source of 1-op instructions */
216 const midgard_vector_alu_src zero_alu_src
= { 0 };
218 /* Coerce structs to integer */
221 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
224 memcpy(&u
, &src
, sizeof(src
));
228 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
229 * the corresponding Midgard source */
231 static midgard_vector_alu_src
232 vector_alu_modifiers(nir_alu_src
*src
)
234 if (!src
) return blank_alu_src
;
236 midgard_vector_alu_src alu_src
= {
238 .negate
= src
->negate
,
241 .half
= 0, /* TODO */
242 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
248 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
250 static midgard_instruction
251 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
253 midgard_instruction ins
= {
256 .src0
= SSA_UNUSED_1
,
261 .op
= midgard_alu_op_fmov
,
262 .reg_mode
= midgard_reg_mode_full
,
263 .dest_override
= midgard_dest_override_none
,
265 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
266 .src2
= vector_alu_srco_unsigned(mod
)
273 /* load/store instructions have both 32-bit and 16-bit variants, depending on
274 * whether we are using vectors composed of highp or mediump. At the moment, we
275 * don't support half-floats -- this requires changes in other parts of the
276 * compiler -- therefore the 16-bit versions are commented out. */
278 //M_LOAD(load_attr_16);
279 M_LOAD(load_attr_32
);
280 //M_LOAD(load_vary_16);
281 M_LOAD(load_vary_32
);
282 //M_LOAD(load_uniform_16);
283 M_LOAD(load_uniform_32
);
284 M_LOAD(load_color_buffer_8
);
285 //M_STORE(store_vary_16);
286 M_STORE(store_vary_32
);
288 static midgard_instruction
289 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
291 midgard_branch_cond branch
= {
299 memcpy(&compact
, &branch
, sizeof(branch
));
301 midgard_instruction ins
= {
303 .unit
= ALU_ENAB_BR_COMPACT
,
304 .prepacked_branch
= true,
305 .compact_branch
= true,
306 .br_compact
= compact
309 if (op
== midgard_jmp_writeout_op_writeout
)
315 static midgard_instruction
316 v_branch(bool conditional
, bool invert
)
318 midgard_instruction ins
= {
320 .unit
= ALU_ENAB_BRANCH
,
321 .compact_branch
= true,
323 .conditional
= conditional
,
324 .invert_conditional
= invert
331 static midgard_branch_extended
332 midgard_create_branch_extended( midgard_condition cond
,
333 midgard_jmp_writeout_op op
,
335 signed quadword_offset
)
337 /* For unclear reasons, the condition code is repeated 8 times */
338 uint16_t duplicated_cond
=
348 midgard_branch_extended branch
= {
350 .dest_tag
= dest_tag
,
351 .offset
= quadword_offset
,
352 .cond
= duplicated_cond
358 typedef struct midgard_bundle
{
359 /* Tag for the overall bundle */
362 /* Instructions contained by the bundle */
363 int instruction_count
;
364 midgard_instruction instructions
[5];
366 /* Bundle-wide ALU configuration */
369 bool has_embedded_constants
;
371 bool has_blend_constant
;
373 uint16_t register_words
[8];
374 int register_words_count
;
376 uint64_t body_words
[8];
378 int body_words_count
;
381 typedef struct compiler_context
{
383 gl_shader_stage stage
;
385 /* Is internally a blend shader? Depends on stage == FRAGMENT */
388 /* Tracking for blend constant patching */
389 int blend_constant_number
;
390 int blend_constant_offset
;
392 /* Current NIR function */
395 /* Unordered list of midgard_blocks */
397 struct list_head blocks
;
399 midgard_block
*initial_block
;
400 midgard_block
*previous_source_block
;
401 midgard_block
*final_block
;
403 /* List of midgard_instructions emitted for the current block */
404 midgard_block
*current_block
;
406 /* The index corresponding to the current loop, e.g. for breaks/contineus */
409 /* Constants which have been loaded, for later inlining */
410 struct hash_table_u64
*ssa_constants
;
412 /* SSA indices to be outputted to corresponding varying offset */
413 struct hash_table_u64
*ssa_varyings
;
415 /* SSA values / registers which have been aliased. Naively, these
416 * demand a fmov output; instead, we alias them in a later pass to
417 * avoid the wasted op.
419 * A note on encoding: to avoid dynamic memory management here, rather
420 * than ampping to a pointer, we map to the source index; the key
421 * itself is just the destination index. */
423 struct hash_table_u64
*ssa_to_alias
;
424 struct set
*leftover_ssa_to_alias
;
426 /* Actual SSA-to-register for RA */
427 struct hash_table_u64
*ssa_to_register
;
429 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
430 struct hash_table_u64
*hash_to_temp
;
434 /* Uniform IDs for mdg */
435 struct hash_table_u64
*uniform_nir_to_mdg
;
438 /* Just the count of the max register used. Higher count => higher
439 * register pressure */
442 /* Used for cont/last hinting. Increase when a tex op is added.
443 * Decrease when a tex op is removed. */
444 int texture_op_count
;
446 /* Mapping of texture register -> SSA index for unaliasing */
447 int texture_index
[2];
449 /* Count of special uniforms (viewport, etc) in vec4 units */
450 int special_uniforms
;
452 /* If any path hits a discard instruction */
455 /* The number of uniforms allowable for the fast path */
458 /* Count of instructions emitted from NIR overall, across all blocks */
459 int instruction_count
;
461 /* Alpha ref value passed in */
464 /* The index corresponding to the fragment output */
465 unsigned fragment_output
;
468 /* Append instruction to end of current block */
470 static midgard_instruction
*
471 mir_upload_ins(struct midgard_instruction ins
)
473 midgard_instruction
*heap
= malloc(sizeof(ins
));
474 memcpy(heap
, &ins
, sizeof(ins
));
479 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
481 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
485 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
487 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
491 mir_remove_instruction(struct midgard_instruction
*ins
)
493 list_del(&ins
->link
);
496 static midgard_instruction
*
497 mir_prev_op(struct midgard_instruction
*ins
)
499 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
502 static midgard_instruction
*
503 mir_next_op(struct midgard_instruction
*ins
)
505 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
508 static midgard_block
*
509 mir_next_block(struct midgard_block
*blk
)
511 return list_first_entry(&(blk
->link
), midgard_block
, link
);
515 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
516 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
518 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
519 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
520 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
521 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
522 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
523 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
526 static midgard_instruction
*
527 mir_last_in_block(struct midgard_block
*block
)
529 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
532 static midgard_block
*
533 mir_get_block(compiler_context
*ctx
, int idx
)
535 struct list_head
*lst
= &ctx
->blocks
;
540 return (struct midgard_block
*) lst
;
543 /* Pretty printer for internal Midgard IR */
546 print_mir_source(int source
)
548 if (source
>= SSA_FIXED_MINIMUM
) {
549 /* Specific register */
550 int reg
= SSA_REG_FROM_FIXED(source
);
552 /* TODO: Moving threshold */
553 if (reg
> 16 && reg
< 24)
554 printf("u%d", 23 - reg
);
558 printf("%d", source
);
563 print_mir_instruction(midgard_instruction
*ins
)
569 midgard_alu_op op
= ins
->alu
.op
;
570 const char *name
= alu_opcode_names
[op
];
573 printf("%d.", ins
->unit
);
575 printf("%s", name
? name
: "??");
579 case TAG_LOAD_STORE_4
: {
580 midgard_load_store_op op
= ins
->load_store
.op
;
581 const char *name
= load_store_opcode_names
[op
];
588 case TAG_TEXTURE_4
: {
597 ssa_args
*args
= &ins
->ssa_args
;
599 printf(" %d, ", args
->dest
);
601 print_mir_source(args
->src0
);
604 if (args
->inline_constant
)
605 printf("#%d", ins
->inline_constant
);
607 print_mir_source(args
->src1
);
609 if (ins
->has_constants
)
610 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
616 print_mir_block(midgard_block
*block
)
620 mir_foreach_instr_in_block(block
, ins
) {
621 print_mir_instruction(ins
);
630 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
632 ins
->has_constants
= true;
633 memcpy(&ins
->constants
, constants
, 16);
635 /* If this is the special blend constant, mark this instruction */
637 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
638 ins
->has_blend_constant
= true;
642 glsl_type_size(const struct glsl_type
*type
)
644 return glsl_count_attribute_slots(type
, false);
647 /* Lower fdot2 to a vector multiplication followed by channel addition */
649 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
651 if (alu
->op
!= nir_op_fdot2
)
654 b
->cursor
= nir_before_instr(&alu
->instr
);
656 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
657 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
659 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
661 nir_ssa_def
*sum
= nir_fadd(b
,
662 nir_channel(b
, product
, 0),
663 nir_channel(b
, product
, 1));
665 /* Replace the fdot2 with this sum */
666 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
670 midgard_nir_lower_fdot2(nir_shader
*shader
)
672 bool progress
= false;
674 nir_foreach_function(function
, shader
) {
675 if (!function
->impl
) continue;
678 nir_builder
*b
= &_b
;
679 nir_builder_init(b
, function
->impl
);
681 nir_foreach_block(block
, function
->impl
) {
682 nir_foreach_instr_safe(instr
, block
) {
683 if (instr
->type
!= nir_instr_type_alu
) continue;
685 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
686 midgard_nir_lower_fdot2_body(b
, alu
);
692 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
700 optimise_nir(nir_shader
*nir
)
704 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
705 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
707 nir_lower_tex_options lower_tex_options
= {
711 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
716 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
717 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
718 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
719 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
721 NIR_PASS(progress
, nir
, nir_copy_prop
);
722 NIR_PASS(progress
, nir
, nir_opt_dce
);
723 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
724 NIR_PASS(progress
, nir
, nir_opt_cse
);
725 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
726 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
727 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
728 NIR_PASS(progress
, nir
, nir_opt_undef
);
729 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
732 nir_var_function_temp
);
734 /* TODO: Enable vectorize when merged upstream */
735 // NIR_PASS(progress, nir, nir_opt_vectorize);
738 /* Must be run at the end to prevent creation of fsin/fcos ops */
739 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
744 NIR_PASS(progress
, nir
, nir_opt_dce
);
745 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
746 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
747 NIR_PASS(progress
, nir
, nir_copy_prop
);
750 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
753 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_all_source_mods
);
754 NIR_PASS(progress
, nir
, nir_copy_prop
);
755 NIR_PASS(progress
, nir
, nir_opt_dce
);
757 /* Take us out of SSA */
758 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
759 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
761 /* We are a vector architecture; write combine where possible */
762 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
763 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
765 NIR_PASS(progress
, nir
, nir_opt_dce
);
768 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
769 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
770 * r0. See the comments in compiler_context */
773 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
775 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
776 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
779 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
782 unalias_ssa(compiler_context
*ctx
, int dest
)
784 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
785 /* TODO: Remove from leftover or no? */
789 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
791 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
795 midgard_is_pinned(compiler_context
*ctx
, int index
)
797 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
800 /* Do not actually emit a load; instead, cache the constant for inlining */
803 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
805 nir_ssa_def def
= instr
->def
;
807 float *v
= ralloc_array(NULL
, float, 4);
808 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
809 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
812 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
816 expand_writemask(unsigned mask
)
820 for (int i
= 0; i
< 4; ++i
)
828 squeeze_writemask(unsigned mask
)
832 for (int i
= 0; i
< 4; ++i
)
833 if (mask
& (3 << (2 * i
)))
840 /* Determines effective writemask, taking quirks and expansion into account */
842 effective_writemask(midgard_vector_alu
*alu
)
844 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
847 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
849 /* If there is a fixed channel count, construct the appropriate mask */
852 return (1 << channel_count
) - 1;
854 /* Otherwise, just squeeze the existing mask */
855 return squeeze_writemask(alu
->mask
);
859 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
861 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
864 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
869 /* If no temp is find, allocate one */
870 temp
= ctx
->temp_count
++;
871 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
873 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
879 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
882 return src
->ssa
->index
;
884 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
888 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
891 return dst
->ssa
.index
;
893 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
897 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
899 return nir_src_index(ctx
, &src
->src
);
902 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
903 * a conditional test) into that register */
906 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
908 /* XXX: Force component correct */
909 int condition
= nir_src_index(ctx
, src
);
911 /* There is no boolean move instruction. Instead, we simulate a move by
912 * ANDing the condition with itself to get it into r31.w */
914 midgard_instruction ins
= {
916 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
920 .dest
= SSA_FIXED_REGISTER(31),
923 .op
= midgard_alu_op_iand
,
924 .reg_mode
= midgard_reg_mode_full
,
925 .dest_override
= midgard_dest_override_none
,
926 .mask
= (0x3 << 6), /* w */
927 .src1
= vector_alu_srco_unsigned(blank_alu_src_xxxx
),
928 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
932 emit_mir_instruction(ctx
, ins
);
935 #define ALU_CASE(nir, _op) \
937 op = midgard_alu_op_##_op; \
941 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
943 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
945 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
946 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
947 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
949 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
950 * supported. A few do not and are commented for now. Also, there are a
951 * number of NIR ops which Midgard does not support and need to be
952 * lowered, also TODO. This switch block emits the opcode and calling
953 * convention of the Midgard instruction; actual packing is done in
959 ALU_CASE(fadd
, fadd
);
960 ALU_CASE(fmul
, fmul
);
961 ALU_CASE(fmin
, fmin
);
962 ALU_CASE(fmax
, fmax
);
963 ALU_CASE(imin
, imin
);
964 ALU_CASE(imax
, imax
);
965 ALU_CASE(fmov
, fmov
);
966 ALU_CASE(ffloor
, ffloor
);
967 ALU_CASE(fround_even
, froundeven
);
968 ALU_CASE(ftrunc
, ftrunc
);
969 ALU_CASE(fceil
, fceil
);
970 ALU_CASE(fdot3
, fdot3
);
971 ALU_CASE(fdot4
, fdot4
);
972 ALU_CASE(iadd
, iadd
);
973 ALU_CASE(isub
, isub
);
974 ALU_CASE(imul
, imul
);
976 /* XXX: Use fmov, not imov, since imov was causing major
977 * issues with texture precision? XXX research */
978 ALU_CASE(imov
, fmov
);
987 ALU_CASE(frcp
, frcp
);
988 ALU_CASE(frsq
, frsqrt
);
989 ALU_CASE(fsqrt
, fsqrt
);
990 ALU_CASE(fpow
, fpow
);
991 ALU_CASE(fexp2
, fexp2
);
992 ALU_CASE(flog2
, flog2
);
994 ALU_CASE(f2i32
, f2i
);
995 ALU_CASE(f2u32
, f2u
);
996 ALU_CASE(i2f32
, i2f
);
997 ALU_CASE(u2f32
, u2f
);
999 ALU_CASE(fsin
, fsin
);
1000 ALU_CASE(fcos
, fcos
);
1002 ALU_CASE(iand
, iand
);
1004 ALU_CASE(ixor
, ixor
);
1005 ALU_CASE(inot
, inot
);
1006 ALU_CASE(ishl
, ishl
);
1007 ALU_CASE(ishr
, iasr
);
1008 ALU_CASE(ushr
, ilsr
);
1010 ALU_CASE(ball_fequal4
, fball_eq
);
1011 ALU_CASE(bany_fnequal4
, fbany_neq
);
1012 ALU_CASE(ball_iequal4
, iball_eq
);
1013 ALU_CASE(bany_inequal4
, ibany_neq
);
1015 /* For greater-or-equal, we use less-or-equal and flip the
1019 op
= midgard_alu_op_ile
;
1021 /* Swap via temporary */
1022 nir_alu_src temp
= instr
->src
[1];
1023 instr
->src
[1] = instr
->src
[0];
1024 instr
->src
[0] = temp
;
1029 case nir_op_bcsel
: {
1030 op
= midgard_alu_op_fcsel
;
1032 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1035 emit_condition(ctx
, &instr
->src
[0].src
, false);
1037 /* The condition is the first argument; move the other
1038 * arguments up one to be a binary instruction for
1041 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1045 /* We don't have a native b2f32 instruction. Instead, like many GPUs,
1046 * we exploit booleans as 0/~0 for false/true, and correspondingly AND
1047 * by 1.0 to do the type conversion. For the moment, prime us to emit:
1049 * iand [whatever], #0
1051 * At the end of emit_alu (as MIR), we'll fix-up the constant */
1053 case nir_op_b2f32
: {
1054 op
= midgard_alu_op_iand
;
1059 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1064 /* Fetch unit, quirks, etc information */
1065 unsigned opcode_props
= alu_opcode_props
[op
];
1066 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1068 /* Initialise fields common between scalar/vector instructions */
1069 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1071 /* src0 will always exist afaik, but src1 will not for 1-argument
1072 * instructions. The latter can only be fetched if the instruction
1073 * needs it, or else we may segfault. */
1075 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1076 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1078 /* Rather than use the instruction generation helpers, we do it
1079 * ourselves here to avoid the mess */
1081 midgard_instruction ins
= {
1084 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1085 .src1
= quirk_flipped_r24
? src0
: src1
,
1090 nir_alu_src
*nirmods
[2] = { NULL
};
1092 if (nr_inputs
== 2) {
1093 nirmods
[0] = &instr
->src
[0];
1094 nirmods
[1] = &instr
->src
[1];
1095 } else if (nr_inputs
== 1) {
1096 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1101 midgard_vector_alu alu
= {
1103 .reg_mode
= midgard_reg_mode_full
,
1104 .dest_override
= midgard_dest_override_none
,
1107 /* Writemask only valid for non-SSA NIR */
1108 .mask
= expand_writemask((1 << nr_components
) - 1),
1110 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1111 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1114 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1117 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1121 /* Late fixup for emulated instructions */
1123 if (instr
->op
== nir_op_b2f32
) {
1124 /* Presently, our second argument is an inline #0 constant.
1125 * Switch over to an embedded 1.0 constant (that can't fit
1126 * inline, since we're 32-bit, not 16-bit like the inline
1129 ins
.ssa_args
.inline_constant
= false;
1130 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1131 ins
.has_constants
= true;
1132 ins
.constants
[0] = 1.0;
1134 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1137 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1138 /* To avoid duplicating the lookup tables (probably), true LUT
1139 * instructions can only operate as if they were scalars. Lower
1140 * them here by changing the component. */
1142 uint8_t original_swizzle
[4];
1143 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1145 for (int i
= 0; i
< nr_components
; ++i
) {
1146 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1148 for (int j
= 0; j
< 4; ++j
)
1149 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1151 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1152 emit_mir_instruction(ctx
, ins
);
1155 emit_mir_instruction(ctx
, ins
);
1162 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1164 nir_const_value
*const_offset
;
1165 unsigned offset
, reg
;
1167 switch (instr
->intrinsic
) {
1168 case nir_intrinsic_discard_if
:
1169 emit_condition(ctx
, &instr
->src
[0], true);
1173 case nir_intrinsic_discard
: {
1174 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1175 struct midgard_instruction discard
= v_branch(conditional
, false);
1176 discard
.branch
.target_type
= TARGET_DISCARD
;
1177 emit_mir_instruction(ctx
, discard
);
1179 ctx
->can_discard
= true;
1183 case nir_intrinsic_load_uniform
:
1184 case nir_intrinsic_load_input
:
1185 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1186 assert (const_offset
&& "no indirect inputs");
1188 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1190 reg
= nir_dest_index(ctx
, &instr
->dest
);
1192 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1193 /* TODO: half-floats */
1195 int uniform_offset
= 0;
1197 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1198 /* XXX: Resolve which uniform */
1201 /* Offset away from the special
1204 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1208 DBG("WARNING: Unknown uniform %d\n", offset
);
1212 uniform_offset
= (uintptr_t) (entry
) - 1;
1213 uniform_offset
+= ctx
->special_uniforms
;
1216 if (uniform_offset
< ctx
->uniform_cutoff
) {
1217 /* Fast path: For the first 16 uniform,
1218 * accesses are 0-cycle, since they're
1219 * just a register fetch in the usual
1220 * case. So, we alias the registers
1221 * while we're still in SSA-space */
1223 int reg_slot
= 23 - uniform_offset
;
1224 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1226 /* Otherwise, read from the 'special'
1227 * UBO to access higher-indexed
1228 * uniforms, at a performance cost */
1230 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1232 /* TODO: Don't split */
1233 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1234 ins
.load_store
.address
= uniform_offset
>> 3;
1236 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1237 emit_mir_instruction(ctx
, ins
);
1239 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1240 /* XXX: Half-floats? */
1241 /* TODO: swizzle, mask */
1243 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1245 midgard_varying_parameter p
= {
1247 .interpolation
= midgard_interp_default
,
1248 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1252 memcpy(&u
, &p
, sizeof(p
));
1253 ins
.load_store
.varying_parameters
= u
;
1255 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1256 emit_mir_instruction(ctx
, ins
);
1257 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1258 /* Constant encoded as a pinned constant */
1260 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1261 ins
.has_constants
= true;
1262 ins
.has_blend_constant
= true;
1263 emit_mir_instruction(ctx
, ins
);
1264 } else if (ctx
->is_blend
) {
1265 /* For blend shaders, a load might be
1266 * translated various ways depending on what
1267 * we're loading. Figure out how this is used */
1269 nir_variable
*out
= NULL
;
1271 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1272 int drvloc
= var
->data
.driver_location
;
1274 if (nir_intrinsic_base(instr
) == drvloc
) {
1282 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1283 /* Source color preloaded to r0 */
1285 midgard_pin_output(ctx
, reg
, 0);
1286 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1287 /* Destination color must be read from framebuffer */
1289 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1290 ins
.load_store
.swizzle
= 0; /* xxxx */
1292 /* Read each component sequentially */
1294 for (int c
= 0; c
< 4; ++c
) {
1295 ins
.load_store
.mask
= (1 << c
);
1296 ins
.load_store
.unknown
= c
;
1297 emit_mir_instruction(ctx
, ins
);
1300 /* vadd.u2f hr2, abs(hr2), #0 */
1302 midgard_vector_alu_src alu_src
= blank_alu_src
;
1304 alu_src
.half
= true;
1306 midgard_instruction u2f
= {
1310 .src1
= SSA_UNUSED_0
,
1312 .inline_constant
= true
1315 .op
= midgard_alu_op_u2f
,
1316 .reg_mode
= midgard_reg_mode_half
,
1317 .dest_override
= midgard_dest_override_none
,
1319 .src1
= vector_alu_srco_unsigned(alu_src
),
1320 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1324 emit_mir_instruction(ctx
, u2f
);
1326 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1328 alu_src
.abs
= false;
1330 midgard_instruction fmul
= {
1332 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1336 .src1
= SSA_UNUSED_0
,
1337 .inline_constant
= true
1340 .op
= midgard_alu_op_fmul
,
1341 .reg_mode
= midgard_reg_mode_full
,
1342 .dest_override
= midgard_dest_override_none
,
1343 .outmod
= midgard_outmod_sat
,
1345 .src1
= vector_alu_srco_unsigned(alu_src
),
1346 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1350 emit_mir_instruction(ctx
, fmul
);
1352 DBG("Unknown input in blend shader\n");
1355 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1356 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1357 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1358 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1359 emit_mir_instruction(ctx
, ins
);
1361 DBG("Unknown load\n");
1367 case nir_intrinsic_store_output
:
1368 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1369 assert(const_offset
&& "no indirect outputs");
1371 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1373 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1375 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1376 /* gl_FragColor is not emitted with load/store
1377 * instructions. Instead, it gets plonked into
1378 * r0 at the end of the shader and we do the
1379 * framebuffer writeout dance. TODO: Defer
1382 midgard_pin_output(ctx
, reg
, 0);
1384 /* Save the index we're writing to for later reference
1385 * in the epilogue */
1387 ctx
->fragment_output
= reg
;
1388 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1389 /* Varyings are written into one of two special
1390 * varying register, r26 or r27. The register itself is selected as the register
1391 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1393 * Normally emitting fmov's is frowned upon,
1394 * but due to unique constraints of
1395 * REGISTER_VARYING, fmov emission + a
1396 * dedicated cleanup pass is the only way to
1397 * guarantee correctness when considering some
1398 * (common) edge cases XXX: FIXME */
1400 /* If this varying corresponds to a constant (why?!),
1401 * emit that now since it won't get picked up by
1402 * hoisting (since there is no corresponding move
1403 * emitted otherwise) */
1405 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1407 if (constant_value
) {
1408 /* Special case: emit the varying write
1409 * directly to r26 (looks funny in asm but it's
1410 * fine) and emit the store _now_. Possibly
1411 * slightly slower, but this is a really stupid
1412 * special case anyway (why on earth would you
1413 * have a constant varying? Your own fault for
1414 * slightly worse perf :P) */
1416 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1417 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1418 emit_mir_instruction(ctx
, ins
);
1420 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1421 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1422 emit_mir_instruction(ctx
, st
);
1424 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1426 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1429 DBG("Unknown store\n");
1435 case nir_intrinsic_load_alpha_ref_float
:
1436 assert(instr
->dest
.is_ssa
);
1438 float ref_value
= ctx
->alpha_ref
;
1440 float *v
= ralloc_array(NULL
, float, 4);
1441 memcpy(v
, &ref_value
, sizeof(float));
1442 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1447 printf ("Unhandled intrinsic\n");
1454 midgard_tex_format(enum glsl_sampler_dim dim
)
1457 case GLSL_SAMPLER_DIM_2D
:
1458 case GLSL_SAMPLER_DIM_EXTERNAL
:
1461 case GLSL_SAMPLER_DIM_3D
:
1464 case GLSL_SAMPLER_DIM_CUBE
:
1465 return TEXTURE_CUBE
;
1468 DBG("Unknown sampler dim type\n");
1475 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1478 //assert (!instr->sampler);
1479 //assert (!instr->texture_array_size);
1480 assert (instr
->op
== nir_texop_tex
);
1482 /* Allocate registers via a round robin scheme to alternate between the two registers */
1483 int reg
= ctx
->texture_op_count
& 1;
1484 int in_reg
= reg
, out_reg
= reg
;
1486 /* Make room for the reg */
1488 if (ctx
->texture_index
[reg
] > -1)
1489 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1491 int texture_index
= instr
->texture_index
;
1492 int sampler_index
= texture_index
;
1494 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1495 switch (instr
->src
[i
].src_type
) {
1496 case nir_tex_src_coord
: {
1497 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1499 midgard_vector_alu_src alu_src
= blank_alu_src
;
1500 alu_src
.swizzle
= (COMPONENT_Y
<< 2);
1502 midgard_instruction ins
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
));
1503 emit_mir_instruction(ctx
, ins
);
1505 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1511 DBG("Unknown source type\n");
1518 /* No helper to build texture words -- we do it all here */
1519 midgard_instruction ins
= {
1520 .type
= TAG_TEXTURE_4
,
1522 .op
= TEXTURE_OP_NORMAL
,
1523 .format
= midgard_tex_format(instr
->sampler_dim
),
1524 .texture_handle
= texture_index
,
1525 .sampler_handle
= sampler_index
,
1527 /* TODO: Don't force xyzw */
1528 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1540 /* Assume we can continue; hint it out later */
1545 /* Set registers to read and write from the same place */
1546 ins
.texture
.in_reg_select
= in_reg
;
1547 ins
.texture
.out_reg_select
= out_reg
;
1549 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1550 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1551 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1552 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1553 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1555 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1556 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1557 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1560 emit_mir_instruction(ctx
, ins
);
1562 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1564 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1565 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1566 ctx
->texture_index
[reg
] = o_index
;
1568 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1569 emit_mir_instruction(ctx
, ins2
);
1571 /* Used for .cont and .last hinting */
1572 ctx
->texture_op_count
++;
1576 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1578 switch (instr
->type
) {
1579 case nir_jump_break
: {
1580 /* Emit a branch out of the loop */
1581 struct midgard_instruction br
= v_branch(false, false);
1582 br
.branch
.target_type
= TARGET_BREAK
;
1583 br
.branch
.target_break
= ctx
->current_loop
;
1584 emit_mir_instruction(ctx
, br
);
1591 DBG("Unknown jump type %d\n", instr
->type
);
1597 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1599 switch (instr
->type
) {
1600 case nir_instr_type_load_const
:
1601 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1604 case nir_instr_type_intrinsic
:
1605 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1608 case nir_instr_type_alu
:
1609 emit_alu(ctx
, nir_instr_as_alu(instr
));
1612 case nir_instr_type_tex
:
1613 emit_tex(ctx
, nir_instr_as_tex(instr
));
1616 case nir_instr_type_jump
:
1617 emit_jump(ctx
, nir_instr_as_jump(instr
));
1620 case nir_instr_type_ssa_undef
:
1625 DBG("Unhandled instruction type\n");
1630 /* Determine the actual hardware from the index based on the RA results or special values */
1633 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1635 if (reg
>= SSA_FIXED_MINIMUM
)
1636 return SSA_REG_FROM_FIXED(reg
);
1639 assert(reg
< maxreg
);
1640 int r
= ra_get_node_reg(g
, reg
);
1641 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1646 /* fmov style unused */
1648 return REGISTER_UNUSED
;
1650 /* lut style unused */
1652 return REGISTER_UNUSED
;
1655 DBG("Unknown SSA register alias %d\n", reg
);
1662 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1664 /* Choose the first available register to minimise reported register pressure */
1666 for (int i
= 0; i
< 16; ++i
) {
1667 if (BITSET_TEST(regs
, i
)) {
1677 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1679 if (ins
->ssa_args
.src0
== src
) return true;
1680 if (ins
->ssa_args
.src1
== src
) return true;
1686 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1688 /* Check the rest of the block for liveness */
1689 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1690 if (midgard_is_live_in_instr(ins
, src
))
1694 /* Check the rest of the blocks for liveness */
1695 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1696 mir_foreach_instr_in_block(b
, ins
) {
1697 if (midgard_is_live_in_instr(ins
, src
))
1702 /* TODO: How does control flow interact in complex shaders? */
1708 allocate_registers(compiler_context
*ctx
)
1710 /* First, initialize the RA */
1711 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1713 /* Create a primary (general purpose) class, as well as special purpose
1714 * pipeline register classes */
1716 int primary_class
= ra_alloc_reg_class(regs
);
1717 int varying_class
= ra_alloc_reg_class(regs
);
1719 /* Add the full set of work registers */
1720 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1721 for (int i
= 0; i
< work_count
; ++i
)
1722 ra_class_add_reg(regs
, primary_class
, i
);
1724 /* Add special registers */
1725 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1726 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1728 /* We're done setting up */
1729 ra_set_finalize(regs
, NULL
);
1731 /* Transform the MIR into squeezed index form */
1732 mir_foreach_block(ctx
, block
) {
1733 mir_foreach_instr_in_block(block
, ins
) {
1734 if (ins
->compact_branch
) continue;
1736 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1737 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1738 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1740 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1741 print_mir_block(block
);
1744 /* Let's actually do register allocation */
1745 int nodes
= ctx
->temp_count
;
1746 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1748 /* Set everything to the work register class, unless it has somewhere
1751 mir_foreach_block(ctx
, block
) {
1752 mir_foreach_instr_in_block(block
, ins
) {
1753 if (ins
->compact_branch
) continue;
1755 if (ins
->ssa_args
.dest
< 0) continue;
1757 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1759 int class = primary_class
;
1761 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1765 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1766 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1769 unsigned reg
= temp
- 1;
1770 int t
= find_or_allocate_temp(ctx
, index
);
1771 ra_set_node_reg(g
, t
, reg
);
1775 /* Determine liveness */
1777 int *live_start
= malloc(nodes
* sizeof(int));
1778 int *live_end
= malloc(nodes
* sizeof(int));
1780 /* Initialize as non-existent */
1782 for (int i
= 0; i
< nodes
; ++i
) {
1783 live_start
[i
] = live_end
[i
] = -1;
1788 mir_foreach_block(ctx
, block
) {
1789 mir_foreach_instr_in_block(block
, ins
) {
1790 if (ins
->compact_branch
) continue;
1792 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1793 /* If this destination is not yet live, it is now since we just wrote it */
1795 int dest
= ins
->ssa_args
.dest
;
1797 if (live_start
[dest
] == -1)
1798 live_start
[dest
] = d
;
1801 /* Since we just used a source, the source might be
1802 * dead now. Scan the rest of the block for
1803 * invocations, and if there are none, the source dies
1806 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1808 for (int src
= 0; src
< 2; ++src
) {
1809 int s
= sources
[src
];
1811 if (s
< 0) continue;
1813 if (s
>= SSA_FIXED_MINIMUM
) continue;
1815 if (!is_live_after(ctx
, block
, ins
, s
)) {
1824 /* If a node still hasn't been killed, kill it now */
1826 for (int i
= 0; i
< nodes
; ++i
) {
1827 /* live_start == -1 most likely indicates a pinned output */
1829 if (live_end
[i
] == -1)
1833 /* Setup interference between nodes that are live at the same time */
1835 for (int i
= 0; i
< nodes
; ++i
) {
1836 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1837 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1838 ra_add_node_interference(g
, i
, j
);
1842 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1844 if (!ra_allocate(g
)) {
1845 DBG("Error allocating registers\n");
1853 mir_foreach_block(ctx
, block
) {
1854 mir_foreach_instr_in_block(block
, ins
) {
1855 if (ins
->compact_branch
) continue;
1857 ssa_args args
= ins
->ssa_args
;
1859 switch (ins
->type
) {
1861 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1863 ins
->registers
.src2_imm
= args
.inline_constant
;
1865 if (args
.inline_constant
) {
1866 /* Encode inline 16-bit constant as a vector by default */
1868 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1870 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1872 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1873 ins
->alu
.src2
= imm
<< 2;
1875 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1878 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1882 case TAG_LOAD_STORE_4
: {
1883 if (OP_IS_STORE(ins
->load_store
.op
)) {
1884 /* TODO: use ssa_args for store_vary */
1885 ins
->load_store
.reg
= 0;
1887 bool has_dest
= args
.dest
>= 0;
1888 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1890 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1903 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1904 * use scalar ALU instructions, for functional or performance reasons. To do
1905 * this, we just demote vector ALU payloads to scalar. */
1908 component_from_mask(unsigned mask
)
1910 for (int c
= 0; c
< 4; ++c
) {
1911 if (mask
& (3 << (2 * c
)))
1920 is_single_component_mask(unsigned mask
)
1924 for (int c
= 0; c
< 4; ++c
)
1925 if (mask
& (3 << (2 * c
)))
1928 return components
== 1;
1931 /* Create a mask of accessed components from a swizzle to figure out vector
1935 swizzle_to_access_mask(unsigned swizzle
)
1937 unsigned component_mask
= 0;
1939 for (int i
= 0; i
< 4; ++i
) {
1940 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1941 component_mask
|= (1 << c
);
1944 return component_mask
;
1948 vector_to_scalar_source(unsigned u
)
1950 midgard_vector_alu_src v
;
1951 memcpy(&v
, &u
, sizeof(v
));
1953 midgard_scalar_alu_src s
= {
1957 .component
= (v
.swizzle
& 3) << 1
1961 memcpy(&o
, &s
, sizeof(s
));
1963 return o
& ((1 << 6) - 1);
1966 static midgard_scalar_alu
1967 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1969 /* The output component is from the mask */
1970 midgard_scalar_alu s
= {
1972 .src1
= vector_to_scalar_source(v
.src1
),
1973 .src2
= vector_to_scalar_source(v
.src2
),
1976 .output_full
= 1, /* TODO: Half */
1977 .output_component
= component_from_mask(v
.mask
) << 1,
1980 /* Inline constant is passed along rather than trying to extract it
1983 if (ins
->ssa_args
.inline_constant
) {
1985 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1986 imm
|= (lower_11
>> 9) & 3;
1987 imm
|= (lower_11
>> 6) & 4;
1988 imm
|= (lower_11
>> 2) & 0x38;
1989 imm
|= (lower_11
& 63) << 6;
1997 /* Midgard prefetches instruction types, so during emission we need to
1998 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1999 * if this is the second to last and the last is an ALU, then it's also 1... */
2001 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2002 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2004 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2005 bytes_emitted += sizeof(type)
2008 emit_binary_vector_instruction(midgard_instruction
*ains
,
2009 uint16_t *register_words
, int *register_words_count
,
2010 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2011 size_t *bytes_emitted
)
2013 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2014 *bytes_emitted
+= sizeof(midgard_reg_info
);
2016 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2017 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2018 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2021 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2022 * mind that we are a vector architecture and we can write to different
2023 * components simultaneously */
2026 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2028 /* Each instruction reads some registers and writes to a register. See
2029 * where the first writes */
2031 /* Figure out where exactly we wrote to */
2032 int source
= first
->ssa_args
.dest
;
2033 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2035 /* As long as the second doesn't read from the first, we're okay */
2036 if (second
->ssa_args
.src0
== source
) {
2037 if (first
->type
== TAG_ALU_4
) {
2038 /* Figure out which components we just read from */
2040 int q
= second
->alu
.src1
;
2041 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2043 /* Check if there are components in common, and fail if so */
2044 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2051 if (second
->ssa_args
.src1
== source
)
2054 /* Otherwise, it's safe in that regard. Another data hazard is both
2055 * writing to the same place, of course */
2057 if (second
->ssa_args
.dest
== source
) {
2058 /* ...but only if the components overlap */
2059 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2061 if (dest_mask
& source_mask
)
2071 midgard_instruction
**segment
, unsigned segment_size
,
2072 midgard_instruction
*ains
)
2074 for (int s
= 0; s
< segment_size
; ++s
)
2075 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2083 /* Schedules, but does not emit, a single basic block. After scheduling, the
2084 * final tag and size of the block are known, which are necessary for branching
2087 static midgard_bundle
2088 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2090 int instructions_emitted
= 0, instructions_consumed
= -1;
2091 midgard_bundle bundle
= { 0 };
2093 uint8_t tag
= ins
->type
;
2095 /* Default to the instruction's tag */
2098 switch (ins
->type
) {
2100 uint32_t control
= 0;
2101 size_t bytes_emitted
= sizeof(control
);
2103 /* TODO: Constant combining */
2104 int index
= 0, last_unit
= 0;
2106 /* Previous instructions, for the purpose of parallelism */
2107 midgard_instruction
*segment
[4] = {0};
2108 int segment_size
= 0;
2110 instructions_emitted
= -1;
2111 midgard_instruction
*pins
= ins
;
2114 midgard_instruction
*ains
= pins
;
2116 /* Advance instruction pointer */
2118 ains
= mir_next_op(pins
);
2122 /* Out-of-work condition */
2123 if ((struct list_head
*) ains
== &block
->instructions
)
2126 /* Ensure that the chain can continue */
2127 if (ains
->type
!= TAG_ALU_4
) break;
2129 /* According to the presentation "The ARM
2130 * Mali-T880 Mobile GPU" from HotChips 27,
2131 * there are two pipeline stages. Branching
2132 * position determined experimentally. Lines
2133 * are executed in parallel:
2136 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2138 * Verify that there are no ordering dependencies here.
2140 * TODO: Allow for parallelism!!!
2143 /* Pick a unit for it if it doesn't force a particular unit */
2145 int unit
= ains
->unit
;
2148 int op
= ains
->alu
.op
;
2149 int units
= alu_opcode_props
[op
];
2151 /* TODO: Promotion of scalars to vectors */
2152 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2155 assert(units
& UNITS_SCALAR
);
2158 if (last_unit
>= UNIT_VADD
) {
2159 if (units
& UNIT_VLUT
)
2164 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2166 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2168 else if (units
& UNIT_VLUT
)
2174 if (last_unit
>= UNIT_VADD
) {
2175 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2177 else if (units
& UNIT_VLUT
)
2182 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2184 else if (units
& UNIT_SMUL
)
2185 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2186 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2193 assert(unit
& units
);
2196 /* Late unit check, this time for encoding (not parallelism) */
2197 if (unit
<= last_unit
) break;
2199 /* Clear the segment */
2200 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2203 if (midgard_has_hazard(segment
, segment_size
, ains
))
2206 /* We're good to go -- emit the instruction */
2209 segment
[segment_size
++] = ains
;
2211 /* Only one set of embedded constants per
2212 * bundle possible; if we have more, we must
2213 * break the chain early, unfortunately */
2215 if (ains
->has_constants
) {
2216 if (bundle
.has_embedded_constants
) {
2217 /* ...but if there are already
2218 * constants but these are the
2219 * *same* constants, we let it
2222 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2225 bundle
.has_embedded_constants
= true;
2226 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2228 /* If this is a blend shader special constant, track it for patching */
2229 if (ains
->has_blend_constant
)
2230 bundle
.has_blend_constant
= true;
2234 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2235 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2236 &bundle
.register_words_count
, bundle
.body_words
,
2237 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2238 } else if (ains
->compact_branch
) {
2239 /* All of r0 has to be written out
2240 * along with the branch writeout.
2243 if (ains
->writeout
) {
2245 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2246 ins
.unit
= UNIT_VMUL
;
2248 control
|= ins
.unit
;
2250 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2251 &bundle
.register_words_count
, bundle
.body_words
,
2252 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2254 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2255 bool written_late
= false;
2256 bool components
[4] = { 0 };
2257 uint16_t register_dep_mask
= 0;
2258 uint16_t written_mask
= 0;
2260 midgard_instruction
*qins
= ins
;
2261 for (int t
= 0; t
< index
; ++t
) {
2262 if (qins
->registers
.out_reg
!= 0) {
2263 /* Mark down writes */
2265 written_mask
|= (1 << qins
->registers
.out_reg
);
2267 /* Mark down the register dependencies for errata check */
2269 if (qins
->registers
.src1_reg
< 16)
2270 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2272 if (qins
->registers
.src2_reg
< 16)
2273 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2275 int mask
= qins
->alu
.mask
;
2277 for (int c
= 0; c
< 4; ++c
)
2278 if (mask
& (0x3 << (2 * c
)))
2279 components
[c
] = true;
2281 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2283 if (qins
->unit
== UNIT_VLUT
)
2284 written_late
= true;
2287 /* Advance instruction pointer */
2288 qins
= mir_next_op(qins
);
2292 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2293 if (register_dep_mask
& written_mask
) {
2294 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2301 /* If even a single component is not written, break it up (conservative check). */
2302 bool breakup
= false;
2304 for (int c
= 0; c
< 4; ++c
)
2311 /* Otherwise, we're free to proceed */
2315 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2316 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2317 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2318 bytes_emitted
+= sizeof(midgard_branch_extended
);
2320 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2321 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2322 bytes_emitted
+= sizeof(ains
->br_compact
);
2325 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2326 bytes_emitted
+= sizeof(midgard_reg_info
);
2328 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2329 bundle
.body_words_count
++;
2330 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2333 /* Defer marking until after writing to allow for break */
2334 control
|= ains
->unit
;
2335 last_unit
= ains
->unit
;
2336 ++instructions_emitted
;
2340 /* Bubble up the number of instructions for skipping */
2341 instructions_consumed
= index
- 1;
2345 /* Pad ALU op to nearest word */
2347 if (bytes_emitted
& 15) {
2348 padding
= 16 - (bytes_emitted
& 15);
2349 bytes_emitted
+= padding
;
2352 /* Constants must always be quadwords */
2353 if (bundle
.has_embedded_constants
)
2354 bytes_emitted
+= 16;
2356 /* Size ALU instruction for tag */
2357 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2358 bundle
.padding
= padding
;
2359 bundle
.control
= bundle
.tag
| control
;
2364 case TAG_LOAD_STORE_4
: {
2365 /* Load store instructions have two words at once. If
2366 * we only have one queued up, we need to NOP pad.
2367 * Otherwise, we store both in succession to save space
2368 * and cycles -- letting them go in parallel -- skip
2369 * the next. The usefulness of this optimisation is
2370 * greatly dependent on the quality of the instruction
2374 midgard_instruction
*next_op
= mir_next_op(ins
);
2376 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2377 /* As the two operate concurrently, make sure
2378 * they are not dependent */
2380 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2381 /* Skip ahead, since it's redundant with the pair */
2382 instructions_consumed
= 1 + (instructions_emitted
++);
2390 /* Texture ops default to single-op-per-bundle scheduling */
2394 /* Copy the instructions into the bundle */
2395 bundle
.instruction_count
= instructions_emitted
+ 1;
2399 midgard_instruction
*uins
= ins
;
2400 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2401 bundle
.instructions
[used_idx
++] = *uins
;
2402 uins
= mir_next_op(uins
);
2405 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2411 quadword_size(int tag
)
2426 case TAG_LOAD_STORE_4
:
2438 /* Schedule a single block by iterating its instruction to create bundles.
2439 * While we go, tally about the bundle sizes to compute the block size. */
2442 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2444 util_dynarray_init(&block
->bundles
, NULL
);
2446 block
->quadword_count
= 0;
2448 mir_foreach_instr_in_block(block
, ins
) {
2450 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2451 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2453 if (bundle
.has_blend_constant
) {
2454 /* TODO: Multiblock? */
2455 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2456 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2460 ins
= mir_next_op(ins
);
2462 block
->quadword_count
+= quadword_size(bundle
.tag
);
2465 block
->is_scheduled
= true;
2469 schedule_program(compiler_context
*ctx
)
2471 allocate_registers(ctx
);
2473 mir_foreach_block(ctx
, block
) {
2474 schedule_block(ctx
, block
);
2478 /* After everything is scheduled, emit whole bundles at a time */
2481 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2483 int lookahead
= next_tag
<< 4;
2485 switch (bundle
->tag
) {
2490 /* Actually emit each component */
2491 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2493 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2494 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2496 /* Emit body words based on the instructions bundled */
2497 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2498 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2500 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2501 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2502 } else if (ins
->compact_branch
) {
2503 /* Dummy move, XXX DRY */
2504 if ((i
== 0) && ins
->writeout
) {
2505 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2506 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2509 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2510 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2512 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2516 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2517 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2521 /* Emit padding (all zero) */
2522 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2524 /* Tack on constants */
2526 if (bundle
->has_embedded_constants
) {
2527 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2528 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2529 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2530 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2536 case TAG_LOAD_STORE_4
: {
2537 /* One or two composing instructions */
2539 uint64_t current64
, next64
= LDST_NOP
;
2541 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2543 if (bundle
->instruction_count
== 2)
2544 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2546 midgard_load_store instruction
= {
2547 .type
= bundle
->tag
,
2548 .next_type
= next_tag
,
2553 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2558 case TAG_TEXTURE_4
: {
2559 /* Texture instructions are easy, since there is no
2560 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2562 midgard_instruction
*ins
= &bundle
->instructions
[0];
2564 ins
->texture
.type
= TAG_TEXTURE_4
;
2565 ins
->texture
.next_type
= next_tag
;
2567 ctx
->texture_op_count
--;
2569 if (!ctx
->texture_op_count
) {
2570 ins
->texture
.cont
= 0;
2571 ins
->texture
.last
= 1;
2574 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2579 DBG("Unknown midgard instruction type\n");
2586 /* ALU instructions can inline or embed constants, which decreases register
2587 * pressure and saves space. */
2589 #define CONDITIONAL_ATTACH(src) { \
2590 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2593 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2594 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2599 inline_alu_constants(compiler_context
*ctx
)
2601 mir_foreach_instr(ctx
, alu
) {
2602 /* Other instructions cannot inline constants */
2603 if (alu
->type
!= TAG_ALU_4
) continue;
2605 /* If there is already a constant here, we can do nothing */
2606 if (alu
->has_constants
) continue;
2608 CONDITIONAL_ATTACH(src0
);
2610 if (!alu
->has_constants
) {
2611 CONDITIONAL_ATTACH(src1
)
2612 } else if (!alu
->inline_constant
) {
2613 /* Corner case: _two_ vec4 constants, for instance with a
2614 * csel. For this case, we can only use a constant
2615 * register for one, we'll have to emit a move for the
2616 * other. Note, if both arguments are constants, then
2617 * necessarily neither argument depends on the value of
2618 * any particular register. As the destination register
2619 * will be wiped, that means we can spill the constant
2620 * to the destination register.
2623 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2624 unsigned scratch
= alu
->ssa_args
.dest
;
2627 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2628 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2630 /* Force a break XXX Defer r31 writes */
2631 ins
.unit
= UNIT_VLUT
;
2633 /* Set the source */
2634 alu
->ssa_args
.src1
= scratch
;
2636 /* Inject us -before- the last instruction which set r31 */
2637 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2643 /* Midgard supports two types of constants, embedded constants (128-bit) and
2644 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2645 * constants can be demoted to inline constants, for space savings and
2646 * sometimes a performance boost */
2649 embedded_to_inline_constant(compiler_context
*ctx
)
2651 mir_foreach_instr(ctx
, ins
) {
2652 if (!ins
->has_constants
) continue;
2654 if (ins
->ssa_args
.inline_constant
) continue;
2656 /* Blend constants must not be inlined by definition */
2657 if (ins
->has_blend_constant
) continue;
2659 /* src1 cannot be an inline constant due to encoding
2660 * restrictions. So, if possible we try to flip the arguments
2663 int op
= ins
->alu
.op
;
2665 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2666 /* Flip based on op. Fallthrough intentional */
2669 /* These ops require an operational change to flip their arguments TODO */
2670 case midgard_alu_op_flt
:
2671 case midgard_alu_op_fle
:
2672 case midgard_alu_op_ilt
:
2673 case midgard_alu_op_ile
:
2674 case midgard_alu_op_fcsel
:
2675 case midgard_alu_op_icsel
:
2676 case midgard_alu_op_isub
:
2677 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2680 /* These ops are commutative and Just Flip */
2681 case midgard_alu_op_fne
:
2682 case midgard_alu_op_fadd
:
2683 case midgard_alu_op_fmul
:
2684 case midgard_alu_op_fmin
:
2685 case midgard_alu_op_fmax
:
2686 case midgard_alu_op_iadd
:
2687 case midgard_alu_op_imul
:
2688 case midgard_alu_op_feq
:
2689 case midgard_alu_op_ieq
:
2690 case midgard_alu_op_ine
:
2691 case midgard_alu_op_iand
:
2692 case midgard_alu_op_ior
:
2693 case midgard_alu_op_ixor
:
2694 /* Flip the SSA numbers */
2695 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2696 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2698 /* And flip the modifiers */
2702 src_temp
= ins
->alu
.src2
;
2703 ins
->alu
.src2
= ins
->alu
.src1
;
2704 ins
->alu
.src1
= src_temp
;
2711 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2712 /* Extract the source information */
2714 midgard_vector_alu_src
*src
;
2715 int q
= ins
->alu
.src2
;
2716 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2719 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2720 int component
= src
->swizzle
& 3;
2722 /* Scale constant appropriately, if we can legally */
2723 uint16_t scaled_constant
= 0;
2725 /* XXX: Check legality */
2726 if (midgard_is_integer_op(op
)) {
2727 /* TODO: Inline integer */
2730 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2731 scaled_constant
= (uint16_t) iconstants
[component
];
2733 /* Constant overflow after resize */
2734 if (scaled_constant
!= iconstants
[component
])
2737 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2740 /* We don't know how to handle these with a constant */
2742 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2743 DBG("Bailing inline constant...\n");
2747 /* Make sure that the constant is not itself a
2748 * vector by checking if all accessed values
2749 * (by the swizzle) are the same. */
2751 uint32_t *cons
= (uint32_t *) ins
->constants
;
2752 uint32_t value
= cons
[component
];
2754 bool is_vector
= false;
2755 unsigned mask
= effective_writemask(&ins
->alu
);
2757 for (int c
= 1; c
< 4; ++c
) {
2758 /* We only care if this component is actually used */
2759 if (!(mask
& (1 << c
)))
2762 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2764 if (test
!= value
) {
2773 /* Get rid of the embedded constant */
2774 ins
->has_constants
= false;
2775 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2776 ins
->ssa_args
.inline_constant
= true;
2777 ins
->inline_constant
= scaled_constant
;
2782 /* Map normal SSA sources to other SSA sources / fixed registers (like
2786 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2788 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2791 /* Remove entry in leftovers to avoid a redunant fmov */
2793 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2796 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2798 /* Assign the alias map */
2804 #define AS_SRC(to, u) \
2805 int q##to = ins->alu.src2; \
2806 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2808 /* Removing unused moves is necessary to clean up the texture pipeline results.
2810 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2813 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2815 mir_foreach_instr_in_block_safe(block
, ins
) {
2816 if (ins
->type
!= TAG_ALU_4
) continue;
2818 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2820 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2822 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2824 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2826 mir_remove_instruction(ins
);
2830 /* The following passes reorder MIR instructions to enable better scheduling */
2833 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2835 mir_foreach_instr_in_block_safe(block
, ins
) {
2836 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2838 /* We've found a load/store op. Check if next is also load/store. */
2839 midgard_instruction
*next_op
= mir_next_op(ins
);
2840 if (&next_op
->link
!= &block
->instructions
) {
2841 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2842 /* If so, we're done since we're a pair */
2843 ins
= mir_next_op(ins
);
2847 /* Maximum search distance to pair, to avoid register pressure disasters */
2848 int search_distance
= 8;
2850 /* Otherwise, we have an orphaned load/store -- search for another load */
2851 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2852 /* Terminate search if necessary */
2853 if (!(search_distance
--)) break;
2855 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2857 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2859 /* We found one! Move it up to pair and remove it from the old location */
2861 mir_insert_instruction_before(ins
, *c
);
2862 mir_remove_instruction(c
);
2870 /* Emit varying stores late */
2873 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2874 /* Iterate in reverse to get the final write, rather than the first */
2876 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2877 /* Check if what we just wrote needs a store */
2878 int idx
= ins
->ssa_args
.dest
;
2879 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2881 if (!varying
) continue;
2885 /* We need to store to the appropriate varying, so emit the
2888 /* TODO: Integrate with special purpose RA (and scheduler?) */
2889 bool high_varying_register
= false;
2891 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2893 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2894 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2896 mir_insert_instruction_before(mir_next_op(ins
), st
);
2897 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2899 /* We no longer need to store this varying */
2900 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2904 /* If there are leftovers after the below pass, emit actual fmov
2905 * instructions for the slow-but-correct path */
2908 emit_leftover_move(compiler_context
*ctx
)
2910 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2911 int base
= ((uintptr_t) leftover
->key
) - 1;
2914 map_ssa_to_alias(ctx
, &mapped
);
2915 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2920 actualise_ssa_to_alias(compiler_context
*ctx
)
2922 mir_foreach_instr(ctx
, ins
) {
2923 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2924 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2927 emit_leftover_move(ctx
);
2930 /* Vertex shaders do not write gl_Position as is; instead, they write a
2931 * transformed screen space position as a varying. See section 12.5 "Coordinate
2932 * Transformation" of the ES 3.2 full specification for details.
2934 * This transformation occurs early on, as NIR and prior to optimisation, in
2935 * order to take advantage of NIR optimisation passes of the transform itself.
2939 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
2941 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
2943 /* Get viewport from the uniforms */
2944 nir_intrinsic_instr
*load
;
2945 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
2946 load
->num_components
= 4;
2947 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
2948 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
2949 nir_builder_instr_insert(b
, &load
->instr
);
2951 /* Formatted as <width, height, centerx, centery> */
2952 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
2953 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
2954 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
2955 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
2957 /* XXX: From uniforms? */
2958 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
2959 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
2961 /* World space to normalised device coordinates */
2963 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
2964 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
2966 /* Normalised device coordinates to screen space */
2968 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
2969 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
2971 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2972 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2973 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
2975 /* gl_Position will be written out in screenspace xyz, with w set to
2976 * the reciprocal we computed earlier. The transformed w component is
2977 * then used for perspective-correct varying interpolation. The
2978 * transformed w component must preserve its original sign; this is
2979 * used in depth clipping computations */
2981 nir_ssa_def
*screen_space
= nir_vec4(b
,
2982 nir_channel(b
, viewport_xy
, 0),
2983 nir_channel(b
, viewport_xy
, 1),
2987 /* Finally, write out the transformed values to the varying */
2989 nir_intrinsic_instr
*store
;
2990 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
2991 store
->num_components
= 4;
2992 nir_intrinsic_set_base(store
, 0);
2993 nir_intrinsic_set_write_mask(store
, 0xf);
2994 store
->src
[0].ssa
= screen_space
;
2995 store
->src
[0].is_ssa
= true;
2996 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
2997 nir_builder_instr_insert(b
, &store
->instr
);
3001 transform_position_writes(nir_shader
*shader
)
3003 nir_foreach_function(func
, shader
) {
3004 nir_foreach_block(block
, func
->impl
) {
3005 nir_foreach_instr_safe(instr
, block
) {
3006 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
3008 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
3009 nir_variable
*out
= NULL
;
3011 switch (intr
->intrinsic
) {
3012 case nir_intrinsic_store_output
:
3013 /* already had i/o lowered.. lookup the matching output var: */
3014 nir_foreach_variable(var
, &shader
->outputs
) {
3015 int drvloc
= var
->data
.driver_location
;
3017 if (nir_intrinsic_base(intr
) == drvloc
) {
3031 if (out
->data
.mode
!= nir_var_shader_out
)
3034 if (out
->data
.location
!= VARYING_SLOT_POS
)
3038 nir_builder_init(&b
, func
->impl
);
3039 b
.cursor
= nir_before_instr(instr
);
3041 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
3042 nir_instr_remove(instr
);
3049 emit_fragment_epilogue(compiler_context
*ctx
)
3051 /* Special case: writing out constants requires us to include the move
3052 * explicitly now, so shove it into r0 */
3054 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3056 if (constant_value
) {
3057 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3058 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3059 emit_mir_instruction(ctx
, ins
);
3062 /* Perform the actual fragment writeout. We have two writeout/branch
3063 * instructions, forming a loop until writeout is successful as per the
3064 * docs. TODO: gl_FragDepth */
3066 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3067 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3070 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3071 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3072 * with the int8 analogue to the fragment epilogue */
3075 emit_blend_epilogue(compiler_context
*ctx
)
3077 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3079 midgard_instruction scale
= {
3082 .inline_constant
= _mesa_float_to_half(255.0),
3084 .src0
= SSA_FIXED_REGISTER(0),
3085 .src1
= SSA_UNUSED_0
,
3086 .dest
= SSA_FIXED_REGISTER(24),
3087 .inline_constant
= true
3090 .op
= midgard_alu_op_fmul
,
3091 .reg_mode
= midgard_reg_mode_full
,
3092 .dest_override
= midgard_dest_override_lower
,
3094 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3095 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3099 emit_mir_instruction(ctx
, scale
);
3101 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3103 midgard_vector_alu_src alu_src
= blank_alu_src
;
3104 alu_src
.half
= true;
3106 midgard_instruction f2u8
= {
3109 .src0
= SSA_FIXED_REGISTER(24),
3110 .src1
= SSA_UNUSED_0
,
3111 .dest
= SSA_FIXED_REGISTER(0),
3112 .inline_constant
= true
3115 .op
= midgard_alu_op_f2u8
,
3116 .reg_mode
= midgard_reg_mode_half
,
3117 .dest_override
= midgard_dest_override_lower
,
3118 .outmod
= midgard_outmod_pos
,
3120 .src1
= vector_alu_srco_unsigned(alu_src
),
3121 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3125 emit_mir_instruction(ctx
, f2u8
);
3127 /* vmul.imov.quarter r0, r0, r0 */
3129 midgard_instruction imov_8
= {
3132 .src0
= SSA_UNUSED_1
,
3133 .src1
= SSA_FIXED_REGISTER(0),
3134 .dest
= SSA_FIXED_REGISTER(0),
3137 .op
= midgard_alu_op_imov
,
3138 .reg_mode
= midgard_reg_mode_quarter
,
3139 .dest_override
= midgard_dest_override_none
,
3141 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3142 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3146 /* Emit branch epilogue with the 8-bit move as the source */
3148 emit_mir_instruction(ctx
, imov_8
);
3149 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3151 emit_mir_instruction(ctx
, imov_8
);
3152 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3155 static midgard_block
*
3156 emit_block(compiler_context
*ctx
, nir_block
*block
)
3158 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3159 list_addtail(&this_block
->link
, &ctx
->blocks
);
3161 this_block
->is_scheduled
= false;
3164 ctx
->texture_index
[0] = -1;
3165 ctx
->texture_index
[1] = -1;
3167 /* Set up current block */
3168 list_inithead(&this_block
->instructions
);
3169 ctx
->current_block
= this_block
;
3171 nir_foreach_instr(instr
, block
) {
3172 emit_instr(ctx
, instr
);
3173 ++ctx
->instruction_count
;
3176 inline_alu_constants(ctx
);
3177 embedded_to_inline_constant(ctx
);
3179 /* Perform heavylifting for aliasing */
3180 actualise_ssa_to_alias(ctx
);
3182 midgard_emit_store(ctx
, this_block
);
3183 midgard_eliminate_orphan_moves(ctx
, this_block
);
3184 midgard_pair_load_store(ctx
, this_block
);
3186 /* Append fragment shader epilogue (value writeout) */
3187 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3188 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3190 emit_blend_epilogue(ctx
);
3192 emit_fragment_epilogue(ctx
);
3196 /* Fallthrough save */
3197 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3199 if (block
== nir_start_block(ctx
->func
->impl
))
3200 ctx
->initial_block
= this_block
;
3202 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3203 ctx
->final_block
= this_block
;
3205 /* Allow the next control flow to access us retroactively, for
3207 ctx
->current_block
= this_block
;
3209 /* Document the fallthrough chain */
3210 ctx
->previous_source_block
= this_block
;
3215 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3218 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3220 /* Conditional branches expect the condition in r31.w; emit a move for
3221 * that in the _previous_ block (which is the current block). */
3222 emit_condition(ctx
, &nif
->condition
, true);
3224 /* Speculatively emit the branch, but we can't fill it in until later */
3225 EMIT(branch
, true, true);
3226 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3228 /* Emit the two subblocks */
3229 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3231 /* Emit a jump from the end of the then block to the end of the else */
3232 EMIT(branch
, false, false);
3233 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3235 /* Emit second block, and check if it's empty */
3237 int else_idx
= ctx
->block_count
;
3238 int count_in
= ctx
->instruction_count
;
3239 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3240 int after_else_idx
= ctx
->block_count
;
3242 /* Now that we have the subblocks emitted, fix up the branches */
3247 if (ctx
->instruction_count
== count_in
) {
3248 /* The else block is empty, so don't emit an exit jump */
3249 mir_remove_instruction(then_exit
);
3250 then_branch
->branch
.target_block
= after_else_idx
;
3252 then_branch
->branch
.target_block
= else_idx
;
3253 then_exit
->branch
.target_block
= after_else_idx
;
3258 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3260 /* Remember where we are */
3261 midgard_block
*start_block
= ctx
->current_block
;
3263 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3264 * single current_loop variable, maybe we need a stack */
3266 int loop_idx
= ++ctx
->current_loop
;
3268 /* Get index from before the body so we can loop back later */
3269 int start_idx
= ctx
->block_count
;
3271 /* Emit the body itself */
3272 emit_cf_list(ctx
, &nloop
->body
);
3274 /* Branch back to loop back */
3275 struct midgard_instruction br_back
= v_branch(false, false);
3276 br_back
.branch
.target_block
= start_idx
;
3277 emit_mir_instruction(ctx
, br_back
);
3279 /* Find the index of the block about to follow us (note: we don't add
3280 * one; blocks are 0-indexed so we get a fencepost problem) */
3281 int break_block_idx
= ctx
->block_count
;
3283 /* Fix up the break statements we emitted to point to the right place,
3284 * now that we can allocate a block number for them */
3286 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3287 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3288 print_mir_block(block
);
3289 mir_foreach_instr_in_block(block
, ins
) {
3290 if (ins
->type
!= TAG_ALU_4
) continue;
3291 if (!ins
->compact_branch
) continue;
3292 if (ins
->prepacked_branch
) continue;
3294 /* We found a branch -- check the type to see if we need to do anything */
3295 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3297 /* It's a break! Check if it's our break */
3298 if (ins
->branch
.target_break
!= loop_idx
) continue;
3300 /* Okay, cool, we're breaking out of this loop.
3301 * Rewrite from a break to a goto */
3303 ins
->branch
.target_type
= TARGET_GOTO
;
3304 ins
->branch
.target_block
= break_block_idx
;
3309 static midgard_block
*
3310 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3312 midgard_block
*start_block
= NULL
;
3314 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3315 switch (node
->type
) {
3316 case nir_cf_node_block
: {
3317 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3320 start_block
= block
;
3325 case nir_cf_node_if
:
3326 emit_if(ctx
, nir_cf_node_as_if(node
));
3329 case nir_cf_node_loop
:
3330 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3333 case nir_cf_node_function
:
3342 /* Due to lookahead, we need to report the first tag executed in the command
3343 * stream and in branch targets. An initial block might be empty, so iterate
3344 * until we find one that 'works' */
3347 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3349 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3351 unsigned first_tag
= 0;
3354 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3356 if (initial_bundle
) {
3357 first_tag
= initial_bundle
->tag
;
3361 /* Initial block is empty, try the next block */
3362 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3363 } while(initial_block
!= NULL
);
3370 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3372 struct util_dynarray
*compiled
= &program
->compiled
;
3374 midgard_debug
= debug_get_option_midgard_debug();
3376 compiler_context ictx
= {
3378 .stage
= nir
->info
.stage
,
3380 .is_blend
= is_blend
,
3381 .blend_constant_offset
= -1,
3383 .alpha_ref
= program
->alpha_ref
3386 compiler_context
*ctx
= &ictx
;
3388 /* TODO: Decide this at runtime */
3389 ctx
->uniform_cutoff
= 8;
3391 switch (ctx
->stage
) {
3392 case MESA_SHADER_VERTEX
:
3393 ctx
->special_uniforms
= 1;
3397 ctx
->special_uniforms
= 0;
3401 /* Append epilogue uniforms if necessary. The cmdstream depends on
3402 * these being at the -end-; see assign_var_locations. */
3404 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3405 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3408 /* Assign var locations early, so the epilogue can use them if necessary */
3410 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3411 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3412 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3414 /* Initialize at a global (not block) level hash tables */
3416 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3417 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3418 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3419 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3420 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3421 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3423 /* Assign actual uniform location, skipping over samplers */
3425 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3427 nir_foreach_variable(var
, &nir
->uniforms
) {
3428 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3430 unsigned length
= glsl_get_aoa_size(var
->type
);
3433 length
= glsl_get_length(var
->type
);
3437 length
= glsl_get_matrix_columns(var
->type
);
3440 for (int col
= 0; col
< length
; ++col
) {
3441 int id
= ctx
->uniform_count
++;
3442 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3446 /* Record the varying mapping for the command stream's bookkeeping */
3448 struct exec_list
*varyings
=
3449 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3451 nir_foreach_variable(var
, varyings
) {
3452 unsigned loc
= var
->data
.driver_location
;
3453 program
->varyings
[loc
] = var
->data
.location
;
3456 /* Lower vars -- not I/O -- before epilogue */
3458 NIR_PASS_V(nir
, nir_lower_var_copies
);
3459 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3460 NIR_PASS_V(nir
, nir_split_var_copies
);
3461 NIR_PASS_V(nir
, nir_lower_var_copies
);
3462 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3463 NIR_PASS_V(nir
, nir_lower_var_copies
);
3464 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3465 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3467 /* Append vertex epilogue before optimisation, so the epilogue itself
3470 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3471 transform_position_writes(nir
);
3473 /* Optimisation passes */
3477 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3478 nir_print_shader(nir
, stdout
);
3481 /* Assign counts, now that we're sure (post-optimisation) */
3482 program
->uniform_count
= nir
->num_uniforms
;
3484 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3485 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3488 nir_foreach_function(func
, nir
) {
3492 list_inithead(&ctx
->blocks
);
3493 ctx
->block_count
= 0;
3496 emit_cf_list(ctx
, &func
->impl
->body
);
3497 emit_block(ctx
, func
->impl
->end_block
);
3499 break; /* TODO: Multi-function shaders */
3502 util_dynarray_init(compiled
, NULL
);
3505 schedule_program(ctx
);
3507 /* Now that all the bundles are scheduled and we can calculate block
3508 * sizes, emit actual branch instructions rather than placeholders */
3510 int br_block_idx
= 0;
3512 mir_foreach_block(ctx
, block
) {
3513 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3514 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3515 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3517 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3519 if (ins
->prepacked_branch
) continue;
3521 /* Parse some basic branch info */
3522 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3523 bool is_conditional
= ins
->branch
.conditional
;
3524 bool is_inverted
= ins
->branch
.invert_conditional
;
3525 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3527 /* Determine the block we're jumping to */
3528 int target_number
= ins
->branch
.target_block
;
3530 /* Report the destination tag. Discards don't need this */
3531 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3533 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3534 int quadword_offset
= 0;
3537 /* Jump to the end of the shader. We
3538 * need to include not only the
3539 * following blocks, but also the
3540 * contents of our current block (since
3541 * discard can come in the middle of
3544 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3546 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3547 quadword_offset
+= quadword_size(bun
->tag
);
3550 mir_foreach_block_from(ctx
, blk
, b
) {
3551 quadword_offset
+= b
->quadword_count
;
3554 } else if (target_number
> br_block_idx
) {
3557 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3558 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3561 quadword_offset
+= blk
->quadword_count
;
3564 /* Jump backwards */
3566 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3567 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3570 quadword_offset
-= blk
->quadword_count
;
3574 /* Unconditional extended branches (far jumps)
3575 * have issues, so we always use a conditional
3576 * branch, setting the condition to always for
3577 * unconditional. For compact unconditional
3578 * branches, cond isn't used so it doesn't
3579 * matter what we pick. */
3581 midgard_condition cond
=
3582 !is_conditional
? midgard_condition_always
:
3583 is_inverted
? midgard_condition_false
:
3584 midgard_condition_true
;
3586 midgard_jmp_writeout_op op
=
3587 is_discard
? midgard_jmp_writeout_op_discard
:
3588 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3589 midgard_jmp_writeout_op_branch_cond
;
3592 midgard_branch_extended branch
=
3593 midgard_create_branch_extended(
3598 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3599 } else if (is_conditional
|| is_discard
) {
3600 midgard_branch_cond branch
= {
3602 .dest_tag
= dest_tag
,
3603 .offset
= quadword_offset
,
3607 assert(branch
.offset
== quadword_offset
);
3609 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3611 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3613 midgard_branch_uncond branch
= {
3615 .dest_tag
= dest_tag
,
3616 .offset
= quadword_offset
,
3620 assert(branch
.offset
== quadword_offset
);
3622 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3630 /* Emit flat binary from the instruction arrays. Iterate each block in
3631 * sequence. Save instruction boundaries such that lookahead tags can
3632 * be assigned easily */
3634 /* Cache _all_ bundles in source order for lookahead across failed branches */
3636 int bundle_count
= 0;
3637 mir_foreach_block(ctx
, block
) {
3638 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3640 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3642 mir_foreach_block(ctx
, block
) {
3643 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3644 source_order_bundles
[bundle_idx
++] = bundle
;
3648 int current_bundle
= 0;
3650 mir_foreach_block(ctx
, block
) {
3651 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3654 if (current_bundle
+ 1 < bundle_count
) {
3655 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3657 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3664 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3668 /* TODO: Free deeper */
3669 //util_dynarray_fini(&block->instructions);
3672 free(source_order_bundles
);
3674 /* Report the very first tag executed */
3675 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3677 /* Deal with off-by-one related to the fencepost problem */
3678 program
->work_register_count
= ctx
->work_registers
+ 1;
3680 program
->can_discard
= ctx
->can_discard
;
3681 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3683 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3685 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3686 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);