2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
60 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
62 int midgard_debug
= 0;
64 #define DBG(fmt, ...) \
65 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
66 fprintf(stderr, "%s:%d: "fmt, \
67 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
70 midgard_is_branch_unit(unsigned unit
)
72 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
76 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
78 block
->successors
[block
->nr_successors
++] = successor
;
79 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
82 /* Helpers to generate midgard_instruction's using macro magic, since every
83 * driver seems to do it that way */
85 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
97 .op = midgard_op_##name, \
99 .swizzle = SWIZZLE_XYZW, \
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
)
116 if (!src
) return blank_alu_src
;
118 /* Figure out how many components there are so we can adjust the
119 * swizzle. Specifically we want to broadcast the last channel so
120 * things like ball2/3 work
123 if (broadcast_count
) {
124 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
126 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
127 src
->swizzle
[c
] = last_component
;
131 midgard_vector_alu_src alu_src
= {
134 .half
= 0, /* TODO */
135 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
139 /* TODO: sign-extend/zero-extend */
140 alu_src
.mod
= midgard_int_normal
;
142 /* These should have been lowered away */
143 assert(!(src
->abs
|| src
->negate
));
145 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
151 /* load/store instructions have both 32-bit and 16-bit variants, depending on
152 * whether we are using vectors composed of highp or mediump. At the moment, we
153 * don't support half-floats -- this requires changes in other parts of the
154 * compiler -- therefore the 16-bit versions are commented out. */
156 //M_LOAD(ld_attr_16);
158 //M_LOAD(ld_vary_16);
160 //M_LOAD(ld_uniform_16);
161 M_LOAD(ld_uniform_32
);
162 M_LOAD(ld_color_buffer_8
);
163 //M_STORE(st_vary_16);
165 M_STORE(st_cubemap_coords
);
167 static midgard_instruction
168 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
170 midgard_branch_cond branch
= {
178 memcpy(&compact
, &branch
, sizeof(branch
));
180 midgard_instruction ins
= {
182 .unit
= ALU_ENAB_BR_COMPACT
,
183 .prepacked_branch
= true,
184 .compact_branch
= true,
185 .br_compact
= compact
188 if (op
== midgard_jmp_writeout_op_writeout
)
194 static midgard_instruction
195 v_branch(bool conditional
, bool invert
)
197 midgard_instruction ins
= {
199 .unit
= ALU_ENAB_BRANCH
,
200 .compact_branch
= true,
202 .conditional
= conditional
,
203 .invert_conditional
= invert
210 static midgard_branch_extended
211 midgard_create_branch_extended( midgard_condition cond
,
212 midgard_jmp_writeout_op op
,
214 signed quadword_offset
)
216 /* For unclear reasons, the condition code is repeated 8 times */
217 uint16_t duplicated_cond
=
227 midgard_branch_extended branch
= {
229 .dest_tag
= dest_tag
,
230 .offset
= quadword_offset
,
231 .cond
= duplicated_cond
238 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
240 ins
->has_constants
= true;
241 memcpy(&ins
->constants
, constants
, 16);
245 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
247 return glsl_count_attribute_slots(type
, false);
250 /* Lower fdot2 to a vector multiplication followed by channel addition */
252 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
254 if (alu
->op
!= nir_op_fdot2
)
257 b
->cursor
= nir_before_instr(&alu
->instr
);
259 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
260 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
262 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
264 nir_ssa_def
*sum
= nir_fadd(b
,
265 nir_channel(b
, product
, 0),
266 nir_channel(b
, product
, 1));
268 /* Replace the fdot2 with this sum */
269 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
273 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
275 switch (instr
->intrinsic
) {
276 case nir_intrinsic_load_viewport_scale
:
277 return PAN_SYSVAL_VIEWPORT_SCALE
;
278 case nir_intrinsic_load_viewport_offset
:
279 return PAN_SYSVAL_VIEWPORT_OFFSET
;
286 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
289 return dst
->ssa
.index
;
291 assert(!dst
->reg
.indirect
);
292 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
296 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
299 nir_intrinsic_instr
*intr
;
300 nir_dest
*dst
= NULL
;
304 switch (instr
->type
) {
305 case nir_instr_type_intrinsic
:
306 intr
= nir_instr_as_intrinsic(instr
);
307 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
310 case nir_instr_type_tex
:
311 tex
= nir_instr_as_tex(instr
);
312 if (tex
->op
!= nir_texop_txs
)
315 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
316 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
317 nir_tex_instr_dest_size(tex
) -
318 (tex
->is_array
? 1 : 0),
327 *dest
= nir_dest_index(ctx
, dst
);
333 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
337 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
341 /* We have a sysval load; check if it's already been assigned */
343 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
346 /* It hasn't -- so assign it now! */
348 unsigned id
= ctx
->sysval_count
++;
349 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
350 ctx
->sysvals
[id
] = sysval
;
354 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
356 ctx
->sysval_count
= 0;
358 nir_foreach_function(function
, shader
) {
359 if (!function
->impl
) continue;
361 nir_foreach_block(block
, function
->impl
) {
362 nir_foreach_instr_safe(instr
, block
) {
363 midgard_nir_assign_sysval_body(ctx
, instr
);
370 midgard_nir_lower_fdot2(nir_shader
*shader
)
372 bool progress
= false;
374 nir_foreach_function(function
, shader
) {
375 if (!function
->impl
) continue;
378 nir_builder
*b
= &_b
;
379 nir_builder_init(b
, function
->impl
);
381 nir_foreach_block(block
, function
->impl
) {
382 nir_foreach_instr_safe(instr
, block
) {
383 if (instr
->type
!= nir_instr_type_alu
) continue;
385 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
386 midgard_nir_lower_fdot2_body(b
, alu
);
392 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
400 optimise_nir(nir_shader
*nir
)
403 unsigned lower_flrp
=
404 (nir
->options
->lower_flrp16
? 16 : 0) |
405 (nir
->options
->lower_flrp32
? 32 : 0) |
406 (nir
->options
->lower_flrp64
? 64 : 0);
408 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
409 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
410 NIR_PASS(progress
, nir
, nir_lower_idiv
);
412 nir_lower_tex_options lower_tex_1st_pass_options
= {
417 nir_lower_tex_options lower_tex_2nd_pass_options
= {
418 .lower_txs_lod
= true,
421 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
422 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
427 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
428 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
430 NIR_PASS(progress
, nir
, nir_copy_prop
);
431 NIR_PASS(progress
, nir
, nir_opt_dce
);
432 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
433 NIR_PASS(progress
, nir
, nir_opt_cse
);
434 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
435 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
436 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
438 if (lower_flrp
!= 0) {
439 bool lower_flrp_progress
= false;
440 NIR_PASS(lower_flrp_progress
,
444 false /* always_precise */,
445 nir
->options
->lower_ffma
);
446 if (lower_flrp_progress
) {
447 NIR_PASS(progress
, nir
,
448 nir_opt_constant_folding
);
452 /* Nothing should rematerialize any flrps, so we only
453 * need to do this lowering once.
458 NIR_PASS(progress
, nir
, nir_opt_undef
);
459 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
462 nir_var_function_temp
);
464 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
467 /* Must be run at the end to prevent creation of fsin/fcos ops */
468 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
473 NIR_PASS(progress
, nir
, nir_opt_dce
);
474 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
475 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
476 NIR_PASS(progress
, nir
, nir_copy_prop
);
479 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
481 /* We implement booleans as 32-bit 0/~0 */
482 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
484 /* Now that booleans are lowered, we can run out late opts */
485 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
487 /* Lower mods for float ops only. Integer ops don't support modifiers
488 * (saturate doesn't make sense on integers, neg/abs require dedicated
491 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
492 NIR_PASS(progress
, nir
, nir_copy_prop
);
493 NIR_PASS(progress
, nir
, nir_opt_dce
);
495 /* Take us out of SSA */
496 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
497 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
499 /* We are a vector architecture; write combine where possible */
500 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
501 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
503 NIR_PASS(progress
, nir
, nir_opt_dce
);
506 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
507 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
508 * r0. See the comments in compiler_context */
511 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
513 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
514 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
517 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
520 unalias_ssa(compiler_context
*ctx
, int dest
)
522 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
523 /* TODO: Remove from leftover or no? */
526 /* Do not actually emit a load; instead, cache the constant for inlining */
529 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
531 nir_ssa_def def
= instr
->def
;
533 float *v
= rzalloc_array(NULL
, float, 4);
534 nir_const_load_to_arr(v
, instr
, f32
);
535 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
539 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
542 return src
->ssa
->index
;
544 assert(!src
->reg
.indirect
);
545 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
550 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
552 return nir_src_index(ctx
, &src
->src
);
556 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
558 unsigned comp
= src
->swizzle
[0];
560 for (unsigned c
= 1; c
< nr_components
; ++c
) {
561 if (src
->swizzle
[c
] != comp
)
568 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
569 * output of a conditional test) into that register */
572 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
574 int condition
= nir_src_index(ctx
, src
);
576 /* Source to swizzle the desired component into w */
578 const midgard_vector_alu_src alu_src
= {
579 .swizzle
= SWIZZLE(component
, component
, component
, component
),
582 /* There is no boolean move instruction. Instead, we simulate a move by
583 * ANDing the condition with itself to get it into r31.w */
585 midgard_instruction ins
= {
588 /* We need to set the conditional as close as possible */
589 .precede_break
= true,
590 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
595 .dest
= SSA_FIXED_REGISTER(31),
599 .op
= midgard_alu_op_iand
,
600 .outmod
= midgard_outmod_int_wrap
,
601 .reg_mode
= midgard_reg_mode_32
,
602 .dest_override
= midgard_dest_override_none
,
603 .mask
= (0x3 << 6), /* w */
604 .src1
= vector_alu_srco_unsigned(alu_src
),
605 .src2
= vector_alu_srco_unsigned(alu_src
)
609 emit_mir_instruction(ctx
, ins
);
612 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
616 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
618 int condition
= nir_src_index(ctx
, &src
->src
);
620 /* Source to swizzle the desired component into w */
622 const midgard_vector_alu_src alu_src
= {
623 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
626 /* There is no boolean move instruction. Instead, we simulate a move by
627 * ANDing the condition with itself to get it into r31.w */
629 midgard_instruction ins
= {
631 .precede_break
= true,
635 .dest
= SSA_FIXED_REGISTER(31),
638 .op
= midgard_alu_op_iand
,
639 .outmod
= midgard_outmod_int_wrap
,
640 .reg_mode
= midgard_reg_mode_32
,
641 .dest_override
= midgard_dest_override_none
,
642 .mask
= expand_writemask(mask_of(nr_comp
)),
643 .src1
= vector_alu_srco_unsigned(alu_src
),
644 .src2
= vector_alu_srco_unsigned(alu_src
)
648 emit_mir_instruction(ctx
, ins
);
653 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
654 * pinning to eliminate this move in all known cases */
657 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
659 int offset
= nir_src_index(ctx
, src
);
661 midgard_instruction ins
= {
664 .src0
= SSA_UNUSED_1
,
666 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
669 .op
= midgard_alu_op_imov
,
670 .outmod
= midgard_outmod_int_wrap
,
671 .reg_mode
= midgard_reg_mode_32
,
672 .dest_override
= midgard_dest_override_none
,
673 .mask
= (0x3 << 6), /* w */
674 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
675 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
679 emit_mir_instruction(ctx
, ins
);
682 #define ALU_CASE(nir, _op) \
684 op = midgard_alu_op_##_op; \
687 #define ALU_CASE_BCAST(nir, _op, count) \
689 op = midgard_alu_op_##_op; \
690 broadcast_swizzle = count; \
693 nir_is_fzero_constant(nir_src src
)
695 if (!nir_src_is_const(src
))
698 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
699 if (nir_src_comp_as_float(src
, c
) != 0.0)
707 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
709 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
711 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
712 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
713 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
715 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
716 * supported. A few do not and are commented for now. Also, there are a
717 * number of NIR ops which Midgard does not support and need to be
718 * lowered, also TODO. This switch block emits the opcode and calling
719 * convention of the Midgard instruction; actual packing is done in
724 /* Number of components valid to check for the instruction (the rest
725 * will be forced to the last), or 0 to use as-is. Relevant as
726 * ball-type instructions have a channel count in NIR but are all vec4
729 unsigned broadcast_swizzle
= 0;
732 ALU_CASE(fadd
, fadd
);
733 ALU_CASE(fmul
, fmul
);
734 ALU_CASE(fmin
, fmin
);
735 ALU_CASE(fmax
, fmax
);
736 ALU_CASE(imin
, imin
);
737 ALU_CASE(imax
, imax
);
738 ALU_CASE(umin
, umin
);
739 ALU_CASE(umax
, umax
);
740 ALU_CASE(ffloor
, ffloor
);
741 ALU_CASE(fround_even
, froundeven
);
742 ALU_CASE(ftrunc
, ftrunc
);
743 ALU_CASE(fceil
, fceil
);
744 ALU_CASE(fdot3
, fdot3
);
745 ALU_CASE(fdot4
, fdot4
);
746 ALU_CASE(iadd
, iadd
);
747 ALU_CASE(isub
, isub
);
748 ALU_CASE(imul
, imul
);
750 /* Zero shoved as second-arg */
751 ALU_CASE(iabs
, iabsdiff
);
755 ALU_CASE(feq32
, feq
);
756 ALU_CASE(fne32
, fne
);
757 ALU_CASE(flt32
, flt
);
758 ALU_CASE(ieq32
, ieq
);
759 ALU_CASE(ine32
, ine
);
760 ALU_CASE(ilt32
, ilt
);
761 ALU_CASE(ult32
, ult
);
763 /* We don't have a native b2f32 instruction. Instead, like many
764 * GPUs, we exploit booleans as 0/~0 for false/true, and
765 * correspondingly AND
766 * by 1.0 to do the type conversion. For the moment, prime us
769 * iand [whatever], #0
771 * At the end of emit_alu (as MIR), we'll fix-up the constant
774 ALU_CASE(b2f32
, iand
);
775 ALU_CASE(b2i32
, iand
);
777 /* Likewise, we don't have a dedicated f2b32 instruction, but
778 * we can do a "not equal to 0.0" test. */
780 ALU_CASE(f2b32
, fne
);
781 ALU_CASE(i2b32
, ine
);
783 ALU_CASE(frcp
, frcp
);
784 ALU_CASE(frsq
, frsqrt
);
785 ALU_CASE(fsqrt
, fsqrt
);
786 ALU_CASE(fexp2
, fexp2
);
787 ALU_CASE(flog2
, flog2
);
789 ALU_CASE(f2i32
, f2i_rtz
);
790 ALU_CASE(f2u32
, f2u_rtz
);
791 ALU_CASE(i2f32
, i2f_rtz
);
792 ALU_CASE(u2f32
, u2f_rtz
);
794 ALU_CASE(fsin
, fsin
);
795 ALU_CASE(fcos
, fcos
);
797 /* Second op implicit #0 */
798 ALU_CASE(inot
, inor
);
799 ALU_CASE(iand
, iand
);
801 ALU_CASE(ixor
, ixor
);
802 ALU_CASE(ishl
, ishl
);
803 ALU_CASE(ishr
, iasr
);
804 ALU_CASE(ushr
, ilsr
);
806 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
807 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
808 ALU_CASE(b32all_fequal4
, fball_eq
);
810 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
811 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
812 ALU_CASE(b32any_fnequal4
, fbany_neq
);
814 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
815 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
816 ALU_CASE(b32all_iequal4
, iball_eq
);
818 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
819 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
820 ALU_CASE(b32any_inequal4
, ibany_neq
);
822 /* Source mods will be shoved in later */
823 ALU_CASE(fabs
, fmov
);
824 ALU_CASE(fneg
, fmov
);
825 ALU_CASE(fsat
, fmov
);
827 /* For greater-or-equal, we lower to less-or-equal and flip the
835 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
836 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
837 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
838 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
841 /* Swap via temporary */
842 nir_alu_src temp
= instr
->src
[1];
843 instr
->src
[1] = instr
->src
[0];
844 instr
->src
[0] = temp
;
849 case nir_op_b32csel
: {
850 /* Midgard features both fcsel and icsel, depending on
851 * the type of the arguments/output. However, as long
852 * as we're careful we can _always_ use icsel and
853 * _never_ need fcsel, since the latter does additional
854 * floating-point-specific processing whereas the
855 * former just moves bits on the wire. It's not obvious
856 * why these are separate opcodes, save for the ability
857 * to do things like sat/pos/abs/neg for free */
859 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
860 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
862 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
865 /* Emit the condition into r31 */
868 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
870 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
872 /* The condition is the first argument; move the other
873 * arguments up one to be a binary instruction for
876 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
881 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
886 /* Midgard can perform certain modifiers on output of an ALU op */
889 if (midgard_is_integer_out_op(op
)) {
890 outmod
= midgard_outmod_int_wrap
;
892 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
893 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
896 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
898 if (instr
->op
== nir_op_fmax
) {
899 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
900 op
= midgard_alu_op_fmov
;
902 outmod
= midgard_outmod_pos
;
903 instr
->src
[0] = instr
->src
[1];
904 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
905 op
= midgard_alu_op_fmov
;
907 outmod
= midgard_outmod_pos
;
911 /* Fetch unit, quirks, etc information */
912 unsigned opcode_props
= alu_opcode_props
[op
].props
;
913 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
915 /* src0 will always exist afaik, but src1 will not for 1-argument
916 * instructions. The latter can only be fetched if the instruction
917 * needs it, or else we may segfault. */
919 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
920 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
922 /* Rather than use the instruction generation helpers, we do it
923 * ourselves here to avoid the mess */
925 midgard_instruction ins
= {
928 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
929 .src1
= quirk_flipped_r24
? src0
: src1
,
934 nir_alu_src
*nirmods
[2] = { NULL
};
936 if (nr_inputs
== 2) {
937 nirmods
[0] = &instr
->src
[0];
938 nirmods
[1] = &instr
->src
[1];
939 } else if (nr_inputs
== 1) {
940 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
945 /* These were lowered to a move, so apply the corresponding mod */
947 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
948 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
950 if (instr
->op
== nir_op_fneg
)
951 s
->negate
= !s
->negate
;
953 if (instr
->op
== nir_op_fabs
)
957 bool is_int
= midgard_is_integer_op(op
);
959 midgard_vector_alu alu
= {
961 .reg_mode
= midgard_reg_mode_32
,
962 .dest_override
= midgard_dest_override_none
,
965 /* Writemask only valid for non-SSA NIR */
966 .mask
= expand_writemask(mask_of(nr_components
)),
968 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
)),
969 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
)),
972 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
975 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
979 /* Late fixup for emulated instructions */
981 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
982 /* Presently, our second argument is an inline #0 constant.
983 * Switch over to an embedded 1.0 constant (that can't fit
984 * inline, since we're 32-bit, not 16-bit like the inline
987 ins
.ssa_args
.inline_constant
= false;
988 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
989 ins
.has_constants
= true;
991 if (instr
->op
== nir_op_b2f32
) {
992 ins
.constants
[0] = 1.0f
;
994 /* Type pun it into place */
996 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
999 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1000 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1001 /* Lots of instructions need a 0 plonked in */
1002 ins
.ssa_args
.inline_constant
= false;
1003 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1004 ins
.has_constants
= true;
1005 ins
.constants
[0] = 0.0f
;
1006 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1007 } else if (instr
->op
== nir_op_inot
) {
1008 /* ~b = ~(b & b), so duplicate the source */
1009 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1010 ins
.alu
.src2
= ins
.alu
.src1
;
1013 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1014 /* To avoid duplicating the lookup tables (probably), true LUT
1015 * instructions can only operate as if they were scalars. Lower
1016 * them here by changing the component. */
1018 uint8_t original_swizzle
[4];
1019 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1021 for (int i
= 0; i
< nr_components
; ++i
) {
1022 /* Mask the associated component, dropping the
1023 * instruction if needed */
1025 ins
.alu
.mask
= (0x3) << (2 * i
);
1026 ins
.alu
.mask
&= alu
.mask
;
1031 for (int j
= 0; j
< 4; ++j
)
1032 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1034 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
));
1035 emit_mir_instruction(ctx
, ins
);
1038 emit_mir_instruction(ctx
, ins
);
1044 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1045 * optimized) versions of UBO #0 */
1049 compiler_context
*ctx
,
1052 nir_src
*indirect_offset
,
1055 /* TODO: half-floats */
1057 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
&& index
== 0) {
1058 /* Fast path: For the first 16 uniforms, direct accesses are
1059 * 0-cycle, since they're just a register fetch in the usual
1060 * case. So, we alias the registers while we're still in
1063 int reg_slot
= 23 - offset
;
1064 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1066 /* Otherwise, read from the 'special' UBO to access
1067 * higher-indexed uniforms, at a performance cost. More
1068 * generally, we're emitting a UBO read instruction. */
1070 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1072 /* TODO: Don't split */
1073 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1074 ins
.load_store
.address
= offset
>> 3;
1076 if (indirect_offset
) {
1077 emit_indirect_offset(ctx
, indirect_offset
);
1078 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1080 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1083 /* TODO respect index */
1085 emit_mir_instruction(ctx
, ins
);
1091 compiler_context
*ctx
,
1092 unsigned dest
, unsigned offset
,
1093 unsigned nr_comp
, unsigned component
,
1094 nir_src
*indirect_offset
)
1096 /* XXX: Half-floats? */
1097 /* TODO: swizzle, mask */
1099 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1100 ins
.load_store
.mask
= mask_of(nr_comp
);
1101 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1103 midgard_varying_parameter p
= {
1105 .interpolation
= midgard_interp_default
,
1106 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1110 memcpy(&u
, &p
, sizeof(p
));
1111 ins
.load_store
.varying_parameters
= u
;
1113 if (indirect_offset
) {
1114 /* We need to add in the dynamic index, moved to r27.w */
1115 emit_indirect_offset(ctx
, indirect_offset
);
1116 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1118 /* Just a direct load */
1119 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1122 emit_mir_instruction(ctx
, ins
);
1126 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1129 /* Figure out which uniform this is */
1130 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1131 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1133 /* Sysvals are prefix uniforms */
1134 unsigned uniform
= ((uintptr_t) val
) - 1;
1136 /* Emit the read itself -- this is never indirect */
1137 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1140 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1141 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1142 * generations have faster vectorized reads. This operation is for blend
1143 * shaders in particular; reading the tilebuffer from the fragment shader
1144 * remains an open problem. */
1147 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1149 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1150 ins
.load_store
.swizzle
= 0; /* xxxx */
1152 /* Read each component sequentially */
1154 for (unsigned c
= 0; c
< 4; ++c
) {
1155 ins
.load_store
.mask
= (1 << c
);
1156 ins
.load_store
.unknown
= c
;
1157 emit_mir_instruction(ctx
, ins
);
1160 /* vadd.u2f hr2, zext(hr2), #0 */
1162 midgard_vector_alu_src alu_src
= blank_alu_src
;
1163 alu_src
.mod
= midgard_int_zero_extend
;
1164 alu_src
.half
= true;
1166 midgard_instruction u2f
= {
1170 .src1
= SSA_UNUSED_0
,
1172 .inline_constant
= true
1175 .op
= midgard_alu_op_u2f_rtz
,
1176 .reg_mode
= midgard_reg_mode_16
,
1177 .dest_override
= midgard_dest_override_none
,
1179 .src1
= vector_alu_srco_unsigned(alu_src
),
1180 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1184 emit_mir_instruction(ctx
, u2f
);
1186 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1190 midgard_instruction fmul
= {
1192 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1196 .src1
= SSA_UNUSED_0
,
1197 .inline_constant
= true
1200 .op
= midgard_alu_op_fmul
,
1201 .reg_mode
= midgard_reg_mode_32
,
1202 .dest_override
= midgard_dest_override_none
,
1203 .outmod
= midgard_outmod_sat
,
1205 .src1
= vector_alu_srco_unsigned(alu_src
),
1206 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1210 emit_mir_instruction(ctx
, fmul
);
1214 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1216 unsigned offset
= 0, reg
;
1218 switch (instr
->intrinsic
) {
1219 case nir_intrinsic_discard_if
:
1220 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1224 case nir_intrinsic_discard
: {
1225 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1226 struct midgard_instruction discard
= v_branch(conditional
, false);
1227 discard
.branch
.target_type
= TARGET_DISCARD
;
1228 emit_mir_instruction(ctx
, discard
);
1230 ctx
->can_discard
= true;
1234 case nir_intrinsic_load_uniform
:
1235 case nir_intrinsic_load_ubo
:
1236 case nir_intrinsic_load_input
: {
1237 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1238 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1240 /* Get the base type of the intrinsic */
1241 nir_alu_type t
= nir_intrinsic_type(instr
);
1242 t
= nir_alu_type_get_base_type(t
);
1245 offset
= nir_intrinsic_base(instr
);
1248 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1250 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1252 bool direct
= nir_src_is_const(*src_offset
);
1255 offset
+= nir_src_as_uint(*src_offset
);
1257 /* We may need to apply a fractional offset */
1258 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1259 nir_intrinsic_component(instr
) : 0;
1260 reg
= nir_dest_index(ctx
, &instr
->dest
);
1262 if (is_uniform
&& !ctx
->is_blend
) {
1263 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1264 } else if (is_ubo
) {
1265 nir_src index
= instr
->src
[0];
1267 /* We don't yet support indirect UBOs. For indirect
1268 * block numbers (if that's possible), we don't know
1269 * enough about the hardware yet. For indirect sources,
1270 * we know what we need but we need to add some NIR
1271 * support for lowering correctly with respect to
1274 assert(nir_src_is_const(index
));
1275 assert(nir_src_is_const(*src_offset
));
1277 /* TODO: Alignment */
1278 assert((offset
& 0xF) == 0);
1280 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1281 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1282 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1283 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
);
1284 } else if (ctx
->is_blend
) {
1285 /* For blend shaders, load the input color, which is
1286 * preloaded to r0 */
1288 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1289 emit_mir_instruction(ctx
, move
);
1290 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1291 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1292 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1293 ins
.load_store
.mask
= mask_of(nr_comp
);
1295 /* Use the type appropriate load */
1299 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1302 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1304 case nir_type_float
:
1305 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1308 unreachable("Attempted to load unknown type");
1312 emit_mir_instruction(ctx
, ins
);
1314 DBG("Unknown load\n");
1321 case nir_intrinsic_load_output
:
1322 assert(nir_src_is_const(instr
->src
[0]));
1323 reg
= nir_dest_index(ctx
, &instr
->dest
);
1325 if (ctx
->is_blend
) {
1327 emit_fb_read_blend_scalar(ctx
, reg
);
1329 DBG("Unknown output load\n");
1335 case nir_intrinsic_load_blend_const_color_rgba
: {
1336 assert(ctx
->is_blend
);
1337 reg
= nir_dest_index(ctx
, &instr
->dest
);
1339 /* Blend constants are embedded directly in the shader and
1340 * patched in, so we use some magic routing */
1342 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1343 ins
.has_constants
= true;
1344 ins
.has_blend_constant
= true;
1345 emit_mir_instruction(ctx
, ins
);
1349 case nir_intrinsic_store_output
:
1350 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1352 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1354 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1356 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1357 /* gl_FragColor is not emitted with load/store
1358 * instructions. Instead, it gets plonked into
1359 * r0 at the end of the shader and we do the
1360 * framebuffer writeout dance. TODO: Defer
1363 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1364 emit_mir_instruction(ctx
, move
);
1366 /* Save the index we're writing to for later reference
1367 * in the epilogue */
1369 ctx
->fragment_output
= reg
;
1370 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1371 /* Varyings are written into one of two special
1372 * varying register, r26 or r27. The register itself is
1373 * selected as the register in the st_vary instruction,
1374 * minus the base of 26. E.g. write into r27 and then
1375 * call st_vary(1) */
1377 midgard_instruction ins
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1378 emit_mir_instruction(ctx
, ins
);
1380 /* We should have been vectorized, though we don't
1381 * currently check that st_vary is emitted only once
1382 * per slot (this is relevant, since there's not a mask
1383 * parameter available on the store [set to 0 by the
1384 * blob]). We do respect the component by adjusting the
1387 unsigned component
= nir_intrinsic_component(instr
);
1389 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1390 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1391 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1392 emit_mir_instruction(ctx
, st
);
1394 DBG("Unknown store\n");
1400 case nir_intrinsic_load_alpha_ref_float
:
1401 assert(instr
->dest
.is_ssa
);
1403 float ref_value
= ctx
->alpha_ref
;
1405 float *v
= ralloc_array(NULL
, float, 4);
1406 memcpy(v
, &ref_value
, sizeof(float));
1407 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1410 case nir_intrinsic_load_viewport_scale
:
1411 case nir_intrinsic_load_viewport_offset
:
1412 emit_sysval_read(ctx
, &instr
->instr
);
1416 printf ("Unhandled intrinsic\n");
1423 midgard_tex_format(enum glsl_sampler_dim dim
)
1426 case GLSL_SAMPLER_DIM_1D
:
1427 case GLSL_SAMPLER_DIM_BUF
:
1430 case GLSL_SAMPLER_DIM_2D
:
1431 case GLSL_SAMPLER_DIM_EXTERNAL
:
1434 case GLSL_SAMPLER_DIM_3D
:
1437 case GLSL_SAMPLER_DIM_CUBE
:
1438 return MALI_TEX_CUBE
;
1441 DBG("Unknown sampler dim type\n");
1447 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1451 pan_attach_constant_bias(
1452 compiler_context
*ctx
,
1454 midgard_texture_word
*word
)
1456 /* To attach as constant, it has to *be* constant */
1458 if (!nir_src_is_const(lod
))
1461 float f
= nir_src_as_float(lod
);
1463 /* Break into fixed-point */
1465 float lod_frac
= f
- lod_int
;
1467 /* Carry over negative fractions */
1468 if (lod_frac
< 0.0) {
1474 word
->bias
= float_to_ubyte(lod_frac
);
1475 word
->bias_int
= lod_int
;
1480 static enum mali_sampler_type
1481 midgard_sampler_type(nir_alu_type t
)
1483 switch (nir_alu_type_get_base_type(t
)) {
1484 case nir_type_float
:
1485 return MALI_SAMPLER_FLOAT
;
1487 return MALI_SAMPLER_SIGNED
;
1489 return MALI_SAMPLER_UNSIGNED
;
1491 unreachable("Unknown sampler type");
1496 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1497 unsigned midgard_texop
)
1500 //assert (!instr->sampler);
1501 //assert (!instr->texture_array_size);
1503 /* Allocate registers via a round robin scheme to alternate between the two registers */
1504 int reg
= ctx
->texture_op_count
& 1;
1505 int in_reg
= reg
, out_reg
= reg
;
1507 /* Make room for the reg */
1509 if (ctx
->texture_index
[reg
] > -1)
1510 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1512 int texture_index
= instr
->texture_index
;
1513 int sampler_index
= texture_index
;
1515 /* No helper to build texture words -- we do it all here */
1516 midgard_instruction ins
= {
1517 .type
= TAG_TEXTURE_4
,
1519 .op
= midgard_texop
,
1520 .format
= midgard_tex_format(instr
->sampler_dim
),
1521 .texture_handle
= texture_index
,
1522 .sampler_handle
= sampler_index
,
1524 /* TODO: Regalloc it in */
1525 .swizzle
= SWIZZLE_XYZW
,
1532 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1536 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1537 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1538 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1539 int nr_comp
= nir_src_num_components(instr
->src
[i
].src
);
1540 midgard_vector_alu_src alu_src
= blank_alu_src
;
1542 switch (instr
->src
[i
].src_type
) {
1543 case nir_tex_src_coord
: {
1544 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1545 /* texelFetch is undefined on samplerCube */
1546 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1548 /* For cubemaps, we need to load coords into
1549 * special r27, and then use a special ld/st op
1550 * to select the face and copy the xy into the
1551 * texture register */
1553 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1555 midgard_instruction move
= v_mov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1556 emit_mir_instruction(ctx
, move
);
1558 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1559 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1560 st
.load_store
.mask
= 0x3; /* xy */
1561 st
.load_store
.swizzle
= alu_src
.swizzle
;
1562 emit_mir_instruction(ctx
, st
);
1564 ins
.texture
.in_reg_swizzle
= swizzle_of(2);
1566 ins
.texture
.in_reg_swizzle
= alu_src
.swizzle
= swizzle_of(nr_comp
);
1568 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1569 mov
.alu
.mask
= expand_writemask(mask_of(nr_comp
));
1570 emit_mir_instruction(ctx
, mov
);
1572 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1573 /* Texel fetch opcodes care about the
1574 * values of z and w, so we actually
1575 * need to spill into a second register
1576 * for a texel fetch with register bias
1577 * (for non-2D). TODO: Implement that
1580 assert(instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
);
1582 midgard_instruction zero
= v_mov(index
, alu_src
, reg
);
1583 zero
.ssa_args
.inline_constant
= true;
1584 zero
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1585 zero
.has_constants
= true;
1586 zero
.alu
.mask
= ~mov
.alu
.mask
;
1587 emit_mir_instruction(ctx
, zero
);
1589 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1591 /* Non-texel fetch doesn't need that
1592 * nonsense. However we do use the Z
1593 * for array indexing */
1594 bool is_3d
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
;
1595 ins
.texture
.in_reg_swizzle
= is_3d
? SWIZZLE_XYZZ
: SWIZZLE_XYXZ
;
1602 case nir_tex_src_bias
:
1603 case nir_tex_src_lod
: {
1604 /* Try as a constant if we can */
1606 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1607 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1610 /* Otherwise we use a register. To keep RA simple, we
1611 * put the bias/LOD into the w component of the input
1612 * source, which is otherwise in xy */
1614 alu_src
.swizzle
= SWIZZLE_XXXX
;
1616 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1617 mov
.alu
.mask
= expand_writemask(1 << COMPONENT_W
);
1618 emit_mir_instruction(ctx
, mov
);
1620 ins
.texture
.lod_register
= true;
1622 midgard_tex_register_select sel
= {
1632 memcpy(&packed
, &sel
, sizeof(packed
));
1633 ins
.texture
.bias
= packed
;
1639 unreachable("Unknown texture source type\n");
1643 /* Set registers to read and write from the same place */
1644 ins
.texture
.in_reg_select
= in_reg
;
1645 ins
.texture
.out_reg_select
= out_reg
;
1647 emit_mir_instruction(ctx
, ins
);
1649 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1651 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1652 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1653 ctx
->texture_index
[reg
] = o_index
;
1655 midgard_instruction ins2
= v_mov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1656 emit_mir_instruction(ctx
, ins2
);
1658 /* Used for .cont and .last hinting */
1659 ctx
->texture_op_count
++;
1663 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1665 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1666 * generic tex in some cases (which confuses the hardware) */
1668 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1670 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1671 instr
->op
= nir_texop_txl
;
1673 switch (instr
->op
) {
1676 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1679 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1682 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1685 emit_sysval_read(ctx
, &instr
->instr
);
1688 unreachable("Unhanlded texture op");
1693 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1695 switch (instr
->type
) {
1696 case nir_jump_break
: {
1697 /* Emit a branch out of the loop */
1698 struct midgard_instruction br
= v_branch(false, false);
1699 br
.branch
.target_type
= TARGET_BREAK
;
1700 br
.branch
.target_break
= ctx
->current_loop_depth
;
1701 emit_mir_instruction(ctx
, br
);
1708 DBG("Unknown jump type %d\n", instr
->type
);
1714 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1716 switch (instr
->type
) {
1717 case nir_instr_type_load_const
:
1718 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1721 case nir_instr_type_intrinsic
:
1722 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1725 case nir_instr_type_alu
:
1726 emit_alu(ctx
, nir_instr_as_alu(instr
));
1729 case nir_instr_type_tex
:
1730 emit_tex(ctx
, nir_instr_as_tex(instr
));
1733 case nir_instr_type_jump
:
1734 emit_jump(ctx
, nir_instr_as_jump(instr
));
1737 case nir_instr_type_ssa_undef
:
1742 DBG("Unhandled instruction type\n");
1748 /* ALU instructions can inline or embed constants, which decreases register
1749 * pressure and saves space. */
1751 #define CONDITIONAL_ATTACH(src) { \
1752 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1755 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1756 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1761 inline_alu_constants(compiler_context
*ctx
)
1763 mir_foreach_instr(ctx
, alu
) {
1764 /* Other instructions cannot inline constants */
1765 if (alu
->type
!= TAG_ALU_4
) continue;
1767 /* If there is already a constant here, we can do nothing */
1768 if (alu
->has_constants
) continue;
1770 /* It makes no sense to inline constants on a branch */
1771 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1773 CONDITIONAL_ATTACH(src0
);
1775 if (!alu
->has_constants
) {
1776 CONDITIONAL_ATTACH(src1
)
1777 } else if (!alu
->inline_constant
) {
1778 /* Corner case: _two_ vec4 constants, for instance with a
1779 * csel. For this case, we can only use a constant
1780 * register for one, we'll have to emit a move for the
1781 * other. Note, if both arguments are constants, then
1782 * necessarily neither argument depends on the value of
1783 * any particular register. As the destination register
1784 * will be wiped, that means we can spill the constant
1785 * to the destination register.
1788 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1789 unsigned scratch
= alu
->ssa_args
.dest
;
1792 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1793 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1795 /* Force a break XXX Defer r31 writes */
1796 ins
.unit
= UNIT_VLUT
;
1798 /* Set the source */
1799 alu
->ssa_args
.src1
= scratch
;
1801 /* Inject us -before- the last instruction which set r31 */
1802 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1808 /* Midgard supports two types of constants, embedded constants (128-bit) and
1809 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1810 * constants can be demoted to inline constants, for space savings and
1811 * sometimes a performance boost */
1814 embedded_to_inline_constant(compiler_context
*ctx
)
1816 mir_foreach_instr(ctx
, ins
) {
1817 if (!ins
->has_constants
) continue;
1819 if (ins
->ssa_args
.inline_constant
) continue;
1821 /* Blend constants must not be inlined by definition */
1822 if (ins
->has_blend_constant
) continue;
1824 /* src1 cannot be an inline constant due to encoding
1825 * restrictions. So, if possible we try to flip the arguments
1828 int op
= ins
->alu
.op
;
1830 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1832 /* These ops require an operational change to flip
1833 * their arguments TODO */
1834 case midgard_alu_op_flt
:
1835 case midgard_alu_op_fle
:
1836 case midgard_alu_op_ilt
:
1837 case midgard_alu_op_ile
:
1838 case midgard_alu_op_fcsel
:
1839 case midgard_alu_op_icsel
:
1840 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1845 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1846 /* Flip the SSA numbers */
1847 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1848 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1850 /* And flip the modifiers */
1854 src_temp
= ins
->alu
.src2
;
1855 ins
->alu
.src2
= ins
->alu
.src1
;
1856 ins
->alu
.src1
= src_temp
;
1860 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1861 /* Extract the source information */
1863 midgard_vector_alu_src
*src
;
1864 int q
= ins
->alu
.src2
;
1865 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1868 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1869 int component
= src
->swizzle
& 3;
1871 /* Scale constant appropriately, if we can legally */
1872 uint16_t scaled_constant
= 0;
1874 if (midgard_is_integer_op(op
)) {
1875 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1876 scaled_constant
= (uint16_t) iconstants
[component
];
1878 /* Constant overflow after resize */
1879 if (scaled_constant
!= iconstants
[component
])
1882 float original
= (float) ins
->constants
[component
];
1883 scaled_constant
= _mesa_float_to_half(original
);
1885 /* Check for loss of precision. If this is
1886 * mediump, we don't care, but for a highp
1887 * shader, we need to pay attention. NIR
1888 * doesn't yet tell us which mode we're in!
1889 * Practically this prevents most constants
1890 * from being inlined, sadly. */
1892 float fp32
= _mesa_half_to_float(scaled_constant
);
1894 if (fp32
!= original
)
1898 /* We don't know how to handle these with a constant */
1900 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1901 DBG("Bailing inline constant...\n");
1905 /* Make sure that the constant is not itself a
1906 * vector by checking if all accessed values
1907 * (by the swizzle) are the same. */
1909 uint32_t *cons
= (uint32_t *) ins
->constants
;
1910 uint32_t value
= cons
[component
];
1912 bool is_vector
= false;
1913 unsigned mask
= effective_writemask(&ins
->alu
);
1915 for (int c
= 1; c
< 4; ++c
) {
1916 /* We only care if this component is actually used */
1917 if (!(mask
& (1 << c
)))
1920 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1922 if (test
!= value
) {
1931 /* Get rid of the embedded constant */
1932 ins
->has_constants
= false;
1933 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1934 ins
->ssa_args
.inline_constant
= true;
1935 ins
->inline_constant
= scaled_constant
;
1940 /* Map normal SSA sources to other SSA sources / fixed registers (like
1944 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
1946 /* Sign is used quite deliberately for unused */
1950 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
1953 /* Remove entry in leftovers to avoid a redunant fmov */
1955 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
1958 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
1960 /* Assign the alias map */
1966 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1967 * texture pipeline */
1970 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
1972 bool progress
= false;
1974 mir_foreach_instr_in_block_safe(block
, ins
) {
1975 if (ins
->type
!= TAG_ALU_4
) continue;
1976 if (ins
->compact_branch
) continue;
1978 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1979 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
1981 mir_remove_instruction(ins
);
1988 /* Dead code elimination for branches at the end of a block - only one branch
1989 * per block is legal semantically */
1992 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1994 bool branched
= false;
1996 mir_foreach_instr_in_block_safe(block
, ins
) {
1997 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1999 /* We ignore prepacked branches since the fragment epilogue is
2000 * just generally special */
2001 if (ins
->prepacked_branch
) continue;
2003 /* Discards are similarly special and may not correspond to the
2006 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
2009 /* We already branched, so this is dead */
2010 mir_remove_instruction(ins
);
2018 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
2021 if (!is_int
&& src
.mod
) return true;
2024 for (unsigned c
= 0; c
< 4; ++c
) {
2025 if (!(mask
& (1 << c
))) continue;
2026 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
2033 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
2035 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
2036 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2038 midgard_vector_alu_src src2
=
2039 vector_alu_from_unsigned(ins
->alu
.src2
);
2041 return mir_nontrivial_mod(src2
, is_int
, mask
);
2045 mir_nontrivial_outmod(midgard_instruction
*ins
)
2047 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2048 unsigned mod
= ins
->alu
.outmod
;
2051 return mod
!= midgard_outmod_int_wrap
;
2053 return mod
!= midgard_outmod_none
;
2057 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
2059 bool progress
= false;
2061 mir_foreach_instr_in_block_safe(block
, ins
) {
2062 if (ins
->type
!= TAG_ALU_4
) continue;
2063 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2065 unsigned from
= ins
->ssa_args
.src1
;
2066 unsigned to
= ins
->ssa_args
.dest
;
2068 /* We only work on pure SSA */
2070 if (to
>= SSA_FIXED_MINIMUM
) continue;
2071 if (from
>= SSA_FIXED_MINIMUM
) continue;
2072 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
2073 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2075 /* Constant propagation is not handled here, either */
2076 if (ins
->ssa_args
.inline_constant
) continue;
2077 if (ins
->has_constants
) continue;
2079 if (mir_nontrivial_source2_mod(ins
)) continue;
2080 if (mir_nontrivial_outmod(ins
)) continue;
2082 /* We're clear -- rewrite */
2083 mir_rewrite_index_src(ctx
, to
, from
);
2084 mir_remove_instruction(ins
);
2091 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2092 * the move can be propagated away entirely */
2095 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2098 if (comp
== midgard_outmod_none
)
2101 if (*outmod
== midgard_outmod_none
) {
2106 /* TODO: Compose rules */
2111 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2113 bool progress
= false;
2115 mir_foreach_instr_in_block_safe(block
, ins
) {
2116 if (ins
->type
!= TAG_ALU_4
) continue;
2117 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2118 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2120 /* TODO: Registers? */
2121 unsigned src
= ins
->ssa_args
.src1
;
2122 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
2123 assert(!mir_has_multiple_writes(ctx
, src
));
2125 /* There might be a source modifier, too */
2126 if (mir_nontrivial_source2_mod(ins
)) continue;
2128 /* Backpropagate the modifier */
2129 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2130 if (v
->type
!= TAG_ALU_4
) continue;
2131 if (v
->ssa_args
.dest
!= src
) continue;
2133 /* Can we even take a float outmod? */
2134 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2136 midgard_outmod_float temp
= v
->alu
.outmod
;
2137 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2139 /* Throw in the towel.. */
2140 if (!progress
) break;
2142 /* Otherwise, transfer the modifier */
2143 v
->alu
.outmod
= temp
;
2144 ins
->alu
.outmod
= midgard_outmod_none
;
2154 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
2156 bool progress
= false;
2158 mir_foreach_instr_in_block_safe(block
, ins
) {
2159 if (ins
->type
!= TAG_ALU_4
) continue;
2160 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2162 unsigned from
= ins
->ssa_args
.src1
;
2163 unsigned to
= ins
->ssa_args
.dest
;
2165 /* Make sure it's simple enough for us to handle */
2167 if (from
>= SSA_FIXED_MINIMUM
) continue;
2168 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2169 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
2170 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
2172 bool eliminated
= false;
2174 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2175 /* The texture registers are not SSA so be careful.
2176 * Conservatively, just stop if we hit a texture op
2177 * (even if it may not write) to where we are */
2179 if (v
->type
!= TAG_ALU_4
)
2182 if (v
->ssa_args
.dest
== from
) {
2183 /* We don't want to track partial writes ... */
2184 if (v
->alu
.mask
== 0xF) {
2185 v
->ssa_args
.dest
= to
;
2194 mir_remove_instruction(ins
);
2196 progress
|= eliminated
;
2202 /* The following passes reorder MIR instructions to enable better scheduling */
2205 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2207 mir_foreach_instr_in_block_safe(block
, ins
) {
2208 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2210 /* We've found a load/store op. Check if next is also load/store. */
2211 midgard_instruction
*next_op
= mir_next_op(ins
);
2212 if (&next_op
->link
!= &block
->instructions
) {
2213 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2214 /* If so, we're done since we're a pair */
2215 ins
= mir_next_op(ins
);
2219 /* Maximum search distance to pair, to avoid register pressure disasters */
2220 int search_distance
= 8;
2222 /* Otherwise, we have an orphaned load/store -- search for another load */
2223 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2224 /* Terminate search if necessary */
2225 if (!(search_distance
--)) break;
2227 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2229 /* Stores cannot be reordered, since they have
2230 * dependencies. For the same reason, indirect
2231 * loads cannot be reordered as their index is
2232 * loaded in r27.w */
2234 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2236 /* It appears the 0x800 bit is set whenever a
2237 * load is direct, unset when it is indirect.
2238 * Skip indirect loads. */
2240 if (!(c
->load_store
.unknown
& 0x800)) continue;
2242 /* We found one! Move it up to pair and remove it from the old location */
2244 mir_insert_instruction_before(ins
, *c
);
2245 mir_remove_instruction(c
);
2253 /* If there are leftovers after the below pass, emit actual fmov
2254 * instructions for the slow-but-correct path */
2257 emit_leftover_move(compiler_context
*ctx
)
2259 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2260 int base
= ((uintptr_t) leftover
->key
) - 1;
2263 map_ssa_to_alias(ctx
, &mapped
);
2264 EMIT(mov
, mapped
, blank_alu_src
, base
);
2269 actualise_ssa_to_alias(compiler_context
*ctx
)
2271 mir_foreach_instr(ctx
, ins
) {
2272 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2273 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2276 emit_leftover_move(ctx
);
2280 emit_fragment_epilogue(compiler_context
*ctx
)
2282 /* Special case: writing out constants requires us to include the move
2283 * explicitly now, so shove it into r0 */
2285 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2287 if (constant_value
) {
2288 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2289 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2290 emit_mir_instruction(ctx
, ins
);
2293 /* Perform the actual fragment writeout. We have two writeout/branch
2294 * instructions, forming a loop until writeout is successful as per the
2295 * docs. TODO: gl_FragDepth */
2297 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2298 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2301 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2302 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2303 * with the int8 analogue to the fragment epilogue */
2306 emit_blend_epilogue(compiler_context
*ctx
)
2308 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2310 midgard_instruction scale
= {
2313 .inline_constant
= _mesa_float_to_half(255.0),
2315 .src0
= SSA_FIXED_REGISTER(0),
2316 .src1
= SSA_UNUSED_0
,
2317 .dest
= SSA_FIXED_REGISTER(24),
2318 .inline_constant
= true
2321 .op
= midgard_alu_op_fmul
,
2322 .reg_mode
= midgard_reg_mode_32
,
2323 .dest_override
= midgard_dest_override_lower
,
2325 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2326 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2330 emit_mir_instruction(ctx
, scale
);
2332 /* vadd.f2u_rte.pos.low hr0, hr48, #0 */
2334 midgard_vector_alu_src alu_src
= blank_alu_src
;
2335 alu_src
.half
= true;
2337 midgard_instruction f2u_rte
= {
2340 .src0
= SSA_FIXED_REGISTER(24),
2341 .src1
= SSA_UNUSED_0
,
2342 .dest
= SSA_FIXED_REGISTER(0),
2343 .inline_constant
= true
2346 .op
= midgard_alu_op_f2u_rte
,
2347 .reg_mode
= midgard_reg_mode_16
,
2348 .dest_override
= midgard_dest_override_lower
,
2349 .outmod
= midgard_outmod_pos
,
2351 .src1
= vector_alu_srco_unsigned(alu_src
),
2352 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2356 emit_mir_instruction(ctx
, f2u_rte
);
2358 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2359 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2362 static midgard_block
*
2363 emit_block(compiler_context
*ctx
, nir_block
*block
)
2365 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2366 list_addtail(&this_block
->link
, &ctx
->blocks
);
2368 this_block
->is_scheduled
= false;
2371 ctx
->texture_index
[0] = -1;
2372 ctx
->texture_index
[1] = -1;
2374 /* Add us as a successor to the block we are following */
2375 if (ctx
->current_block
)
2376 midgard_block_add_successor(ctx
->current_block
, this_block
);
2378 /* Set up current block */
2379 list_inithead(&this_block
->instructions
);
2380 ctx
->current_block
= this_block
;
2382 nir_foreach_instr(instr
, block
) {
2383 emit_instr(ctx
, instr
);
2384 ++ctx
->instruction_count
;
2387 inline_alu_constants(ctx
);
2388 embedded_to_inline_constant(ctx
);
2390 /* Perform heavylifting for aliasing */
2391 actualise_ssa_to_alias(ctx
);
2393 midgard_pair_load_store(ctx
, this_block
);
2395 /* Append fragment shader epilogue (value writeout) */
2396 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2397 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2399 emit_blend_epilogue(ctx
);
2401 emit_fragment_epilogue(ctx
);
2405 if (block
== nir_start_block(ctx
->func
->impl
))
2406 ctx
->initial_block
= this_block
;
2408 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2409 ctx
->final_block
= this_block
;
2411 /* Allow the next control flow to access us retroactively, for
2413 ctx
->current_block
= this_block
;
2415 /* Document the fallthrough chain */
2416 ctx
->previous_source_block
= this_block
;
2421 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2424 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2426 /* Conditional branches expect the condition in r31.w; emit a move for
2427 * that in the _previous_ block (which is the current block). */
2428 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2430 /* Speculatively emit the branch, but we can't fill it in until later */
2431 EMIT(branch
, true, true);
2432 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2434 /* Emit the two subblocks */
2435 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2437 /* Emit a jump from the end of the then block to the end of the else */
2438 EMIT(branch
, false, false);
2439 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2441 /* Emit second block, and check if it's empty */
2443 int else_idx
= ctx
->block_count
;
2444 int count_in
= ctx
->instruction_count
;
2445 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2446 int after_else_idx
= ctx
->block_count
;
2448 /* Now that we have the subblocks emitted, fix up the branches */
2453 if (ctx
->instruction_count
== count_in
) {
2454 /* The else block is empty, so don't emit an exit jump */
2455 mir_remove_instruction(then_exit
);
2456 then_branch
->branch
.target_block
= after_else_idx
;
2458 then_branch
->branch
.target_block
= else_idx
;
2459 then_exit
->branch
.target_block
= after_else_idx
;
2464 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2466 /* Remember where we are */
2467 midgard_block
*start_block
= ctx
->current_block
;
2469 /* Allocate a loop number, growing the current inner loop depth */
2470 int loop_idx
= ++ctx
->current_loop_depth
;
2472 /* Get index from before the body so we can loop back later */
2473 int start_idx
= ctx
->block_count
;
2475 /* Emit the body itself */
2476 emit_cf_list(ctx
, &nloop
->body
);
2478 /* Branch back to loop back */
2479 struct midgard_instruction br_back
= v_branch(false, false);
2480 br_back
.branch
.target_block
= start_idx
;
2481 emit_mir_instruction(ctx
, br_back
);
2483 /* Mark down that branch in the graph. Note that we're really branching
2484 * to the block *after* we started in. TODO: Why doesn't the branch
2485 * itself have an off-by-one then...? */
2486 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2488 /* Find the index of the block about to follow us (note: we don't add
2489 * one; blocks are 0-indexed so we get a fencepost problem) */
2490 int break_block_idx
= ctx
->block_count
;
2492 /* Fix up the break statements we emitted to point to the right place,
2493 * now that we can allocate a block number for them */
2495 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2496 mir_foreach_instr_in_block(block
, ins
) {
2497 if (ins
->type
!= TAG_ALU_4
) continue;
2498 if (!ins
->compact_branch
) continue;
2499 if (ins
->prepacked_branch
) continue;
2501 /* We found a branch -- check the type to see if we need to do anything */
2502 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2504 /* It's a break! Check if it's our break */
2505 if (ins
->branch
.target_break
!= loop_idx
) continue;
2507 /* Okay, cool, we're breaking out of this loop.
2508 * Rewrite from a break to a goto */
2510 ins
->branch
.target_type
= TARGET_GOTO
;
2511 ins
->branch
.target_block
= break_block_idx
;
2515 /* Now that we've finished emitting the loop, free up the depth again
2516 * so we play nice with recursion amid nested loops */
2517 --ctx
->current_loop_depth
;
2520 static midgard_block
*
2521 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2523 midgard_block
*start_block
= NULL
;
2525 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2526 switch (node
->type
) {
2527 case nir_cf_node_block
: {
2528 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2531 start_block
= block
;
2536 case nir_cf_node_if
:
2537 emit_if(ctx
, nir_cf_node_as_if(node
));
2540 case nir_cf_node_loop
:
2541 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2544 case nir_cf_node_function
:
2553 /* Due to lookahead, we need to report the first tag executed in the command
2554 * stream and in branch targets. An initial block might be empty, so iterate
2555 * until we find one that 'works' */
2558 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2560 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2562 unsigned first_tag
= 0;
2565 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2567 if (initial_bundle
) {
2568 first_tag
= initial_bundle
->tag
;
2572 /* Initial block is empty, try the next block */
2573 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2574 } while(initial_block
!= NULL
);
2581 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2583 struct util_dynarray
*compiled
= &program
->compiled
;
2585 midgard_debug
= debug_get_option_midgard_debug();
2587 compiler_context ictx
= {
2589 .stage
= nir
->info
.stage
,
2591 .is_blend
= is_blend
,
2592 .blend_constant_offset
= -1,
2594 .alpha_ref
= program
->alpha_ref
2597 compiler_context
*ctx
= &ictx
;
2599 /* TODO: Decide this at runtime */
2600 ctx
->uniform_cutoff
= 8;
2602 /* Initialize at a global (not block) level hash tables */
2604 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2605 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2606 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2607 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2608 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2610 /* Record the varying mapping for the command stream's bookkeeping */
2612 struct exec_list
*varyings
=
2613 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2615 unsigned max_varying
= 0;
2616 nir_foreach_variable(var
, varyings
) {
2617 unsigned loc
= var
->data
.driver_location
;
2618 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2620 for (int c
= 0; c
< sz
; ++c
) {
2621 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2622 max_varying
= MAX2(max_varying
, loc
+ c
);
2626 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2627 * (so we don't accidentally duplicate the epilogue since mesa/st has
2628 * messed with our I/O quite a bit already) */
2630 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2632 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2633 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2635 NIR_PASS_V(nir
, nir_lower_var_copies
);
2636 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2637 NIR_PASS_V(nir
, nir_split_var_copies
);
2638 NIR_PASS_V(nir
, nir_lower_var_copies
);
2639 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2640 NIR_PASS_V(nir
, nir_lower_var_copies
);
2641 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2643 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2645 /* Optimisation passes */
2649 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2650 nir_print_shader(nir
, stdout
);
2653 /* Assign sysvals and counts, now that we're sure
2654 * (post-optimisation) */
2656 midgard_nir_assign_sysvals(ctx
, nir
);
2658 program
->uniform_count
= nir
->num_uniforms
;
2659 program
->sysval_count
= ctx
->sysval_count
;
2660 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2662 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2663 program
->varying_count
= max_varying
+ 1; /* Fencepost off-by-one */
2665 nir_foreach_function(func
, nir
) {
2669 list_inithead(&ctx
->blocks
);
2670 ctx
->block_count
= 0;
2673 emit_cf_list(ctx
, &func
->impl
->body
);
2674 emit_block(ctx
, func
->impl
->end_block
);
2676 break; /* TODO: Multi-function shaders */
2679 util_dynarray_init(compiled
, NULL
);
2681 /* MIR-level optimizations */
2683 bool progress
= false;
2688 mir_foreach_block(ctx
, block
) {
2689 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2690 progress
|= midgard_opt_copy_prop(ctx
, block
);
2691 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
2692 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2696 /* Nested control-flow can result in dead branches at the end of the
2697 * block. This messes with our analysis and is just dead code, so cull
2699 mir_foreach_block(ctx
, block
) {
2700 midgard_opt_cull_dead_branch(ctx
, block
);
2704 schedule_program(ctx
);
2706 /* Now that all the bundles are scheduled and we can calculate block
2707 * sizes, emit actual branch instructions rather than placeholders */
2709 int br_block_idx
= 0;
2711 mir_foreach_block(ctx
, block
) {
2712 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2713 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2714 midgard_instruction
*ins
= bundle
->instructions
[c
];
2716 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2718 if (ins
->prepacked_branch
) continue;
2720 /* Parse some basic branch info */
2721 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2722 bool is_conditional
= ins
->branch
.conditional
;
2723 bool is_inverted
= ins
->branch
.invert_conditional
;
2724 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2726 /* Determine the block we're jumping to */
2727 int target_number
= ins
->branch
.target_block
;
2729 /* Report the destination tag */
2730 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2732 /* Count up the number of quadwords we're
2733 * jumping over = number of quadwords until
2734 * (br_block_idx, target_number) */
2736 int quadword_offset
= 0;
2739 /* Jump to the end of the shader. We
2740 * need to include not only the
2741 * following blocks, but also the
2742 * contents of our current block (since
2743 * discard can come in the middle of
2746 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2748 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2749 quadword_offset
+= quadword_size(bun
->tag
);
2752 mir_foreach_block_from(ctx
, blk
, b
) {
2753 quadword_offset
+= b
->quadword_count
;
2756 } else if (target_number
> br_block_idx
) {
2759 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2760 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2763 quadword_offset
+= blk
->quadword_count
;
2766 /* Jump backwards */
2768 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2769 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2772 quadword_offset
-= blk
->quadword_count
;
2776 /* Unconditional extended branches (far jumps)
2777 * have issues, so we always use a conditional
2778 * branch, setting the condition to always for
2779 * unconditional. For compact unconditional
2780 * branches, cond isn't used so it doesn't
2781 * matter what we pick. */
2783 midgard_condition cond
=
2784 !is_conditional
? midgard_condition_always
:
2785 is_inverted
? midgard_condition_false
:
2786 midgard_condition_true
;
2788 midgard_jmp_writeout_op op
=
2789 is_discard
? midgard_jmp_writeout_op_discard
:
2790 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2791 midgard_jmp_writeout_op_branch_cond
;
2794 midgard_branch_extended branch
=
2795 midgard_create_branch_extended(
2800 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2801 } else if (is_conditional
|| is_discard
) {
2802 midgard_branch_cond branch
= {
2804 .dest_tag
= dest_tag
,
2805 .offset
= quadword_offset
,
2809 assert(branch
.offset
== quadword_offset
);
2811 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2813 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2815 midgard_branch_uncond branch
= {
2817 .dest_tag
= dest_tag
,
2818 .offset
= quadword_offset
,
2822 assert(branch
.offset
== quadword_offset
);
2824 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2832 /* Emit flat binary from the instruction arrays. Iterate each block in
2833 * sequence. Save instruction boundaries such that lookahead tags can
2834 * be assigned easily */
2836 /* Cache _all_ bundles in source order for lookahead across failed branches */
2838 int bundle_count
= 0;
2839 mir_foreach_block(ctx
, block
) {
2840 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2842 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2844 mir_foreach_block(ctx
, block
) {
2845 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2846 source_order_bundles
[bundle_idx
++] = bundle
;
2850 int current_bundle
= 0;
2852 /* Midgard prefetches instruction types, so during emission we
2853 * need to lookahead. Unless this is the last instruction, in
2854 * which we return 1. Or if this is the second to last and the
2855 * last is an ALU, then it's also 1... */
2857 mir_foreach_block(ctx
, block
) {
2858 mir_foreach_bundle_in_block(block
, bundle
) {
2861 if (current_bundle
+ 1 < bundle_count
) {
2862 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2864 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2871 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2875 /* TODO: Free deeper */
2876 //util_dynarray_fini(&block->instructions);
2879 free(source_order_bundles
);
2881 /* Report the very first tag executed */
2882 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2884 /* Deal with off-by-one related to the fencepost problem */
2885 program
->work_register_count
= ctx
->work_registers
+ 1;
2887 program
->can_discard
= ctx
->can_discard
;
2888 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2890 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2892 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2893 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);