2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 /* Successors: always one forward (the block after us), maybe
173 * one backwards (for a backward branch). No need for a second
174 * forward, since graph traversal would get there eventually
176 struct midgard_block
*successors
[2];
177 unsigned nr_successors
;
179 /* The successors pointer form a graph, and in the case of
180 * complex control flow, this graph has a cycles. To aid
181 * traversal during liveness analysis, we have a visited?
182 * boolean for passes to use as they see fit, provided they
188 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
190 block
->successors
[block
->nr_successors
++] = successor
;
191 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
194 /* Helpers to generate midgard_instruction's using macro magic, since every
195 * driver seems to do it that way */
197 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
198 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
200 #define M_LOAD_STORE(name, rname, uname) \
201 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
202 midgard_instruction i = { \
203 .type = TAG_LOAD_STORE_4, \
210 .op = midgard_op_##name, \
212 .swizzle = SWIZZLE_XYZW, \
220 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
221 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
223 const midgard_vector_alu_src blank_alu_src
= {
224 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
227 const midgard_vector_alu_src blank_alu_src_xxxx
= {
228 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
231 const midgard_scalar_alu_src blank_scalar_alu_src
= {
235 /* Used for encoding the unused source of 1-op instructions */
236 const midgard_vector_alu_src zero_alu_src
= { 0 };
238 /* Coerce structs to integer */
241 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
244 memcpy(&u
, &src
, sizeof(src
));
248 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
249 * the corresponding Midgard source */
251 static midgard_vector_alu_src
252 vector_alu_modifiers(nir_alu_src
*src
)
254 if (!src
) return blank_alu_src
;
256 midgard_vector_alu_src alu_src
= {
258 .negate
= src
->negate
,
261 .half
= 0, /* TODO */
262 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
268 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
270 static midgard_instruction
271 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
273 midgard_instruction ins
= {
276 .src0
= SSA_UNUSED_1
,
281 .op
= midgard_alu_op_fmov
,
282 .reg_mode
= midgard_reg_mode_full
,
283 .dest_override
= midgard_dest_override_none
,
285 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
286 .src2
= vector_alu_srco_unsigned(mod
)
293 /* load/store instructions have both 32-bit and 16-bit variants, depending on
294 * whether we are using vectors composed of highp or mediump. At the moment, we
295 * don't support half-floats -- this requires changes in other parts of the
296 * compiler -- therefore the 16-bit versions are commented out. */
298 //M_LOAD(load_attr_16);
299 M_LOAD(load_attr_32
);
300 //M_LOAD(load_vary_16);
301 M_LOAD(load_vary_32
);
302 //M_LOAD(load_uniform_16);
303 M_LOAD(load_uniform_32
);
304 M_LOAD(load_color_buffer_8
);
305 //M_STORE(store_vary_16);
306 M_STORE(store_vary_32
);
307 M_STORE(store_cubemap_coords
);
309 static midgard_instruction
310 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
312 midgard_branch_cond branch
= {
320 memcpy(&compact
, &branch
, sizeof(branch
));
322 midgard_instruction ins
= {
324 .unit
= ALU_ENAB_BR_COMPACT
,
325 .prepacked_branch
= true,
326 .compact_branch
= true,
327 .br_compact
= compact
330 if (op
== midgard_jmp_writeout_op_writeout
)
336 static midgard_instruction
337 v_branch(bool conditional
, bool invert
)
339 midgard_instruction ins
= {
341 .unit
= ALU_ENAB_BRANCH
,
342 .compact_branch
= true,
344 .conditional
= conditional
,
345 .invert_conditional
= invert
352 static midgard_branch_extended
353 midgard_create_branch_extended( midgard_condition cond
,
354 midgard_jmp_writeout_op op
,
356 signed quadword_offset
)
358 /* For unclear reasons, the condition code is repeated 8 times */
359 uint16_t duplicated_cond
=
369 midgard_branch_extended branch
= {
371 .dest_tag
= dest_tag
,
372 .offset
= quadword_offset
,
373 .cond
= duplicated_cond
379 typedef struct midgard_bundle
{
380 /* Tag for the overall bundle */
383 /* Instructions contained by the bundle */
384 int instruction_count
;
385 midgard_instruction instructions
[5];
387 /* Bundle-wide ALU configuration */
390 bool has_embedded_constants
;
392 bool has_blend_constant
;
394 uint16_t register_words
[8];
395 int register_words_count
;
397 uint64_t body_words
[8];
399 int body_words_count
;
402 typedef struct compiler_context
{
404 gl_shader_stage stage
;
406 /* Is internally a blend shader? Depends on stage == FRAGMENT */
409 /* Tracking for blend constant patching */
410 int blend_constant_number
;
411 int blend_constant_offset
;
413 /* Current NIR function */
416 /* Unordered list of midgard_blocks */
418 struct list_head blocks
;
420 midgard_block
*initial_block
;
421 midgard_block
*previous_source_block
;
422 midgard_block
*final_block
;
424 /* List of midgard_instructions emitted for the current block */
425 midgard_block
*current_block
;
427 /* The index corresponding to the current loop, e.g. for breaks/contineus */
430 /* Constants which have been loaded, for later inlining */
431 struct hash_table_u64
*ssa_constants
;
433 /* SSA indices to be outputted to corresponding varying offset */
434 struct hash_table_u64
*ssa_varyings
;
436 /* SSA values / registers which have been aliased. Naively, these
437 * demand a fmov output; instead, we alias them in a later pass to
438 * avoid the wasted op.
440 * A note on encoding: to avoid dynamic memory management here, rather
441 * than ampping to a pointer, we map to the source index; the key
442 * itself is just the destination index. */
444 struct hash_table_u64
*ssa_to_alias
;
445 struct set
*leftover_ssa_to_alias
;
447 /* Actual SSA-to-register for RA */
448 struct hash_table_u64
*ssa_to_register
;
450 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
451 struct hash_table_u64
*hash_to_temp
;
455 /* Just the count of the max register used. Higher count => higher
456 * register pressure */
459 /* Used for cont/last hinting. Increase when a tex op is added.
460 * Decrease when a tex op is removed. */
461 int texture_op_count
;
463 /* Mapping of texture register -> SSA index for unaliasing */
464 int texture_index
[2];
466 /* If any path hits a discard instruction */
469 /* The number of uniforms allowable for the fast path */
472 /* Count of instructions emitted from NIR overall, across all blocks */
473 int instruction_count
;
475 /* Alpha ref value passed in */
478 /* The index corresponding to the fragment output */
479 unsigned fragment_output
;
481 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
482 unsigned sysvals
[MAX_SYSVAL_COUNT
];
483 unsigned sysval_count
;
484 struct hash_table_u64
*sysval_to_id
;
487 /* Append instruction to end of current block */
489 static midgard_instruction
*
490 mir_upload_ins(struct midgard_instruction ins
)
492 midgard_instruction
*heap
= malloc(sizeof(ins
));
493 memcpy(heap
, &ins
, sizeof(ins
));
498 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
500 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
504 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
506 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
510 mir_remove_instruction(struct midgard_instruction
*ins
)
512 list_del(&ins
->link
);
515 static midgard_instruction
*
516 mir_prev_op(struct midgard_instruction
*ins
)
518 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
521 static midgard_instruction
*
522 mir_next_op(struct midgard_instruction
*ins
)
524 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
527 static midgard_block
*
528 mir_next_block(struct midgard_block
*blk
)
530 return list_first_entry(&(blk
->link
), midgard_block
, link
);
534 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
535 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
537 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
538 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
539 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
540 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
541 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
542 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
545 static midgard_instruction
*
546 mir_last_in_block(struct midgard_block
*block
)
548 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
551 static midgard_block
*
552 mir_get_block(compiler_context
*ctx
, int idx
)
554 struct list_head
*lst
= &ctx
->blocks
;
559 return (struct midgard_block
*) lst
;
562 /* Pretty printer for internal Midgard IR */
565 print_mir_source(int source
)
567 if (source
>= SSA_FIXED_MINIMUM
) {
568 /* Specific register */
569 int reg
= SSA_REG_FROM_FIXED(source
);
571 /* TODO: Moving threshold */
572 if (reg
> 16 && reg
< 24)
573 printf("u%d", 23 - reg
);
577 printf("%d", source
);
582 print_mir_instruction(midgard_instruction
*ins
)
588 midgard_alu_op op
= ins
->alu
.op
;
589 const char *name
= alu_opcode_names
[op
];
592 printf("%d.", ins
->unit
);
594 printf("%s", name
? name
: "??");
598 case TAG_LOAD_STORE_4
: {
599 midgard_load_store_op op
= ins
->load_store
.op
;
600 const char *name
= load_store_opcode_names
[op
];
607 case TAG_TEXTURE_4
: {
616 ssa_args
*args
= &ins
->ssa_args
;
618 printf(" %d, ", args
->dest
);
620 print_mir_source(args
->src0
);
623 if (args
->inline_constant
)
624 printf("#%d", ins
->inline_constant
);
626 print_mir_source(args
->src1
);
628 if (ins
->has_constants
)
629 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
635 print_mir_block(midgard_block
*block
)
639 mir_foreach_instr_in_block(block
, ins
) {
640 print_mir_instruction(ins
);
649 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
651 ins
->has_constants
= true;
652 memcpy(&ins
->constants
, constants
, 16);
654 /* If this is the special blend constant, mark this instruction */
656 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
657 ins
->has_blend_constant
= true;
661 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
663 return glsl_count_attribute_slots(type
, false);
666 /* Lower fdot2 to a vector multiplication followed by channel addition */
668 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
670 if (alu
->op
!= nir_op_fdot2
)
673 b
->cursor
= nir_before_instr(&alu
->instr
);
675 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
676 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
678 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
680 nir_ssa_def
*sum
= nir_fadd(b
,
681 nir_channel(b
, product
, 0),
682 nir_channel(b
, product
, 1));
684 /* Replace the fdot2 with this sum */
685 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
689 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
691 switch (instr
->intrinsic
) {
692 case nir_intrinsic_load_viewport_scale
:
693 return PAN_SYSVAL_VIEWPORT_SCALE
;
694 case nir_intrinsic_load_viewport_offset
:
695 return PAN_SYSVAL_VIEWPORT_OFFSET
;
702 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
706 if (instr
->type
== nir_instr_type_intrinsic
) {
707 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
708 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
714 /* We have a sysval load; check if it's already been assigned */
716 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
719 /* It hasn't -- so assign it now! */
721 unsigned id
= ctx
->sysval_count
++;
722 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
723 ctx
->sysvals
[id
] = sysval
;
727 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
729 ctx
->sysval_count
= 0;
731 nir_foreach_function(function
, shader
) {
732 if (!function
->impl
) continue;
734 nir_foreach_block(block
, function
->impl
) {
735 nir_foreach_instr_safe(instr
, block
) {
736 midgard_nir_assign_sysval_body(ctx
, instr
);
743 midgard_nir_lower_fdot2(nir_shader
*shader
)
745 bool progress
= false;
747 nir_foreach_function(function
, shader
) {
748 if (!function
->impl
) continue;
751 nir_builder
*b
= &_b
;
752 nir_builder_init(b
, function
->impl
);
754 nir_foreach_block(block
, function
->impl
) {
755 nir_foreach_instr_safe(instr
, block
) {
756 if (instr
->type
!= nir_instr_type_alu
) continue;
758 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
759 midgard_nir_lower_fdot2_body(b
, alu
);
765 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
773 optimise_nir(nir_shader
*nir
)
777 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
778 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
780 nir_lower_tex_options lower_tex_options
= {
784 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
789 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
790 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
792 NIR_PASS(progress
, nir
, nir_copy_prop
);
793 NIR_PASS(progress
, nir
, nir_opt_dce
);
794 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
795 NIR_PASS(progress
, nir
, nir_opt_cse
);
796 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
797 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
798 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
799 NIR_PASS(progress
, nir
, nir_opt_undef
);
800 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
803 nir_var_function_temp
);
805 /* TODO: Enable vectorize when merged upstream */
806 // NIR_PASS(progress, nir, nir_opt_vectorize);
809 /* Must be run at the end to prevent creation of fsin/fcos ops */
810 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
815 NIR_PASS(progress
, nir
, nir_opt_dce
);
816 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
817 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
818 NIR_PASS(progress
, nir
, nir_copy_prop
);
821 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
822 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
824 /* Lower mods for float ops only. Integer ops don't support modifiers
825 * (saturate doesn't make sense on integers, neg/abs require dedicated
828 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
829 NIR_PASS(progress
, nir
, nir_copy_prop
);
830 NIR_PASS(progress
, nir
, nir_opt_dce
);
832 /* We implement booleans as 32-bit 0/~0 */
833 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
835 /* Take us out of SSA */
836 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
837 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
839 /* We are a vector architecture; write combine where possible */
840 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
841 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
843 NIR_PASS(progress
, nir
, nir_opt_dce
);
846 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
847 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
848 * r0. See the comments in compiler_context */
851 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
853 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
854 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
857 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
860 unalias_ssa(compiler_context
*ctx
, int dest
)
862 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
863 /* TODO: Remove from leftover or no? */
867 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
869 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
873 midgard_is_pinned(compiler_context
*ctx
, int index
)
875 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
878 /* Do not actually emit a load; instead, cache the constant for inlining */
881 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
883 nir_ssa_def def
= instr
->def
;
885 float *v
= ralloc_array(NULL
, float, 4);
886 nir_const_load_to_arr(v
, instr
, f32
);
887 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
890 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
894 expand_writemask(unsigned mask
)
898 for (int i
= 0; i
< 4; ++i
)
906 squeeze_writemask(unsigned mask
)
910 for (int i
= 0; i
< 4; ++i
)
911 if (mask
& (3 << (2 * i
)))
918 /* Determines effective writemask, taking quirks and expansion into account */
920 effective_writemask(midgard_vector_alu
*alu
)
922 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
925 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
927 /* If there is a fixed channel count, construct the appropriate mask */
930 return (1 << channel_count
) - 1;
932 /* Otherwise, just squeeze the existing mask */
933 return squeeze_writemask(alu
->mask
);
937 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
939 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
942 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
947 /* If no temp is find, allocate one */
948 temp
= ctx
->temp_count
++;
949 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
951 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
957 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
960 return src
->ssa
->index
;
962 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
966 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
969 return dst
->ssa
.index
;
971 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
975 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
977 return nir_src_index(ctx
, &src
->src
);
980 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
981 * a conditional test) into that register */
984 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
986 int condition
= nir_src_index(ctx
, src
);
988 /* Source to swizzle the desired component into w */
990 const midgard_vector_alu_src alu_src
= {
991 .swizzle
= SWIZZLE(component
, component
, component
, component
),
994 /* There is no boolean move instruction. Instead, we simulate a move by
995 * ANDing the condition with itself to get it into r31.w */
997 midgard_instruction ins
= {
999 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
1003 .dest
= SSA_FIXED_REGISTER(31),
1006 .op
= midgard_alu_op_iand
,
1007 .reg_mode
= midgard_reg_mode_full
,
1008 .dest_override
= midgard_dest_override_none
,
1009 .mask
= (0x3 << 6), /* w */
1010 .src1
= vector_alu_srco_unsigned(alu_src
),
1011 .src2
= vector_alu_srco_unsigned(alu_src
)
1015 emit_mir_instruction(ctx
, ins
);
1018 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1019 * pinning to eliminate this move in all known cases */
1022 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1024 int offset
= nir_src_index(ctx
, src
);
1026 midgard_instruction ins
= {
1029 .src0
= SSA_UNUSED_1
,
1031 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1034 .op
= midgard_alu_op_imov
,
1035 .reg_mode
= midgard_reg_mode_full
,
1036 .dest_override
= midgard_dest_override_none
,
1037 .mask
= (0x3 << 6), /* w */
1038 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1039 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1043 emit_mir_instruction(ctx
, ins
);
1046 #define ALU_CASE(nir, _op) \
1047 case nir_op_##nir: \
1048 op = midgard_alu_op_##_op; \
1052 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1054 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1056 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1057 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1058 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1060 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1061 * supported. A few do not and are commented for now. Also, there are a
1062 * number of NIR ops which Midgard does not support and need to be
1063 * lowered, also TODO. This switch block emits the opcode and calling
1064 * convention of the Midgard instruction; actual packing is done in
1069 switch (instr
->op
) {
1070 ALU_CASE(fadd
, fadd
);
1071 ALU_CASE(fmul
, fmul
);
1072 ALU_CASE(fmin
, fmin
);
1073 ALU_CASE(fmax
, fmax
);
1074 ALU_CASE(imin
, imin
);
1075 ALU_CASE(imax
, imax
);
1076 ALU_CASE(umin
, umin
);
1077 ALU_CASE(umax
, umax
);
1078 ALU_CASE(fmov
, fmov
);
1079 ALU_CASE(ffloor
, ffloor
);
1080 ALU_CASE(fround_even
, froundeven
);
1081 ALU_CASE(ftrunc
, ftrunc
);
1082 ALU_CASE(fceil
, fceil
);
1083 ALU_CASE(fdot3
, fdot3
);
1084 ALU_CASE(fdot4
, fdot4
);
1085 ALU_CASE(iadd
, iadd
);
1086 ALU_CASE(isub
, isub
);
1087 ALU_CASE(imul
, imul
);
1088 ALU_CASE(iabs
, iabs
);
1090 /* XXX: Use fmov, not imov, since imov was causing major
1091 * issues with texture precision? XXX research */
1092 ALU_CASE(imov
, fmov
);
1094 ALU_CASE(feq32
, feq
);
1095 ALU_CASE(fne32
, fne
);
1096 ALU_CASE(flt32
, flt
);
1097 ALU_CASE(ieq32
, ieq
);
1098 ALU_CASE(ine32
, ine
);
1099 ALU_CASE(ilt32
, ilt
);
1100 ALU_CASE(ult32
, ult
);
1102 /* We don't have a native b2f32 instruction. Instead, like many
1103 * GPUs, we exploit booleans as 0/~0 for false/true, and
1104 * correspondingly AND
1105 * by 1.0 to do the type conversion. For the moment, prime us
1108 * iand [whatever], #0
1110 * At the end of emit_alu (as MIR), we'll fix-up the constant
1113 ALU_CASE(b2f32
, iand
);
1114 ALU_CASE(b2i32
, iand
);
1116 /* Likewise, we don't have a dedicated f2b32 instruction, but
1117 * we can do a "not equal to 0.0" test. */
1119 ALU_CASE(f2b32
, fne
);
1120 ALU_CASE(i2b32
, ine
);
1122 ALU_CASE(frcp
, frcp
);
1123 ALU_CASE(frsq
, frsqrt
);
1124 ALU_CASE(fsqrt
, fsqrt
);
1125 ALU_CASE(fexp2
, fexp2
);
1126 ALU_CASE(flog2
, flog2
);
1128 ALU_CASE(f2i32
, f2i
);
1129 ALU_CASE(f2u32
, f2u
);
1130 ALU_CASE(i2f32
, i2f
);
1131 ALU_CASE(u2f32
, u2f
);
1133 ALU_CASE(fsin
, fsin
);
1134 ALU_CASE(fcos
, fcos
);
1136 ALU_CASE(iand
, iand
);
1138 ALU_CASE(ixor
, ixor
);
1139 ALU_CASE(inot
, inot
);
1140 ALU_CASE(ishl
, ishl
);
1141 ALU_CASE(ishr
, iasr
);
1142 ALU_CASE(ushr
, ilsr
);
1144 ALU_CASE(b32all_fequal2
, fball_eq
);
1145 ALU_CASE(b32all_fequal3
, fball_eq
);
1146 ALU_CASE(b32all_fequal4
, fball_eq
);
1148 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1149 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1150 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1152 ALU_CASE(b32all_iequal2
, iball_eq
);
1153 ALU_CASE(b32all_iequal3
, iball_eq
);
1154 ALU_CASE(b32all_iequal4
, iball_eq
);
1156 ALU_CASE(b32any_inequal2
, ibany_neq
);
1157 ALU_CASE(b32any_inequal3
, ibany_neq
);
1158 ALU_CASE(b32any_inequal4
, ibany_neq
);
1160 /* For greater-or-equal, we lower to less-or-equal and flip the
1166 case nir_op_uge32
: {
1168 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1169 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1170 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1171 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1174 /* Swap via temporary */
1175 nir_alu_src temp
= instr
->src
[1];
1176 instr
->src
[1] = instr
->src
[0];
1177 instr
->src
[0] = temp
;
1182 case nir_op_b32csel
: {
1183 op
= midgard_alu_op_fcsel
;
1185 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1188 /* Figure out which component the condition is in */
1190 unsigned comp
= instr
->src
[0].swizzle
[0];
1192 /* Make sure NIR isn't throwing a mixed condition at us */
1194 for (unsigned c
= 1; c
< nr_components
; ++c
)
1195 assert(instr
->src
[0].swizzle
[c
] == comp
);
1197 /* Emit the condition into r31.w */
1198 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1200 /* The condition is the first argument; move the other
1201 * arguments up one to be a binary instruction for
1204 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1209 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1214 /* Fetch unit, quirks, etc information */
1215 unsigned opcode_props
= alu_opcode_props
[op
];
1216 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1218 /* Initialise fields common between scalar/vector instructions */
1219 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1221 /* src0 will always exist afaik, but src1 will not for 1-argument
1222 * instructions. The latter can only be fetched if the instruction
1223 * needs it, or else we may segfault. */
1225 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1226 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1228 /* Rather than use the instruction generation helpers, we do it
1229 * ourselves here to avoid the mess */
1231 midgard_instruction ins
= {
1234 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1235 .src1
= quirk_flipped_r24
? src0
: src1
,
1240 nir_alu_src
*nirmods
[2] = { NULL
};
1242 if (nr_inputs
== 2) {
1243 nirmods
[0] = &instr
->src
[0];
1244 nirmods
[1] = &instr
->src
[1];
1245 } else if (nr_inputs
== 1) {
1246 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1251 midgard_vector_alu alu
= {
1253 .reg_mode
= midgard_reg_mode_full
,
1254 .dest_override
= midgard_dest_override_none
,
1257 /* Writemask only valid for non-SSA NIR */
1258 .mask
= expand_writemask((1 << nr_components
) - 1),
1260 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1261 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1264 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1267 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1271 /* Late fixup for emulated instructions */
1273 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1274 /* Presently, our second argument is an inline #0 constant.
1275 * Switch over to an embedded 1.0 constant (that can't fit
1276 * inline, since we're 32-bit, not 16-bit like the inline
1279 ins
.ssa_args
.inline_constant
= false;
1280 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1281 ins
.has_constants
= true;
1283 if (instr
->op
== nir_op_b2f32
) {
1284 ins
.constants
[0] = 1.0f
;
1286 /* Type pun it into place */
1288 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1291 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1292 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1293 ins
.ssa_args
.inline_constant
= false;
1294 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1295 ins
.has_constants
= true;
1296 ins
.constants
[0] = 0.0f
;
1297 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1300 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1301 /* To avoid duplicating the lookup tables (probably), true LUT
1302 * instructions can only operate as if they were scalars. Lower
1303 * them here by changing the component. */
1305 uint8_t original_swizzle
[4];
1306 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1308 for (int i
= 0; i
< nr_components
; ++i
) {
1309 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1311 for (int j
= 0; j
< 4; ++j
)
1312 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1314 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1315 emit_mir_instruction(ctx
, ins
);
1318 emit_mir_instruction(ctx
, ins
);
1325 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1327 /* TODO: half-floats */
1329 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1330 /* Fast path: For the first 16 uniforms, direct accesses are
1331 * 0-cycle, since they're just a register fetch in the usual
1332 * case. So, we alias the registers while we're still in
1335 int reg_slot
= 23 - offset
;
1336 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1338 /* Otherwise, read from the 'special' UBO to access
1339 * higher-indexed uniforms, at a performance cost. More
1340 * generally, we're emitting a UBO read instruction. */
1342 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1344 /* TODO: Don't split */
1345 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1346 ins
.load_store
.address
= offset
>> 3;
1348 if (indirect_offset
) {
1349 emit_indirect_offset(ctx
, indirect_offset
);
1350 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1352 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1355 emit_mir_instruction(ctx
, ins
);
1360 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1362 /* First, pull out the destination */
1363 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1365 /* Now, figure out which uniform this is */
1366 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1367 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1369 /* Sysvals are prefix uniforms */
1370 unsigned uniform
= ((uintptr_t) val
) - 1;
1372 /* Emit the read itself -- this is never indirect */
1373 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1377 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1379 unsigned offset
, reg
;
1381 switch (instr
->intrinsic
) {
1382 case nir_intrinsic_discard_if
:
1383 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1387 case nir_intrinsic_discard
: {
1388 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1389 struct midgard_instruction discard
= v_branch(conditional
, false);
1390 discard
.branch
.target_type
= TARGET_DISCARD
;
1391 emit_mir_instruction(ctx
, discard
);
1393 ctx
->can_discard
= true;
1397 case nir_intrinsic_load_uniform
:
1398 case nir_intrinsic_load_input
:
1399 offset
= nir_intrinsic_base(instr
);
1401 bool direct
= nir_src_is_const(instr
->src
[0]);
1404 offset
+= nir_src_as_uint(instr
->src
[0]);
1407 reg
= nir_dest_index(ctx
, &instr
->dest
);
1409 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1410 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1411 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1412 /* XXX: Half-floats? */
1413 /* TODO: swizzle, mask */
1415 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1417 midgard_varying_parameter p
= {
1419 .interpolation
= midgard_interp_default
,
1420 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1424 memcpy(&u
, &p
, sizeof(p
));
1425 ins
.load_store
.varying_parameters
= u
;
1428 /* We have the offset totally ready */
1429 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1431 /* We have it partially ready, but we need to
1432 * add in the dynamic index, moved to r27.w */
1433 emit_indirect_offset(ctx
, &instr
->src
[0]);
1434 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1437 emit_mir_instruction(ctx
, ins
);
1438 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1439 /* Constant encoded as a pinned constant */
1441 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1442 ins
.has_constants
= true;
1443 ins
.has_blend_constant
= true;
1444 emit_mir_instruction(ctx
, ins
);
1445 } else if (ctx
->is_blend
) {
1446 /* For blend shaders, a load might be
1447 * translated various ways depending on what
1448 * we're loading. Figure out how this is used */
1450 nir_variable
*out
= NULL
;
1452 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1453 int drvloc
= var
->data
.driver_location
;
1455 if (nir_intrinsic_base(instr
) == drvloc
) {
1463 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1464 /* Source color preloaded to r0 */
1466 midgard_pin_output(ctx
, reg
, 0);
1467 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1468 /* Destination color must be read from framebuffer */
1470 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1471 ins
.load_store
.swizzle
= 0; /* xxxx */
1473 /* Read each component sequentially */
1475 for (int c
= 0; c
< 4; ++c
) {
1476 ins
.load_store
.mask
= (1 << c
);
1477 ins
.load_store
.unknown
= c
;
1478 emit_mir_instruction(ctx
, ins
);
1481 /* vadd.u2f hr2, abs(hr2), #0 */
1483 midgard_vector_alu_src alu_src
= blank_alu_src
;
1485 alu_src
.half
= true;
1487 midgard_instruction u2f
= {
1491 .src1
= SSA_UNUSED_0
,
1493 .inline_constant
= true
1496 .op
= midgard_alu_op_u2f
,
1497 .reg_mode
= midgard_reg_mode_half
,
1498 .dest_override
= midgard_dest_override_none
,
1500 .src1
= vector_alu_srco_unsigned(alu_src
),
1501 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1505 emit_mir_instruction(ctx
, u2f
);
1507 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1509 alu_src
.abs
= false;
1511 midgard_instruction fmul
= {
1513 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1517 .src1
= SSA_UNUSED_0
,
1518 .inline_constant
= true
1521 .op
= midgard_alu_op_fmul
,
1522 .reg_mode
= midgard_reg_mode_full
,
1523 .dest_override
= midgard_dest_override_none
,
1524 .outmod
= midgard_outmod_sat
,
1526 .src1
= vector_alu_srco_unsigned(alu_src
),
1527 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1531 emit_mir_instruction(ctx
, fmul
);
1533 DBG("Unknown input in blend shader\n");
1536 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1537 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1538 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1539 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1540 emit_mir_instruction(ctx
, ins
);
1542 DBG("Unknown load\n");
1548 case nir_intrinsic_store_output
:
1549 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1551 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1553 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1555 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1556 /* gl_FragColor is not emitted with load/store
1557 * instructions. Instead, it gets plonked into
1558 * r0 at the end of the shader and we do the
1559 * framebuffer writeout dance. TODO: Defer
1562 midgard_pin_output(ctx
, reg
, 0);
1564 /* Save the index we're writing to for later reference
1565 * in the epilogue */
1567 ctx
->fragment_output
= reg
;
1568 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1569 /* Varyings are written into one of two special
1570 * varying register, r26 or r27. The register itself is selected as the register
1571 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1573 * Normally emitting fmov's is frowned upon,
1574 * but due to unique constraints of
1575 * REGISTER_VARYING, fmov emission + a
1576 * dedicated cleanup pass is the only way to
1577 * guarantee correctness when considering some
1578 * (common) edge cases XXX: FIXME */
1580 /* If this varying corresponds to a constant (why?!),
1581 * emit that now since it won't get picked up by
1582 * hoisting (since there is no corresponding move
1583 * emitted otherwise) */
1585 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1587 if (constant_value
) {
1588 /* Special case: emit the varying write
1589 * directly to r26 (looks funny in asm but it's
1590 * fine) and emit the store _now_. Possibly
1591 * slightly slower, but this is a really stupid
1592 * special case anyway (why on earth would you
1593 * have a constant varying? Your own fault for
1594 * slightly worse perf :P) */
1596 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1597 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1598 emit_mir_instruction(ctx
, ins
);
1600 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1601 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1602 emit_mir_instruction(ctx
, st
);
1604 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1606 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1609 DBG("Unknown store\n");
1615 case nir_intrinsic_load_alpha_ref_float
:
1616 assert(instr
->dest
.is_ssa
);
1618 float ref_value
= ctx
->alpha_ref
;
1620 float *v
= ralloc_array(NULL
, float, 4);
1621 memcpy(v
, &ref_value
, sizeof(float));
1622 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1625 case nir_intrinsic_load_viewport_scale
:
1626 case nir_intrinsic_load_viewport_offset
:
1627 emit_sysval_read(ctx
, instr
);
1631 printf ("Unhandled intrinsic\n");
1638 midgard_tex_format(enum glsl_sampler_dim dim
)
1641 case GLSL_SAMPLER_DIM_2D
:
1642 case GLSL_SAMPLER_DIM_EXTERNAL
:
1645 case GLSL_SAMPLER_DIM_3D
:
1648 case GLSL_SAMPLER_DIM_CUBE
:
1649 return TEXTURE_CUBE
;
1652 DBG("Unknown sampler dim type\n");
1659 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1662 //assert (!instr->sampler);
1663 //assert (!instr->texture_array_size);
1664 assert (instr
->op
== nir_texop_tex
);
1666 /* Allocate registers via a round robin scheme to alternate between the two registers */
1667 int reg
= ctx
->texture_op_count
& 1;
1668 int in_reg
= reg
, out_reg
= reg
;
1670 /* Make room for the reg */
1672 if (ctx
->texture_index
[reg
] > -1)
1673 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1675 int texture_index
= instr
->texture_index
;
1676 int sampler_index
= texture_index
;
1678 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1679 switch (instr
->src
[i
].src_type
) {
1680 case nir_tex_src_coord
: {
1681 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1683 midgard_vector_alu_src alu_src
= blank_alu_src
;
1685 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1687 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1688 /* For cubemaps, we need to load coords into
1689 * special r27, and then use a special ld/st op
1690 * to copy into the texture register */
1692 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1694 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1695 emit_mir_instruction(ctx
, move
);
1697 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1698 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1699 st
.load_store
.mask
= 0x3; /* xy? */
1700 st
.load_store
.swizzle
= alu_src
.swizzle
;
1701 emit_mir_instruction(ctx
, st
);
1704 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1706 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1707 emit_mir_instruction(ctx
, ins
);
1710 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1716 DBG("Unknown source type\n");
1723 /* No helper to build texture words -- we do it all here */
1724 midgard_instruction ins
= {
1725 .type
= TAG_TEXTURE_4
,
1727 .op
= TEXTURE_OP_NORMAL
,
1728 .format
= midgard_tex_format(instr
->sampler_dim
),
1729 .texture_handle
= texture_index
,
1730 .sampler_handle
= sampler_index
,
1732 /* TODO: Don't force xyzw */
1733 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1745 /* Assume we can continue; hint it out later */
1750 /* Set registers to read and write from the same place */
1751 ins
.texture
.in_reg_select
= in_reg
;
1752 ins
.texture
.out_reg_select
= out_reg
;
1754 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1755 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1756 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1757 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1758 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1760 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1761 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1762 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1765 emit_mir_instruction(ctx
, ins
);
1767 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1769 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1770 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1771 ctx
->texture_index
[reg
] = o_index
;
1773 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1774 emit_mir_instruction(ctx
, ins2
);
1776 /* Used for .cont and .last hinting */
1777 ctx
->texture_op_count
++;
1781 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1783 switch (instr
->type
) {
1784 case nir_jump_break
: {
1785 /* Emit a branch out of the loop */
1786 struct midgard_instruction br
= v_branch(false, false);
1787 br
.branch
.target_type
= TARGET_BREAK
;
1788 br
.branch
.target_break
= ctx
->current_loop
;
1789 emit_mir_instruction(ctx
, br
);
1796 DBG("Unknown jump type %d\n", instr
->type
);
1802 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1804 switch (instr
->type
) {
1805 case nir_instr_type_load_const
:
1806 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1809 case nir_instr_type_intrinsic
:
1810 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1813 case nir_instr_type_alu
:
1814 emit_alu(ctx
, nir_instr_as_alu(instr
));
1817 case nir_instr_type_tex
:
1818 emit_tex(ctx
, nir_instr_as_tex(instr
));
1821 case nir_instr_type_jump
:
1822 emit_jump(ctx
, nir_instr_as_jump(instr
));
1825 case nir_instr_type_ssa_undef
:
1830 DBG("Unhandled instruction type\n");
1835 /* Determine the actual hardware from the index based on the RA results or special values */
1838 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1840 if (reg
>= SSA_FIXED_MINIMUM
)
1841 return SSA_REG_FROM_FIXED(reg
);
1844 assert(reg
< maxreg
);
1845 int r
= ra_get_node_reg(g
, reg
);
1846 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1851 /* fmov style unused */
1853 return REGISTER_UNUSED
;
1855 /* lut style unused */
1857 return REGISTER_UNUSED
;
1860 DBG("Unknown SSA register alias %d\n", reg
);
1867 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1869 /* Choose the first available register to minimise reported register pressure */
1871 for (int i
= 0; i
< 16; ++i
) {
1872 if (BITSET_TEST(regs
, i
)) {
1882 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1884 if (ins
->ssa_args
.src0
== src
) return true;
1885 if (ins
->ssa_args
.src1
== src
) return true;
1890 /* Determine if a variable is live in the successors of a block */
1892 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
1894 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
1895 midgard_block
*succ
= bl
->successors
[i
];
1897 /* If we already visited, the value we're seeking
1898 * isn't down this path (or we would have short
1901 if (succ
->visited
) continue;
1903 /* Otherwise (it's visited *now*), check the block */
1905 succ
->visited
= true;
1907 mir_foreach_instr_in_block(succ
, ins
) {
1908 if (midgard_is_live_in_instr(ins
, src
))
1912 /* ...and also, check *its* successors */
1913 if (is_live_after_successors(ctx
, succ
, src
))
1918 /* Welp. We're really not live. */
1924 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1926 /* Check the rest of the block for liveness */
1928 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1929 if (midgard_is_live_in_instr(ins
, src
))
1933 /* Check the rest of the blocks for liveness recursively */
1935 bool succ
= is_live_after_successors(ctx
, block
, src
);
1937 mir_foreach_block(ctx
, block
) {
1938 block
->visited
= false;
1945 allocate_registers(compiler_context
*ctx
)
1947 /* First, initialize the RA */
1948 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1950 /* Create a primary (general purpose) class, as well as special purpose
1951 * pipeline register classes */
1953 int primary_class
= ra_alloc_reg_class(regs
);
1954 int varying_class
= ra_alloc_reg_class(regs
);
1956 /* Add the full set of work registers */
1957 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1958 for (int i
= 0; i
< work_count
; ++i
)
1959 ra_class_add_reg(regs
, primary_class
, i
);
1961 /* Add special registers */
1962 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1963 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1965 /* We're done setting up */
1966 ra_set_finalize(regs
, NULL
);
1968 /* Transform the MIR into squeezed index form */
1969 mir_foreach_block(ctx
, block
) {
1970 mir_foreach_instr_in_block(block
, ins
) {
1971 if (ins
->compact_branch
) continue;
1973 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1974 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1975 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1977 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1978 print_mir_block(block
);
1981 /* Let's actually do register allocation */
1982 int nodes
= ctx
->temp_count
;
1983 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1985 /* Set everything to the work register class, unless it has somewhere
1988 mir_foreach_block(ctx
, block
) {
1989 mir_foreach_instr_in_block(block
, ins
) {
1990 if (ins
->compact_branch
) continue;
1992 if (ins
->ssa_args
.dest
< 0) continue;
1994 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1996 int class = primary_class
;
1998 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2002 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2003 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2006 unsigned reg
= temp
- 1;
2007 int t
= find_or_allocate_temp(ctx
, index
);
2008 ra_set_node_reg(g
, t
, reg
);
2012 /* Determine liveness */
2014 int *live_start
= malloc(nodes
* sizeof(int));
2015 int *live_end
= malloc(nodes
* sizeof(int));
2017 /* Initialize as non-existent */
2019 for (int i
= 0; i
< nodes
; ++i
) {
2020 live_start
[i
] = live_end
[i
] = -1;
2025 mir_foreach_block(ctx
, block
) {
2026 mir_foreach_instr_in_block(block
, ins
) {
2027 if (ins
->compact_branch
) continue;
2029 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2030 /* If this destination is not yet live, it is now since we just wrote it */
2032 int dest
= ins
->ssa_args
.dest
;
2034 if (live_start
[dest
] == -1)
2035 live_start
[dest
] = d
;
2038 /* Since we just used a source, the source might be
2039 * dead now. Scan the rest of the block for
2040 * invocations, and if there are none, the source dies
2043 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2045 for (int src
= 0; src
< 2; ++src
) {
2046 int s
= sources
[src
];
2048 if (s
< 0) continue;
2050 if (s
>= SSA_FIXED_MINIMUM
) continue;
2052 if (!is_live_after(ctx
, block
, ins
, s
)) {
2061 /* If a node still hasn't been killed, kill it now */
2063 for (int i
= 0; i
< nodes
; ++i
) {
2064 /* live_start == -1 most likely indicates a pinned output */
2066 if (live_end
[i
] == -1)
2070 /* Setup interference between nodes that are live at the same time */
2072 for (int i
= 0; i
< nodes
; ++i
) {
2073 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2074 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2075 ra_add_node_interference(g
, i
, j
);
2079 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2081 if (!ra_allocate(g
)) {
2082 DBG("Error allocating registers\n");
2090 mir_foreach_block(ctx
, block
) {
2091 mir_foreach_instr_in_block(block
, ins
) {
2092 if (ins
->compact_branch
) continue;
2094 ssa_args args
= ins
->ssa_args
;
2096 switch (ins
->type
) {
2098 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2100 ins
->registers
.src2_imm
= args
.inline_constant
;
2102 if (args
.inline_constant
) {
2103 /* Encode inline 16-bit constant as a vector by default */
2105 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2107 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2109 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2110 ins
->alu
.src2
= imm
<< 2;
2112 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2115 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2119 case TAG_LOAD_STORE_4
: {
2120 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2121 /* TODO: use ssa_args for store_vary */
2122 ins
->load_store
.reg
= 0;
2124 bool has_dest
= args
.dest
>= 0;
2125 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2127 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2140 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2141 * use scalar ALU instructions, for functional or performance reasons. To do
2142 * this, we just demote vector ALU payloads to scalar. */
2145 component_from_mask(unsigned mask
)
2147 for (int c
= 0; c
< 4; ++c
) {
2148 if (mask
& (3 << (2 * c
)))
2157 is_single_component_mask(unsigned mask
)
2161 for (int c
= 0; c
< 4; ++c
)
2162 if (mask
& (3 << (2 * c
)))
2165 return components
== 1;
2168 /* Create a mask of accessed components from a swizzle to figure out vector
2172 swizzle_to_access_mask(unsigned swizzle
)
2174 unsigned component_mask
= 0;
2176 for (int i
= 0; i
< 4; ++i
) {
2177 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2178 component_mask
|= (1 << c
);
2181 return component_mask
;
2185 vector_to_scalar_source(unsigned u
)
2187 midgard_vector_alu_src v
;
2188 memcpy(&v
, &u
, sizeof(v
));
2190 midgard_scalar_alu_src s
= {
2194 .component
= (v
.swizzle
& 3) << 1
2198 memcpy(&o
, &s
, sizeof(s
));
2200 return o
& ((1 << 6) - 1);
2203 static midgard_scalar_alu
2204 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2206 /* The output component is from the mask */
2207 midgard_scalar_alu s
= {
2209 .src1
= vector_to_scalar_source(v
.src1
),
2210 .src2
= vector_to_scalar_source(v
.src2
),
2213 .output_full
= 1, /* TODO: Half */
2214 .output_component
= component_from_mask(v
.mask
) << 1,
2217 /* Inline constant is passed along rather than trying to extract it
2220 if (ins
->ssa_args
.inline_constant
) {
2222 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2223 imm
|= (lower_11
>> 9) & 3;
2224 imm
|= (lower_11
>> 6) & 4;
2225 imm
|= (lower_11
>> 2) & 0x38;
2226 imm
|= (lower_11
& 63) << 6;
2234 /* Midgard prefetches instruction types, so during emission we need to
2235 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2236 * if this is the second to last and the last is an ALU, then it's also 1... */
2238 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2239 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2241 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2242 bytes_emitted += sizeof(type)
2245 emit_binary_vector_instruction(midgard_instruction
*ains
,
2246 uint16_t *register_words
, int *register_words_count
,
2247 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2248 size_t *bytes_emitted
)
2250 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2251 *bytes_emitted
+= sizeof(midgard_reg_info
);
2253 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2254 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2255 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2258 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2259 * mind that we are a vector architecture and we can write to different
2260 * components simultaneously */
2263 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2265 /* Each instruction reads some registers and writes to a register. See
2266 * where the first writes */
2268 /* Figure out where exactly we wrote to */
2269 int source
= first
->ssa_args
.dest
;
2270 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2272 /* As long as the second doesn't read from the first, we're okay */
2273 if (second
->ssa_args
.src0
== source
) {
2274 if (first
->type
== TAG_ALU_4
) {
2275 /* Figure out which components we just read from */
2277 int q
= second
->alu
.src1
;
2278 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2280 /* Check if there are components in common, and fail if so */
2281 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2288 if (second
->ssa_args
.src1
== source
)
2291 /* Otherwise, it's safe in that regard. Another data hazard is both
2292 * writing to the same place, of course */
2294 if (second
->ssa_args
.dest
== source
) {
2295 /* ...but only if the components overlap */
2296 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2298 if (dest_mask
& source_mask
)
2308 midgard_instruction
**segment
, unsigned segment_size
,
2309 midgard_instruction
*ains
)
2311 for (int s
= 0; s
< segment_size
; ++s
)
2312 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2320 /* Schedules, but does not emit, a single basic block. After scheduling, the
2321 * final tag and size of the block are known, which are necessary for branching
2324 static midgard_bundle
2325 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2327 int instructions_emitted
= 0, instructions_consumed
= -1;
2328 midgard_bundle bundle
= { 0 };
2330 uint8_t tag
= ins
->type
;
2332 /* Default to the instruction's tag */
2335 switch (ins
->type
) {
2337 uint32_t control
= 0;
2338 size_t bytes_emitted
= sizeof(control
);
2340 /* TODO: Constant combining */
2341 int index
= 0, last_unit
= 0;
2343 /* Previous instructions, for the purpose of parallelism */
2344 midgard_instruction
*segment
[4] = {0};
2345 int segment_size
= 0;
2347 instructions_emitted
= -1;
2348 midgard_instruction
*pins
= ins
;
2351 midgard_instruction
*ains
= pins
;
2353 /* Advance instruction pointer */
2355 ains
= mir_next_op(pins
);
2359 /* Out-of-work condition */
2360 if ((struct list_head
*) ains
== &block
->instructions
)
2363 /* Ensure that the chain can continue */
2364 if (ains
->type
!= TAG_ALU_4
) break;
2366 /* According to the presentation "The ARM
2367 * Mali-T880 Mobile GPU" from HotChips 27,
2368 * there are two pipeline stages. Branching
2369 * position determined experimentally. Lines
2370 * are executed in parallel:
2373 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2375 * Verify that there are no ordering dependencies here.
2377 * TODO: Allow for parallelism!!!
2380 /* Pick a unit for it if it doesn't force a particular unit */
2382 int unit
= ains
->unit
;
2385 int op
= ains
->alu
.op
;
2386 int units
= alu_opcode_props
[op
];
2388 /* TODO: Promotion of scalars to vectors */
2389 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2392 assert(units
& UNITS_SCALAR
);
2395 if (last_unit
>= UNIT_VADD
) {
2396 if (units
& UNIT_VLUT
)
2401 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2403 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2405 else if (units
& UNIT_VLUT
)
2411 if (last_unit
>= UNIT_VADD
) {
2412 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2414 else if (units
& UNIT_VLUT
)
2419 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2421 else if (units
& UNIT_SMUL
)
2422 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2423 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2430 assert(unit
& units
);
2433 /* Late unit check, this time for encoding (not parallelism) */
2434 if (unit
<= last_unit
) break;
2436 /* Clear the segment */
2437 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2440 if (midgard_has_hazard(segment
, segment_size
, ains
))
2443 /* We're good to go -- emit the instruction */
2446 segment
[segment_size
++] = ains
;
2448 /* Only one set of embedded constants per
2449 * bundle possible; if we have more, we must
2450 * break the chain early, unfortunately */
2452 if (ains
->has_constants
) {
2453 if (bundle
.has_embedded_constants
) {
2454 /* ...but if there are already
2455 * constants but these are the
2456 * *same* constants, we let it
2459 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2462 bundle
.has_embedded_constants
= true;
2463 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2465 /* If this is a blend shader special constant, track it for patching */
2466 if (ains
->has_blend_constant
)
2467 bundle
.has_blend_constant
= true;
2471 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2472 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2473 &bundle
.register_words_count
, bundle
.body_words
,
2474 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2475 } else if (ains
->compact_branch
) {
2476 /* All of r0 has to be written out
2477 * along with the branch writeout.
2480 if (ains
->writeout
) {
2482 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2483 ins
.unit
= UNIT_VMUL
;
2485 control
|= ins
.unit
;
2487 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2488 &bundle
.register_words_count
, bundle
.body_words
,
2489 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2491 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2492 bool written_late
= false;
2493 bool components
[4] = { 0 };
2494 uint16_t register_dep_mask
= 0;
2495 uint16_t written_mask
= 0;
2497 midgard_instruction
*qins
= ins
;
2498 for (int t
= 0; t
< index
; ++t
) {
2499 if (qins
->registers
.out_reg
!= 0) {
2500 /* Mark down writes */
2502 written_mask
|= (1 << qins
->registers
.out_reg
);
2504 /* Mark down the register dependencies for errata check */
2506 if (qins
->registers
.src1_reg
< 16)
2507 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2509 if (qins
->registers
.src2_reg
< 16)
2510 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2512 int mask
= qins
->alu
.mask
;
2514 for (int c
= 0; c
< 4; ++c
)
2515 if (mask
& (0x3 << (2 * c
)))
2516 components
[c
] = true;
2518 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2520 if (qins
->unit
== UNIT_VLUT
)
2521 written_late
= true;
2524 /* Advance instruction pointer */
2525 qins
= mir_next_op(qins
);
2529 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2530 if (register_dep_mask
& written_mask
) {
2531 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2538 /* If even a single component is not written, break it up (conservative check). */
2539 bool breakup
= false;
2541 for (int c
= 0; c
< 4; ++c
)
2548 /* Otherwise, we're free to proceed */
2552 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2553 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2554 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2555 bytes_emitted
+= sizeof(midgard_branch_extended
);
2557 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2558 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2559 bytes_emitted
+= sizeof(ains
->br_compact
);
2562 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2563 bytes_emitted
+= sizeof(midgard_reg_info
);
2565 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2566 bundle
.body_words_count
++;
2567 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2570 /* Defer marking until after writing to allow for break */
2571 control
|= ains
->unit
;
2572 last_unit
= ains
->unit
;
2573 ++instructions_emitted
;
2577 /* Bubble up the number of instructions for skipping */
2578 instructions_consumed
= index
- 1;
2582 /* Pad ALU op to nearest word */
2584 if (bytes_emitted
& 15) {
2585 padding
= 16 - (bytes_emitted
& 15);
2586 bytes_emitted
+= padding
;
2589 /* Constants must always be quadwords */
2590 if (bundle
.has_embedded_constants
)
2591 bytes_emitted
+= 16;
2593 /* Size ALU instruction for tag */
2594 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2595 bundle
.padding
= padding
;
2596 bundle
.control
= bundle
.tag
| control
;
2601 case TAG_LOAD_STORE_4
: {
2602 /* Load store instructions have two words at once. If
2603 * we only have one queued up, we need to NOP pad.
2604 * Otherwise, we store both in succession to save space
2605 * and cycles -- letting them go in parallel -- skip
2606 * the next. The usefulness of this optimisation is
2607 * greatly dependent on the quality of the instruction
2611 midgard_instruction
*next_op
= mir_next_op(ins
);
2613 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2614 /* As the two operate concurrently, make sure
2615 * they are not dependent */
2617 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2618 /* Skip ahead, since it's redundant with the pair */
2619 instructions_consumed
= 1 + (instructions_emitted
++);
2627 /* Texture ops default to single-op-per-bundle scheduling */
2631 /* Copy the instructions into the bundle */
2632 bundle
.instruction_count
= instructions_emitted
+ 1;
2636 midgard_instruction
*uins
= ins
;
2637 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2638 bundle
.instructions
[used_idx
++] = *uins
;
2639 uins
= mir_next_op(uins
);
2642 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2648 quadword_size(int tag
)
2663 case TAG_LOAD_STORE_4
:
2675 /* Schedule a single block by iterating its instruction to create bundles.
2676 * While we go, tally about the bundle sizes to compute the block size. */
2679 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2681 util_dynarray_init(&block
->bundles
, NULL
);
2683 block
->quadword_count
= 0;
2685 mir_foreach_instr_in_block(block
, ins
) {
2687 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2688 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2690 if (bundle
.has_blend_constant
) {
2691 /* TODO: Multiblock? */
2692 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2693 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2697 ins
= mir_next_op(ins
);
2699 block
->quadword_count
+= quadword_size(bundle
.tag
);
2702 block
->is_scheduled
= true;
2706 schedule_program(compiler_context
*ctx
)
2708 allocate_registers(ctx
);
2710 mir_foreach_block(ctx
, block
) {
2711 schedule_block(ctx
, block
);
2715 /* After everything is scheduled, emit whole bundles at a time */
2718 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2720 int lookahead
= next_tag
<< 4;
2722 switch (bundle
->tag
) {
2727 /* Actually emit each component */
2728 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2730 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2731 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2733 /* Emit body words based on the instructions bundled */
2734 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2735 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2737 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2738 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2739 } else if (ins
->compact_branch
) {
2740 /* Dummy move, XXX DRY */
2741 if ((i
== 0) && ins
->writeout
) {
2742 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2743 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2746 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2747 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2749 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2753 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2754 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2758 /* Emit padding (all zero) */
2759 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2761 /* Tack on constants */
2763 if (bundle
->has_embedded_constants
) {
2764 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2765 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2766 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2767 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2773 case TAG_LOAD_STORE_4
: {
2774 /* One or two composing instructions */
2776 uint64_t current64
, next64
= LDST_NOP
;
2778 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2780 if (bundle
->instruction_count
== 2)
2781 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2783 midgard_load_store instruction
= {
2784 .type
= bundle
->tag
,
2785 .next_type
= next_tag
,
2790 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2795 case TAG_TEXTURE_4
: {
2796 /* Texture instructions are easy, since there is no
2797 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2799 midgard_instruction
*ins
= &bundle
->instructions
[0];
2801 ins
->texture
.type
= TAG_TEXTURE_4
;
2802 ins
->texture
.next_type
= next_tag
;
2804 ctx
->texture_op_count
--;
2806 if (!ctx
->texture_op_count
) {
2807 ins
->texture
.cont
= 0;
2808 ins
->texture
.last
= 1;
2811 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2816 DBG("Unknown midgard instruction type\n");
2823 /* ALU instructions can inline or embed constants, which decreases register
2824 * pressure and saves space. */
2826 #define CONDITIONAL_ATTACH(src) { \
2827 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2830 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2831 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2836 inline_alu_constants(compiler_context
*ctx
)
2838 mir_foreach_instr(ctx
, alu
) {
2839 /* Other instructions cannot inline constants */
2840 if (alu
->type
!= TAG_ALU_4
) continue;
2842 /* If there is already a constant here, we can do nothing */
2843 if (alu
->has_constants
) continue;
2845 CONDITIONAL_ATTACH(src0
);
2847 if (!alu
->has_constants
) {
2848 CONDITIONAL_ATTACH(src1
)
2849 } else if (!alu
->inline_constant
) {
2850 /* Corner case: _two_ vec4 constants, for instance with a
2851 * csel. For this case, we can only use a constant
2852 * register for one, we'll have to emit a move for the
2853 * other. Note, if both arguments are constants, then
2854 * necessarily neither argument depends on the value of
2855 * any particular register. As the destination register
2856 * will be wiped, that means we can spill the constant
2857 * to the destination register.
2860 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2861 unsigned scratch
= alu
->ssa_args
.dest
;
2864 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2865 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2867 /* Force a break XXX Defer r31 writes */
2868 ins
.unit
= UNIT_VLUT
;
2870 /* Set the source */
2871 alu
->ssa_args
.src1
= scratch
;
2873 /* Inject us -before- the last instruction which set r31 */
2874 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2880 /* Midgard supports two types of constants, embedded constants (128-bit) and
2881 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2882 * constants can be demoted to inline constants, for space savings and
2883 * sometimes a performance boost */
2886 embedded_to_inline_constant(compiler_context
*ctx
)
2888 mir_foreach_instr(ctx
, ins
) {
2889 if (!ins
->has_constants
) continue;
2891 if (ins
->ssa_args
.inline_constant
) continue;
2893 /* Blend constants must not be inlined by definition */
2894 if (ins
->has_blend_constant
) continue;
2896 /* src1 cannot be an inline constant due to encoding
2897 * restrictions. So, if possible we try to flip the arguments
2900 int op
= ins
->alu
.op
;
2902 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2903 /* Flip based on op. Fallthrough intentional */
2906 /* These ops require an operational change to flip their arguments TODO */
2907 case midgard_alu_op_flt
:
2908 case midgard_alu_op_fle
:
2909 case midgard_alu_op_ilt
:
2910 case midgard_alu_op_ile
:
2911 case midgard_alu_op_fcsel
:
2912 case midgard_alu_op_icsel
:
2913 case midgard_alu_op_isub
:
2914 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2917 /* These ops are commutative and Just Flip */
2918 case midgard_alu_op_fne
:
2919 case midgard_alu_op_fadd
:
2920 case midgard_alu_op_fmul
:
2921 case midgard_alu_op_fmin
:
2922 case midgard_alu_op_fmax
:
2923 case midgard_alu_op_iadd
:
2924 case midgard_alu_op_imul
:
2925 case midgard_alu_op_feq
:
2926 case midgard_alu_op_ieq
:
2927 case midgard_alu_op_ine
:
2928 case midgard_alu_op_iand
:
2929 case midgard_alu_op_ior
:
2930 case midgard_alu_op_ixor
:
2931 /* Flip the SSA numbers */
2932 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2933 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2935 /* And flip the modifiers */
2939 src_temp
= ins
->alu
.src2
;
2940 ins
->alu
.src2
= ins
->alu
.src1
;
2941 ins
->alu
.src1
= src_temp
;
2948 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2949 /* Extract the source information */
2951 midgard_vector_alu_src
*src
;
2952 int q
= ins
->alu
.src2
;
2953 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2956 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2957 int component
= src
->swizzle
& 3;
2959 /* Scale constant appropriately, if we can legally */
2960 uint16_t scaled_constant
= 0;
2962 /* XXX: Check legality */
2963 if (midgard_is_integer_op(op
)) {
2964 /* TODO: Inline integer */
2967 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2968 scaled_constant
= (uint16_t) iconstants
[component
];
2970 /* Constant overflow after resize */
2971 if (scaled_constant
!= iconstants
[component
])
2974 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2977 /* We don't know how to handle these with a constant */
2979 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2980 DBG("Bailing inline constant...\n");
2984 /* Make sure that the constant is not itself a
2985 * vector by checking if all accessed values
2986 * (by the swizzle) are the same. */
2988 uint32_t *cons
= (uint32_t *) ins
->constants
;
2989 uint32_t value
= cons
[component
];
2991 bool is_vector
= false;
2992 unsigned mask
= effective_writemask(&ins
->alu
);
2994 for (int c
= 1; c
< 4; ++c
) {
2995 /* We only care if this component is actually used */
2996 if (!(mask
& (1 << c
)))
2999 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3001 if (test
!= value
) {
3010 /* Get rid of the embedded constant */
3011 ins
->has_constants
= false;
3012 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3013 ins
->ssa_args
.inline_constant
= true;
3014 ins
->inline_constant
= scaled_constant
;
3019 /* Map normal SSA sources to other SSA sources / fixed registers (like
3023 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3025 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3028 /* Remove entry in leftovers to avoid a redunant fmov */
3030 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3033 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3035 /* Assign the alias map */
3041 #define AS_SRC(to, u) \
3042 int q##to = ins->alu.src2; \
3043 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
3045 /* Removing unused moves is necessary to clean up the texture pipeline results.
3047 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
3050 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
3052 mir_foreach_instr_in_block_safe(block
, ins
) {
3053 if (ins
->type
!= TAG_ALU_4
) continue;
3055 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
3057 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3059 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3061 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3063 mir_remove_instruction(ins
);
3067 /* The following passes reorder MIR instructions to enable better scheduling */
3070 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3072 mir_foreach_instr_in_block_safe(block
, ins
) {
3073 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3075 /* We've found a load/store op. Check if next is also load/store. */
3076 midgard_instruction
*next_op
= mir_next_op(ins
);
3077 if (&next_op
->link
!= &block
->instructions
) {
3078 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3079 /* If so, we're done since we're a pair */
3080 ins
= mir_next_op(ins
);
3084 /* Maximum search distance to pair, to avoid register pressure disasters */
3085 int search_distance
= 8;
3087 /* Otherwise, we have an orphaned load/store -- search for another load */
3088 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3089 /* Terminate search if necessary */
3090 if (!(search_distance
--)) break;
3092 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3094 /* Stores cannot be reordered, since they have
3095 * dependencies. For the same reason, indirect
3096 * loads cannot be reordered as their index is
3097 * loaded in r27.w */
3099 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3101 /* It appears the 0x800 bit is set whenever a
3102 * load is direct, unset when it is indirect.
3103 * Skip indirect loads. */
3105 if (!(c
->load_store
.unknown
& 0x800)) continue;
3107 /* We found one! Move it up to pair and remove it from the old location */
3109 mir_insert_instruction_before(ins
, *c
);
3110 mir_remove_instruction(c
);
3118 /* Emit varying stores late */
3121 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3122 /* Iterate in reverse to get the final write, rather than the first */
3124 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3125 /* Check if what we just wrote needs a store */
3126 int idx
= ins
->ssa_args
.dest
;
3127 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3129 if (!varying
) continue;
3133 /* We need to store to the appropriate varying, so emit the
3136 /* TODO: Integrate with special purpose RA (and scheduler?) */
3137 bool high_varying_register
= false;
3139 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3141 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3142 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3144 mir_insert_instruction_before(mir_next_op(ins
), st
);
3145 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3147 /* We no longer need to store this varying */
3148 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3152 /* If there are leftovers after the below pass, emit actual fmov
3153 * instructions for the slow-but-correct path */
3156 emit_leftover_move(compiler_context
*ctx
)
3158 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3159 int base
= ((uintptr_t) leftover
->key
) - 1;
3162 map_ssa_to_alias(ctx
, &mapped
);
3163 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3168 actualise_ssa_to_alias(compiler_context
*ctx
)
3170 mir_foreach_instr(ctx
, ins
) {
3171 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3172 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3175 emit_leftover_move(ctx
);
3179 emit_fragment_epilogue(compiler_context
*ctx
)
3181 /* Special case: writing out constants requires us to include the move
3182 * explicitly now, so shove it into r0 */
3184 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3186 if (constant_value
) {
3187 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3188 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3189 emit_mir_instruction(ctx
, ins
);
3192 /* Perform the actual fragment writeout. We have two writeout/branch
3193 * instructions, forming a loop until writeout is successful as per the
3194 * docs. TODO: gl_FragDepth */
3196 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3197 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3200 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3201 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3202 * with the int8 analogue to the fragment epilogue */
3205 emit_blend_epilogue(compiler_context
*ctx
)
3207 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3209 midgard_instruction scale
= {
3212 .inline_constant
= _mesa_float_to_half(255.0),
3214 .src0
= SSA_FIXED_REGISTER(0),
3215 .src1
= SSA_UNUSED_0
,
3216 .dest
= SSA_FIXED_REGISTER(24),
3217 .inline_constant
= true
3220 .op
= midgard_alu_op_fmul
,
3221 .reg_mode
= midgard_reg_mode_full
,
3222 .dest_override
= midgard_dest_override_lower
,
3224 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3225 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3229 emit_mir_instruction(ctx
, scale
);
3231 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3233 midgard_vector_alu_src alu_src
= blank_alu_src
;
3234 alu_src
.half
= true;
3236 midgard_instruction f2u8
= {
3239 .src0
= SSA_FIXED_REGISTER(24),
3240 .src1
= SSA_UNUSED_0
,
3241 .dest
= SSA_FIXED_REGISTER(0),
3242 .inline_constant
= true
3245 .op
= midgard_alu_op_f2u8
,
3246 .reg_mode
= midgard_reg_mode_half
,
3247 .dest_override
= midgard_dest_override_lower
,
3248 .outmod
= midgard_outmod_pos
,
3250 .src1
= vector_alu_srco_unsigned(alu_src
),
3251 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3255 emit_mir_instruction(ctx
, f2u8
);
3257 /* vmul.imov.quarter r0, r0, r0 */
3259 midgard_instruction imov_8
= {
3262 .src0
= SSA_UNUSED_1
,
3263 .src1
= SSA_FIXED_REGISTER(0),
3264 .dest
= SSA_FIXED_REGISTER(0),
3267 .op
= midgard_alu_op_imov
,
3268 .reg_mode
= midgard_reg_mode_quarter
,
3269 .dest_override
= midgard_dest_override_none
,
3271 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3272 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3276 /* Emit branch epilogue with the 8-bit move as the source */
3278 emit_mir_instruction(ctx
, imov_8
);
3279 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3281 emit_mir_instruction(ctx
, imov_8
);
3282 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3285 static midgard_block
*
3286 emit_block(compiler_context
*ctx
, nir_block
*block
)
3288 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3289 list_addtail(&this_block
->link
, &ctx
->blocks
);
3291 this_block
->is_scheduled
= false;
3294 ctx
->texture_index
[0] = -1;
3295 ctx
->texture_index
[1] = -1;
3297 /* Add us as a successor to the block we are following */
3298 if (ctx
->current_block
)
3299 midgard_block_add_successor(ctx
->current_block
, this_block
);
3301 /* Set up current block */
3302 list_inithead(&this_block
->instructions
);
3303 ctx
->current_block
= this_block
;
3305 nir_foreach_instr(instr
, block
) {
3306 emit_instr(ctx
, instr
);
3307 ++ctx
->instruction_count
;
3310 inline_alu_constants(ctx
);
3311 embedded_to_inline_constant(ctx
);
3313 /* Perform heavylifting for aliasing */
3314 actualise_ssa_to_alias(ctx
);
3316 midgard_emit_store(ctx
, this_block
);
3317 midgard_eliminate_orphan_moves(ctx
, this_block
);
3318 midgard_pair_load_store(ctx
, this_block
);
3320 /* Append fragment shader epilogue (value writeout) */
3321 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3322 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3324 emit_blend_epilogue(ctx
);
3326 emit_fragment_epilogue(ctx
);
3330 if (block
== nir_start_block(ctx
->func
->impl
))
3331 ctx
->initial_block
= this_block
;
3333 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3334 ctx
->final_block
= this_block
;
3336 /* Allow the next control flow to access us retroactively, for
3338 ctx
->current_block
= this_block
;
3340 /* Document the fallthrough chain */
3341 ctx
->previous_source_block
= this_block
;
3346 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3349 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3351 /* Conditional branches expect the condition in r31.w; emit a move for
3352 * that in the _previous_ block (which is the current block). */
3353 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3355 /* Speculatively emit the branch, but we can't fill it in until later */
3356 EMIT(branch
, true, true);
3357 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3359 /* Emit the two subblocks */
3360 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3362 /* Emit a jump from the end of the then block to the end of the else */
3363 EMIT(branch
, false, false);
3364 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3366 /* Emit second block, and check if it's empty */
3368 int else_idx
= ctx
->block_count
;
3369 int count_in
= ctx
->instruction_count
;
3370 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3371 int after_else_idx
= ctx
->block_count
;
3373 /* Now that we have the subblocks emitted, fix up the branches */
3378 if (ctx
->instruction_count
== count_in
) {
3379 /* The else block is empty, so don't emit an exit jump */
3380 mir_remove_instruction(then_exit
);
3381 then_branch
->branch
.target_block
= after_else_idx
;
3383 then_branch
->branch
.target_block
= else_idx
;
3384 then_exit
->branch
.target_block
= after_else_idx
;
3389 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3391 /* Remember where we are */
3392 midgard_block
*start_block
= ctx
->current_block
;
3394 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3395 * single current_loop variable, maybe we need a stack */
3397 int loop_idx
= ++ctx
->current_loop
;
3399 /* Get index from before the body so we can loop back later */
3400 int start_idx
= ctx
->block_count
;
3402 /* Emit the body itself */
3403 emit_cf_list(ctx
, &nloop
->body
);
3405 /* Branch back to loop back */
3406 struct midgard_instruction br_back
= v_branch(false, false);
3407 br_back
.branch
.target_block
= start_idx
;
3408 emit_mir_instruction(ctx
, br_back
);
3410 /* Mark down that branch in the graph */
3411 midgard_block_add_successor(ctx
->current_block
, start_block
);
3413 /* Find the index of the block about to follow us (note: we don't add
3414 * one; blocks are 0-indexed so we get a fencepost problem) */
3415 int break_block_idx
= ctx
->block_count
;
3417 /* Fix up the break statements we emitted to point to the right place,
3418 * now that we can allocate a block number for them */
3420 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3421 mir_foreach_instr_in_block(block
, ins
) {
3422 if (ins
->type
!= TAG_ALU_4
) continue;
3423 if (!ins
->compact_branch
) continue;
3424 if (ins
->prepacked_branch
) continue;
3426 /* We found a branch -- check the type to see if we need to do anything */
3427 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3429 /* It's a break! Check if it's our break */
3430 if (ins
->branch
.target_break
!= loop_idx
) continue;
3432 /* Okay, cool, we're breaking out of this loop.
3433 * Rewrite from a break to a goto */
3435 ins
->branch
.target_type
= TARGET_GOTO
;
3436 ins
->branch
.target_block
= break_block_idx
;
3441 static midgard_block
*
3442 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3444 midgard_block
*start_block
= NULL
;
3446 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3447 switch (node
->type
) {
3448 case nir_cf_node_block
: {
3449 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3452 start_block
= block
;
3457 case nir_cf_node_if
:
3458 emit_if(ctx
, nir_cf_node_as_if(node
));
3461 case nir_cf_node_loop
:
3462 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3465 case nir_cf_node_function
:
3474 /* Due to lookahead, we need to report the first tag executed in the command
3475 * stream and in branch targets. An initial block might be empty, so iterate
3476 * until we find one that 'works' */
3479 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3481 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3483 unsigned first_tag
= 0;
3486 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3488 if (initial_bundle
) {
3489 first_tag
= initial_bundle
->tag
;
3493 /* Initial block is empty, try the next block */
3494 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3495 } while(initial_block
!= NULL
);
3502 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3504 struct util_dynarray
*compiled
= &program
->compiled
;
3506 midgard_debug
= debug_get_option_midgard_debug();
3508 compiler_context ictx
= {
3510 .stage
= nir
->info
.stage
,
3512 .is_blend
= is_blend
,
3513 .blend_constant_offset
= -1,
3515 .alpha_ref
= program
->alpha_ref
3518 compiler_context
*ctx
= &ictx
;
3520 /* TODO: Decide this at runtime */
3521 ctx
->uniform_cutoff
= 8;
3523 /* Assign var locations early, so the epilogue can use them if necessary */
3525 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3526 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3527 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3529 /* Initialize at a global (not block) level hash tables */
3531 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3532 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3533 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3534 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3535 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3536 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3537 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3539 /* Record the varying mapping for the command stream's bookkeeping */
3541 struct exec_list
*varyings
=
3542 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3544 nir_foreach_variable(var
, varyings
) {
3545 unsigned loc
= var
->data
.driver_location
;
3546 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3548 for (int c
= 0; c
< sz
; ++c
) {
3549 program
->varyings
[loc
+ c
] = var
->data
.location
;
3553 /* Lower gl_Position pre-optimisation */
3555 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3556 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3558 NIR_PASS_V(nir
, nir_lower_var_copies
);
3559 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3560 NIR_PASS_V(nir
, nir_split_var_copies
);
3561 NIR_PASS_V(nir
, nir_lower_var_copies
);
3562 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3563 NIR_PASS_V(nir
, nir_lower_var_copies
);
3564 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3566 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3568 /* Optimisation passes */
3572 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3573 nir_print_shader(nir
, stdout
);
3576 /* Assign sysvals and counts, now that we're sure
3577 * (post-optimisation) */
3579 midgard_nir_assign_sysvals(ctx
, nir
);
3581 program
->uniform_count
= nir
->num_uniforms
;
3582 program
->sysval_count
= ctx
->sysval_count
;
3583 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3585 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3586 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3588 nir_foreach_function(func
, nir
) {
3592 list_inithead(&ctx
->blocks
);
3593 ctx
->block_count
= 0;
3596 emit_cf_list(ctx
, &func
->impl
->body
);
3597 emit_block(ctx
, func
->impl
->end_block
);
3599 break; /* TODO: Multi-function shaders */
3602 util_dynarray_init(compiled
, NULL
);
3605 schedule_program(ctx
);
3607 /* Now that all the bundles are scheduled and we can calculate block
3608 * sizes, emit actual branch instructions rather than placeholders */
3610 int br_block_idx
= 0;
3612 mir_foreach_block(ctx
, block
) {
3613 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3614 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3615 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3617 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3619 if (ins
->prepacked_branch
) continue;
3621 /* Parse some basic branch info */
3622 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3623 bool is_conditional
= ins
->branch
.conditional
;
3624 bool is_inverted
= ins
->branch
.invert_conditional
;
3625 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3627 /* Determine the block we're jumping to */
3628 int target_number
= ins
->branch
.target_block
;
3630 /* Report the destination tag. Discards don't need this */
3631 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3633 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3634 int quadword_offset
= 0;
3637 /* Jump to the end of the shader. We
3638 * need to include not only the
3639 * following blocks, but also the
3640 * contents of our current block (since
3641 * discard can come in the middle of
3644 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3646 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3647 quadword_offset
+= quadword_size(bun
->tag
);
3650 mir_foreach_block_from(ctx
, blk
, b
) {
3651 quadword_offset
+= b
->quadword_count
;
3654 } else if (target_number
> br_block_idx
) {
3657 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3658 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3661 quadword_offset
+= blk
->quadword_count
;
3664 /* Jump backwards */
3666 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3667 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3670 quadword_offset
-= blk
->quadword_count
;
3674 /* Unconditional extended branches (far jumps)
3675 * have issues, so we always use a conditional
3676 * branch, setting the condition to always for
3677 * unconditional. For compact unconditional
3678 * branches, cond isn't used so it doesn't
3679 * matter what we pick. */
3681 midgard_condition cond
=
3682 !is_conditional
? midgard_condition_always
:
3683 is_inverted
? midgard_condition_false
:
3684 midgard_condition_true
;
3686 midgard_jmp_writeout_op op
=
3687 is_discard
? midgard_jmp_writeout_op_discard
:
3688 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3689 midgard_jmp_writeout_op_branch_cond
;
3692 midgard_branch_extended branch
=
3693 midgard_create_branch_extended(
3698 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3699 } else if (is_conditional
|| is_discard
) {
3700 midgard_branch_cond branch
= {
3702 .dest_tag
= dest_tag
,
3703 .offset
= quadword_offset
,
3707 assert(branch
.offset
== quadword_offset
);
3709 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3711 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3713 midgard_branch_uncond branch
= {
3715 .dest_tag
= dest_tag
,
3716 .offset
= quadword_offset
,
3720 assert(branch
.offset
== quadword_offset
);
3722 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3730 /* Emit flat binary from the instruction arrays. Iterate each block in
3731 * sequence. Save instruction boundaries such that lookahead tags can
3732 * be assigned easily */
3734 /* Cache _all_ bundles in source order for lookahead across failed branches */
3736 int bundle_count
= 0;
3737 mir_foreach_block(ctx
, block
) {
3738 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3740 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3742 mir_foreach_block(ctx
, block
) {
3743 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3744 source_order_bundles
[bundle_idx
++] = bundle
;
3748 int current_bundle
= 0;
3750 mir_foreach_block(ctx
, block
) {
3751 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3754 if (current_bundle
+ 1 < bundle_count
) {
3755 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3757 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3764 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3768 /* TODO: Free deeper */
3769 //util_dynarray_fini(&block->instructions);
3772 free(source_order_bundles
);
3774 /* Report the very first tag executed */
3775 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3777 /* Deal with off-by-one related to the fencepost problem */
3778 program
->work_register_count
= ctx
->work_registers
+ 1;
3780 program
->can_discard
= ctx
->can_discard
;
3781 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3783 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3785 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3786 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);