2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
51 #include "disassemble.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
61 int midgard_debug
= 0;
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
69 midgard_is_branch_unit(unsigned unit
)
71 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
75 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
77 block
->successors
[block
->nr_successors
++] = successor
;
78 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
97 .op = midgard_op_##name, \
99 .swizzle = SWIZZLE_XYZW, \
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
110 const midgard_vector_alu_src blank_alu_src
= {
111 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
114 const midgard_vector_alu_src blank_alu_src_xxxx
= {
115 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
118 const midgard_scalar_alu_src blank_scalar_alu_src
= {
122 /* Used for encoding the unused source of 1-op instructions */
123 const midgard_vector_alu_src zero_alu_src
= { 0 };
125 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
126 * the corresponding Midgard source */
128 static midgard_vector_alu_src
129 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
131 if (!src
) return blank_alu_src
;
133 midgard_vector_alu_src alu_src
= {
136 .half
= 0, /* TODO */
137 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
141 /* TODO: sign-extend/zero-extend */
142 alu_src
.mod
= midgard_int_normal
;
144 /* These should have been lowered away */
145 assert(!(src
->abs
|| src
->negate
));
147 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
153 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
155 static midgard_instruction
156 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
158 midgard_instruction ins
= {
161 .src0
= SSA_UNUSED_1
,
166 .op
= midgard_alu_op_fmov
,
167 .reg_mode
= midgard_reg_mode_32
,
168 .dest_override
= midgard_dest_override_none
,
170 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
171 .src2
= vector_alu_srco_unsigned(mod
)
178 /* load/store instructions have both 32-bit and 16-bit variants, depending on
179 * whether we are using vectors composed of highp or mediump. At the moment, we
180 * don't support half-floats -- this requires changes in other parts of the
181 * compiler -- therefore the 16-bit versions are commented out. */
183 //M_LOAD(ld_attr_16);
185 //M_LOAD(ld_vary_16);
187 //M_LOAD(ld_uniform_16);
188 M_LOAD(ld_uniform_32
);
189 M_LOAD(ld_color_buffer_8
);
190 //M_STORE(st_vary_16);
192 M_STORE(st_cubemap_coords
);
194 static midgard_instruction
195 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
197 midgard_branch_cond branch
= {
205 memcpy(&compact
, &branch
, sizeof(branch
));
207 midgard_instruction ins
= {
209 .unit
= ALU_ENAB_BR_COMPACT
,
210 .prepacked_branch
= true,
211 .compact_branch
= true,
212 .br_compact
= compact
215 if (op
== midgard_jmp_writeout_op_writeout
)
221 static midgard_instruction
222 v_branch(bool conditional
, bool invert
)
224 midgard_instruction ins
= {
226 .unit
= ALU_ENAB_BRANCH
,
227 .compact_branch
= true,
229 .conditional
= conditional
,
230 .invert_conditional
= invert
237 static midgard_branch_extended
238 midgard_create_branch_extended( midgard_condition cond
,
239 midgard_jmp_writeout_op op
,
241 signed quadword_offset
)
243 /* For unclear reasons, the condition code is repeated 8 times */
244 uint16_t duplicated_cond
=
254 midgard_branch_extended branch
= {
256 .dest_tag
= dest_tag
,
257 .offset
= quadword_offset
,
258 .cond
= duplicated_cond
265 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
267 ins
->has_constants
= true;
268 memcpy(&ins
->constants
, constants
, 16);
272 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
274 return glsl_count_attribute_slots(type
, false);
277 /* Lower fdot2 to a vector multiplication followed by channel addition */
279 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
281 if (alu
->op
!= nir_op_fdot2
)
284 b
->cursor
= nir_before_instr(&alu
->instr
);
286 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
287 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
289 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
291 nir_ssa_def
*sum
= nir_fadd(b
,
292 nir_channel(b
, product
, 0),
293 nir_channel(b
, product
, 1));
295 /* Replace the fdot2 with this sum */
296 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
300 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
302 switch (instr
->intrinsic
) {
303 case nir_intrinsic_load_viewport_scale
:
304 return PAN_SYSVAL_VIEWPORT_SCALE
;
305 case nir_intrinsic_load_viewport_offset
:
306 return PAN_SYSVAL_VIEWPORT_OFFSET
;
313 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
317 if (instr
->type
== nir_instr_type_intrinsic
) {
318 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
319 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
325 /* We have a sysval load; check if it's already been assigned */
327 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
330 /* It hasn't -- so assign it now! */
332 unsigned id
= ctx
->sysval_count
++;
333 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
334 ctx
->sysvals
[id
] = sysval
;
338 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
340 ctx
->sysval_count
= 0;
342 nir_foreach_function(function
, shader
) {
343 if (!function
->impl
) continue;
345 nir_foreach_block(block
, function
->impl
) {
346 nir_foreach_instr_safe(instr
, block
) {
347 midgard_nir_assign_sysval_body(ctx
, instr
);
354 midgard_nir_lower_fdot2(nir_shader
*shader
)
356 bool progress
= false;
358 nir_foreach_function(function
, shader
) {
359 if (!function
->impl
) continue;
362 nir_builder
*b
= &_b
;
363 nir_builder_init(b
, function
->impl
);
365 nir_foreach_block(block
, function
->impl
) {
366 nir_foreach_instr_safe(instr
, block
) {
367 if (instr
->type
!= nir_instr_type_alu
) continue;
369 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
370 midgard_nir_lower_fdot2_body(b
, alu
);
376 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
384 optimise_nir(nir_shader
*nir
)
387 unsigned lower_flrp
=
388 (nir
->options
->lower_flrp16
? 16 : 0) |
389 (nir
->options
->lower_flrp32
? 32 : 0) |
390 (nir
->options
->lower_flrp64
? 64 : 0);
392 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
393 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
395 nir_lower_tex_options lower_tex_options
= {
399 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
404 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
405 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
407 NIR_PASS(progress
, nir
, nir_copy_prop
);
408 NIR_PASS(progress
, nir
, nir_opt_dce
);
409 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
410 NIR_PASS(progress
, nir
, nir_opt_cse
);
411 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
412 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
413 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
415 if (lower_flrp
!= 0) {
416 bool lower_flrp_progress
= false;
417 NIR_PASS(lower_flrp_progress
,
421 false /* always_precise */,
422 nir
->options
->lower_ffma
);
423 if (lower_flrp_progress
) {
424 NIR_PASS(progress
, nir
,
425 nir_opt_constant_folding
);
429 /* Nothing should rematerialize any flrps, so we only
430 * need to do this lowering once.
435 NIR_PASS(progress
, nir
, nir_opt_undef
);
436 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
439 nir_var_function_temp
);
441 /* TODO: Enable vectorize when merged upstream */
442 // NIR_PASS(progress, nir, nir_opt_vectorize);
445 /* Must be run at the end to prevent creation of fsin/fcos ops */
446 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
451 NIR_PASS(progress
, nir
, nir_opt_dce
);
452 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
453 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
454 NIR_PASS(progress
, nir
, nir_copy_prop
);
457 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
459 /* We implement booleans as 32-bit 0/~0 */
460 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
462 /* Now that booleans are lowered, we can run out late opts */
463 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
465 /* Lower mods for float ops only. Integer ops don't support modifiers
466 * (saturate doesn't make sense on integers, neg/abs require dedicated
469 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
470 NIR_PASS(progress
, nir
, nir_copy_prop
);
471 NIR_PASS(progress
, nir
, nir_opt_dce
);
473 /* Take us out of SSA */
474 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
475 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
477 /* We are a vector architecture; write combine where possible */
478 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
479 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
481 NIR_PASS(progress
, nir
, nir_opt_dce
);
484 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
485 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
486 * r0. See the comments in compiler_context */
489 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
491 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
492 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
495 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
498 unalias_ssa(compiler_context
*ctx
, int dest
)
500 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
501 /* TODO: Remove from leftover or no? */
504 /* Do not actually emit a load; instead, cache the constant for inlining */
507 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
509 nir_ssa_def def
= instr
->def
;
511 float *v
= rzalloc_array(NULL
, float, 4);
512 nir_const_load_to_arr(v
, instr
, f32
);
513 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
517 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
520 return src
->ssa
->index
;
522 assert(!src
->reg
.indirect
);
523 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
528 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
531 return dst
->ssa
.index
;
533 assert(!dst
->reg
.indirect
);
534 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
539 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
541 return nir_src_index(ctx
, &src
->src
);
545 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
547 unsigned comp
= src
->swizzle
[0];
549 for (unsigned c
= 1; c
< nr_components
; ++c
) {
550 if (src
->swizzle
[c
] != comp
)
557 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
558 * output of a conditional test) into that register */
561 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
563 int condition
= nir_src_index(ctx
, src
);
565 /* Source to swizzle the desired component into w */
567 const midgard_vector_alu_src alu_src
= {
568 .swizzle
= SWIZZLE(component
, component
, component
, component
),
571 /* There is no boolean move instruction. Instead, we simulate a move by
572 * ANDing the condition with itself to get it into r31.w */
574 midgard_instruction ins
= {
577 /* We need to set the conditional as close as possible */
578 .precede_break
= true,
579 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
585 .dest
= SSA_FIXED_REGISTER(31),
588 .op
= midgard_alu_op_iand
,
589 .outmod
= midgard_outmod_int
,
590 .reg_mode
= midgard_reg_mode_32
,
591 .dest_override
= midgard_dest_override_none
,
592 .mask
= (0x3 << 6), /* w */
593 .src1
= vector_alu_srco_unsigned(alu_src
),
594 .src2
= vector_alu_srco_unsigned(alu_src
)
598 emit_mir_instruction(ctx
, ins
);
601 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
605 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
607 int condition
= nir_src_index(ctx
, &src
->src
);
609 /* Source to swizzle the desired component into w */
611 const midgard_vector_alu_src alu_src
= {
612 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
615 /* There is no boolean move instruction. Instead, we simulate a move by
616 * ANDing the condition with itself to get it into r31.w */
618 midgard_instruction ins
= {
620 .precede_break
= true,
624 .dest
= SSA_FIXED_REGISTER(31),
627 .op
= midgard_alu_op_iand
,
628 .outmod
= midgard_outmod_int
,
629 .reg_mode
= midgard_reg_mode_32
,
630 .dest_override
= midgard_dest_override_none
,
631 .mask
= expand_writemask((1 << nr_comp
) - 1),
632 .src1
= vector_alu_srco_unsigned(alu_src
),
633 .src2
= vector_alu_srco_unsigned(alu_src
)
637 emit_mir_instruction(ctx
, ins
);
642 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
643 * pinning to eliminate this move in all known cases */
646 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
648 int offset
= nir_src_index(ctx
, src
);
650 midgard_instruction ins
= {
653 .src0
= SSA_UNUSED_1
,
655 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
658 .op
= midgard_alu_op_imov
,
659 .outmod
= midgard_outmod_int
,
660 .reg_mode
= midgard_reg_mode_32
,
661 .dest_override
= midgard_dest_override_none
,
662 .mask
= (0x3 << 6), /* w */
663 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
664 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
668 emit_mir_instruction(ctx
, ins
);
671 #define ALU_CASE(nir, _op) \
673 op = midgard_alu_op_##_op; \
676 nir_is_fzero_constant(nir_src src
)
678 if (!nir_src_is_const(src
))
681 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
682 if (nir_src_comp_as_float(src
, c
) != 0.0)
690 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
692 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
694 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
695 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
696 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
698 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
699 * supported. A few do not and are commented for now. Also, there are a
700 * number of NIR ops which Midgard does not support and need to be
701 * lowered, also TODO. This switch block emits the opcode and calling
702 * convention of the Midgard instruction; actual packing is done in
708 ALU_CASE(fadd
, fadd
);
709 ALU_CASE(fmul
, fmul
);
710 ALU_CASE(fmin
, fmin
);
711 ALU_CASE(fmax
, fmax
);
712 ALU_CASE(imin
, imin
);
713 ALU_CASE(imax
, imax
);
714 ALU_CASE(umin
, umin
);
715 ALU_CASE(umax
, umax
);
716 ALU_CASE(ffloor
, ffloor
);
717 ALU_CASE(fround_even
, froundeven
);
718 ALU_CASE(ftrunc
, ftrunc
);
719 ALU_CASE(fceil
, fceil
);
720 ALU_CASE(fdot3
, fdot3
);
721 ALU_CASE(fdot4
, fdot4
);
722 ALU_CASE(iadd
, iadd
);
723 ALU_CASE(isub
, isub
);
724 ALU_CASE(imul
, imul
);
725 ALU_CASE(iabs
, iabs
);
728 ALU_CASE(feq32
, feq
);
729 ALU_CASE(fne32
, fne
);
730 ALU_CASE(flt32
, flt
);
731 ALU_CASE(ieq32
, ieq
);
732 ALU_CASE(ine32
, ine
);
733 ALU_CASE(ilt32
, ilt
);
734 ALU_CASE(ult32
, ult
);
736 /* We don't have a native b2f32 instruction. Instead, like many
737 * GPUs, we exploit booleans as 0/~0 for false/true, and
738 * correspondingly AND
739 * by 1.0 to do the type conversion. For the moment, prime us
742 * iand [whatever], #0
744 * At the end of emit_alu (as MIR), we'll fix-up the constant
747 ALU_CASE(b2f32
, iand
);
748 ALU_CASE(b2i32
, iand
);
750 /* Likewise, we don't have a dedicated f2b32 instruction, but
751 * we can do a "not equal to 0.0" test. */
753 ALU_CASE(f2b32
, fne
);
754 ALU_CASE(i2b32
, ine
);
756 ALU_CASE(frcp
, frcp
);
757 ALU_CASE(frsq
, frsqrt
);
758 ALU_CASE(fsqrt
, fsqrt
);
759 ALU_CASE(fexp2
, fexp2
);
760 ALU_CASE(flog2
, flog2
);
762 ALU_CASE(f2i32
, f2i
);
763 ALU_CASE(f2u32
, f2u
);
764 ALU_CASE(i2f32
, i2f
);
765 ALU_CASE(u2f32
, u2f
);
767 ALU_CASE(fsin
, fsin
);
768 ALU_CASE(fcos
, fcos
);
770 ALU_CASE(iand
, iand
);
772 ALU_CASE(ixor
, ixor
);
773 ALU_CASE(inot
, inand
);
774 ALU_CASE(ishl
, ishl
);
775 ALU_CASE(ishr
, iasr
);
776 ALU_CASE(ushr
, ilsr
);
778 ALU_CASE(b32all_fequal2
, fball_eq
);
779 ALU_CASE(b32all_fequal3
, fball_eq
);
780 ALU_CASE(b32all_fequal4
, fball_eq
);
782 ALU_CASE(b32any_fnequal2
, fbany_neq
);
783 ALU_CASE(b32any_fnequal3
, fbany_neq
);
784 ALU_CASE(b32any_fnequal4
, fbany_neq
);
786 ALU_CASE(b32all_iequal2
, iball_eq
);
787 ALU_CASE(b32all_iequal3
, iball_eq
);
788 ALU_CASE(b32all_iequal4
, iball_eq
);
790 ALU_CASE(b32any_inequal2
, ibany_neq
);
791 ALU_CASE(b32any_inequal3
, ibany_neq
);
792 ALU_CASE(b32any_inequal4
, ibany_neq
);
794 /* Source mods will be shoved in later */
795 ALU_CASE(fabs
, fmov
);
796 ALU_CASE(fneg
, fmov
);
797 ALU_CASE(fsat
, fmov
);
799 /* For greater-or-equal, we lower to less-or-equal and flip the
807 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
808 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
809 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
810 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
813 /* Swap via temporary */
814 nir_alu_src temp
= instr
->src
[1];
815 instr
->src
[1] = instr
->src
[0];
816 instr
->src
[0] = temp
;
821 case nir_op_b32csel
: {
822 /* Midgard features both fcsel and icsel, depending on
823 * the type of the arguments/output. However, as long
824 * as we're careful we can _always_ use icsel and
825 * _never_ need fcsel, since the latter does additional
826 * floating-point-specific processing whereas the
827 * former just moves bits on the wire. It's not obvious
828 * why these are separate opcodes, save for the ability
829 * to do things like sat/pos/abs/neg for free */
831 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
832 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
834 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
837 /* Emit the condition into r31 */
840 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
842 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
844 /* The condition is the first argument; move the other
845 * arguments up one to be a binary instruction for
848 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
853 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
858 /* Midgard can perform certain modifiers on output of an ALU op */
859 midgard_outmod outmod
=
860 midgard_is_integer_out_op(op
) ? midgard_outmod_int
:
861 instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
863 if (instr
->op
== nir_op_fsat
)
864 outmod
= midgard_outmod_sat
;
866 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
868 if (instr
->op
== nir_op_fmax
) {
869 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
870 op
= midgard_alu_op_fmov
;
872 outmod
= midgard_outmod_pos
;
873 instr
->src
[0] = instr
->src
[1];
874 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
875 op
= midgard_alu_op_fmov
;
877 outmod
= midgard_outmod_pos
;
881 /* Fetch unit, quirks, etc information */
882 unsigned opcode_props
= alu_opcode_props
[op
].props
;
883 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
885 /* src0 will always exist afaik, but src1 will not for 1-argument
886 * instructions. The latter can only be fetched if the instruction
887 * needs it, or else we may segfault. */
889 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
890 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
892 /* Rather than use the instruction generation helpers, we do it
893 * ourselves here to avoid the mess */
895 midgard_instruction ins
= {
898 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
899 .src1
= quirk_flipped_r24
? src0
: src1
,
904 nir_alu_src
*nirmods
[2] = { NULL
};
906 if (nr_inputs
== 2) {
907 nirmods
[0] = &instr
->src
[0];
908 nirmods
[1] = &instr
->src
[1];
909 } else if (nr_inputs
== 1) {
910 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
915 /* These were lowered to a move, so apply the corresponding mod */
917 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
918 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
920 if (instr
->op
== nir_op_fneg
)
921 s
->negate
= !s
->negate
;
923 if (instr
->op
== nir_op_fabs
)
927 bool is_int
= midgard_is_integer_op(op
);
929 midgard_vector_alu alu
= {
931 .reg_mode
= midgard_reg_mode_32
,
932 .dest_override
= midgard_dest_override_none
,
935 /* Writemask only valid for non-SSA NIR */
936 .mask
= expand_writemask((1 << nr_components
) - 1),
938 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
939 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
942 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
945 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
949 /* Late fixup for emulated instructions */
951 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
952 /* Presently, our second argument is an inline #0 constant.
953 * Switch over to an embedded 1.0 constant (that can't fit
954 * inline, since we're 32-bit, not 16-bit like the inline
957 ins
.ssa_args
.inline_constant
= false;
958 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
959 ins
.has_constants
= true;
961 if (instr
->op
== nir_op_b2f32
) {
962 ins
.constants
[0] = 1.0f
;
964 /* Type pun it into place */
966 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
969 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
970 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
971 ins
.ssa_args
.inline_constant
= false;
972 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
973 ins
.has_constants
= true;
974 ins
.constants
[0] = 0.0f
;
975 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
976 } else if (instr
->op
== nir_op_inot
) {
977 /* ~b = ~(b & b), so duplicate the source */
978 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
979 ins
.alu
.src2
= ins
.alu
.src1
;
982 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
983 /* To avoid duplicating the lookup tables (probably), true LUT
984 * instructions can only operate as if they were scalars. Lower
985 * them here by changing the component. */
987 uint8_t original_swizzle
[4];
988 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
990 for (int i
= 0; i
< nr_components
; ++i
) {
991 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
993 for (int j
= 0; j
< 4; ++j
)
994 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
996 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
997 emit_mir_instruction(ctx
, ins
);
1000 emit_mir_instruction(ctx
, ins
);
1007 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1009 /* TODO: half-floats */
1011 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1012 /* Fast path: For the first 16 uniforms, direct accesses are
1013 * 0-cycle, since they're just a register fetch in the usual
1014 * case. So, we alias the registers while we're still in
1017 int reg_slot
= 23 - offset
;
1018 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1020 /* Otherwise, read from the 'special' UBO to access
1021 * higher-indexed uniforms, at a performance cost. More
1022 * generally, we're emitting a UBO read instruction. */
1024 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1026 /* TODO: Don't split */
1027 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1028 ins
.load_store
.address
= offset
>> 3;
1030 if (indirect_offset
) {
1031 emit_indirect_offset(ctx
, indirect_offset
);
1032 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1034 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1037 emit_mir_instruction(ctx
, ins
);
1042 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1044 /* First, pull out the destination */
1045 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1047 /* Now, figure out which uniform this is */
1048 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1049 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1051 /* Sysvals are prefix uniforms */
1052 unsigned uniform
= ((uintptr_t) val
) - 1;
1054 /* Emit the read itself -- this is never indirect */
1055 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1058 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1059 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1060 * generations have faster vectorized reads. This operation is for blend
1061 * shaders in particular; reading the tilebuffer from the fragment shader
1062 * remains an open problem. */
1065 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1067 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1068 ins
.load_store
.swizzle
= 0; /* xxxx */
1070 /* Read each component sequentially */
1072 for (unsigned c
= 0; c
< 4; ++c
) {
1073 ins
.load_store
.mask
= (1 << c
);
1074 ins
.load_store
.unknown
= c
;
1075 emit_mir_instruction(ctx
, ins
);
1078 /* vadd.u2f hr2, zext(hr2), #0 */
1080 midgard_vector_alu_src alu_src
= blank_alu_src
;
1081 alu_src
.mod
= midgard_int_zero_extend
;
1082 alu_src
.half
= true;
1084 midgard_instruction u2f
= {
1088 .src1
= SSA_UNUSED_0
,
1090 .inline_constant
= true
1093 .op
= midgard_alu_op_u2f
,
1094 .reg_mode
= midgard_reg_mode_16
,
1095 .dest_override
= midgard_dest_override_none
,
1097 .src1
= vector_alu_srco_unsigned(alu_src
),
1098 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1102 emit_mir_instruction(ctx
, u2f
);
1104 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1108 midgard_instruction fmul
= {
1110 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1114 .src1
= SSA_UNUSED_0
,
1115 .inline_constant
= true
1118 .op
= midgard_alu_op_fmul
,
1119 .reg_mode
= midgard_reg_mode_32
,
1120 .dest_override
= midgard_dest_override_none
,
1121 .outmod
= midgard_outmod_sat
,
1123 .src1
= vector_alu_srco_unsigned(alu_src
),
1124 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1128 emit_mir_instruction(ctx
, fmul
);
1132 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1134 unsigned offset
, reg
;
1136 switch (instr
->intrinsic
) {
1137 case nir_intrinsic_discard_if
:
1138 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1142 case nir_intrinsic_discard
: {
1143 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1144 struct midgard_instruction discard
= v_branch(conditional
, false);
1145 discard
.branch
.target_type
= TARGET_DISCARD
;
1146 emit_mir_instruction(ctx
, discard
);
1148 ctx
->can_discard
= true;
1152 case nir_intrinsic_load_uniform
:
1153 case nir_intrinsic_load_input
:
1154 offset
= nir_intrinsic_base(instr
);
1156 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1157 bool direct
= nir_src_is_const(instr
->src
[0]);
1160 offset
+= nir_src_as_uint(instr
->src
[0]);
1163 reg
= nir_dest_index(ctx
, &instr
->dest
);
1165 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1166 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1167 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1168 /* XXX: Half-floats? */
1169 /* TODO: swizzle, mask */
1171 midgard_instruction ins
= m_ld_vary_32(reg
, offset
);
1172 ins
.load_store
.mask
= (1 << nr_comp
) - 1;
1174 midgard_varying_parameter p
= {
1176 .interpolation
= midgard_interp_default
,
1177 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1181 memcpy(&u
, &p
, sizeof(p
));
1182 ins
.load_store
.varying_parameters
= u
;
1185 /* We have the offset totally ready */
1186 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1188 /* We have it partially ready, but we need to
1189 * add in the dynamic index, moved to r27.w */
1190 emit_indirect_offset(ctx
, &instr
->src
[0]);
1191 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1194 emit_mir_instruction(ctx
, ins
);
1195 } else if (ctx
->is_blend
) {
1196 /* For blend shaders, load the input color, which is
1197 * preloaded to r0 */
1199 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1200 emit_mir_instruction(ctx
, move
);
1201 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1202 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1203 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1204 ins
.load_store
.mask
= (1 << nr_comp
) - 1;
1205 emit_mir_instruction(ctx
, ins
);
1207 DBG("Unknown load\n");
1213 case nir_intrinsic_load_output
:
1214 assert(nir_src_is_const(instr
->src
[0]));
1215 reg
= nir_dest_index(ctx
, &instr
->dest
);
1217 if (ctx
->is_blend
) {
1219 emit_fb_read_blend_scalar(ctx
, reg
);
1221 DBG("Unknown output load\n");
1227 case nir_intrinsic_load_blend_const_color_rgba
: {
1228 assert(ctx
->is_blend
);
1229 reg
= nir_dest_index(ctx
, &instr
->dest
);
1231 /* Blend constants are embedded directly in the shader and
1232 * patched in, so we use some magic routing */
1234 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1235 ins
.has_constants
= true;
1236 ins
.has_blend_constant
= true;
1237 emit_mir_instruction(ctx
, ins
);
1241 case nir_intrinsic_store_output
:
1242 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1244 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1246 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1248 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1249 /* gl_FragColor is not emitted with load/store
1250 * instructions. Instead, it gets plonked into
1251 * r0 at the end of the shader and we do the
1252 * framebuffer writeout dance. TODO: Defer
1255 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1256 emit_mir_instruction(ctx
, move
);
1258 /* Save the index we're writing to for later reference
1259 * in the epilogue */
1261 ctx
->fragment_output
= reg
;
1262 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1263 /* Varyings are written into one of two special
1264 * varying register, r26 or r27. The register itself is selected as the register
1265 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1267 * Normally emitting fmov's is frowned upon,
1268 * but due to unique constraints of
1269 * REGISTER_VARYING, fmov emission + a
1270 * dedicated cleanup pass is the only way to
1271 * guarantee correctness when considering some
1272 * (common) edge cases XXX: FIXME */
1274 /* If this varying corresponds to a constant (why?!),
1275 * emit that now since it won't get picked up by
1276 * hoisting (since there is no corresponding move
1277 * emitted otherwise) */
1279 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1281 if (constant_value
) {
1282 /* Special case: emit the varying write
1283 * directly to r26 (looks funny in asm but it's
1284 * fine) and emit the store _now_. Possibly
1285 * slightly slower, but this is a really stupid
1286 * special case anyway (why on earth would you
1287 * have a constant varying? Your own fault for
1288 * slightly worse perf :P) */
1290 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1291 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1292 emit_mir_instruction(ctx
, ins
);
1294 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1295 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1296 emit_mir_instruction(ctx
, st
);
1298 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1300 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1303 DBG("Unknown store\n");
1309 case nir_intrinsic_load_alpha_ref_float
:
1310 assert(instr
->dest
.is_ssa
);
1312 float ref_value
= ctx
->alpha_ref
;
1314 float *v
= ralloc_array(NULL
, float, 4);
1315 memcpy(v
, &ref_value
, sizeof(float));
1316 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1319 case nir_intrinsic_load_viewport_scale
:
1320 case nir_intrinsic_load_viewport_offset
:
1321 emit_sysval_read(ctx
, instr
);
1325 printf ("Unhandled intrinsic\n");
1332 midgard_tex_format(enum glsl_sampler_dim dim
)
1335 case GLSL_SAMPLER_DIM_2D
:
1336 case GLSL_SAMPLER_DIM_EXTERNAL
:
1339 case GLSL_SAMPLER_DIM_3D
:
1342 case GLSL_SAMPLER_DIM_CUBE
:
1343 return TEXTURE_CUBE
;
1346 DBG("Unknown sampler dim type\n");
1353 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1356 //assert (!instr->sampler);
1357 //assert (!instr->texture_array_size);
1358 assert (instr
->op
== nir_texop_tex
);
1360 /* Allocate registers via a round robin scheme to alternate between the two registers */
1361 int reg
= ctx
->texture_op_count
& 1;
1362 int in_reg
= reg
, out_reg
= reg
;
1364 /* Make room for the reg */
1366 if (ctx
->texture_index
[reg
] > -1)
1367 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1369 int texture_index
= instr
->texture_index
;
1370 int sampler_index
= texture_index
;
1372 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1373 switch (instr
->src
[i
].src_type
) {
1374 case nir_tex_src_coord
: {
1375 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1377 midgard_vector_alu_src alu_src
= blank_alu_src
;
1379 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1381 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1382 /* For cubemaps, we need to load coords into
1383 * special r27, and then use a special ld/st op
1384 * to copy into the texture register */
1386 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1388 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1389 emit_mir_instruction(ctx
, move
);
1391 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1392 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1393 st
.load_store
.mask
= 0x3; /* xy? */
1394 st
.load_store
.swizzle
= alu_src
.swizzle
;
1395 emit_mir_instruction(ctx
, st
);
1398 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1400 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1401 emit_mir_instruction(ctx
, ins
);
1408 DBG("Unknown source type\n");
1415 /* No helper to build texture words -- we do it all here */
1416 midgard_instruction ins
= {
1417 .type
= TAG_TEXTURE_4
,
1419 .op
= TEXTURE_OP_NORMAL
,
1420 .format
= midgard_tex_format(instr
->sampler_dim
),
1421 .texture_handle
= texture_index
,
1422 .sampler_handle
= sampler_index
,
1424 /* TODO: Don't force xyzw */
1425 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1437 /* Assume we can continue; hint it out later */
1442 /* Set registers to read and write from the same place */
1443 ins
.texture
.in_reg_select
= in_reg
;
1444 ins
.texture
.out_reg_select
= out_reg
;
1446 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1447 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1448 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1449 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1450 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1452 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1453 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1454 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1457 emit_mir_instruction(ctx
, ins
);
1459 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1461 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1462 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1463 ctx
->texture_index
[reg
] = o_index
;
1465 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1466 emit_mir_instruction(ctx
, ins2
);
1468 /* Used for .cont and .last hinting */
1469 ctx
->texture_op_count
++;
1473 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1475 switch (instr
->type
) {
1476 case nir_jump_break
: {
1477 /* Emit a branch out of the loop */
1478 struct midgard_instruction br
= v_branch(false, false);
1479 br
.branch
.target_type
= TARGET_BREAK
;
1480 br
.branch
.target_break
= ctx
->current_loop_depth
;
1481 emit_mir_instruction(ctx
, br
);
1488 DBG("Unknown jump type %d\n", instr
->type
);
1494 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1496 switch (instr
->type
) {
1497 case nir_instr_type_load_const
:
1498 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1501 case nir_instr_type_intrinsic
:
1502 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1505 case nir_instr_type_alu
:
1506 emit_alu(ctx
, nir_instr_as_alu(instr
));
1509 case nir_instr_type_tex
:
1510 emit_tex(ctx
, nir_instr_as_tex(instr
));
1513 case nir_instr_type_jump
:
1514 emit_jump(ctx
, nir_instr_as_jump(instr
));
1517 case nir_instr_type_ssa_undef
:
1522 DBG("Unhandled instruction type\n");
1527 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1528 * use scalar ALU instructions, for functional or performance reasons. To do
1529 * this, we just demote vector ALU payloads to scalar. */
1532 component_from_mask(unsigned mask
)
1534 for (int c
= 0; c
< 4; ++c
) {
1535 if (mask
& (3 << (2 * c
)))
1544 is_single_component_mask(unsigned mask
)
1548 for (int c
= 0; c
< 4; ++c
)
1549 if (mask
& (3 << (2 * c
)))
1552 return components
== 1;
1555 /* Create a mask of accessed components from a swizzle to figure out vector
1559 swizzle_to_access_mask(unsigned swizzle
)
1561 unsigned component_mask
= 0;
1563 for (int i
= 0; i
< 4; ++i
) {
1564 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1565 component_mask
|= (1 << c
);
1568 return component_mask
;
1572 vector_to_scalar_source(unsigned u
, bool is_int
)
1574 midgard_vector_alu_src v
;
1575 memcpy(&v
, &u
, sizeof(v
));
1577 /* TODO: Integers */
1579 midgard_scalar_alu_src s
= {
1581 .component
= (v
.swizzle
& 3) << 1
1587 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
1588 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
1592 memcpy(&o
, &s
, sizeof(s
));
1594 return o
& ((1 << 6) - 1);
1597 static midgard_scalar_alu
1598 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1600 bool is_int
= midgard_is_integer_op(v
.op
);
1602 /* The output component is from the mask */
1603 midgard_scalar_alu s
= {
1605 .src1
= vector_to_scalar_source(v
.src1
, is_int
),
1606 .src2
= vector_to_scalar_source(v
.src2
, is_int
),
1609 .output_full
= 1, /* TODO: Half */
1610 .output_component
= component_from_mask(v
.mask
) << 1,
1613 /* Inline constant is passed along rather than trying to extract it
1616 if (ins
->ssa_args
.inline_constant
) {
1618 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1619 imm
|= (lower_11
>> 9) & 3;
1620 imm
|= (lower_11
>> 6) & 4;
1621 imm
|= (lower_11
>> 2) & 0x38;
1622 imm
|= (lower_11
& 63) << 6;
1630 /* Midgard prefetches instruction types, so during emission we need to
1631 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1632 * if this is the second to last and the last is an ALU, then it's also 1... */
1634 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1635 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1637 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
1638 bytes_emitted += sizeof(type)
1641 emit_binary_vector_instruction(midgard_instruction
*ains
,
1642 uint16_t *register_words
, int *register_words_count
,
1643 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
1644 size_t *bytes_emitted
)
1646 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
1647 *bytes_emitted
+= sizeof(midgard_reg_info
);
1649 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
1650 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
1651 *bytes_emitted
+= sizeof(midgard_vector_alu
);
1654 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
1655 * mind that we are a vector architecture and we can write to different
1656 * components simultaneously */
1659 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
1661 /* Each instruction reads some registers and writes to a register. See
1662 * where the first writes */
1664 /* Figure out where exactly we wrote to */
1665 int source
= first
->ssa_args
.dest
;
1666 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
1668 /* As long as the second doesn't read from the first, we're okay */
1669 if (second
->ssa_args
.src0
== source
) {
1670 if (first
->type
== TAG_ALU_4
) {
1671 /* Figure out which components we just read from */
1673 int q
= second
->alu
.src1
;
1674 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1676 /* Check if there are components in common, and fail if so */
1677 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
1684 if (second
->ssa_args
.src1
== source
)
1687 /* Otherwise, it's safe in that regard. Another data hazard is both
1688 * writing to the same place, of course */
1690 if (second
->ssa_args
.dest
== source
) {
1691 /* ...but only if the components overlap */
1692 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
1694 if (dest_mask
& source_mask
)
1704 midgard_instruction
**segment
, unsigned segment_size
,
1705 midgard_instruction
*ains
)
1707 for (int s
= 0; s
< segment_size
; ++s
)
1708 if (!can_run_concurrent_ssa(segment
[s
], ains
))
1716 /* Schedules, but does not emit, a single basic block. After scheduling, the
1717 * final tag and size of the block are known, which are necessary for branching
1720 static midgard_bundle
1721 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
1723 int instructions_emitted
= 0, instructions_consumed
= -1;
1724 midgard_bundle bundle
= { 0 };
1726 uint8_t tag
= ins
->type
;
1728 /* Default to the instruction's tag */
1731 switch (ins
->type
) {
1733 uint32_t control
= 0;
1734 size_t bytes_emitted
= sizeof(control
);
1736 /* TODO: Constant combining */
1737 int index
= 0, last_unit
= 0;
1739 /* Previous instructions, for the purpose of parallelism */
1740 midgard_instruction
*segment
[4] = {0};
1741 int segment_size
= 0;
1743 instructions_emitted
= -1;
1744 midgard_instruction
*pins
= ins
;
1747 midgard_instruction
*ains
= pins
;
1749 /* Advance instruction pointer */
1751 ains
= mir_next_op(pins
);
1755 /* Out-of-work condition */
1756 if ((struct list_head
*) ains
== &block
->instructions
)
1759 /* Ensure that the chain can continue */
1760 if (ains
->type
!= TAG_ALU_4
) break;
1762 /* If there's already something in the bundle and we
1763 * have weird scheduler constraints, break now */
1764 if (ains
->precede_break
&& index
) break;
1766 /* According to the presentation "The ARM
1767 * Mali-T880 Mobile GPU" from HotChips 27,
1768 * there are two pipeline stages. Branching
1769 * position determined experimentally. Lines
1770 * are executed in parallel:
1773 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
1775 * Verify that there are no ordering dependencies here.
1777 * TODO: Allow for parallelism!!!
1780 /* Pick a unit for it if it doesn't force a particular unit */
1782 int unit
= ains
->unit
;
1785 int op
= ains
->alu
.op
;
1786 int units
= alu_opcode_props
[op
].props
;
1788 /* TODO: Promotion of scalars to vectors */
1789 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
1792 assert(units
& UNITS_SCALAR
);
1795 if (last_unit
>= UNIT_VADD
) {
1796 if (units
& UNIT_VLUT
)
1801 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
1803 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
1805 else if (units
& UNIT_VLUT
)
1811 if (last_unit
>= UNIT_VADD
) {
1812 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
1814 else if (units
& UNIT_VLUT
)
1819 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
1821 else if (units
& UNIT_SMUL
)
1822 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
1823 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
1830 assert(unit
& units
);
1833 /* Late unit check, this time for encoding (not parallelism) */
1834 if (unit
<= last_unit
) break;
1836 /* Clear the segment */
1837 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
1840 if (midgard_has_hazard(segment
, segment_size
, ains
))
1843 /* We're good to go -- emit the instruction */
1846 segment
[segment_size
++] = ains
;
1848 /* Only one set of embedded constants per
1849 * bundle possible; if we have more, we must
1850 * break the chain early, unfortunately */
1852 if (ains
->has_constants
) {
1853 if (bundle
.has_embedded_constants
) {
1854 /* The blend constant needs to be
1855 * alone, since it conflicts with
1856 * everything by definition*/
1858 if (ains
->has_blend_constant
|| bundle
.has_blend_constant
)
1861 /* ...but if there are already
1862 * constants but these are the
1863 * *same* constants, we let it
1866 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
1869 bundle
.has_embedded_constants
= true;
1870 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
1872 /* If this is a blend shader special constant, track it for patching */
1873 bundle
.has_blend_constant
|= ains
->has_blend_constant
;
1877 if (ains
->unit
& UNITS_ANY_VECTOR
) {
1878 emit_binary_vector_instruction(ains
, bundle
.register_words
,
1879 &bundle
.register_words_count
, bundle
.body_words
,
1880 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
1881 } else if (ains
->compact_branch
) {
1882 /* All of r0 has to be written out
1883 * along with the branch writeout.
1886 if (ains
->writeout
) {
1888 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
1889 ins
.unit
= UNIT_VMUL
;
1891 control
|= ins
.unit
;
1893 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
1894 &bundle
.register_words_count
, bundle
.body_words
,
1895 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
1897 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
1898 bool written_late
= false;
1899 bool components
[4] = { 0 };
1900 uint16_t register_dep_mask
= 0;
1901 uint16_t written_mask
= 0;
1903 midgard_instruction
*qins
= ins
;
1904 for (int t
= 0; t
< index
; ++t
) {
1905 if (qins
->registers
.out_reg
!= 0) {
1906 /* Mark down writes */
1908 written_mask
|= (1 << qins
->registers
.out_reg
);
1910 /* Mark down the register dependencies for errata check */
1912 if (qins
->registers
.src1_reg
< 16)
1913 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
1915 if (qins
->registers
.src2_reg
< 16)
1916 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
1918 int mask
= qins
->alu
.mask
;
1920 for (int c
= 0; c
< 4; ++c
)
1921 if (mask
& (0x3 << (2 * c
)))
1922 components
[c
] = true;
1924 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
1926 if (qins
->unit
== UNIT_VLUT
)
1927 written_late
= true;
1930 /* Advance instruction pointer */
1931 qins
= mir_next_op(qins
);
1935 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
1936 if (register_dep_mask
& written_mask
) {
1937 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
1944 /* If even a single component is not written, break it up (conservative check). */
1945 bool breakup
= false;
1947 for (int c
= 0; c
< 4; ++c
)
1954 /* Otherwise, we're free to proceed */
1958 if (ains
->unit
== ALU_ENAB_BRANCH
) {
1959 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
1960 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
1961 bytes_emitted
+= sizeof(midgard_branch_extended
);
1963 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
1964 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
1965 bytes_emitted
+= sizeof(ains
->br_compact
);
1968 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
1969 bytes_emitted
+= sizeof(midgard_reg_info
);
1971 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
1972 bundle
.body_words_count
++;
1973 bytes_emitted
+= sizeof(midgard_scalar_alu
);
1976 /* Defer marking until after writing to allow for break */
1977 control
|= ains
->unit
;
1978 last_unit
= ains
->unit
;
1979 ++instructions_emitted
;
1983 /* Bubble up the number of instructions for skipping */
1984 instructions_consumed
= index
- 1;
1988 /* Pad ALU op to nearest word */
1990 if (bytes_emitted
& 15) {
1991 padding
= 16 - (bytes_emitted
& 15);
1992 bytes_emitted
+= padding
;
1995 /* Constants must always be quadwords */
1996 if (bundle
.has_embedded_constants
)
1997 bytes_emitted
+= 16;
1999 /* Size ALU instruction for tag */
2000 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2001 bundle
.padding
= padding
;
2002 bundle
.control
= bundle
.tag
| control
;
2007 case TAG_LOAD_STORE_4
: {
2008 /* Load store instructions have two words at once. If
2009 * we only have one queued up, we need to NOP pad.
2010 * Otherwise, we store both in succession to save space
2011 * and cycles -- letting them go in parallel -- skip
2012 * the next. The usefulness of this optimisation is
2013 * greatly dependent on the quality of the instruction
2017 midgard_instruction
*next_op
= mir_next_op(ins
);
2019 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2020 /* As the two operate concurrently, make sure
2021 * they are not dependent */
2023 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2024 /* Skip ahead, since it's redundant with the pair */
2025 instructions_consumed
= 1 + (instructions_emitted
++);
2033 /* Texture ops default to single-op-per-bundle scheduling */
2037 /* Copy the instructions into the bundle */
2038 bundle
.instruction_count
= instructions_emitted
+ 1;
2042 midgard_instruction
*uins
= ins
;
2043 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2044 bundle
.instructions
[used_idx
++] = *uins
;
2045 uins
= mir_next_op(uins
);
2048 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2054 quadword_size(int tag
)
2069 case TAG_LOAD_STORE_4
:
2081 /* Schedule a single block by iterating its instruction to create bundles.
2082 * While we go, tally about the bundle sizes to compute the block size. */
2085 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2087 util_dynarray_init(&block
->bundles
, NULL
);
2089 block
->quadword_count
= 0;
2091 mir_foreach_instr_in_block(block
, ins
) {
2093 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2094 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2096 if (bundle
.has_blend_constant
) {
2097 /* TODO: Multiblock? */
2098 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2099 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2103 ins
= mir_next_op(ins
);
2105 block
->quadword_count
+= quadword_size(bundle
.tag
);
2108 block
->is_scheduled
= true;
2112 schedule_program(compiler_context
*ctx
)
2114 /* We run RA prior to scheduling */
2115 struct ra_graph
*g
= allocate_registers(ctx
);
2116 install_registers(ctx
, g
);
2118 mir_foreach_block(ctx
, block
) {
2119 schedule_block(ctx
, block
);
2123 /* After everything is scheduled, emit whole bundles at a time */
2126 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2128 int lookahead
= next_tag
<< 4;
2130 switch (bundle
->tag
) {
2135 /* Actually emit each component */
2136 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2138 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2139 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2141 /* Emit body words based on the instructions bundled */
2142 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2143 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2145 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2146 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2147 } else if (ins
->compact_branch
) {
2148 /* Dummy move, XXX DRY */
2149 if ((i
== 0) && ins
->writeout
) {
2150 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2151 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2154 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2155 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2157 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2161 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2162 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2166 /* Emit padding (all zero) */
2167 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2169 /* Tack on constants */
2171 if (bundle
->has_embedded_constants
) {
2172 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2173 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2174 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2175 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2181 case TAG_LOAD_STORE_4
: {
2182 /* One or two composing instructions */
2184 uint64_t current64
, next64
= LDST_NOP
;
2186 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2188 if (bundle
->instruction_count
== 2)
2189 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2191 midgard_load_store instruction
= {
2192 .type
= bundle
->tag
,
2193 .next_type
= next_tag
,
2198 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2203 case TAG_TEXTURE_4
: {
2204 /* Texture instructions are easy, since there is no
2205 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2207 midgard_instruction
*ins
= &bundle
->instructions
[0];
2209 ins
->texture
.type
= TAG_TEXTURE_4
;
2210 ins
->texture
.next_type
= next_tag
;
2212 ctx
->texture_op_count
--;
2214 if (!ctx
->texture_op_count
) {
2215 ins
->texture
.cont
= 0;
2216 ins
->texture
.last
= 1;
2219 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2224 DBG("Unknown midgard instruction type\n");
2231 /* ALU instructions can inline or embed constants, which decreases register
2232 * pressure and saves space. */
2234 #define CONDITIONAL_ATTACH(src) { \
2235 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2238 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2239 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2244 inline_alu_constants(compiler_context
*ctx
)
2246 mir_foreach_instr(ctx
, alu
) {
2247 /* Other instructions cannot inline constants */
2248 if (alu
->type
!= TAG_ALU_4
) continue;
2250 /* If there is already a constant here, we can do nothing */
2251 if (alu
->has_constants
) continue;
2253 /* It makes no sense to inline constants on a branch */
2254 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2256 CONDITIONAL_ATTACH(src0
);
2258 if (!alu
->has_constants
) {
2259 CONDITIONAL_ATTACH(src1
)
2260 } else if (!alu
->inline_constant
) {
2261 /* Corner case: _two_ vec4 constants, for instance with a
2262 * csel. For this case, we can only use a constant
2263 * register for one, we'll have to emit a move for the
2264 * other. Note, if both arguments are constants, then
2265 * necessarily neither argument depends on the value of
2266 * any particular register. As the destination register
2267 * will be wiped, that means we can spill the constant
2268 * to the destination register.
2271 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2272 unsigned scratch
= alu
->ssa_args
.dest
;
2275 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2276 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2278 /* Force a break XXX Defer r31 writes */
2279 ins
.unit
= UNIT_VLUT
;
2281 /* Set the source */
2282 alu
->ssa_args
.src1
= scratch
;
2284 /* Inject us -before- the last instruction which set r31 */
2285 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2291 /* Midgard supports two types of constants, embedded constants (128-bit) and
2292 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2293 * constants can be demoted to inline constants, for space savings and
2294 * sometimes a performance boost */
2297 embedded_to_inline_constant(compiler_context
*ctx
)
2299 mir_foreach_instr(ctx
, ins
) {
2300 if (!ins
->has_constants
) continue;
2302 if (ins
->ssa_args
.inline_constant
) continue;
2304 /* Blend constants must not be inlined by definition */
2305 if (ins
->has_blend_constant
) continue;
2307 /* src1 cannot be an inline constant due to encoding
2308 * restrictions. So, if possible we try to flip the arguments
2311 int op
= ins
->alu
.op
;
2313 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2315 /* These ops require an operational change to flip
2316 * their arguments TODO */
2317 case midgard_alu_op_flt
:
2318 case midgard_alu_op_fle
:
2319 case midgard_alu_op_ilt
:
2320 case midgard_alu_op_ile
:
2321 case midgard_alu_op_fcsel
:
2322 case midgard_alu_op_icsel
:
2323 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2328 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2329 /* Flip the SSA numbers */
2330 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2331 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2333 /* And flip the modifiers */
2337 src_temp
= ins
->alu
.src2
;
2338 ins
->alu
.src2
= ins
->alu
.src1
;
2339 ins
->alu
.src1
= src_temp
;
2343 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2344 /* Extract the source information */
2346 midgard_vector_alu_src
*src
;
2347 int q
= ins
->alu
.src2
;
2348 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2351 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2352 int component
= src
->swizzle
& 3;
2354 /* Scale constant appropriately, if we can legally */
2355 uint16_t scaled_constant
= 0;
2357 if (midgard_is_integer_op(op
)) {
2358 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2359 scaled_constant
= (uint16_t) iconstants
[component
];
2361 /* Constant overflow after resize */
2362 if (scaled_constant
!= iconstants
[component
])
2365 float original
= (float) ins
->constants
[component
];
2366 scaled_constant
= _mesa_float_to_half(original
);
2368 /* Check for loss of precision. If this is
2369 * mediump, we don't care, but for a highp
2370 * shader, we need to pay attention. NIR
2371 * doesn't yet tell us which mode we're in!
2372 * Practically this prevents most constants
2373 * from being inlined, sadly. */
2375 float fp32
= _mesa_half_to_float(scaled_constant
);
2377 if (fp32
!= original
)
2381 /* We don't know how to handle these with a constant */
2383 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2384 DBG("Bailing inline constant...\n");
2388 /* Make sure that the constant is not itself a
2389 * vector by checking if all accessed values
2390 * (by the swizzle) are the same. */
2392 uint32_t *cons
= (uint32_t *) ins
->constants
;
2393 uint32_t value
= cons
[component
];
2395 bool is_vector
= false;
2396 unsigned mask
= effective_writemask(&ins
->alu
);
2398 for (int c
= 1; c
< 4; ++c
) {
2399 /* We only care if this component is actually used */
2400 if (!(mask
& (1 << c
)))
2403 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2405 if (test
!= value
) {
2414 /* Get rid of the embedded constant */
2415 ins
->has_constants
= false;
2416 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2417 ins
->ssa_args
.inline_constant
= true;
2418 ins
->inline_constant
= scaled_constant
;
2423 /* Map normal SSA sources to other SSA sources / fixed registers (like
2427 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2429 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2432 /* Remove entry in leftovers to avoid a redunant fmov */
2434 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2437 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2439 /* Assign the alias map */
2445 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
2446 * texture pipeline */
2449 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
2451 bool progress
= false;
2453 mir_foreach_instr_in_block_safe(block
, ins
) {
2454 if (ins
->type
!= TAG_ALU_4
) continue;
2455 if (ins
->compact_branch
) continue;
2457 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2458 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2460 mir_remove_instruction(ins
);
2468 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
2471 if (!is_int
&& src
.mod
) return true;
2474 for (unsigned c
= 0; c
< 4; ++c
) {
2475 if (!(mask
& (1 << c
))) continue;
2476 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
2483 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
2485 bool progress
= false;
2487 mir_foreach_instr_in_block_safe(block
, ins
) {
2488 if (ins
->type
!= TAG_ALU_4
) continue;
2489 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2491 unsigned from
= ins
->ssa_args
.src1
;
2492 unsigned to
= ins
->ssa_args
.dest
;
2494 /* We only work on pure SSA */
2496 if (to
>= SSA_FIXED_MINIMUM
) continue;
2497 if (from
>= SSA_FIXED_MINIMUM
) continue;
2498 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
2499 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2501 /* Constant propagation is not handled here, either */
2502 if (ins
->ssa_args
.inline_constant
) continue;
2503 if (ins
->has_constants
) continue;
2505 /* Also, if the move has side effects, we're helpless */
2507 midgard_vector_alu_src src
=
2508 vector_alu_from_unsigned(ins
->alu
.src2
);
2509 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
2510 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2512 if (mir_nontrivial_mod(src
, is_int
, mask
)) continue;
2513 if (ins
->alu
.outmod
!= midgard_outmod_none
) continue;
2515 mir_foreach_instr_in_block_from(block
, v
, mir_next_op(ins
)) {
2516 if (v
->ssa_args
.src0
== to
) {
2517 v
->ssa_args
.src0
= from
;
2521 if (v
->ssa_args
.src1
== to
&& !v
->ssa_args
.inline_constant
) {
2522 v
->ssa_args
.src1
= from
;
2532 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
2534 bool progress
= false;
2536 mir_foreach_instr_in_block_safe(block
, ins
) {
2537 if (ins
->type
!= TAG_ALU_4
) continue;
2538 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2540 unsigned from
= ins
->ssa_args
.src1
;
2541 unsigned to
= ins
->ssa_args
.dest
;
2543 /* Make sure it's simple enough for us to handle */
2545 if (from
>= SSA_FIXED_MINIMUM
) continue;
2546 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2547 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
2548 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
2550 bool eliminated
= false;
2552 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2553 /* The texture registers are not SSA so be careful.
2554 * Conservatively, just stop if we hit a texture op
2555 * (even if it may not write) to where we are */
2557 if (v
->type
!= TAG_ALU_4
)
2560 if (v
->ssa_args
.dest
== from
) {
2561 /* We don't want to track partial writes ... */
2562 if (v
->alu
.mask
== 0xF) {
2563 v
->ssa_args
.dest
= to
;
2572 mir_remove_instruction(ins
);
2574 progress
|= eliminated
;
2580 /* The following passes reorder MIR instructions to enable better scheduling */
2583 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2585 mir_foreach_instr_in_block_safe(block
, ins
) {
2586 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2588 /* We've found a load/store op. Check if next is also load/store. */
2589 midgard_instruction
*next_op
= mir_next_op(ins
);
2590 if (&next_op
->link
!= &block
->instructions
) {
2591 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2592 /* If so, we're done since we're a pair */
2593 ins
= mir_next_op(ins
);
2597 /* Maximum search distance to pair, to avoid register pressure disasters */
2598 int search_distance
= 8;
2600 /* Otherwise, we have an orphaned load/store -- search for another load */
2601 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2602 /* Terminate search if necessary */
2603 if (!(search_distance
--)) break;
2605 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2607 /* Stores cannot be reordered, since they have
2608 * dependencies. For the same reason, indirect
2609 * loads cannot be reordered as their index is
2610 * loaded in r27.w */
2612 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2614 /* It appears the 0x800 bit is set whenever a
2615 * load is direct, unset when it is indirect.
2616 * Skip indirect loads. */
2618 if (!(c
->load_store
.unknown
& 0x800)) continue;
2620 /* We found one! Move it up to pair and remove it from the old location */
2622 mir_insert_instruction_before(ins
, *c
);
2623 mir_remove_instruction(c
);
2631 /* Emit varying stores late */
2634 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2635 /* Iterate in reverse to get the final write, rather than the first */
2637 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2638 /* Check if what we just wrote needs a store */
2639 int idx
= ins
->ssa_args
.dest
;
2640 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2642 if (!varying
) continue;
2646 /* We need to store to the appropriate varying, so emit the
2649 /* TODO: Integrate with special purpose RA (and scheduler?) */
2650 bool high_varying_register
= false;
2652 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2654 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2655 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2657 mir_insert_instruction_before(mir_next_op(ins
), st
);
2658 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2660 /* We no longer need to store this varying */
2661 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2665 /* If there are leftovers after the below pass, emit actual fmov
2666 * instructions for the slow-but-correct path */
2669 emit_leftover_move(compiler_context
*ctx
)
2671 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2672 int base
= ((uintptr_t) leftover
->key
) - 1;
2675 map_ssa_to_alias(ctx
, &mapped
);
2676 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2681 actualise_ssa_to_alias(compiler_context
*ctx
)
2683 mir_foreach_instr(ctx
, ins
) {
2684 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2685 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2688 emit_leftover_move(ctx
);
2692 emit_fragment_epilogue(compiler_context
*ctx
)
2694 /* Special case: writing out constants requires us to include the move
2695 * explicitly now, so shove it into r0 */
2697 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2699 if (constant_value
) {
2700 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2701 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2702 emit_mir_instruction(ctx
, ins
);
2705 /* Perform the actual fragment writeout. We have two writeout/branch
2706 * instructions, forming a loop until writeout is successful as per the
2707 * docs. TODO: gl_FragDepth */
2709 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2710 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2713 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2714 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2715 * with the int8 analogue to the fragment epilogue */
2718 emit_blend_epilogue(compiler_context
*ctx
)
2720 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2722 midgard_instruction scale
= {
2725 .inline_constant
= _mesa_float_to_half(255.0),
2727 .src0
= SSA_FIXED_REGISTER(0),
2728 .src1
= SSA_UNUSED_0
,
2729 .dest
= SSA_FIXED_REGISTER(24),
2730 .inline_constant
= true
2733 .op
= midgard_alu_op_fmul
,
2734 .reg_mode
= midgard_reg_mode_32
,
2735 .dest_override
= midgard_dest_override_lower
,
2737 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2738 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2742 emit_mir_instruction(ctx
, scale
);
2744 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2746 midgard_vector_alu_src alu_src
= blank_alu_src
;
2747 alu_src
.half
= true;
2749 midgard_instruction f2u8
= {
2752 .src0
= SSA_FIXED_REGISTER(24),
2753 .src1
= SSA_UNUSED_0
,
2754 .dest
= SSA_FIXED_REGISTER(0),
2755 .inline_constant
= true
2758 .op
= midgard_alu_op_f2u8
,
2759 .reg_mode
= midgard_reg_mode_16
,
2760 .dest_override
= midgard_dest_override_lower
,
2761 .outmod
= midgard_outmod_pos
,
2763 .src1
= vector_alu_srco_unsigned(alu_src
),
2764 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2768 emit_mir_instruction(ctx
, f2u8
);
2770 /* vmul.imov.quarter r0, r0, r0 */
2772 midgard_instruction imov_8
= {
2775 .src0
= SSA_UNUSED_1
,
2776 .src1
= SSA_FIXED_REGISTER(0),
2777 .dest
= SSA_FIXED_REGISTER(0),
2780 .op
= midgard_alu_op_imov
,
2781 .reg_mode
= midgard_reg_mode_8
,
2782 .dest_override
= midgard_dest_override_none
,
2783 .outmod
= midgard_outmod_int
,
2785 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2786 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2790 /* Emit branch epilogue with the 8-bit move as the source */
2792 emit_mir_instruction(ctx
, imov_8
);
2793 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2795 emit_mir_instruction(ctx
, imov_8
);
2796 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2799 static midgard_block
*
2800 emit_block(compiler_context
*ctx
, nir_block
*block
)
2802 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2803 list_addtail(&this_block
->link
, &ctx
->blocks
);
2805 this_block
->is_scheduled
= false;
2808 ctx
->texture_index
[0] = -1;
2809 ctx
->texture_index
[1] = -1;
2811 /* Add us as a successor to the block we are following */
2812 if (ctx
->current_block
)
2813 midgard_block_add_successor(ctx
->current_block
, this_block
);
2815 /* Set up current block */
2816 list_inithead(&this_block
->instructions
);
2817 ctx
->current_block
= this_block
;
2819 nir_foreach_instr(instr
, block
) {
2820 emit_instr(ctx
, instr
);
2821 ++ctx
->instruction_count
;
2824 inline_alu_constants(ctx
);
2825 embedded_to_inline_constant(ctx
);
2827 /* Perform heavylifting for aliasing */
2828 actualise_ssa_to_alias(ctx
);
2830 midgard_emit_store(ctx
, this_block
);
2831 midgard_pair_load_store(ctx
, this_block
);
2833 /* Append fragment shader epilogue (value writeout) */
2834 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2835 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2837 emit_blend_epilogue(ctx
);
2839 emit_fragment_epilogue(ctx
);
2843 if (block
== nir_start_block(ctx
->func
->impl
))
2844 ctx
->initial_block
= this_block
;
2846 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2847 ctx
->final_block
= this_block
;
2849 /* Allow the next control flow to access us retroactively, for
2851 ctx
->current_block
= this_block
;
2853 /* Document the fallthrough chain */
2854 ctx
->previous_source_block
= this_block
;
2859 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2862 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2864 /* Conditional branches expect the condition in r31.w; emit a move for
2865 * that in the _previous_ block (which is the current block). */
2866 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2868 /* Speculatively emit the branch, but we can't fill it in until later */
2869 EMIT(branch
, true, true);
2870 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2872 /* Emit the two subblocks */
2873 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2875 /* Emit a jump from the end of the then block to the end of the else */
2876 EMIT(branch
, false, false);
2877 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2879 /* Emit second block, and check if it's empty */
2881 int else_idx
= ctx
->block_count
;
2882 int count_in
= ctx
->instruction_count
;
2883 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2884 int after_else_idx
= ctx
->block_count
;
2886 /* Now that we have the subblocks emitted, fix up the branches */
2891 if (ctx
->instruction_count
== count_in
) {
2892 /* The else block is empty, so don't emit an exit jump */
2893 mir_remove_instruction(then_exit
);
2894 then_branch
->branch
.target_block
= after_else_idx
;
2896 then_branch
->branch
.target_block
= else_idx
;
2897 then_exit
->branch
.target_block
= after_else_idx
;
2902 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2904 /* Remember where we are */
2905 midgard_block
*start_block
= ctx
->current_block
;
2907 /* Allocate a loop number, growing the current inner loop depth */
2908 int loop_idx
= ++ctx
->current_loop_depth
;
2910 /* Get index from before the body so we can loop back later */
2911 int start_idx
= ctx
->block_count
;
2913 /* Emit the body itself */
2914 emit_cf_list(ctx
, &nloop
->body
);
2916 /* Branch back to loop back */
2917 struct midgard_instruction br_back
= v_branch(false, false);
2918 br_back
.branch
.target_block
= start_idx
;
2919 emit_mir_instruction(ctx
, br_back
);
2921 /* Mark down that branch in the graph. Note that we're really branching
2922 * to the block *after* we started in. TODO: Why doesn't the branch
2923 * itself have an off-by-one then...? */
2924 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2926 /* Find the index of the block about to follow us (note: we don't add
2927 * one; blocks are 0-indexed so we get a fencepost problem) */
2928 int break_block_idx
= ctx
->block_count
;
2930 /* Fix up the break statements we emitted to point to the right place,
2931 * now that we can allocate a block number for them */
2933 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2934 mir_foreach_instr_in_block(block
, ins
) {
2935 if (ins
->type
!= TAG_ALU_4
) continue;
2936 if (!ins
->compact_branch
) continue;
2937 if (ins
->prepacked_branch
) continue;
2939 /* We found a branch -- check the type to see if we need to do anything */
2940 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2942 /* It's a break! Check if it's our break */
2943 if (ins
->branch
.target_break
!= loop_idx
) continue;
2945 /* Okay, cool, we're breaking out of this loop.
2946 * Rewrite from a break to a goto */
2948 ins
->branch
.target_type
= TARGET_GOTO
;
2949 ins
->branch
.target_block
= break_block_idx
;
2953 /* Now that we've finished emitting the loop, free up the depth again
2954 * so we play nice with recursion amid nested loops */
2955 --ctx
->current_loop_depth
;
2958 static midgard_block
*
2959 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2961 midgard_block
*start_block
= NULL
;
2963 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2964 switch (node
->type
) {
2965 case nir_cf_node_block
: {
2966 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2969 start_block
= block
;
2974 case nir_cf_node_if
:
2975 emit_if(ctx
, nir_cf_node_as_if(node
));
2978 case nir_cf_node_loop
:
2979 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2982 case nir_cf_node_function
:
2991 /* Due to lookahead, we need to report the first tag executed in the command
2992 * stream and in branch targets. An initial block might be empty, so iterate
2993 * until we find one that 'works' */
2996 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2998 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3000 unsigned first_tag
= 0;
3003 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3005 if (initial_bundle
) {
3006 first_tag
= initial_bundle
->tag
;
3010 /* Initial block is empty, try the next block */
3011 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3012 } while(initial_block
!= NULL
);
3019 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3021 struct util_dynarray
*compiled
= &program
->compiled
;
3023 midgard_debug
= debug_get_option_midgard_debug();
3025 compiler_context ictx
= {
3027 .stage
= nir
->info
.stage
,
3029 .is_blend
= is_blend
,
3030 .blend_constant_offset
= -1,
3032 .alpha_ref
= program
->alpha_ref
3035 compiler_context
*ctx
= &ictx
;
3037 /* TODO: Decide this at runtime */
3038 ctx
->uniform_cutoff
= 8;
3040 /* Assign var locations early, so the epilogue can use them if necessary */
3042 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3043 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3044 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3046 /* Initialize at a global (not block) level hash tables */
3048 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3049 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3050 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3051 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3052 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3053 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3055 /* Record the varying mapping for the command stream's bookkeeping */
3057 struct exec_list
*varyings
=
3058 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3060 nir_foreach_variable(var
, varyings
) {
3061 unsigned loc
= var
->data
.driver_location
;
3062 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3064 for (int c
= 0; c
< sz
; ++c
) {
3065 program
->varyings
[loc
+ c
] = var
->data
.location
;
3069 /* Lower gl_Position pre-optimisation */
3071 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3072 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3074 NIR_PASS_V(nir
, nir_lower_var_copies
);
3075 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3076 NIR_PASS_V(nir
, nir_split_var_copies
);
3077 NIR_PASS_V(nir
, nir_lower_var_copies
);
3078 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3079 NIR_PASS_V(nir
, nir_lower_var_copies
);
3080 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3082 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3084 /* Optimisation passes */
3088 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3089 nir_print_shader(nir
, stdout
);
3092 /* Assign sysvals and counts, now that we're sure
3093 * (post-optimisation) */
3095 midgard_nir_assign_sysvals(ctx
, nir
);
3097 program
->uniform_count
= nir
->num_uniforms
;
3098 program
->sysval_count
= ctx
->sysval_count
;
3099 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3101 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3102 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3104 nir_foreach_function(func
, nir
) {
3108 list_inithead(&ctx
->blocks
);
3109 ctx
->block_count
= 0;
3112 emit_cf_list(ctx
, &func
->impl
->body
);
3113 emit_block(ctx
, func
->impl
->end_block
);
3115 break; /* TODO: Multi-function shaders */
3118 util_dynarray_init(compiled
, NULL
);
3120 /* MIR-level optimizations */
3122 bool progress
= false;
3127 mir_foreach_block(ctx
, block
) {
3128 progress
|= midgard_opt_copy_prop(ctx
, block
);
3129 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
3130 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
3135 schedule_program(ctx
);
3137 /* Now that all the bundles are scheduled and we can calculate block
3138 * sizes, emit actual branch instructions rather than placeholders */
3140 int br_block_idx
= 0;
3142 mir_foreach_block(ctx
, block
) {
3143 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3144 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3145 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3147 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3149 if (ins
->prepacked_branch
) continue;
3151 /* Parse some basic branch info */
3152 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3153 bool is_conditional
= ins
->branch
.conditional
;
3154 bool is_inverted
= ins
->branch
.invert_conditional
;
3155 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3157 /* Determine the block we're jumping to */
3158 int target_number
= ins
->branch
.target_block
;
3160 /* Report the destination tag. Discards don't need this */
3161 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3163 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3164 int quadword_offset
= 0;
3167 /* Jump to the end of the shader. We
3168 * need to include not only the
3169 * following blocks, but also the
3170 * contents of our current block (since
3171 * discard can come in the middle of
3174 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3176 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3177 quadword_offset
+= quadword_size(bun
->tag
);
3180 mir_foreach_block_from(ctx
, blk
, b
) {
3181 quadword_offset
+= b
->quadword_count
;
3184 } else if (target_number
> br_block_idx
) {
3187 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3188 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3191 quadword_offset
+= blk
->quadword_count
;
3194 /* Jump backwards */
3196 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3197 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3200 quadword_offset
-= blk
->quadword_count
;
3204 /* Unconditional extended branches (far jumps)
3205 * have issues, so we always use a conditional
3206 * branch, setting the condition to always for
3207 * unconditional. For compact unconditional
3208 * branches, cond isn't used so it doesn't
3209 * matter what we pick. */
3211 midgard_condition cond
=
3212 !is_conditional
? midgard_condition_always
:
3213 is_inverted
? midgard_condition_false
:
3214 midgard_condition_true
;
3216 midgard_jmp_writeout_op op
=
3217 is_discard
? midgard_jmp_writeout_op_discard
:
3218 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3219 midgard_jmp_writeout_op_branch_cond
;
3222 midgard_branch_extended branch
=
3223 midgard_create_branch_extended(
3228 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3229 } else if (is_conditional
|| is_discard
) {
3230 midgard_branch_cond branch
= {
3232 .dest_tag
= dest_tag
,
3233 .offset
= quadword_offset
,
3237 assert(branch
.offset
== quadword_offset
);
3239 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3241 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3243 midgard_branch_uncond branch
= {
3245 .dest_tag
= dest_tag
,
3246 .offset
= quadword_offset
,
3250 assert(branch
.offset
== quadword_offset
);
3252 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3260 /* Emit flat binary from the instruction arrays. Iterate each block in
3261 * sequence. Save instruction boundaries such that lookahead tags can
3262 * be assigned easily */
3264 /* Cache _all_ bundles in source order for lookahead across failed branches */
3266 int bundle_count
= 0;
3267 mir_foreach_block(ctx
, block
) {
3268 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3270 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3272 mir_foreach_block(ctx
, block
) {
3273 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3274 source_order_bundles
[bundle_idx
++] = bundle
;
3278 int current_bundle
= 0;
3280 mir_foreach_block(ctx
, block
) {
3281 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3284 if (current_bundle
+ 1 < bundle_count
) {
3285 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3287 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3294 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3298 /* TODO: Free deeper */
3299 //util_dynarray_fini(&block->instructions);
3302 free(source_order_bundles
);
3304 /* Report the very first tag executed */
3305 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3307 /* Deal with off-by-one related to the fencepost problem */
3308 program
->work_register_count
= ctx
->work_registers
+ 1;
3310 program
->can_discard
= ctx
->can_discard
;
3311 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3313 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3315 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3316 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);