2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "compiler/glsl/glsl_to_nir.h"
34 #include "compiler/nir_types.h"
35 #include "main/imports.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/register_allocate.h"
39 #include "util/u_dynarray.h"
40 #include "util/list.h"
41 #include "main/mtypes.h"
44 #include "midgard_nir.h"
45 #include "midgard_compile.h"
48 #include "disassemble.h"
50 /* Instruction arguments represented as block-local SSA indices, rather than
51 * registers. Negative values mean unused. */
58 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
59 * in. Only valid for ALU ops. */
63 /* Forward declare so midgard_branch can reference */
66 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
67 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
68 * instruction is actually a discard op. */
71 #define TARGET_BREAK 1
72 #define TARGET_CONTINUE 2
73 #define TARGET_DISCARD 3
75 typedef struct midgard_branch
{
76 /* If conditional, the condition is specified in r31.w */
79 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
80 bool invert_conditional
;
82 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
85 /* The actual target */
93 /* Generic in-memory data type repesenting a single logical instruction, rather
94 * than a single instruction group. This is the preferred form for code gen.
95 * Multiple midgard_insturctions will later be combined during scheduling,
96 * though this is not represented in this structure. Its format bridges
97 * the low-level binary representation with the higher level semantic meaning.
99 * Notably, it allows registers to be specified as block local SSA, for code
100 * emitted before the register allocation pass.
103 typedef struct midgard_instruction
{
104 /* Must be first for casting */
105 struct list_head link
;
107 unsigned type
; /* ALU, load/store, texture */
109 /* If the register allocator has not run yet... */
112 /* Special fields for an ALU instruction */
113 midgard_reg_info registers
;
115 /* I.e. (1 << alu_bit) */
120 uint16_t inline_constant
;
121 bool has_blend_constant
;
125 bool prepacked_branch
;
128 midgard_load_store_word load_store
;
129 midgard_vector_alu alu
;
130 midgard_texture_word texture
;
131 midgard_branch_extended branch_extended
;
134 /* General branch, rather than packed br_compact. Higher level
135 * than the other components */
136 midgard_branch branch
;
138 } midgard_instruction
;
140 typedef struct midgard_block
{
141 /* Link to next block. Must be first for mir_get_block */
142 struct list_head link
;
144 /* List of midgard_instructions emitted for the current block */
145 struct list_head instructions
;
149 /* List of midgard_bundles emitted (after the scheduler has run) */
150 struct util_dynarray bundles
;
152 /* Number of quadwords _actually_ emitted, as determined after scheduling */
153 unsigned quadword_count
;
155 struct midgard_block
*next_fallthrough
;
158 /* Helpers to generate midgard_instruction's using macro magic, since every
159 * driver seems to do it that way */
161 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
163 #define M_LOAD_STORE(name, rname, uname) \
164 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
165 midgard_instruction i = { \
166 .type = TAG_LOAD_STORE_4, \
173 .op = midgard_op_##name, \
175 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
183 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
184 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
186 const midgard_vector_alu_src blank_alu_src
= {
187 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
190 const midgard_scalar_alu_src blank_scalar_alu_src
= {
194 /* Used for encoding the unused source of 1-op instructions */
195 const midgard_vector_alu_src zero_alu_src
= { 0 };
197 /* Coerce structs to integer */
200 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
203 memcpy(&u
, &src
, sizeof(src
));
207 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
208 * the corresponding Midgard source */
210 static midgard_vector_alu_src
211 vector_alu_modifiers(nir_alu_src
*src
)
213 if (!src
) return blank_alu_src
;
215 midgard_vector_alu_src alu_src
= {
217 .negate
= src
->negate
,
220 .half
= 0, /* TODO */
221 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
227 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
229 static midgard_instruction
230 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
232 midgard_instruction ins
= {
235 .src0
= SSA_UNUSED_1
,
240 .op
= midgard_alu_op_fmov
,
241 .reg_mode
= midgard_reg_mode_full
,
242 .dest_override
= midgard_dest_override_none
,
244 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
245 .src2
= vector_alu_srco_unsigned(mod
)
252 /* load/store instructions have both 32-bit and 16-bit variants, depending on
253 * whether we are using vectors composed of highp or mediump. At the moment, we
254 * don't support half-floats -- this requires changes in other parts of the
255 * compiler -- therefore the 16-bit versions are commented out. */
257 //M_LOAD(load_attr_16);
258 M_LOAD(load_attr_32
);
259 //M_LOAD(load_vary_16);
260 M_LOAD(load_vary_32
);
261 //M_LOAD(load_uniform_16);
262 M_LOAD(load_uniform_32
);
263 M_LOAD(load_color_buffer_8
);
264 //M_STORE(store_vary_16);
265 M_STORE(store_vary_32
);
267 static midgard_instruction
268 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
270 midgard_branch_cond branch
= {
278 memcpy(&compact
, &branch
, sizeof(branch
));
280 midgard_instruction ins
= {
282 .unit
= ALU_ENAB_BR_COMPACT
,
283 .prepacked_branch
= true,
284 .compact_branch
= true,
285 .br_compact
= compact
288 if (op
== midgard_jmp_writeout_op_writeout
)
294 static midgard_instruction
295 v_branch(bool conditional
, bool invert
)
297 midgard_instruction ins
= {
299 .unit
= ALU_ENAB_BRANCH
,
300 .compact_branch
= true,
302 .conditional
= conditional
,
303 .invert_conditional
= invert
310 static midgard_branch_extended
311 midgard_create_branch_extended( midgard_condition cond
,
312 midgard_jmp_writeout_op op
,
314 signed quadword_offset
)
316 /* For unclear reasons, the condition code is repeated 8 times */
317 uint16_t duplicated_cond
=
327 midgard_branch_extended branch
= {
329 .dest_tag
= dest_tag
,
330 .offset
= quadword_offset
,
331 .cond
= duplicated_cond
337 typedef struct midgard_bundle
{
338 /* Tag for the overall bundle */
341 /* Instructions contained by the bundle */
342 int instruction_count
;
343 midgard_instruction instructions
[5];
345 /* Bundle-wide ALU configuration */
348 bool has_embedded_constants
;
350 bool has_blend_constant
;
352 uint16_t register_words
[8];
353 int register_words_count
;
355 uint64_t body_words
[8];
357 int body_words_count
;
360 typedef struct compiler_context
{
362 gl_shader_stage stage
;
364 /* Is internally a blend shader? Depends on stage == FRAGMENT */
367 /* Tracking for blend constant patching */
368 int blend_constant_number
;
369 int blend_constant_offset
;
371 /* Current NIR function */
374 /* Unordered list of midgard_blocks */
376 struct list_head blocks
;
378 midgard_block
*initial_block
;
379 midgard_block
*previous_source_block
;
380 midgard_block
*final_block
;
382 /* List of midgard_instructions emitted for the current block */
383 midgard_block
*current_block
;
385 /* The index corresponding to the current loop, e.g. for breaks/contineus */
388 /* Constants which have been loaded, for later inlining */
389 struct hash_table_u64
*ssa_constants
;
391 /* SSA indices to be outputted to corresponding varying offset */
392 struct hash_table_u64
*ssa_varyings
;
394 /* SSA values / registers which have been aliased. Naively, these
395 * demand a fmov output; instead, we alias them in a later pass to
396 * avoid the wasted op.
398 * A note on encoding: to avoid dynamic memory management here, rather
399 * than ampping to a pointer, we map to the source index; the key
400 * itself is just the destination index. */
402 struct hash_table_u64
*ssa_to_alias
;
403 struct set
*leftover_ssa_to_alias
;
405 /* Actual SSA-to-register for RA */
406 struct hash_table_u64
*ssa_to_register
;
408 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
409 struct hash_table_u64
*hash_to_temp
;
413 /* Uniform IDs for mdg */
414 struct hash_table_u64
*uniform_nir_to_mdg
;
417 struct hash_table_u64
*varying_nir_to_mdg
;
420 /* Just the count of the max register used. Higher count => higher
421 * register pressure */
424 /* Used for cont/last hinting. Increase when a tex op is added.
425 * Decrease when a tex op is removed. */
426 int texture_op_count
;
428 /* Mapping of texture register -> SSA index for unaliasing */
429 int texture_index
[2];
431 /* Count of special uniforms (viewport, etc) in vec4 units */
432 int special_uniforms
;
434 /* If any path hits a discard instruction */
437 /* The number of uniforms allowable for the fast path */
440 /* Count of instructions emitted from NIR overall, across all blocks */
441 int instruction_count
;
443 /* Alpha ref value passed in */
446 /* The index corresponding to the fragment output */
447 unsigned fragment_output
;
450 /* Append instruction to end of current block */
452 static midgard_instruction
*
453 mir_upload_ins(struct midgard_instruction ins
)
455 midgard_instruction
*heap
= malloc(sizeof(ins
));
456 memcpy(heap
, &ins
, sizeof(ins
));
461 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
463 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
467 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
469 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
473 mir_remove_instruction(struct midgard_instruction
*ins
)
475 list_del(&ins
->link
);
478 static midgard_instruction
*
479 mir_prev_op(struct midgard_instruction
*ins
)
481 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
484 static midgard_instruction
*
485 mir_next_op(struct midgard_instruction
*ins
)
487 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
490 static midgard_block
*
491 mir_next_block(struct midgard_block
*blk
)
493 return list_first_entry(&(blk
->link
), midgard_block
, link
);
497 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
498 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
500 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
501 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
502 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
503 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
504 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
505 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
508 static midgard_instruction
*
509 mir_last_in_block(struct midgard_block
*block
)
511 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
514 static midgard_block
*
515 mir_get_block(compiler_context
*ctx
, int idx
)
517 struct list_head
*lst
= &ctx
->blocks
;
522 return (struct midgard_block
*) lst
;
525 /* Pretty printer for internal Midgard IR */
528 print_mir_source(int source
)
530 if (source
>= SSA_FIXED_MINIMUM
) {
531 /* Specific register */
532 int reg
= SSA_REG_FROM_FIXED(source
);
534 /* TODO: Moving threshold */
535 if (reg
> 16 && reg
< 24)
536 printf("u%d", 23 - reg
);
540 printf("%d", source
);
545 print_mir_instruction(midgard_instruction
*ins
)
551 midgard_alu_op op
= ins
->alu
.op
;
552 const char *name
= alu_opcode_names
[op
];
555 printf("%d.", ins
->unit
);
557 printf("%s", name
? name
: "??");
561 case TAG_LOAD_STORE_4
: {
562 midgard_load_store_op op
= ins
->load_store
.op
;
563 const char *name
= load_store_opcode_names
[op
];
570 case TAG_TEXTURE_4
: {
579 ssa_args
*args
= &ins
->ssa_args
;
581 printf(" %d, ", args
->dest
);
583 print_mir_source(args
->src0
);
586 if (args
->inline_constant
)
587 printf("#%d", ins
->inline_constant
);
589 print_mir_source(args
->src1
);
591 if (ins
->has_constants
)
592 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
598 print_mir_block(midgard_block
*block
)
602 mir_foreach_instr_in_block(block
, ins
) {
603 print_mir_instruction(ins
);
612 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
614 ins
->has_constants
= true;
615 memcpy(&ins
->constants
, constants
, 16);
617 /* If this is the special blend constant, mark this instruction */
619 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
620 ins
->has_blend_constant
= true;
624 glsl_type_size(const struct glsl_type
*type
)
626 return glsl_count_attribute_slots(type
, false);
629 /* Lower fdot2 to a vector multiplication followed by channel addition */
631 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
633 if (alu
->op
!= nir_op_fdot2
)
636 b
->cursor
= nir_before_instr(&alu
->instr
);
638 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
639 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
641 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
643 nir_ssa_def
*sum
= nir_fadd(b
,
644 nir_channel(b
, product
, 0),
645 nir_channel(b
, product
, 1));
647 /* Replace the fdot2 with this sum */
648 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
652 midgard_nir_lower_fdot2(nir_shader
*shader
)
654 bool progress
= false;
656 nir_foreach_function(function
, shader
) {
657 if (!function
->impl
) continue;
660 nir_builder
*b
= &_b
;
661 nir_builder_init(b
, function
->impl
);
663 nir_foreach_block(block
, function
->impl
) {
664 nir_foreach_instr_safe(instr
, block
) {
665 if (instr
->type
!= nir_instr_type_alu
) continue;
667 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
668 midgard_nir_lower_fdot2_body(b
, alu
);
674 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
682 optimise_nir(nir_shader
*nir
)
686 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
687 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
689 nir_lower_tex_options lower_tex_options
= {
693 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
698 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
699 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
700 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
701 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
703 NIR_PASS(progress
, nir
, nir_copy_prop
);
704 NIR_PASS(progress
, nir
, nir_opt_dce
);
705 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
706 NIR_PASS(progress
, nir
, nir_opt_cse
);
707 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
708 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
709 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
710 NIR_PASS(progress
, nir
, nir_opt_undef
);
711 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
714 nir_var_function_temp
);
716 /* TODO: Enable vectorize when merged upstream */
717 // NIR_PASS(progress, nir, nir_opt_vectorize);
720 /* Must be run at the end to prevent creation of fsin/fcos ops */
721 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
726 NIR_PASS(progress
, nir
, nir_opt_dce
);
727 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
728 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
729 NIR_PASS(progress
, nir
, nir_copy_prop
);
732 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
735 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_all_source_mods
);
736 NIR_PASS(progress
, nir
, nir_copy_prop
);
737 NIR_PASS(progress
, nir
, nir_opt_dce
);
739 /* Take us out of SSA */
740 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
741 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
743 /* We are a vector architecture; write combine where possible */
744 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
745 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
747 NIR_PASS(progress
, nir
, nir_opt_dce
);
750 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
751 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
752 * r0. See the comments in compiler_context */
755 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
757 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
758 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
761 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
764 unalias_ssa(compiler_context
*ctx
, int dest
)
766 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
767 /* TODO: Remove from leftover or no? */
771 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
773 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
777 midgard_is_pinned(compiler_context
*ctx
, int index
)
779 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
782 /* Do not actually emit a load; instead, cache the constant for inlining */
785 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
787 nir_ssa_def def
= instr
->def
;
789 float *v
= ralloc_array(NULL
, float, 4);
790 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
791 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
794 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
798 expand_writemask(unsigned mask
)
802 for (int i
= 0; i
< 4; ++i
)
810 squeeze_writemask(unsigned mask
)
814 for (int i
= 0; i
< 4; ++i
)
815 if (mask
& (3 << (2 * i
)))
822 /* Determines effective writemask, taking quirks and expansion into account */
824 effective_writemask(midgard_vector_alu
*alu
)
826 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
829 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
831 /* If there is a fixed channel count, construct the appropriate mask */
834 return (1 << channel_count
) - 1;
836 /* Otherwise, just squeeze the existing mask */
837 return squeeze_writemask(alu
->mask
);
841 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
843 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
846 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
851 /* If no temp is find, allocate one */
852 temp
= ctx
->temp_count
++;
853 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
855 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
861 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
864 return src
->ssa
->index
;
866 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
870 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
873 return dst
->ssa
.index
;
875 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
879 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
881 return nir_src_index(ctx
, &src
->src
);
884 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
885 * a conditional test) into that register */
888 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
890 /* XXX: Force component correct */
891 int condition
= nir_src_index(ctx
, src
);
893 const midgard_vector_alu_src alu_src
= {
894 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
897 /* There is no boolean move instruction. Instead, we simulate a move by
898 * ANDing the condition with itself to get it into r31.w */
900 midgard_instruction ins
= {
902 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
906 .dest
= SSA_FIXED_REGISTER(31),
909 .op
= midgard_alu_op_iand
,
910 .reg_mode
= midgard_reg_mode_full
,
911 .dest_override
= midgard_dest_override_none
,
912 .mask
= (0x3 << 6), /* w */
913 .src1
= vector_alu_srco_unsigned(alu_src
),
914 .src2
= vector_alu_srco_unsigned(alu_src
)
918 emit_mir_instruction(ctx
, ins
);
921 #define ALU_CASE(nir, _op) \
923 op = midgard_alu_op_##_op; \
927 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
929 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
931 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
932 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
933 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
935 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
936 * supported. A few do not and are commented for now. Also, there are a
937 * number of NIR ops which Midgard does not support and need to be
938 * lowered, also TODO. This switch block emits the opcode and calling
939 * convention of the Midgard instruction; actual packing is done in
945 ALU_CASE(fadd
, fadd
);
946 ALU_CASE(fmul
, fmul
);
947 ALU_CASE(fmin
, fmin
);
948 ALU_CASE(fmax
, fmax
);
949 ALU_CASE(imin
, imin
);
950 ALU_CASE(imax
, imax
);
951 ALU_CASE(fmov
, fmov
);
952 ALU_CASE(ffloor
, ffloor
);
953 ALU_CASE(fround_even
, froundeven
);
954 ALU_CASE(ftrunc
, ftrunc
);
955 ALU_CASE(fceil
, fceil
);
956 ALU_CASE(fdot3
, fdot3
);
957 ALU_CASE(fdot4
, fdot4
);
958 ALU_CASE(iadd
, iadd
);
959 ALU_CASE(isub
, isub
);
960 ALU_CASE(imul
, imul
);
962 /* XXX: Use fmov, not imov, since imov was causing major
963 * issues with texture precision? XXX research */
964 ALU_CASE(imov
, fmov
);
973 ALU_CASE(frcp
, frcp
);
974 ALU_CASE(frsq
, frsqrt
);
975 ALU_CASE(fsqrt
, fsqrt
);
976 ALU_CASE(fexp2
, fexp2
);
977 ALU_CASE(flog2
, flog2
);
979 ALU_CASE(f2i32
, f2i
);
980 ALU_CASE(f2u32
, f2u
);
981 ALU_CASE(i2f32
, i2f
);
982 ALU_CASE(u2f32
, u2f
);
984 ALU_CASE(fsin
, fsin
);
985 ALU_CASE(fcos
, fcos
);
987 ALU_CASE(iand
, iand
);
989 ALU_CASE(ixor
, ixor
);
990 ALU_CASE(inot
, inot
);
991 ALU_CASE(ishl
, ishl
);
992 ALU_CASE(ishr
, iasr
);
993 ALU_CASE(ushr
, ilsr
);
995 ALU_CASE(ball_fequal4
, fball_eq
);
996 ALU_CASE(bany_fnequal4
, fbany_neq
);
997 ALU_CASE(ball_iequal4
, iball_eq
);
998 ALU_CASE(bany_inequal4
, ibany_neq
);
1000 /* For greater-or-equal, we use less-or-equal and flip the
1004 op
= midgard_alu_op_ile
;
1006 /* Swap via temporary */
1007 nir_alu_src temp
= instr
->src
[1];
1008 instr
->src
[1] = instr
->src
[0];
1009 instr
->src
[0] = temp
;
1014 case nir_op_bcsel
: {
1015 op
= midgard_alu_op_fcsel
;
1017 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1020 emit_condition(ctx
, &instr
->src
[0].src
, false);
1022 /* The condition is the first argument; move the other
1023 * arguments up one to be a binary instruction for
1026 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1030 /* We don't have a native b2f32 instruction. Instead, like many GPUs,
1031 * we exploit booleans as 0/~0 for false/true, and correspondingly AND
1032 * by 1.0 to do the type conversion. For the moment, prime us to emit:
1034 * iand [whatever], #0
1036 * At the end of emit_alu (as MIR), we'll fix-up the constant */
1038 case nir_op_b2f32
: {
1039 op
= midgard_alu_op_iand
;
1044 printf("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1049 /* Fetch unit, quirks, etc information */
1050 unsigned opcode_props
= alu_opcode_props
[op
];
1051 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1053 /* Initialise fields common between scalar/vector instructions */
1054 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1056 /* src0 will always exist afaik, but src1 will not for 1-argument
1057 * instructions. The latter can only be fetched if the instruction
1058 * needs it, or else we may segfault. */
1060 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1061 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1063 /* Rather than use the instruction generation helpers, we do it
1064 * ourselves here to avoid the mess */
1066 midgard_instruction ins
= {
1069 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1070 .src1
= quirk_flipped_r24
? src0
: src1
,
1072 .inline_constant
= (nr_inputs
== 1) && !quirk_flipped_r24
1076 nir_alu_src
*nirmods
[2] = { NULL
};
1078 if (nr_inputs
== 2) {
1079 nirmods
[0] = &instr
->src
[0];
1080 nirmods
[1] = &instr
->src
[1];
1081 } else if (nr_inputs
== 1) {
1082 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1087 midgard_vector_alu alu
= {
1089 .reg_mode
= midgard_reg_mode_full
,
1090 .dest_override
= midgard_dest_override_none
,
1093 /* Writemask only valid for non-SSA NIR */
1094 .mask
= expand_writemask((1 << nr_components
) - 1),
1096 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1097 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1100 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1103 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1107 /* Late fixup for emulated instructions */
1109 if (instr
->op
== nir_op_b2f32
) {
1110 /* Presently, our second argument is an inline #0 constant.
1111 * Switch over to an embedded 1.0 constant (that can't fit
1112 * inline, since we're 32-bit, not 16-bit like the inline
1115 ins
.ssa_args
.inline_constant
= false;
1116 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1117 ins
.has_constants
= true;
1118 ins
.constants
[0] = 1.0;
1121 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1122 /* To avoid duplicating the lookup tables (probably), true LUT
1123 * instructions can only operate as if they were scalars. Lower
1124 * them here by changing the component. */
1126 uint8_t original_swizzle
[4];
1127 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1129 for (int i
= 0; i
< nr_components
; ++i
) {
1130 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1132 for (int j
= 0; j
< 4; ++j
)
1133 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1135 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1136 emit_mir_instruction(ctx
, ins
);
1139 emit_mir_instruction(ctx
, ins
);
1146 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1148 nir_const_value
*const_offset
;
1149 unsigned offset
, reg
;
1151 switch (instr
->intrinsic
) {
1152 case nir_intrinsic_discard_if
:
1153 emit_condition(ctx
, &instr
->src
[0], true);
1157 case nir_intrinsic_discard
: {
1158 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1159 struct midgard_instruction discard
= v_branch(conditional
, false);
1160 discard
.branch
.target_type
= TARGET_DISCARD
;
1161 emit_mir_instruction(ctx
, discard
);
1163 ctx
->can_discard
= true;
1167 case nir_intrinsic_load_uniform
:
1168 case nir_intrinsic_load_input
:
1169 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1170 assert (const_offset
&& "no indirect inputs");
1172 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1174 reg
= nir_dest_index(ctx
, &instr
->dest
);
1176 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1177 /* TODO: half-floats */
1179 int uniform_offset
= 0;
1181 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1182 /* XXX: Resolve which uniform */
1185 /* Offset away from the special
1188 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1192 printf("WARNING: Unknown uniform %d\n", offset
);
1196 uniform_offset
= (uintptr_t) (entry
) - 1;
1197 uniform_offset
+= ctx
->special_uniforms
;
1200 if (uniform_offset
< ctx
->uniform_cutoff
) {
1201 /* Fast path: For the first 16 uniform,
1202 * accesses are 0-cycle, since they're
1203 * just a register fetch in the usual
1204 * case. So, we alias the registers
1205 * while we're still in SSA-space */
1207 int reg_slot
= 23 - uniform_offset
;
1208 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1210 /* Otherwise, read from the 'special'
1211 * UBO to access higher-indexed
1212 * uniforms, at a performance cost */
1214 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1216 /* TODO: Don't split */
1217 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1218 ins
.load_store
.address
= uniform_offset
>> 3;
1220 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1221 emit_mir_instruction(ctx
, ins
);
1223 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1224 /* XXX: Half-floats? */
1225 /* TODO: swizzle, mask */
1227 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1229 midgard_varying_parameter p
= {
1231 .interpolation
= midgard_interp_default
,
1232 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1236 memcpy(&u
, &p
, sizeof(p
));
1237 ins
.load_store
.varying_parameters
= u
;
1239 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1240 emit_mir_instruction(ctx
, ins
);
1241 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1242 /* Constant encoded as a pinned constant */
1244 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1245 ins
.has_constants
= true;
1246 ins
.has_blend_constant
= true;
1247 emit_mir_instruction(ctx
, ins
);
1248 } else if (ctx
->is_blend
) {
1249 /* For blend shaders, a load might be
1250 * translated various ways depending on what
1251 * we're loading. Figure out how this is used */
1253 nir_variable
*out
= NULL
;
1255 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1256 int drvloc
= var
->data
.driver_location
;
1258 if (nir_intrinsic_base(instr
) == drvloc
) {
1266 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1267 /* Source color preloaded to r0 */
1269 midgard_pin_output(ctx
, reg
, 0);
1270 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1271 /* Destination color must be read from framebuffer */
1273 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1274 ins
.load_store
.swizzle
= 0; /* xxxx */
1276 /* Read each component sequentially */
1278 for (int c
= 0; c
< 4; ++c
) {
1279 ins
.load_store
.mask
= (1 << c
);
1280 ins
.load_store
.unknown
= c
;
1281 emit_mir_instruction(ctx
, ins
);
1284 /* vadd.u2f hr2, abs(hr2), #0 */
1286 midgard_vector_alu_src alu_src
= blank_alu_src
;
1288 alu_src
.half
= true;
1290 midgard_instruction u2f
= {
1294 .src1
= SSA_UNUSED_0
,
1296 .inline_constant
= true
1299 .op
= midgard_alu_op_u2f
,
1300 .reg_mode
= midgard_reg_mode_half
,
1301 .dest_override
= midgard_dest_override_none
,
1303 .src1
= vector_alu_srco_unsigned(alu_src
),
1304 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1308 emit_mir_instruction(ctx
, u2f
);
1310 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1312 alu_src
.abs
= false;
1314 midgard_instruction fmul
= {
1316 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1320 .src1
= SSA_UNUSED_0
,
1321 .inline_constant
= true
1324 .op
= midgard_alu_op_fmul
,
1325 .reg_mode
= midgard_reg_mode_full
,
1326 .dest_override
= midgard_dest_override_none
,
1327 .outmod
= midgard_outmod_sat
,
1329 .src1
= vector_alu_srco_unsigned(alu_src
),
1330 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1334 emit_mir_instruction(ctx
, fmul
);
1336 printf("Unknown input in blend shader\n");
1339 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1340 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1341 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1342 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1343 emit_mir_instruction(ctx
, ins
);
1345 printf("Unknown load\n");
1351 case nir_intrinsic_store_output
:
1352 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1353 assert(const_offset
&& "no indirect outputs");
1355 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1357 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1359 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1360 /* gl_FragColor is not emitted with load/store
1361 * instructions. Instead, it gets plonked into
1362 * r0 at the end of the shader and we do the
1363 * framebuffer writeout dance. TODO: Defer
1366 midgard_pin_output(ctx
, reg
, 0);
1368 /* Save the index we're writing to for later reference
1369 * in the epilogue */
1371 ctx
->fragment_output
= reg
;
1372 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1373 /* Varyings are written into one of two special
1374 * varying register, r26 or r27. The register itself is selected as the register
1375 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1377 * Normally emitting fmov's is frowned upon,
1378 * but due to unique constraints of
1379 * REGISTER_VARYING, fmov emission + a
1380 * dedicated cleanup pass is the only way to
1381 * guarantee correctness when considering some
1382 * (common) edge cases XXX: FIXME */
1384 /* Look up how it was actually laid out */
1386 void *entry
= _mesa_hash_table_u64_search(ctx
->varying_nir_to_mdg
, offset
+ 1);
1389 printf("WARNING: skipping varying\n");
1393 offset
= (uintptr_t) (entry
) - 1;
1395 /* If this varying corresponds to a constant (why?!),
1396 * emit that now since it won't get picked up by
1397 * hoisting (since there is no corresponding move
1398 * emitted otherwise) */
1400 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1402 if (constant_value
) {
1403 /* Special case: emit the varying write
1404 * directly to r26 (looks funny in asm but it's
1405 * fine) and emit the store _now_. Possibly
1406 * slightly slower, but this is a really stupid
1407 * special case anyway (why on earth would you
1408 * have a constant varying? Your own fault for
1409 * slightly worse perf :P) */
1411 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1412 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1413 emit_mir_instruction(ctx
, ins
);
1415 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1416 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1417 emit_mir_instruction(ctx
, st
);
1419 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1421 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1424 printf("Unknown store\n");
1430 case nir_intrinsic_load_alpha_ref_float
:
1431 assert(instr
->dest
.is_ssa
);
1433 float ref_value
= ctx
->alpha_ref
;
1435 float *v
= ralloc_array(NULL
, float, 4);
1436 memcpy(v
, &ref_value
, sizeof(float));
1437 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1442 printf ("Unhandled intrinsic\n");
1449 midgard_tex_format(enum glsl_sampler_dim dim
)
1452 case GLSL_SAMPLER_DIM_2D
:
1453 case GLSL_SAMPLER_DIM_EXTERNAL
:
1456 case GLSL_SAMPLER_DIM_3D
:
1459 case GLSL_SAMPLER_DIM_CUBE
:
1460 return TEXTURE_CUBE
;
1463 printf("Unknown sampler dim type\n");
1470 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1473 //assert (!instr->sampler);
1474 //assert (!instr->texture_array_size);
1475 assert (instr
->op
== nir_texop_tex
);
1477 /* Allocate registers via a round robin scheme to alternate between the two registers */
1478 int reg
= ctx
->texture_op_count
& 1;
1479 int in_reg
= reg
, out_reg
= reg
;
1481 /* Make room for the reg */
1483 if (ctx
->texture_index
[reg
] > -1)
1484 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1486 int texture_index
= instr
->texture_index
;
1487 int sampler_index
= texture_index
;
1489 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1490 switch (instr
->src
[i
].src_type
) {
1491 case nir_tex_src_coord
: {
1492 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1494 midgard_vector_alu_src alu_src
= blank_alu_src
;
1495 alu_src
.swizzle
= (COMPONENT_Y
<< 2);
1497 midgard_instruction ins
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
));
1498 emit_mir_instruction(ctx
, ins
);
1500 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1506 printf("Unknown source type\n");
1513 /* No helper to build texture words -- we do it all here */
1514 midgard_instruction ins
= {
1515 .type
= TAG_TEXTURE_4
,
1517 .op
= TEXTURE_OP_NORMAL
,
1518 .format
= midgard_tex_format(instr
->sampler_dim
),
1519 .texture_handle
= texture_index
,
1520 .sampler_handle
= sampler_index
,
1522 /* TODO: Don't force xyzw */
1523 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1535 /* Assume we can continue; hint it out later */
1540 /* Set registers to read and write from the same place */
1541 ins
.texture
.in_reg_select
= in_reg
;
1542 ins
.texture
.out_reg_select
= out_reg
;
1544 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1545 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1546 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1547 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1548 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1550 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1551 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1552 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1555 emit_mir_instruction(ctx
, ins
);
1557 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1559 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1560 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1561 ctx
->texture_index
[reg
] = o_index
;
1563 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1564 emit_mir_instruction(ctx
, ins2
);
1566 /* Used for .cont and .last hinting */
1567 ctx
->texture_op_count
++;
1571 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1573 switch (instr
->type
) {
1574 case nir_jump_break
: {
1575 /* Emit a branch out of the loop */
1576 struct midgard_instruction br
= v_branch(false, false);
1577 br
.branch
.target_type
= TARGET_BREAK
;
1578 br
.branch
.target_break
= ctx
->current_loop
;
1579 emit_mir_instruction(ctx
, br
);
1581 printf("break..\n");
1586 printf("Unknown jump type %d\n", instr
->type
);
1592 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1594 switch (instr
->type
) {
1595 case nir_instr_type_load_const
:
1596 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1599 case nir_instr_type_intrinsic
:
1600 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1603 case nir_instr_type_alu
:
1604 emit_alu(ctx
, nir_instr_as_alu(instr
));
1607 case nir_instr_type_tex
:
1608 emit_tex(ctx
, nir_instr_as_tex(instr
));
1611 case nir_instr_type_jump
:
1612 emit_jump(ctx
, nir_instr_as_jump(instr
));
1615 case nir_instr_type_ssa_undef
:
1620 printf("Unhandled instruction type\n");
1625 /* Determine the actual hardware from the index based on the RA results or special values */
1628 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1630 if (reg
>= SSA_FIXED_MINIMUM
)
1631 return SSA_REG_FROM_FIXED(reg
);
1634 assert(reg
< maxreg
);
1635 int r
= ra_get_node_reg(g
, reg
);
1636 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1641 /* fmov style unused */
1643 return REGISTER_UNUSED
;
1645 /* lut style unused */
1647 return REGISTER_UNUSED
;
1650 printf("Unknown SSA register alias %d\n", reg
);
1657 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1659 /* Choose the first available register to minimise reported register pressure */
1661 for (int i
= 0; i
< 16; ++i
) {
1662 if (BITSET_TEST(regs
, i
)) {
1672 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1674 if (ins
->ssa_args
.src0
== src
) return true;
1675 if (ins
->ssa_args
.src1
== src
) return true;
1681 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1683 /* Check the rest of the block for liveness */
1684 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1685 if (midgard_is_live_in_instr(ins
, src
))
1689 /* Check the rest of the blocks for liveness */
1690 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1691 mir_foreach_instr_in_block(b
, ins
) {
1692 if (midgard_is_live_in_instr(ins
, src
))
1697 /* TODO: How does control flow interact in complex shaders? */
1703 allocate_registers(compiler_context
*ctx
)
1705 /* First, initialize the RA */
1706 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1708 /* Create a primary (general purpose) class, as well as special purpose
1709 * pipeline register classes */
1711 int primary_class
= ra_alloc_reg_class(regs
);
1712 int varying_class
= ra_alloc_reg_class(regs
);
1714 /* Add the full set of work registers */
1715 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1716 for (int i
= 0; i
< work_count
; ++i
)
1717 ra_class_add_reg(regs
, primary_class
, i
);
1719 /* Add special registers */
1720 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1721 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1723 /* We're done setting up */
1724 ra_set_finalize(regs
, NULL
);
1726 /* Transform the MIR into squeezed index form */
1727 mir_foreach_block(ctx
, block
) {
1728 mir_foreach_instr_in_block(block
, ins
) {
1729 if (ins
->compact_branch
) continue;
1731 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1732 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1733 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1736 print_mir_block(block
);
1739 /* Let's actually do register allocation */
1740 int nodes
= ctx
->temp_count
;
1741 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1743 /* Set everything to the work register class, unless it has somewhere
1746 mir_foreach_block(ctx
, block
) {
1747 mir_foreach_instr_in_block(block
, ins
) {
1748 if (ins
->compact_branch
) continue;
1750 if (ins
->ssa_args
.dest
< 0) continue;
1752 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1754 int class = primary_class
;
1756 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1760 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1761 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1764 unsigned reg
= temp
- 1;
1765 int t
= find_or_allocate_temp(ctx
, index
);
1766 ra_set_node_reg(g
, t
, reg
);
1770 /* Determine liveness */
1772 int *live_start
= malloc(nodes
* sizeof(int));
1773 int *live_end
= malloc(nodes
* sizeof(int));
1775 /* Initialize as non-existent */
1777 for (int i
= 0; i
< nodes
; ++i
) {
1778 live_start
[i
] = live_end
[i
] = -1;
1783 mir_foreach_block(ctx
, block
) {
1784 mir_foreach_instr_in_block(block
, ins
) {
1785 if (ins
->compact_branch
) continue;
1787 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1788 /* If this destination is not yet live, it is now since we just wrote it */
1790 int dest
= ins
->ssa_args
.dest
;
1792 if (live_start
[dest
] == -1)
1793 live_start
[dest
] = d
;
1796 /* Since we just used a source, the source might be
1797 * dead now. Scan the rest of the block for
1798 * invocations, and if there are none, the source dies
1801 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1803 for (int src
= 0; src
< 2; ++src
) {
1804 int s
= sources
[src
];
1806 if (s
< 0) continue;
1808 if (s
>= SSA_FIXED_MINIMUM
) continue;
1810 if (!is_live_after(ctx
, block
, ins
, s
)) {
1819 /* If a node still hasn't been killed, kill it now */
1821 for (int i
= 0; i
< nodes
; ++i
) {
1822 /* live_start == -1 most likely indicates a pinned output */
1824 if (live_end
[i
] == -1)
1828 /* Setup interference between nodes that are live at the same time */
1830 for (int i
= 0; i
< nodes
; ++i
) {
1831 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1832 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1833 ra_add_node_interference(g
, i
, j
);
1837 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1839 if (!ra_allocate(g
)) {
1840 printf("Error allocating registers\n");
1848 mir_foreach_block(ctx
, block
) {
1849 mir_foreach_instr_in_block(block
, ins
) {
1850 if (ins
->compact_branch
) continue;
1852 ssa_args args
= ins
->ssa_args
;
1854 switch (ins
->type
) {
1856 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1858 ins
->registers
.src2_imm
= args
.inline_constant
;
1860 if (args
.inline_constant
) {
1861 /* Encode inline 16-bit constant as a vector by default */
1863 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1865 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1867 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1868 ins
->alu
.src2
= imm
<< 2;
1870 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1873 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1877 case TAG_LOAD_STORE_4
: {
1878 if (OP_IS_STORE(ins
->load_store
.op
)) {
1879 /* TODO: use ssa_args for store_vary */
1880 ins
->load_store
.reg
= 0;
1882 bool has_dest
= args
.dest
>= 0;
1883 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1885 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1898 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1899 * use scalar ALU instructions, for functional or performance reasons. To do
1900 * this, we just demote vector ALU payloads to scalar. */
1903 component_from_mask(unsigned mask
)
1905 for (int c
= 0; c
< 4; ++c
) {
1906 if (mask
& (3 << (2 * c
)))
1915 is_single_component_mask(unsigned mask
)
1919 for (int c
= 0; c
< 4; ++c
)
1920 if (mask
& (3 << (2 * c
)))
1923 return components
== 1;
1926 /* Create a mask of accessed components from a swizzle to figure out vector
1930 swizzle_to_access_mask(unsigned swizzle
)
1932 unsigned component_mask
= 0;
1934 for (int i
= 0; i
< 4; ++i
) {
1935 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1936 component_mask
|= (1 << c
);
1939 return component_mask
;
1943 vector_to_scalar_source(unsigned u
)
1945 midgard_vector_alu_src v
;
1946 memcpy(&v
, &u
, sizeof(v
));
1948 midgard_scalar_alu_src s
= {
1952 .component
= (v
.swizzle
& 3) << 1
1956 memcpy(&o
, &s
, sizeof(s
));
1958 return o
& ((1 << 6) - 1);
1961 static midgard_scalar_alu
1962 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1964 /* The output component is from the mask */
1965 midgard_scalar_alu s
= {
1967 .src1
= vector_to_scalar_source(v
.src1
),
1968 .src2
= vector_to_scalar_source(v
.src2
),
1971 .output_full
= 1, /* TODO: Half */
1972 .output_component
= component_from_mask(v
.mask
) << 1,
1975 /* Inline constant is passed along rather than trying to extract it
1978 if (ins
->ssa_args
.inline_constant
) {
1980 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1981 imm
|= (lower_11
>> 9) & 3;
1982 imm
|= (lower_11
>> 6) & 4;
1983 imm
|= (lower_11
>> 2) & 0x38;
1984 imm
|= (lower_11
& 63) << 6;
1992 /* Midgard prefetches instruction types, so during emission we need to
1993 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1994 * if this is the second to last and the last is an ALU, then it's also 1... */
1996 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1997 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1999 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2000 bytes_emitted += sizeof(type)
2003 emit_binary_vector_instruction(midgard_instruction
*ains
,
2004 uint16_t *register_words
, int *register_words_count
,
2005 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2006 size_t *bytes_emitted
)
2008 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2009 *bytes_emitted
+= sizeof(midgard_reg_info
);
2011 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2012 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2013 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2016 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2017 * mind that we are a vector architecture and we can write to different
2018 * components simultaneously */
2021 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2023 /* Each instruction reads some registers and writes to a register. See
2024 * where the first writes */
2026 /* Figure out where exactly we wrote to */
2027 int source
= first
->ssa_args
.dest
;
2028 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2030 /* As long as the second doesn't read from the first, we're okay */
2031 if (second
->ssa_args
.src0
== source
) {
2032 if (first
->type
== TAG_ALU_4
) {
2033 /* Figure out which components we just read from */
2035 int q
= second
->alu
.src1
;
2036 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2038 /* Check if there are components in common, and fail if so */
2039 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2046 if (second
->ssa_args
.src1
== source
)
2049 /* Otherwise, it's safe in that regard. Another data hazard is both
2050 * writing to the same place, of course */
2052 if (second
->ssa_args
.dest
== source
) {
2053 /* ...but only if the components overlap */
2054 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2056 if (dest_mask
& source_mask
)
2064 /* Schedules, but does not emit, a single basic block. After scheduling, the
2065 * final tag and size of the block are known, which are necessary for branching
2068 static midgard_bundle
2069 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2071 int instructions_emitted
= 0, instructions_consumed
= -1;
2072 midgard_bundle bundle
= { 0 };
2074 uint8_t tag
= ins
->type
;
2076 /* Default to the instruction's tag */
2079 switch (ins
->type
) {
2081 uint32_t control
= 0;
2082 size_t bytes_emitted
= sizeof(control
);
2084 /* TODO: Constant combining */
2085 int index
= 0, last_unit
= 0;
2087 /* Previous instructions, for the purpose of parallelism */
2088 midgard_instruction
*segment
[4] = {0};
2089 int segment_size
= 0;
2091 instructions_emitted
= -1;
2092 midgard_instruction
*pins
= ins
;
2095 midgard_instruction
*ains
= pins
;
2097 /* Advance instruction pointer */
2099 ains
= mir_next_op(pins
);
2103 /* Out-of-work condition */
2104 if ((struct list_head
*) ains
== &block
->instructions
)
2107 /* Ensure that the chain can continue */
2108 if (ains
->type
!= TAG_ALU_4
) break;
2110 /* According to the presentation "The ARM
2111 * Mali-T880 Mobile GPU" from HotChips 27,
2112 * there are two pipeline stages. Branching
2113 * position determined experimentally. Lines
2114 * are executed in parallel:
2117 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2119 * Verify that there are no ordering dependencies here.
2121 * TODO: Allow for parallelism!!!
2124 /* Pick a unit for it if it doesn't force a particular unit */
2126 int unit
= ains
->unit
;
2129 int op
= ains
->alu
.op
;
2130 int units
= alu_opcode_props
[op
];
2132 /* TODO: Promotion of scalars to vectors */
2133 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2136 assert(units
& UNITS_SCALAR
);
2139 if (last_unit
>= UNIT_VADD
) {
2140 if (units
& UNIT_VLUT
)
2145 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2147 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2149 else if (units
& UNIT_VLUT
)
2155 if (last_unit
>= UNIT_VADD
) {
2156 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2158 else if (units
& UNIT_VLUT
)
2163 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
))
2165 else if (units
& UNIT_SMUL
)
2167 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2174 assert(unit
& units
);
2177 /* Late unit check, this time for encoding (not parallelism) */
2178 if (unit
<= last_unit
) break;
2180 /* Clear the segment */
2181 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2184 /* Check for data hazards */
2185 int has_hazard
= false;
2187 for (int s
= 0; s
< segment_size
; ++s
)
2188 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2194 /* We're good to go -- emit the instruction */
2197 segment
[segment_size
++] = ains
;
2199 /* Only one set of embedded constants per
2200 * bundle possible; if we have more, we must
2201 * break the chain early, unfortunately */
2203 if (ains
->has_constants
) {
2204 if (bundle
.has_embedded_constants
) {
2205 /* ...but if there are already
2206 * constants but these are the
2207 * *same* constants, we let it
2210 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2213 bundle
.has_embedded_constants
= true;
2214 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2216 /* If this is a blend shader special constant, track it for patching */
2217 if (ains
->has_blend_constant
)
2218 bundle
.has_blend_constant
= true;
2222 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2223 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2224 &bundle
.register_words_count
, bundle
.body_words
,
2225 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2226 } else if (ains
->compact_branch
) {
2227 /* All of r0 has to be written out
2228 * along with the branch writeout.
2231 if (ains
->writeout
) {
2233 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2234 ins
.unit
= UNIT_VMUL
;
2236 control
|= ins
.unit
;
2238 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2239 &bundle
.register_words_count
, bundle
.body_words
,
2240 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2242 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2243 bool written_late
= false;
2244 bool components
[4] = { 0 };
2245 uint16_t register_dep_mask
= 0;
2246 uint16_t written_mask
= 0;
2248 midgard_instruction
*qins
= ins
;
2249 for (int t
= 0; t
< index
; ++t
) {
2250 if (qins
->registers
.out_reg
!= 0) {
2251 /* Mark down writes */
2253 written_mask
|= (1 << qins
->registers
.out_reg
);
2255 /* Mark down the register dependencies for errata check */
2257 if (qins
->registers
.src1_reg
< 16)
2258 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2260 if (qins
->registers
.src2_reg
< 16)
2261 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2263 int mask
= qins
->alu
.mask
;
2265 for (int c
= 0; c
< 4; ++c
)
2266 if (mask
& (0x3 << (2 * c
)))
2267 components
[c
] = true;
2269 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2271 if (qins
->unit
== UNIT_VLUT
)
2272 written_late
= true;
2275 /* Advance instruction pointer */
2276 qins
= mir_next_op(qins
);
2280 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2281 if (register_dep_mask
& written_mask
) {
2282 printf("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2289 /* If even a single component is not written, break it up (conservative check). */
2290 bool breakup
= false;
2292 for (int c
= 0; c
< 4; ++c
)
2299 /* Otherwise, we're free to proceed */
2303 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2304 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2305 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2306 bytes_emitted
+= sizeof(midgard_branch_extended
);
2308 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2309 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2310 bytes_emitted
+= sizeof(ains
->br_compact
);
2313 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2314 bytes_emitted
+= sizeof(midgard_reg_info
);
2316 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2317 bundle
.body_words_count
++;
2318 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2321 /* Defer marking until after writing to allow for break */
2322 control
|= ains
->unit
;
2323 last_unit
= ains
->unit
;
2324 ++instructions_emitted
;
2328 /* Bubble up the number of instructions for skipping */
2329 instructions_consumed
= index
- 1;
2333 /* Pad ALU op to nearest word */
2335 if (bytes_emitted
& 15) {
2336 padding
= 16 - (bytes_emitted
& 15);
2337 bytes_emitted
+= padding
;
2340 /* Constants must always be quadwords */
2341 if (bundle
.has_embedded_constants
)
2342 bytes_emitted
+= 16;
2344 /* Size ALU instruction for tag */
2345 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2346 bundle
.padding
= padding
;
2347 bundle
.control
= bundle
.tag
| control
;
2352 case TAG_LOAD_STORE_4
: {
2353 /* Load store instructions have two words at once. If
2354 * we only have one queued up, we need to NOP pad.
2355 * Otherwise, we store both in succession to save space
2356 * and cycles -- letting them go in parallel -- skip
2357 * the next. The usefulness of this optimisation is
2358 * greatly dependent on the quality of the instruction
2362 midgard_instruction
*next_op
= mir_next_op(ins
);
2364 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2365 /* As the two operate concurrently, make sure
2366 * they are not dependent */
2368 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2369 /* Skip ahead, since it's redundant with the pair */
2370 instructions_consumed
= 1 + (instructions_emitted
++);
2378 /* Texture ops default to single-op-per-bundle scheduling */
2382 /* Copy the instructions into the bundle */
2383 bundle
.instruction_count
= instructions_emitted
+ 1;
2387 midgard_instruction
*uins
= ins
;
2388 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2389 bundle
.instructions
[used_idx
++] = *uins
;
2390 uins
= mir_next_op(uins
);
2393 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2399 quadword_size(int tag
)
2414 case TAG_LOAD_STORE_4
:
2426 /* Schedule a single block by iterating its instruction to create bundles.
2427 * While we go, tally about the bundle sizes to compute the block size. */
2430 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2432 util_dynarray_init(&block
->bundles
, NULL
);
2434 block
->quadword_count
= 0;
2436 mir_foreach_instr_in_block(block
, ins
) {
2438 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2439 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2441 if (bundle
.has_blend_constant
) {
2442 /* TODO: Multiblock? */
2443 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2444 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2448 ins
= mir_next_op(ins
);
2450 block
->quadword_count
+= quadword_size(bundle
.tag
);
2453 block
->is_scheduled
= true;
2457 schedule_program(compiler_context
*ctx
)
2459 allocate_registers(ctx
);
2461 mir_foreach_block(ctx
, block
) {
2462 schedule_block(ctx
, block
);
2466 /* After everything is scheduled, emit whole bundles at a time */
2469 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2471 int lookahead
= next_tag
<< 4;
2473 switch (bundle
->tag
) {
2478 /* Actually emit each component */
2479 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2481 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2482 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2484 /* Emit body words based on the instructions bundled */
2485 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2486 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2488 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2489 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2490 } else if (ins
->compact_branch
) {
2491 /* Dummy move, XXX DRY */
2492 if ((i
== 0) && ins
->writeout
) {
2493 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2494 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2497 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2498 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2500 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2504 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2505 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2509 /* Emit padding (all zero) */
2510 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2512 /* Tack on constants */
2514 if (bundle
->has_embedded_constants
) {
2515 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2516 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2517 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2518 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2524 case TAG_LOAD_STORE_4
: {
2525 /* One or two composing instructions */
2527 uint64_t current64
, next64
= LDST_NOP
;
2529 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2531 if (bundle
->instruction_count
== 2)
2532 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2534 midgard_load_store instruction
= {
2535 .type
= bundle
->tag
,
2536 .next_type
= next_tag
,
2541 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2546 case TAG_TEXTURE_4
: {
2547 /* Texture instructions are easy, since there is no
2548 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2550 midgard_instruction
*ins
= &bundle
->instructions
[0];
2552 ins
->texture
.type
= TAG_TEXTURE_4
;
2553 ins
->texture
.next_type
= next_tag
;
2555 ctx
->texture_op_count
--;
2557 if (!ctx
->texture_op_count
) {
2558 ins
->texture
.cont
= 0;
2559 ins
->texture
.last
= 1;
2562 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2567 printf("Unknown midgard instruction type\n");
2574 /* ALU instructions can inline or embed constants, which decreases register
2575 * pressure and saves space. */
2577 #define CONDITIONAL_ATTACH(src) { \
2578 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2581 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2582 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2587 inline_alu_constants(compiler_context
*ctx
)
2589 mir_foreach_instr(ctx
, alu
) {
2590 /* Other instructions cannot inline constants */
2591 if (alu
->type
!= TAG_ALU_4
) continue;
2593 /* If there is already a constant here, we can do nothing */
2594 if (alu
->has_constants
) continue;
2596 CONDITIONAL_ATTACH(src0
);
2598 if (!alu
->has_constants
) {
2599 CONDITIONAL_ATTACH(src1
)
2600 } else if (!alu
->inline_constant
) {
2601 /* Corner case: _two_ vec4 constants, for instance with a
2602 * csel. For this case, we can only use a constant
2603 * register for one, we'll have to emit a move for the
2604 * other. Note, if both arguments are constants, then
2605 * necessarily neither argument depends on the value of
2606 * any particular register. As the destination register
2607 * will be wiped, that means we can spill the constant
2608 * to the destination register.
2611 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2612 unsigned scratch
= alu
->ssa_args
.dest
;
2615 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2616 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2618 /* Force a break XXX Defer r31 writes */
2619 ins
.unit
= UNIT_VLUT
;
2621 /* Set the source */
2622 alu
->ssa_args
.src1
= scratch
;
2624 /* Inject us -before- the last instruction which set r31 */
2625 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2631 /* Midgard supports two types of constants, embedded constants (128-bit) and
2632 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2633 * constants can be demoted to inline constants, for space savings and
2634 * sometimes a performance boost */
2637 embedded_to_inline_constant(compiler_context
*ctx
)
2639 mir_foreach_instr(ctx
, ins
) {
2640 if (!ins
->has_constants
) continue;
2642 if (ins
->ssa_args
.inline_constant
) continue;
2644 /* Blend constants must not be inlined by definition */
2645 if (ins
->has_blend_constant
) continue;
2647 /* src1 cannot be an inline constant due to encoding
2648 * restrictions. So, if possible we try to flip the arguments
2651 int op
= ins
->alu
.op
;
2653 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2654 /* Flip based on op. Fallthrough intentional */
2657 /* These ops require an operational change to flip their arguments TODO */
2658 case midgard_alu_op_flt
:
2659 case midgard_alu_op_fle
:
2660 case midgard_alu_op_ilt
:
2661 case midgard_alu_op_ile
:
2662 case midgard_alu_op_fcsel
:
2663 case midgard_alu_op_icsel
:
2664 case midgard_alu_op_isub
:
2665 printf("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2668 /* These ops are commutative and Just Flip */
2669 case midgard_alu_op_fne
:
2670 case midgard_alu_op_fadd
:
2671 case midgard_alu_op_fmul
:
2672 case midgard_alu_op_fmin
:
2673 case midgard_alu_op_fmax
:
2674 case midgard_alu_op_iadd
:
2675 case midgard_alu_op_imul
:
2676 case midgard_alu_op_feq
:
2677 case midgard_alu_op_ieq
:
2678 case midgard_alu_op_ine
:
2679 case midgard_alu_op_iand
:
2680 case midgard_alu_op_ior
:
2681 case midgard_alu_op_ixor
:
2682 /* Flip the SSA numbers */
2683 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2684 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2686 /* And flip the modifiers */
2690 src_temp
= ins
->alu
.src2
;
2691 ins
->alu
.src2
= ins
->alu
.src1
;
2692 ins
->alu
.src1
= src_temp
;
2699 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2700 /* Extract the source information */
2702 midgard_vector_alu_src
*src
;
2703 int q
= ins
->alu
.src2
;
2704 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2707 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2708 int component
= src
->swizzle
& 3;
2710 /* Scale constant appropriately, if we can legally */
2711 uint16_t scaled_constant
= 0;
2713 /* XXX: Check legality */
2714 if (midgard_is_integer_op(op
)) {
2715 /* TODO: Inline integer */
2718 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2719 scaled_constant
= (uint16_t) iconstants
[component
];
2721 /* Constant overflow after resize */
2722 if (scaled_constant
!= iconstants
[component
])
2725 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2728 /* We don't know how to handle these with a constant */
2730 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2731 printf("Bailing inline constant...\n");
2735 /* Make sure that the constant is not itself a
2736 * vector by checking if all accessed values
2737 * (by the swizzle) are the same. */
2739 uint32_t *cons
= (uint32_t *) ins
->constants
;
2740 uint32_t value
= cons
[component
];
2742 bool is_vector
= false;
2743 unsigned mask
= effective_writemask(&ins
->alu
);
2745 for (int c
= 1; c
< 4; ++c
) {
2746 /* We only care if this component is actually used */
2747 if (!(mask
& (1 << c
)))
2750 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2752 if (test
!= value
) {
2761 /* Get rid of the embedded constant */
2762 ins
->has_constants
= false;
2763 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2764 ins
->ssa_args
.inline_constant
= true;
2765 ins
->inline_constant
= scaled_constant
;
2770 /* Map normal SSA sources to other SSA sources / fixed registers (like
2774 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2776 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2779 /* Remove entry in leftovers to avoid a redunant fmov */
2781 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2784 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2786 /* Assign the alias map */
2792 #define AS_SRC(to, u) \
2793 int q##to = ins->alu.src2; \
2794 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2796 /* Removing unused moves is necessary to clean up the texture pipeline results.
2798 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2801 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2803 mir_foreach_instr_in_block_safe(block
, ins
) {
2804 if (ins
->type
!= TAG_ALU_4
) continue;
2806 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2808 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2810 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2812 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2814 mir_remove_instruction(ins
);
2818 /* The following passes reorder MIR instructions to enable better scheduling */
2821 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2823 mir_foreach_instr_in_block_safe(block
, ins
) {
2824 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2826 /* We've found a load/store op. Check if next is also load/store. */
2827 midgard_instruction
*next_op
= mir_next_op(ins
);
2828 if (&next_op
->link
!= &block
->instructions
) {
2829 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2830 /* If so, we're done since we're a pair */
2831 ins
= mir_next_op(ins
);
2835 /* Maximum search distance to pair, to avoid register pressure disasters */
2836 int search_distance
= 8;
2838 /* Otherwise, we have an orphaned load/store -- search for another load */
2839 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2840 /* Terminate search if necessary */
2841 if (!(search_distance
--)) break;
2843 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2845 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2847 /* We found one! Move it up to pair and remove it from the old location */
2849 mir_insert_instruction_before(ins
, *c
);
2850 mir_remove_instruction(c
);
2858 /* Emit varying stores late */
2861 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2862 /* Iterate in reverse to get the final write, rather than the first */
2864 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2865 /* Check if what we just wrote needs a store */
2866 int idx
= ins
->ssa_args
.dest
;
2867 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2869 if (!varying
) continue;
2873 /* We need to store to the appropriate varying, so emit the
2876 /* TODO: Integrate with special purpose RA (and scheduler?) */
2877 bool high_varying_register
= false;
2879 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2881 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2882 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2884 mir_insert_instruction_before(mir_next_op(ins
), st
);
2885 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2887 /* We no longer need to store this varying */
2888 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2892 /* If there are leftovers after the below pass, emit actual fmov
2893 * instructions for the slow-but-correct path */
2896 emit_leftover_move(compiler_context
*ctx
)
2898 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2899 int base
= ((uintptr_t) leftover
->key
) - 1;
2902 map_ssa_to_alias(ctx
, &mapped
);
2903 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2908 actualise_ssa_to_alias(compiler_context
*ctx
)
2910 mir_foreach_instr(ctx
, ins
) {
2911 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2912 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2915 emit_leftover_move(ctx
);
2918 /* Vertex shaders do not write gl_Position as is; instead, they write a
2919 * transformed screen space position as a varying. See section 12.5 "Coordinate
2920 * Transformation" of the ES 3.2 full specification for details.
2922 * This transformation occurs early on, as NIR and prior to optimisation, in
2923 * order to take advantage of NIR optimisation passes of the transform itself.
2927 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
2929 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
2931 /* Get viewport from the uniforms */
2932 nir_intrinsic_instr
*load
;
2933 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
2934 load
->num_components
= 4;
2935 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
2936 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
2937 nir_builder_instr_insert(b
, &load
->instr
);
2939 /* Formatted as <width, height, centerx, centery> */
2940 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
2941 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
2942 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
2943 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
2945 /* XXX: From uniforms? */
2946 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
2947 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
2949 /* World space to normalised device coordinates */
2951 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
2952 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
2954 /* Normalised device coordinates to screen space */
2956 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
2957 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
2959 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2960 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2961 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
2963 /* gl_Position will be written out in screenspace xyz, with w set to
2964 * the reciprocal we computed earlier. The transformed w component is
2965 * then used for perspective-correct varying interpolation. The
2966 * transformed w component must preserve its original sign; this is
2967 * used in depth clipping computations */
2969 nir_ssa_def
*screen_space
= nir_vec4(b
,
2970 nir_channel(b
, viewport_xy
, 0),
2971 nir_channel(b
, viewport_xy
, 1),
2975 /* Finally, write out the transformed values to the varying */
2977 nir_intrinsic_instr
*store
;
2978 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
2979 store
->num_components
= 4;
2980 nir_intrinsic_set_base(store
, 0);
2981 nir_intrinsic_set_write_mask(store
, 0xf);
2982 store
->src
[0].ssa
= screen_space
;
2983 store
->src
[0].is_ssa
= true;
2984 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
2985 nir_builder_instr_insert(b
, &store
->instr
);
2989 transform_position_writes(nir_shader
*shader
)
2991 nir_foreach_function(func
, shader
) {
2992 nir_foreach_block(block
, func
->impl
) {
2993 nir_foreach_instr_safe(instr
, block
) {
2994 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
2996 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
2997 nir_variable
*out
= NULL
;
2999 switch (intr
->intrinsic
) {
3000 case nir_intrinsic_store_output
:
3001 /* already had i/o lowered.. lookup the matching output var: */
3002 nir_foreach_variable(var
, &shader
->outputs
) {
3003 int drvloc
= var
->data
.driver_location
;
3005 if (nir_intrinsic_base(intr
) == drvloc
) {
3019 if (out
->data
.mode
!= nir_var_shader_out
)
3022 if (out
->data
.location
!= VARYING_SLOT_POS
)
3026 nir_builder_init(&b
, func
->impl
);
3027 b
.cursor
= nir_before_instr(instr
);
3029 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
3030 nir_instr_remove(instr
);
3037 emit_fragment_epilogue(compiler_context
*ctx
)
3039 /* Special case: writing out constants requires us to include the move
3040 * explicitly now, so shove it into r0 */
3042 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3044 if (constant_value
) {
3045 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3046 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3047 emit_mir_instruction(ctx
, ins
);
3050 /* Perform the actual fragment writeout. We have two writeout/branch
3051 * instructions, forming a loop until writeout is successful as per the
3052 * docs. TODO: gl_FragDepth */
3054 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3055 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3058 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3059 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3060 * with the int8 analogue to the fragment epilogue */
3063 emit_blend_epilogue(compiler_context
*ctx
)
3065 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3067 midgard_instruction scale
= {
3070 .inline_constant
= _mesa_float_to_half(255.0),
3072 .src0
= SSA_FIXED_REGISTER(0),
3073 .src1
= SSA_UNUSED_0
,
3074 .dest
= SSA_FIXED_REGISTER(24),
3075 .inline_constant
= true
3078 .op
= midgard_alu_op_fmul
,
3079 .reg_mode
= midgard_reg_mode_full
,
3080 .dest_override
= midgard_dest_override_lower
,
3082 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3083 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3087 emit_mir_instruction(ctx
, scale
);
3089 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3091 midgard_vector_alu_src alu_src
= blank_alu_src
;
3092 alu_src
.half
= true;
3094 midgard_instruction f2u8
= {
3097 .src0
= SSA_FIXED_REGISTER(24),
3098 .src1
= SSA_UNUSED_0
,
3099 .dest
= SSA_FIXED_REGISTER(0),
3100 .inline_constant
= true
3103 .op
= midgard_alu_op_f2u8
,
3104 .reg_mode
= midgard_reg_mode_half
,
3105 .dest_override
= midgard_dest_override_lower
,
3106 .outmod
= midgard_outmod_pos
,
3108 .src1
= vector_alu_srco_unsigned(alu_src
),
3109 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3113 emit_mir_instruction(ctx
, f2u8
);
3115 /* vmul.imov.quarter r0, r0, r0 */
3117 midgard_instruction imov_8
= {
3120 .src0
= SSA_UNUSED_1
,
3121 .src1
= SSA_FIXED_REGISTER(0),
3122 .dest
= SSA_FIXED_REGISTER(0),
3125 .op
= midgard_alu_op_imov
,
3126 .reg_mode
= midgard_reg_mode_quarter
,
3127 .dest_override
= midgard_dest_override_none
,
3129 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3130 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3134 /* Emit branch epilogue with the 8-bit move as the source */
3136 emit_mir_instruction(ctx
, imov_8
);
3137 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3139 emit_mir_instruction(ctx
, imov_8
);
3140 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3143 static midgard_block
*
3144 emit_block(compiler_context
*ctx
, nir_block
*block
)
3146 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3147 list_addtail(&this_block
->link
, &ctx
->blocks
);
3149 this_block
->is_scheduled
= false;
3152 ctx
->texture_index
[0] = -1;
3153 ctx
->texture_index
[1] = -1;
3155 /* Set up current block */
3156 list_inithead(&this_block
->instructions
);
3157 ctx
->current_block
= this_block
;
3159 nir_foreach_instr(instr
, block
) {
3160 emit_instr(ctx
, instr
);
3161 ++ctx
->instruction_count
;
3164 inline_alu_constants(ctx
);
3165 embedded_to_inline_constant(ctx
);
3167 /* Perform heavylifting for aliasing */
3168 actualise_ssa_to_alias(ctx
);
3170 midgard_emit_store(ctx
, this_block
);
3171 midgard_eliminate_orphan_moves(ctx
, this_block
);
3172 midgard_pair_load_store(ctx
, this_block
);
3174 /* Append fragment shader epilogue (value writeout) */
3175 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3176 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3178 emit_blend_epilogue(ctx
);
3180 emit_fragment_epilogue(ctx
);
3184 /* Fallthrough save */
3185 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3187 if (block
== nir_start_block(ctx
->func
->impl
))
3188 ctx
->initial_block
= this_block
;
3190 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3191 ctx
->final_block
= this_block
;
3193 /* Allow the next control flow to access us retroactively, for
3195 ctx
->current_block
= this_block
;
3197 /* Document the fallthrough chain */
3198 ctx
->previous_source_block
= this_block
;
3203 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3206 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3208 /* Conditional branches expect the condition in r31.w; emit a move for
3209 * that in the _previous_ block (which is the current block). */
3210 emit_condition(ctx
, &nif
->condition
, true);
3212 /* Speculatively emit the branch, but we can't fill it in until later */
3213 EMIT(branch
, true, true);
3214 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3216 /* Emit the two subblocks */
3217 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3219 /* Emit a jump from the end of the then block to the end of the else */
3220 EMIT(branch
, false, false);
3221 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3223 /* Emit second block, and check if it's empty */
3225 int else_idx
= ctx
->block_count
;
3226 int count_in
= ctx
->instruction_count
;
3227 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3228 int after_else_idx
= ctx
->block_count
;
3230 /* Now that we have the subblocks emitted, fix up the branches */
3235 if (ctx
->instruction_count
== count_in
) {
3236 /* The else block is empty, so don't emit an exit jump */
3237 mir_remove_instruction(then_exit
);
3238 then_branch
->branch
.target_block
= after_else_idx
;
3240 then_branch
->branch
.target_block
= else_idx
;
3241 then_exit
->branch
.target_block
= after_else_idx
;
3246 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3248 /* Remember where we are */
3249 midgard_block
*start_block
= ctx
->current_block
;
3251 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3252 * single current_loop variable, maybe we need a stack */
3254 int loop_idx
= ++ctx
->current_loop
;
3256 /* Get index from before the body so we can loop back later */
3257 int start_idx
= ctx
->block_count
;
3259 /* Emit the body itself */
3260 emit_cf_list(ctx
, &nloop
->body
);
3262 /* Branch back to loop back */
3263 struct midgard_instruction br_back
= v_branch(false, false);
3264 br_back
.branch
.target_block
= start_idx
;
3265 emit_mir_instruction(ctx
, br_back
);
3267 /* Find the index of the block about to follow us (note: we don't add
3268 * one; blocks are 0-indexed so we get a fencepost problem) */
3269 int break_block_idx
= ctx
->block_count
;
3271 /* Fix up the break statements we emitted to point to the right place,
3272 * now that we can allocate a block number for them */
3274 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3275 print_mir_block(block
);
3276 mir_foreach_instr_in_block(block
, ins
) {
3277 if (ins
->type
!= TAG_ALU_4
) continue;
3278 if (!ins
->compact_branch
) continue;
3279 if (ins
->prepacked_branch
) continue;
3281 /* We found a branch -- check the type to see if we need to do anything */
3282 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3284 /* It's a break! Check if it's our break */
3285 if (ins
->branch
.target_break
!= loop_idx
) continue;
3287 /* Okay, cool, we're breaking out of this loop.
3288 * Rewrite from a break to a goto */
3290 ins
->branch
.target_type
= TARGET_GOTO
;
3291 ins
->branch
.target_block
= break_block_idx
;
3296 static midgard_block
*
3297 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3299 midgard_block
*start_block
= NULL
;
3301 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3302 switch (node
->type
) {
3303 case nir_cf_node_block
: {
3304 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3307 start_block
= block
;
3312 case nir_cf_node_if
:
3313 emit_if(ctx
, nir_cf_node_as_if(node
));
3316 case nir_cf_node_loop
:
3317 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3320 case nir_cf_node_function
:
3329 /* Due to lookahead, we need to report the first tag executed in the command
3330 * stream and in branch targets. An initial block might be empty, so iterate
3331 * until we find one that 'works' */
3334 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3336 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3338 unsigned first_tag
= 0;
3341 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3343 if (initial_bundle
) {
3344 first_tag
= initial_bundle
->tag
;
3348 /* Initial block is empty, try the next block */
3349 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3350 } while(initial_block
!= NULL
);
3357 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3359 struct util_dynarray
*compiled
= &program
->compiled
;
3361 compiler_context ictx
= {
3363 .stage
= nir
->info
.stage
,
3365 .is_blend
= is_blend
,
3366 .blend_constant_offset
= -1,
3368 .alpha_ref
= program
->alpha_ref
3371 compiler_context
*ctx
= &ictx
;
3373 /* TODO: Decide this at runtime */
3374 ctx
->uniform_cutoff
= 8;
3376 switch (ctx
->stage
) {
3377 case MESA_SHADER_VERTEX
:
3378 ctx
->special_uniforms
= 1;
3382 ctx
->special_uniforms
= 0;
3386 /* Append epilogue uniforms if necessary. The cmdstream depends on
3387 * these being at the -end-; see assign_var_locations. */
3389 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3390 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3393 /* Assign var locations early, so the epilogue can use them if necessary */
3395 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3396 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3397 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3399 /* Initialize at a global (not block) level hash tables */
3401 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3402 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3403 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3404 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3405 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3406 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3408 /* Assign actual uniform location, skipping over samplers */
3410 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3412 nir_foreach_variable(var
, &nir
->uniforms
) {
3413 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3415 unsigned length
= glsl_get_aoa_size(var
->type
);
3418 length
= glsl_get_length(var
->type
);
3422 length
= glsl_get_matrix_columns(var
->type
);
3425 for (int col
= 0; col
< length
; ++col
) {
3426 int id
= ctx
->uniform_count
++;
3427 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3431 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3432 ctx
->varying_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3434 /* First, collect the special varyings */
3435 nir_foreach_variable(var
, &nir
->outputs
) {
3436 if (var
->data
.location
== VARYING_SLOT_POS
) {
3437 /* Set position first, always. It takes up two
3438 * spots, the latter one is de facto unused (at
3439 * least from the shader's perspective), we
3440 * just need to skip over the spot*/
3442 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (0 + 1)));
3443 ctx
->varying_count
= MAX2(ctx
->varying_count
, 2);
3444 } else if (var
->data
.location
== VARYING_SLOT_PSIZ
) {
3445 /* Set point size second (third, see above) */
3446 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (2 + 1)));
3447 ctx
->varying_count
= MAX2(ctx
->varying_count
, 3);
3449 program
->writes_point_size
= true;
3453 /* Now, collect normal varyings */
3455 nir_foreach_variable(var
, &nir
->outputs
) {
3456 if (var
->data
.location
== VARYING_SLOT_POS
|| var
->data
.location
== VARYING_SLOT_PSIZ
) continue;
3458 for (int col
= 0; col
< glsl_get_matrix_columns(var
->type
); ++col
) {
3459 int id
= ctx
->varying_count
++;
3460 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3467 /* Lower vars -- not I/O -- before epilogue */
3469 NIR_PASS_V(nir
, nir_lower_var_copies
);
3470 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3471 NIR_PASS_V(nir
, nir_split_var_copies
);
3472 NIR_PASS_V(nir
, nir_lower_var_copies
);
3473 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3474 NIR_PASS_V(nir
, nir_lower_var_copies
);
3475 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3476 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3478 /* Append vertex epilogue before optimisation, so the epilogue itself
3481 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3482 transform_position_writes(nir
);
3484 /* Optimisation passes */
3488 nir_print_shader(nir
, stdout
);
3490 /* Assign counts, now that we're sure (post-optimisation) */
3491 program
->uniform_count
= nir
->num_uniforms
;
3493 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3494 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3497 nir_foreach_function(func
, nir
) {
3501 list_inithead(&ctx
->blocks
);
3502 ctx
->block_count
= 0;
3505 emit_cf_list(ctx
, &func
->impl
->body
);
3506 emit_block(ctx
, func
->impl
->end_block
);
3508 break; /* TODO: Multi-function shaders */
3511 util_dynarray_init(compiled
, NULL
);
3514 schedule_program(ctx
);
3516 /* Now that all the bundles are scheduled and we can calculate block
3517 * sizes, emit actual branch instructions rather than placeholders */
3519 int br_block_idx
= 0;
3521 mir_foreach_block(ctx
, block
) {
3522 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3523 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3524 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3526 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3528 if (ins
->prepacked_branch
) continue;
3530 /* Parse some basic branch info */
3531 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3532 bool is_conditional
= ins
->branch
.conditional
;
3533 bool is_inverted
= ins
->branch
.invert_conditional
;
3534 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3536 /* Determine the block we're jumping to */
3537 int target_number
= ins
->branch
.target_block
;
3539 /* Report the destination tag. Discards don't need this */
3540 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3542 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3543 int quadword_offset
= 0;
3546 /* Jump to the end of the shader. We
3547 * need to include not only the
3548 * following blocks, but also the
3549 * contents of our current block (since
3550 * discard can come in the middle of
3553 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3555 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3556 quadword_offset
+= quadword_size(bun
->tag
);
3559 mir_foreach_block_from(ctx
, blk
, b
) {
3560 quadword_offset
+= b
->quadword_count
;
3563 } else if (target_number
> br_block_idx
) {
3566 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3567 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3570 quadword_offset
+= blk
->quadword_count
;
3573 /* Jump backwards */
3575 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3576 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3579 quadword_offset
-= blk
->quadword_count
;
3583 /* Unconditional extended branches (far jumps)
3584 * have issues, so we always use a conditional
3585 * branch, setting the condition to always for
3586 * unconditional. For compact unconditional
3587 * branches, cond isn't used so it doesn't
3588 * matter what we pick. */
3590 midgard_condition cond
=
3591 !is_conditional
? midgard_condition_always
:
3592 is_inverted
? midgard_condition_false
:
3593 midgard_condition_true
;
3595 midgard_jmp_writeout_op op
=
3596 is_discard
? midgard_jmp_writeout_op_discard
:
3597 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3598 midgard_jmp_writeout_op_branch_cond
;
3601 midgard_branch_extended branch
=
3602 midgard_create_branch_extended(
3607 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3608 } else if (is_conditional
|| is_discard
) {
3609 midgard_branch_cond branch
= {
3611 .dest_tag
= dest_tag
,
3612 .offset
= quadword_offset
,
3616 assert(branch
.offset
== quadword_offset
);
3618 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3620 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3622 midgard_branch_uncond branch
= {
3624 .dest_tag
= dest_tag
,
3625 .offset
= quadword_offset
,
3629 assert(branch
.offset
== quadword_offset
);
3631 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3639 /* Emit flat binary from the instruction arrays. Iterate each block in
3640 * sequence. Save instruction boundaries such that lookahead tags can
3641 * be assigned easily */
3643 /* Cache _all_ bundles in source order for lookahead across failed branches */
3645 int bundle_count
= 0;
3646 mir_foreach_block(ctx
, block
) {
3647 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3649 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3651 mir_foreach_block(ctx
, block
) {
3652 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3653 source_order_bundles
[bundle_idx
++] = bundle
;
3657 int current_bundle
= 0;
3659 mir_foreach_block(ctx
, block
) {
3660 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3663 if (current_bundle
+ 1 < bundle_count
) {
3664 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3666 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3673 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3677 /* TODO: Free deeper */
3678 //util_dynarray_fini(&block->instructions);
3681 free(source_order_bundles
);
3683 /* Report the very first tag executed */
3684 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3686 /* Deal with off-by-one related to the fencepost problem */
3687 program
->work_register_count
= ctx
->work_registers
+ 1;
3689 program
->can_discard
= ctx
->can_discard
;
3690 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3692 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3694 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);