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panfrost/midgard: Identify the in_reg_full field
[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value debug_options[] = {
54 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
56 DEBUG_NAMED_VALUE_END
57 };
58
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
60
61 int midgard_debug = 0;
62
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67
68 static bool
69 midgard_is_branch_unit(unsigned unit)
70 {
71 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
72 }
73
74 static void
75 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
76 {
77 block->successors[block->nr_successors++] = successor;
78 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
79 }
80
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
83
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
91 .ssa_args = { \
92 .rname = ssa, \
93 .uname = -1, \
94 .src1 = -1 \
95 }, \
96 .load_store = { \
97 .op = midgard_op_##name, \
98 .mask = 0xF, \
99 .swizzle = SWIZZLE_XYZW, \
100 .address = address \
101 } \
102 }; \
103 \
104 return i; \
105 }
106
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
109
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
112
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src *src, bool is_int)
115 {
116 if (!src) return blank_alu_src;
117
118 midgard_vector_alu_src alu_src = {
119 .rep_low = 0,
120 .rep_high = 0,
121 .half = 0, /* TODO */
122 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
123 };
124
125 if (is_int) {
126 /* TODO: sign-extend/zero-extend */
127 alu_src.mod = midgard_int_normal;
128
129 /* These should have been lowered away */
130 assert(!(src->abs || src->negate));
131 } else {
132 alu_src.mod = (src->abs << 0) | (src->negate << 1);
133 }
134
135 return alu_src;
136 }
137
138 /* load/store instructions have both 32-bit and 16-bit variants, depending on
139 * whether we are using vectors composed of highp or mediump. At the moment, we
140 * don't support half-floats -- this requires changes in other parts of the
141 * compiler -- therefore the 16-bit versions are commented out. */
142
143 //M_LOAD(ld_attr_16);
144 M_LOAD(ld_attr_32);
145 //M_LOAD(ld_vary_16);
146 M_LOAD(ld_vary_32);
147 //M_LOAD(ld_uniform_16);
148 M_LOAD(ld_uniform_32);
149 M_LOAD(ld_color_buffer_8);
150 //M_STORE(st_vary_16);
151 M_STORE(st_vary_32);
152 M_STORE(st_cubemap_coords);
153
154 static midgard_instruction
155 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
156 {
157 midgard_branch_cond branch = {
158 .op = op,
159 .dest_tag = tag,
160 .offset = offset,
161 .cond = cond
162 };
163
164 uint16_t compact;
165 memcpy(&compact, &branch, sizeof(branch));
166
167 midgard_instruction ins = {
168 .type = TAG_ALU_4,
169 .unit = ALU_ENAB_BR_COMPACT,
170 .prepacked_branch = true,
171 .compact_branch = true,
172 .br_compact = compact
173 };
174
175 if (op == midgard_jmp_writeout_op_writeout)
176 ins.writeout = true;
177
178 return ins;
179 }
180
181 static midgard_instruction
182 v_branch(bool conditional, bool invert)
183 {
184 midgard_instruction ins = {
185 .type = TAG_ALU_4,
186 .unit = ALU_ENAB_BRANCH,
187 .compact_branch = true,
188 .branch = {
189 .conditional = conditional,
190 .invert_conditional = invert
191 }
192 };
193
194 return ins;
195 }
196
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond,
199 midgard_jmp_writeout_op op,
200 unsigned dest_tag,
201 signed quadword_offset)
202 {
203 /* For unclear reasons, the condition code is repeated 8 times */
204 uint16_t duplicated_cond =
205 (cond << 14) |
206 (cond << 12) |
207 (cond << 10) |
208 (cond << 8) |
209 (cond << 6) |
210 (cond << 4) |
211 (cond << 2) |
212 (cond << 0);
213
214 midgard_branch_extended branch = {
215 .op = op,
216 .dest_tag = dest_tag,
217 .offset = quadword_offset,
218 .cond = duplicated_cond
219 };
220
221 return branch;
222 }
223
224 static void
225 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
226 {
227 ins->has_constants = true;
228 memcpy(&ins->constants, constants, 16);
229 }
230
231 static int
232 glsl_type_size(const struct glsl_type *type, bool bindless)
233 {
234 return glsl_count_attribute_slots(type, false);
235 }
236
237 /* Lower fdot2 to a vector multiplication followed by channel addition */
238 static void
239 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
240 {
241 if (alu->op != nir_op_fdot2)
242 return;
243
244 b->cursor = nir_before_instr(&alu->instr);
245
246 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
247 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
248
249 nir_ssa_def *product = nir_fmul(b, src0, src1);
250
251 nir_ssa_def *sum = nir_fadd(b,
252 nir_channel(b, product, 0),
253 nir_channel(b, product, 1));
254
255 /* Replace the fdot2 with this sum */
256 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
257 }
258
259 static int
260 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
261 {
262 switch (instr->intrinsic) {
263 case nir_intrinsic_load_viewport_scale:
264 return PAN_SYSVAL_VIEWPORT_SCALE;
265 case nir_intrinsic_load_viewport_offset:
266 return PAN_SYSVAL_VIEWPORT_OFFSET;
267 default:
268 return -1;
269 }
270 }
271
272 static void
273 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
274 {
275 int sysval = -1;
276
277 if (instr->type == nir_instr_type_intrinsic) {
278 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
279 sysval = midgard_nir_sysval_for_intrinsic(intr);
280 }
281
282 if (sysval < 0)
283 return;
284
285 /* We have a sysval load; check if it's already been assigned */
286
287 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
288 return;
289
290 /* It hasn't -- so assign it now! */
291
292 unsigned id = ctx->sysval_count++;
293 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
294 ctx->sysvals[id] = sysval;
295 }
296
297 static void
298 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
299 {
300 ctx->sysval_count = 0;
301
302 nir_foreach_function(function, shader) {
303 if (!function->impl) continue;
304
305 nir_foreach_block(block, function->impl) {
306 nir_foreach_instr_safe(instr, block) {
307 midgard_nir_assign_sysval_body(ctx, instr);
308 }
309 }
310 }
311 }
312
313 static bool
314 midgard_nir_lower_fdot2(nir_shader *shader)
315 {
316 bool progress = false;
317
318 nir_foreach_function(function, shader) {
319 if (!function->impl) continue;
320
321 nir_builder _b;
322 nir_builder *b = &_b;
323 nir_builder_init(b, function->impl);
324
325 nir_foreach_block(block, function->impl) {
326 nir_foreach_instr_safe(instr, block) {
327 if (instr->type != nir_instr_type_alu) continue;
328
329 nir_alu_instr *alu = nir_instr_as_alu(instr);
330 midgard_nir_lower_fdot2_body(b, alu);
331
332 progress |= true;
333 }
334 }
335
336 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
337
338 }
339
340 return progress;
341 }
342
343 static void
344 optimise_nir(nir_shader *nir)
345 {
346 bool progress;
347 unsigned lower_flrp =
348 (nir->options->lower_flrp16 ? 16 : 0) |
349 (nir->options->lower_flrp32 ? 32 : 0) |
350 (nir->options->lower_flrp64 ? 64 : 0);
351
352 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
353 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
354 NIR_PASS(progress, nir, nir_lower_idiv);
355
356 nir_lower_tex_options lower_tex_options = {
357 .lower_rect = true
358 };
359
360 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
361
362 do {
363 progress = false;
364
365 NIR_PASS(progress, nir, nir_lower_var_copies);
366 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
367
368 NIR_PASS(progress, nir, nir_copy_prop);
369 NIR_PASS(progress, nir, nir_opt_dce);
370 NIR_PASS(progress, nir, nir_opt_dead_cf);
371 NIR_PASS(progress, nir, nir_opt_cse);
372 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
373 NIR_PASS(progress, nir, nir_opt_algebraic);
374 NIR_PASS(progress, nir, nir_opt_constant_folding);
375
376 if (lower_flrp != 0) {
377 bool lower_flrp_progress = false;
378 NIR_PASS(lower_flrp_progress,
379 nir,
380 nir_lower_flrp,
381 lower_flrp,
382 false /* always_precise */,
383 nir->options->lower_ffma);
384 if (lower_flrp_progress) {
385 NIR_PASS(progress, nir,
386 nir_opt_constant_folding);
387 progress = true;
388 }
389
390 /* Nothing should rematerialize any flrps, so we only
391 * need to do this lowering once.
392 */
393 lower_flrp = 0;
394 }
395
396 NIR_PASS(progress, nir, nir_opt_undef);
397 NIR_PASS(progress, nir, nir_opt_loop_unroll,
398 nir_var_shader_in |
399 nir_var_shader_out |
400 nir_var_function_temp);
401
402 /* TODO: Enable vectorize when merged upstream */
403 // NIR_PASS(progress, nir, nir_opt_vectorize);
404 } while (progress);
405
406 /* Must be run at the end to prevent creation of fsin/fcos ops */
407 NIR_PASS(progress, nir, midgard_nir_scale_trig);
408
409 do {
410 progress = false;
411
412 NIR_PASS(progress, nir, nir_opt_dce);
413 NIR_PASS(progress, nir, nir_opt_algebraic);
414 NIR_PASS(progress, nir, nir_opt_constant_folding);
415 NIR_PASS(progress, nir, nir_copy_prop);
416 } while (progress);
417
418 NIR_PASS(progress, nir, nir_opt_algebraic_late);
419
420 /* We implement booleans as 32-bit 0/~0 */
421 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
422
423 /* Now that booleans are lowered, we can run out late opts */
424 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
425
426 /* Lower mods for float ops only. Integer ops don't support modifiers
427 * (saturate doesn't make sense on integers, neg/abs require dedicated
428 * instructions) */
429
430 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
431 NIR_PASS(progress, nir, nir_copy_prop);
432 NIR_PASS(progress, nir, nir_opt_dce);
433
434 /* Take us out of SSA */
435 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
436 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
437
438 /* We are a vector architecture; write combine where possible */
439 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
440 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
441
442 NIR_PASS(progress, nir, nir_opt_dce);
443 }
444
445 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
446 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
447 * r0. See the comments in compiler_context */
448
449 static void
450 alias_ssa(compiler_context *ctx, int dest, int src)
451 {
452 _mesa_hash_table_u64_insert(ctx->ssa_to_alias, dest + 1, (void *) ((uintptr_t) src + 1));
453 _mesa_set_add(ctx->leftover_ssa_to_alias, (void *) (uintptr_t) (dest + 1));
454 }
455
456 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
457
458 static void
459 unalias_ssa(compiler_context *ctx, int dest)
460 {
461 _mesa_hash_table_u64_remove(ctx->ssa_to_alias, dest + 1);
462 /* TODO: Remove from leftover or no? */
463 }
464
465 /* Do not actually emit a load; instead, cache the constant for inlining */
466
467 static void
468 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
469 {
470 nir_ssa_def def = instr->def;
471
472 float *v = rzalloc_array(NULL, float, 4);
473 nir_const_load_to_arr(v, instr, f32);
474 _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
475 }
476
477 static unsigned
478 nir_src_index(compiler_context *ctx, nir_src *src)
479 {
480 if (src->is_ssa)
481 return src->ssa->index;
482 else {
483 assert(!src->reg.indirect);
484 return ctx->func->impl->ssa_alloc + src->reg.reg->index;
485 }
486 }
487
488 static unsigned
489 nir_dest_index(compiler_context *ctx, nir_dest *dst)
490 {
491 if (dst->is_ssa)
492 return dst->ssa.index;
493 else {
494 assert(!dst->reg.indirect);
495 return ctx->func->impl->ssa_alloc + dst->reg.reg->index;
496 }
497 }
498
499 static unsigned
500 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
501 {
502 return nir_src_index(ctx, &src->src);
503 }
504
505 static bool
506 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
507 {
508 unsigned comp = src->swizzle[0];
509
510 for (unsigned c = 1; c < nr_components; ++c) {
511 if (src->swizzle[c] != comp)
512 return true;
513 }
514
515 return false;
516 }
517
518 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
519 * output of a conditional test) into that register */
520
521 static void
522 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
523 {
524 int condition = nir_src_index(ctx, src);
525
526 /* Source to swizzle the desired component into w */
527
528 const midgard_vector_alu_src alu_src = {
529 .swizzle = SWIZZLE(component, component, component, component),
530 };
531
532 /* There is no boolean move instruction. Instead, we simulate a move by
533 * ANDing the condition with itself to get it into r31.w */
534
535 midgard_instruction ins = {
536 .type = TAG_ALU_4,
537
538 /* We need to set the conditional as close as possible */
539 .precede_break = true,
540 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
541
542 .ssa_args = {
543 .src0 = condition,
544 .src1 = condition,
545 .dest = SSA_FIXED_REGISTER(31),
546 },
547
548 .alu = {
549 .op = midgard_alu_op_iand,
550 .outmod = midgard_outmod_int_wrap,
551 .reg_mode = midgard_reg_mode_32,
552 .dest_override = midgard_dest_override_none,
553 .mask = (0x3 << 6), /* w */
554 .src1 = vector_alu_srco_unsigned(alu_src),
555 .src2 = vector_alu_srco_unsigned(alu_src)
556 },
557 };
558
559 emit_mir_instruction(ctx, ins);
560 }
561
562 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
563 * r31 instead */
564
565 static void
566 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
567 {
568 int condition = nir_src_index(ctx, &src->src);
569
570 /* Source to swizzle the desired component into w */
571
572 const midgard_vector_alu_src alu_src = {
573 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
574 };
575
576 /* There is no boolean move instruction. Instead, we simulate a move by
577 * ANDing the condition with itself to get it into r31.w */
578
579 midgard_instruction ins = {
580 .type = TAG_ALU_4,
581 .precede_break = true,
582 .ssa_args = {
583 .src0 = condition,
584 .src1 = condition,
585 .dest = SSA_FIXED_REGISTER(31),
586 },
587 .alu = {
588 .op = midgard_alu_op_iand,
589 .outmod = midgard_outmod_int_wrap,
590 .reg_mode = midgard_reg_mode_32,
591 .dest_override = midgard_dest_override_none,
592 .mask = expand_writemask((1 << nr_comp) - 1),
593 .src1 = vector_alu_srco_unsigned(alu_src),
594 .src2 = vector_alu_srco_unsigned(alu_src)
595 },
596 };
597
598 emit_mir_instruction(ctx, ins);
599 }
600
601
602
603 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
604 * pinning to eliminate this move in all known cases */
605
606 static void
607 emit_indirect_offset(compiler_context *ctx, nir_src *src)
608 {
609 int offset = nir_src_index(ctx, src);
610
611 midgard_instruction ins = {
612 .type = TAG_ALU_4,
613 .ssa_args = {
614 .src0 = SSA_UNUSED_1,
615 .src1 = offset,
616 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
617 },
618 .alu = {
619 .op = midgard_alu_op_imov,
620 .outmod = midgard_outmod_int_wrap,
621 .reg_mode = midgard_reg_mode_32,
622 .dest_override = midgard_dest_override_none,
623 .mask = (0x3 << 6), /* w */
624 .src1 = vector_alu_srco_unsigned(zero_alu_src),
625 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
626 },
627 };
628
629 emit_mir_instruction(ctx, ins);
630 }
631
632 #define ALU_CASE(nir, _op) \
633 case nir_op_##nir: \
634 op = midgard_alu_op_##_op; \
635 break;
636 static bool
637 nir_is_fzero_constant(nir_src src)
638 {
639 if (!nir_src_is_const(src))
640 return false;
641
642 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
643 if (nir_src_comp_as_float(src, c) != 0.0)
644 return false;
645 }
646
647 return true;
648 }
649
650 static void
651 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
652 {
653 bool is_ssa = instr->dest.dest.is_ssa;
654
655 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
656 unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components;
657 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
658
659 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
660 * supported. A few do not and are commented for now. Also, there are a
661 * number of NIR ops which Midgard does not support and need to be
662 * lowered, also TODO. This switch block emits the opcode and calling
663 * convention of the Midgard instruction; actual packing is done in
664 * emit_alu below */
665
666 unsigned op;
667
668 switch (instr->op) {
669 ALU_CASE(fadd, fadd);
670 ALU_CASE(fmul, fmul);
671 ALU_CASE(fmin, fmin);
672 ALU_CASE(fmax, fmax);
673 ALU_CASE(imin, imin);
674 ALU_CASE(imax, imax);
675 ALU_CASE(umin, umin);
676 ALU_CASE(umax, umax);
677 ALU_CASE(ffloor, ffloor);
678 ALU_CASE(fround_even, froundeven);
679 ALU_CASE(ftrunc, ftrunc);
680 ALU_CASE(fceil, fceil);
681 ALU_CASE(fdot3, fdot3);
682 ALU_CASE(fdot4, fdot4);
683 ALU_CASE(iadd, iadd);
684 ALU_CASE(isub, isub);
685 ALU_CASE(imul, imul);
686
687 /* Zero shoved as second-arg */
688 ALU_CASE(iabs, iabsdiff);
689
690 ALU_CASE(mov, imov);
691
692 ALU_CASE(feq32, feq);
693 ALU_CASE(fne32, fne);
694 ALU_CASE(flt32, flt);
695 ALU_CASE(ieq32, ieq);
696 ALU_CASE(ine32, ine);
697 ALU_CASE(ilt32, ilt);
698 ALU_CASE(ult32, ult);
699
700 /* We don't have a native b2f32 instruction. Instead, like many
701 * GPUs, we exploit booleans as 0/~0 for false/true, and
702 * correspondingly AND
703 * by 1.0 to do the type conversion. For the moment, prime us
704 * to emit:
705 *
706 * iand [whatever], #0
707 *
708 * At the end of emit_alu (as MIR), we'll fix-up the constant
709 */
710
711 ALU_CASE(b2f32, iand);
712 ALU_CASE(b2i32, iand);
713
714 /* Likewise, we don't have a dedicated f2b32 instruction, but
715 * we can do a "not equal to 0.0" test. */
716
717 ALU_CASE(f2b32, fne);
718 ALU_CASE(i2b32, ine);
719
720 ALU_CASE(frcp, frcp);
721 ALU_CASE(frsq, frsqrt);
722 ALU_CASE(fsqrt, fsqrt);
723 ALU_CASE(fexp2, fexp2);
724 ALU_CASE(flog2, flog2);
725
726 ALU_CASE(f2i32, f2i);
727 ALU_CASE(f2u32, f2u);
728 ALU_CASE(i2f32, i2f);
729 ALU_CASE(u2f32, u2f);
730
731 ALU_CASE(fsin, fsin);
732 ALU_CASE(fcos, fcos);
733
734 /* Second op implicit #0 */
735 ALU_CASE(inot, inor);
736 ALU_CASE(iand, iand);
737 ALU_CASE(ior, ior);
738 ALU_CASE(ixor, ixor);
739 ALU_CASE(ishl, ishl);
740 ALU_CASE(ishr, iasr);
741 ALU_CASE(ushr, ilsr);
742
743 ALU_CASE(b32all_fequal2, fball_eq);
744 ALU_CASE(b32all_fequal3, fball_eq);
745 ALU_CASE(b32all_fequal4, fball_eq);
746
747 ALU_CASE(b32any_fnequal2, fbany_neq);
748 ALU_CASE(b32any_fnequal3, fbany_neq);
749 ALU_CASE(b32any_fnequal4, fbany_neq);
750
751 ALU_CASE(b32all_iequal2, iball_eq);
752 ALU_CASE(b32all_iequal3, iball_eq);
753 ALU_CASE(b32all_iequal4, iball_eq);
754
755 ALU_CASE(b32any_inequal2, ibany_neq);
756 ALU_CASE(b32any_inequal3, ibany_neq);
757 ALU_CASE(b32any_inequal4, ibany_neq);
758
759 /* Source mods will be shoved in later */
760 ALU_CASE(fabs, fmov);
761 ALU_CASE(fneg, fmov);
762 ALU_CASE(fsat, fmov);
763
764 /* For greater-or-equal, we lower to less-or-equal and flip the
765 * arguments */
766
767 case nir_op_fge:
768 case nir_op_fge32:
769 case nir_op_ige32:
770 case nir_op_uge32: {
771 op =
772 instr->op == nir_op_fge ? midgard_alu_op_fle :
773 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
774 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
775 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
776 0;
777
778 /* Swap via temporary */
779 nir_alu_src temp = instr->src[1];
780 instr->src[1] = instr->src[0];
781 instr->src[0] = temp;
782
783 break;
784 }
785
786 case nir_op_b32csel: {
787 /* Midgard features both fcsel and icsel, depending on
788 * the type of the arguments/output. However, as long
789 * as we're careful we can _always_ use icsel and
790 * _never_ need fcsel, since the latter does additional
791 * floating-point-specific processing whereas the
792 * former just moves bits on the wire. It's not obvious
793 * why these are separate opcodes, save for the ability
794 * to do things like sat/pos/abs/neg for free */
795
796 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
797 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
798
799 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
800 nr_inputs = 2;
801
802 /* Emit the condition into r31 */
803
804 if (mixed)
805 emit_condition_mixed(ctx, &instr->src[0], nr_components);
806 else
807 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
808
809 /* The condition is the first argument; move the other
810 * arguments up one to be a binary instruction for
811 * Midgard */
812
813 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
814 break;
815 }
816
817 default:
818 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
819 assert(0);
820 return;
821 }
822
823 /* Midgard can perform certain modifiers on output of an ALU op */
824 unsigned outmod;
825
826 if (midgard_is_integer_out_op(op)) {
827 outmod = midgard_outmod_int_wrap;
828 } else {
829 bool sat = instr->dest.saturate || instr->op == nir_op_fsat;
830 outmod = sat ? midgard_outmod_sat : midgard_outmod_none;
831 }
832
833 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
834
835 if (instr->op == nir_op_fmax) {
836 if (nir_is_fzero_constant(instr->src[0].src)) {
837 op = midgard_alu_op_fmov;
838 nr_inputs = 1;
839 outmod = midgard_outmod_pos;
840 instr->src[0] = instr->src[1];
841 } else if (nir_is_fzero_constant(instr->src[1].src)) {
842 op = midgard_alu_op_fmov;
843 nr_inputs = 1;
844 outmod = midgard_outmod_pos;
845 }
846 }
847
848 /* Fetch unit, quirks, etc information */
849 unsigned opcode_props = alu_opcode_props[op].props;
850 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
851
852 /* src0 will always exist afaik, but src1 will not for 1-argument
853 * instructions. The latter can only be fetched if the instruction
854 * needs it, or else we may segfault. */
855
856 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
857 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
858
859 /* Rather than use the instruction generation helpers, we do it
860 * ourselves here to avoid the mess */
861
862 midgard_instruction ins = {
863 .type = TAG_ALU_4,
864 .ssa_args = {
865 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
866 .src1 = quirk_flipped_r24 ? src0 : src1,
867 .dest = dest,
868 }
869 };
870
871 nir_alu_src *nirmods[2] = { NULL };
872
873 if (nr_inputs == 2) {
874 nirmods[0] = &instr->src[0];
875 nirmods[1] = &instr->src[1];
876 } else if (nr_inputs == 1) {
877 nirmods[quirk_flipped_r24] = &instr->src[0];
878 } else {
879 assert(0);
880 }
881
882 /* These were lowered to a move, so apply the corresponding mod */
883
884 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
885 nir_alu_src *s = nirmods[quirk_flipped_r24];
886
887 if (instr->op == nir_op_fneg)
888 s->negate = !s->negate;
889
890 if (instr->op == nir_op_fabs)
891 s->abs = !s->abs;
892 }
893
894 bool is_int = midgard_is_integer_op(op);
895
896 midgard_vector_alu alu = {
897 .op = op,
898 .reg_mode = midgard_reg_mode_32,
899 .dest_override = midgard_dest_override_none,
900 .outmod = outmod,
901
902 /* Writemask only valid for non-SSA NIR */
903 .mask = expand_writemask((1 << nr_components) - 1),
904
905 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int)),
906 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int)),
907 };
908
909 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
910
911 if (!is_ssa)
912 alu.mask &= expand_writemask(instr->dest.write_mask);
913
914 ins.alu = alu;
915
916 /* Late fixup for emulated instructions */
917
918 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
919 /* Presently, our second argument is an inline #0 constant.
920 * Switch over to an embedded 1.0 constant (that can't fit
921 * inline, since we're 32-bit, not 16-bit like the inline
922 * constants) */
923
924 ins.ssa_args.inline_constant = false;
925 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
926 ins.has_constants = true;
927
928 if (instr->op == nir_op_b2f32) {
929 ins.constants[0] = 1.0f;
930 } else {
931 /* Type pun it into place */
932 uint32_t one = 0x1;
933 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
934 }
935
936 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
937 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
938 /* Lots of instructions need a 0 plonked in */
939 ins.ssa_args.inline_constant = false;
940 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
941 ins.has_constants = true;
942 ins.constants[0] = 0.0f;
943 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
944 } else if (instr->op == nir_op_inot) {
945 /* ~b = ~(b & b), so duplicate the source */
946 ins.ssa_args.src1 = ins.ssa_args.src0;
947 ins.alu.src2 = ins.alu.src1;
948 }
949
950 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
951 /* To avoid duplicating the lookup tables (probably), true LUT
952 * instructions can only operate as if they were scalars. Lower
953 * them here by changing the component. */
954
955 uint8_t original_swizzle[4];
956 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
957
958 for (int i = 0; i < nr_components; ++i) {
959 ins.alu.mask = (0x3) << (2 * i); /* Mask the associated component */
960
961 for (int j = 0; j < 4; ++j)
962 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
963
964 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int));
965 emit_mir_instruction(ctx, ins);
966 }
967 } else {
968 emit_mir_instruction(ctx, ins);
969 }
970 }
971
972 #undef ALU_CASE
973
974 static void
975 emit_uniform_read(compiler_context *ctx, unsigned dest, unsigned offset, nir_src *indirect_offset)
976 {
977 /* TODO: half-floats */
978
979 if (!indirect_offset && offset < ctx->uniform_cutoff) {
980 /* Fast path: For the first 16 uniforms, direct accesses are
981 * 0-cycle, since they're just a register fetch in the usual
982 * case. So, we alias the registers while we're still in
983 * SSA-space */
984
985 int reg_slot = 23 - offset;
986 alias_ssa(ctx, dest, SSA_FIXED_REGISTER(reg_slot));
987 } else {
988 /* Otherwise, read from the 'special' UBO to access
989 * higher-indexed uniforms, at a performance cost. More
990 * generally, we're emitting a UBO read instruction. */
991
992 midgard_instruction ins = m_ld_uniform_32(dest, offset);
993
994 /* TODO: Don't split */
995 ins.load_store.varying_parameters = (offset & 7) << 7;
996 ins.load_store.address = offset >> 3;
997
998 if (indirect_offset) {
999 emit_indirect_offset(ctx, indirect_offset);
1000 ins.load_store.unknown = 0x8700; /* xxx: what is this? */
1001 } else {
1002 ins.load_store.unknown = 0x1E00; /* xxx: what is this? */
1003 }
1004
1005 emit_mir_instruction(ctx, ins);
1006 }
1007 }
1008
1009 static void
1010 emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
1011 {
1012 /* First, pull out the destination */
1013 unsigned dest = nir_dest_index(ctx, &instr->dest);
1014
1015 /* Now, figure out which uniform this is */
1016 int sysval = midgard_nir_sysval_for_intrinsic(instr);
1017 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1018
1019 /* Sysvals are prefix uniforms */
1020 unsigned uniform = ((uintptr_t) val) - 1;
1021
1022 /* Emit the read itself -- this is never indirect */
1023 emit_uniform_read(ctx, dest, uniform, NULL);
1024 }
1025
1026 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1027 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1028 * generations have faster vectorized reads. This operation is for blend
1029 * shaders in particular; reading the tilebuffer from the fragment shader
1030 * remains an open problem. */
1031
1032 static void
1033 emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
1034 {
1035 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1036 ins.load_store.swizzle = 0; /* xxxx */
1037
1038 /* Read each component sequentially */
1039
1040 for (unsigned c = 0; c < 4; ++c) {
1041 ins.load_store.mask = (1 << c);
1042 ins.load_store.unknown = c;
1043 emit_mir_instruction(ctx, ins);
1044 }
1045
1046 /* vadd.u2f hr2, zext(hr2), #0 */
1047
1048 midgard_vector_alu_src alu_src = blank_alu_src;
1049 alu_src.mod = midgard_int_zero_extend;
1050 alu_src.half = true;
1051
1052 midgard_instruction u2f = {
1053 .type = TAG_ALU_4,
1054 .ssa_args = {
1055 .src0 = reg,
1056 .src1 = SSA_UNUSED_0,
1057 .dest = reg,
1058 .inline_constant = true
1059 },
1060 .alu = {
1061 .op = midgard_alu_op_u2f,
1062 .reg_mode = midgard_reg_mode_16,
1063 .dest_override = midgard_dest_override_none,
1064 .mask = 0xF,
1065 .src1 = vector_alu_srco_unsigned(alu_src),
1066 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1067 }
1068 };
1069
1070 emit_mir_instruction(ctx, u2f);
1071
1072 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1073
1074 alu_src.mod = 0;
1075
1076 midgard_instruction fmul = {
1077 .type = TAG_ALU_4,
1078 .inline_constant = _mesa_float_to_half(1.0 / 255.0),
1079 .ssa_args = {
1080 .src0 = reg,
1081 .dest = reg,
1082 .src1 = SSA_UNUSED_0,
1083 .inline_constant = true
1084 },
1085 .alu = {
1086 .op = midgard_alu_op_fmul,
1087 .reg_mode = midgard_reg_mode_32,
1088 .dest_override = midgard_dest_override_none,
1089 .outmod = midgard_outmod_sat,
1090 .mask = 0xFF,
1091 .src1 = vector_alu_srco_unsigned(alu_src),
1092 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1093 }
1094 };
1095
1096 emit_mir_instruction(ctx, fmul);
1097 }
1098
1099 static void
1100 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1101 {
1102 unsigned offset, reg;
1103
1104 switch (instr->intrinsic) {
1105 case nir_intrinsic_discard_if:
1106 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1107
1108 /* fallthrough */
1109
1110 case nir_intrinsic_discard: {
1111 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1112 struct midgard_instruction discard = v_branch(conditional, false);
1113 discard.branch.target_type = TARGET_DISCARD;
1114 emit_mir_instruction(ctx, discard);
1115
1116 ctx->can_discard = true;
1117 break;
1118 }
1119
1120 case nir_intrinsic_load_uniform:
1121 case nir_intrinsic_load_input:
1122 offset = nir_intrinsic_base(instr);
1123
1124 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1125 bool direct = nir_src_is_const(instr->src[0]);
1126
1127 if (direct) {
1128 offset += nir_src_as_uint(instr->src[0]);
1129 }
1130
1131 /* We may need to apply a fractional offset */
1132 int component = instr->intrinsic == nir_intrinsic_load_input ?
1133 nir_intrinsic_component(instr) : 0;
1134 reg = nir_dest_index(ctx, &instr->dest);
1135
1136 if (instr->intrinsic == nir_intrinsic_load_uniform && !ctx->is_blend) {
1137 emit_uniform_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL);
1138 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1139 /* XXX: Half-floats? */
1140 /* TODO: swizzle, mask */
1141
1142 midgard_instruction ins = m_ld_vary_32(reg, offset);
1143 ins.load_store.mask = (1 << nr_comp) - 1;
1144 ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component);
1145
1146 midgard_varying_parameter p = {
1147 .is_varying = 1,
1148 .interpolation = midgard_interp_default,
1149 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1150 };
1151
1152 unsigned u;
1153 memcpy(&u, &p, sizeof(p));
1154 ins.load_store.varying_parameters = u;
1155
1156 if (direct) {
1157 /* We have the offset totally ready */
1158 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1159 } else {
1160 /* We have it partially ready, but we need to
1161 * add in the dynamic index, moved to r27.w */
1162 emit_indirect_offset(ctx, &instr->src[0]);
1163 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1164 }
1165
1166 emit_mir_instruction(ctx, ins);
1167 } else if (ctx->is_blend) {
1168 /* For blend shaders, load the input color, which is
1169 * preloaded to r0 */
1170
1171 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1172 emit_mir_instruction(ctx, move);
1173 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1174 midgard_instruction ins = m_ld_attr_32(reg, offset);
1175 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1176 ins.load_store.mask = (1 << nr_comp) - 1;
1177 emit_mir_instruction(ctx, ins);
1178 } else {
1179 DBG("Unknown load\n");
1180 assert(0);
1181 }
1182
1183 break;
1184
1185 case nir_intrinsic_load_output:
1186 assert(nir_src_is_const(instr->src[0]));
1187 reg = nir_dest_index(ctx, &instr->dest);
1188
1189 if (ctx->is_blend) {
1190 /* TODO: MRT */
1191 emit_fb_read_blend_scalar(ctx, reg);
1192 } else {
1193 DBG("Unknown output load\n");
1194 assert(0);
1195 }
1196
1197 break;
1198
1199 case nir_intrinsic_load_blend_const_color_rgba: {
1200 assert(ctx->is_blend);
1201 reg = nir_dest_index(ctx, &instr->dest);
1202
1203 /* Blend constants are embedded directly in the shader and
1204 * patched in, so we use some magic routing */
1205
1206 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1207 ins.has_constants = true;
1208 ins.has_blend_constant = true;
1209 emit_mir_instruction(ctx, ins);
1210 break;
1211 }
1212
1213 case nir_intrinsic_store_output:
1214 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1215
1216 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1217
1218 reg = nir_src_index(ctx, &instr->src[0]);
1219
1220 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1221 /* gl_FragColor is not emitted with load/store
1222 * instructions. Instead, it gets plonked into
1223 * r0 at the end of the shader and we do the
1224 * framebuffer writeout dance. TODO: Defer
1225 * writes */
1226
1227 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1228 emit_mir_instruction(ctx, move);
1229
1230 /* Save the index we're writing to for later reference
1231 * in the epilogue */
1232
1233 ctx->fragment_output = reg;
1234 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1235 /* Varyings are written into one of two special
1236 * varying register, r26 or r27. The register itself is
1237 * selected as the register in the st_vary instruction,
1238 * minus the base of 26. E.g. write into r27 and then
1239 * call st_vary(1) */
1240
1241 midgard_instruction ins = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(26));
1242 emit_mir_instruction(ctx, ins);
1243
1244 /* We should have been vectorized. That also lets us
1245 * ignore the mask. because the mask component on
1246 * st_vary is (as far as I can tell) ignored [the blob
1247 * sets it to zero] */
1248 assert(nir_intrinsic_component(instr) == 0);
1249
1250 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset);
1251 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1252 emit_mir_instruction(ctx, st);
1253 } else {
1254 DBG("Unknown store\n");
1255 assert(0);
1256 }
1257
1258 break;
1259
1260 case nir_intrinsic_load_alpha_ref_float:
1261 assert(instr->dest.is_ssa);
1262
1263 float ref_value = ctx->alpha_ref;
1264
1265 float *v = ralloc_array(NULL, float, 4);
1266 memcpy(v, &ref_value, sizeof(float));
1267 _mesa_hash_table_u64_insert(ctx->ssa_constants, instr->dest.ssa.index + 1, v);
1268 break;
1269
1270 case nir_intrinsic_load_viewport_scale:
1271 case nir_intrinsic_load_viewport_offset:
1272 emit_sysval_read(ctx, instr);
1273 break;
1274
1275 default:
1276 printf ("Unhandled intrinsic\n");
1277 assert(0);
1278 break;
1279 }
1280 }
1281
1282 static unsigned
1283 midgard_tex_format(enum glsl_sampler_dim dim)
1284 {
1285 switch (dim) {
1286 case GLSL_SAMPLER_DIM_2D:
1287 case GLSL_SAMPLER_DIM_EXTERNAL:
1288 return TEXTURE_2D;
1289
1290 case GLSL_SAMPLER_DIM_3D:
1291 return TEXTURE_3D;
1292
1293 case GLSL_SAMPLER_DIM_CUBE:
1294 return TEXTURE_CUBE;
1295
1296 default:
1297 DBG("Unknown sampler dim type\n");
1298 assert(0);
1299 return 0;
1300 }
1301 }
1302
1303 static void
1304 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1305 {
1306 /* TODO */
1307 //assert (!instr->sampler);
1308 //assert (!instr->texture_array_size);
1309 assert (instr->op == nir_texop_tex);
1310
1311 /* Allocate registers via a round robin scheme to alternate between the two registers */
1312 int reg = ctx->texture_op_count & 1;
1313 int in_reg = reg, out_reg = reg;
1314
1315 /* Make room for the reg */
1316
1317 if (ctx->texture_index[reg] > -1)
1318 unalias_ssa(ctx, ctx->texture_index[reg]);
1319
1320 int texture_index = instr->texture_index;
1321 int sampler_index = texture_index;
1322
1323 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1324 switch (instr->src[i].src_type) {
1325 case nir_tex_src_coord: {
1326 int index = nir_src_index(ctx, &instr->src[i].src);
1327
1328 midgard_vector_alu_src alu_src = blank_alu_src;
1329
1330 int reg = SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + in_reg);
1331
1332 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1333 /* For cubemaps, we need to load coords into
1334 * special r27, and then use a special ld/st op
1335 * to copy into the texture register */
1336
1337 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X);
1338
1339 midgard_instruction move = v_fmov(index, alu_src, SSA_FIXED_REGISTER(27));
1340 emit_mir_instruction(ctx, move);
1341
1342 midgard_instruction st = m_st_cubemap_coords(reg, 0);
1343 st.load_store.unknown = 0x24; /* XXX: What is this? */
1344 st.load_store.mask = 0x3; /* xy? */
1345 st.load_store.swizzle = alu_src.swizzle;
1346 emit_mir_instruction(ctx, st);
1347
1348 } else {
1349 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X);
1350
1351 midgard_instruction ins = v_fmov(index, alu_src, reg);
1352 emit_mir_instruction(ctx, ins);
1353 }
1354
1355 break;
1356 }
1357
1358 default: {
1359 DBG("Unknown source type\n");
1360 //assert(0);
1361 break;
1362 }
1363 }
1364 }
1365
1366 /* No helper to build texture words -- we do it all here */
1367 midgard_instruction ins = {
1368 .type = TAG_TEXTURE_4,
1369 .texture = {
1370 .op = TEXTURE_OP_NORMAL,
1371 .format = midgard_tex_format(instr->sampler_dim),
1372 .texture_handle = texture_index,
1373 .sampler_handle = sampler_index,
1374
1375 /* TODO: Regalloc it in */
1376 .swizzle = SWIZZLE_XYZW,
1377 .mask = 0xF,
1378
1379 /* TODO: half */
1380 .in_reg_full = 1,
1381 .in_reg_swizzle = SWIZZLE_XYZW,
1382 .out_full = 1,
1383
1384 /* Always 1 */
1385 .unknown7 = 1,
1386
1387 /* Assume we can continue; hint it out later */
1388 .cont = 1,
1389 }
1390 };
1391
1392 /* Set registers to read and write from the same place */
1393 ins.texture.in_reg_select = in_reg;
1394 ins.texture.out_reg_select = out_reg;
1395
1396 emit_mir_instruction(ctx, ins);
1397
1398 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1399
1400 int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest);
1401 alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg));
1402 ctx->texture_index[reg] = o_index;
1403
1404 midgard_instruction ins2 = v_fmov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index);
1405 emit_mir_instruction(ctx, ins2);
1406
1407 /* Used for .cont and .last hinting */
1408 ctx->texture_op_count++;
1409 }
1410
1411 static void
1412 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1413 {
1414 switch (instr->type) {
1415 case nir_jump_break: {
1416 /* Emit a branch out of the loop */
1417 struct midgard_instruction br = v_branch(false, false);
1418 br.branch.target_type = TARGET_BREAK;
1419 br.branch.target_break = ctx->current_loop_depth;
1420 emit_mir_instruction(ctx, br);
1421
1422 DBG("break..\n");
1423 break;
1424 }
1425
1426 default:
1427 DBG("Unknown jump type %d\n", instr->type);
1428 break;
1429 }
1430 }
1431
1432 static void
1433 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1434 {
1435 switch (instr->type) {
1436 case nir_instr_type_load_const:
1437 emit_load_const(ctx, nir_instr_as_load_const(instr));
1438 break;
1439
1440 case nir_instr_type_intrinsic:
1441 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1442 break;
1443
1444 case nir_instr_type_alu:
1445 emit_alu(ctx, nir_instr_as_alu(instr));
1446 break;
1447
1448 case nir_instr_type_tex:
1449 emit_tex(ctx, nir_instr_as_tex(instr));
1450 break;
1451
1452 case nir_instr_type_jump:
1453 emit_jump(ctx, nir_instr_as_jump(instr));
1454 break;
1455
1456 case nir_instr_type_ssa_undef:
1457 /* Spurious */
1458 break;
1459
1460 default:
1461 DBG("Unhandled instruction type\n");
1462 break;
1463 }
1464 }
1465
1466
1467 /* ALU instructions can inline or embed constants, which decreases register
1468 * pressure and saves space. */
1469
1470 #define CONDITIONAL_ATTACH(src) { \
1471 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1472 \
1473 if (entry) { \
1474 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1475 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1476 } \
1477 }
1478
1479 static void
1480 inline_alu_constants(compiler_context *ctx)
1481 {
1482 mir_foreach_instr(ctx, alu) {
1483 /* Other instructions cannot inline constants */
1484 if (alu->type != TAG_ALU_4) continue;
1485
1486 /* If there is already a constant here, we can do nothing */
1487 if (alu->has_constants) continue;
1488
1489 /* It makes no sense to inline constants on a branch */
1490 if (alu->compact_branch || alu->prepacked_branch) continue;
1491
1492 CONDITIONAL_ATTACH(src0);
1493
1494 if (!alu->has_constants) {
1495 CONDITIONAL_ATTACH(src1)
1496 } else if (!alu->inline_constant) {
1497 /* Corner case: _two_ vec4 constants, for instance with a
1498 * csel. For this case, we can only use a constant
1499 * register for one, we'll have to emit a move for the
1500 * other. Note, if both arguments are constants, then
1501 * necessarily neither argument depends on the value of
1502 * any particular register. As the destination register
1503 * will be wiped, that means we can spill the constant
1504 * to the destination register.
1505 */
1506
1507 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
1508 unsigned scratch = alu->ssa_args.dest;
1509
1510 if (entry) {
1511 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
1512 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
1513
1514 /* Force a break XXX Defer r31 writes */
1515 ins.unit = UNIT_VLUT;
1516
1517 /* Set the source */
1518 alu->ssa_args.src1 = scratch;
1519
1520 /* Inject us -before- the last instruction which set r31 */
1521 mir_insert_instruction_before(mir_prev_op(alu), ins);
1522 }
1523 }
1524 }
1525 }
1526
1527 /* Midgard supports two types of constants, embedded constants (128-bit) and
1528 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1529 * constants can be demoted to inline constants, for space savings and
1530 * sometimes a performance boost */
1531
1532 static void
1533 embedded_to_inline_constant(compiler_context *ctx)
1534 {
1535 mir_foreach_instr(ctx, ins) {
1536 if (!ins->has_constants) continue;
1537
1538 if (ins->ssa_args.inline_constant) continue;
1539
1540 /* Blend constants must not be inlined by definition */
1541 if (ins->has_blend_constant) continue;
1542
1543 /* src1 cannot be an inline constant due to encoding
1544 * restrictions. So, if possible we try to flip the arguments
1545 * in that case */
1546
1547 int op = ins->alu.op;
1548
1549 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1550 switch (op) {
1551 /* These ops require an operational change to flip
1552 * their arguments TODO */
1553 case midgard_alu_op_flt:
1554 case midgard_alu_op_fle:
1555 case midgard_alu_op_ilt:
1556 case midgard_alu_op_ile:
1557 case midgard_alu_op_fcsel:
1558 case midgard_alu_op_icsel:
1559 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
1560 default:
1561 break;
1562 }
1563
1564 if (alu_opcode_props[op].props & OP_COMMUTES) {
1565 /* Flip the SSA numbers */
1566 ins->ssa_args.src0 = ins->ssa_args.src1;
1567 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1568
1569 /* And flip the modifiers */
1570
1571 unsigned src_temp;
1572
1573 src_temp = ins->alu.src2;
1574 ins->alu.src2 = ins->alu.src1;
1575 ins->alu.src1 = src_temp;
1576 }
1577 }
1578
1579 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1580 /* Extract the source information */
1581
1582 midgard_vector_alu_src *src;
1583 int q = ins->alu.src2;
1584 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1585 src = m;
1586
1587 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1588 int component = src->swizzle & 3;
1589
1590 /* Scale constant appropriately, if we can legally */
1591 uint16_t scaled_constant = 0;
1592
1593 if (midgard_is_integer_op(op)) {
1594 unsigned int *iconstants = (unsigned int *) ins->constants;
1595 scaled_constant = (uint16_t) iconstants[component];
1596
1597 /* Constant overflow after resize */
1598 if (scaled_constant != iconstants[component])
1599 continue;
1600 } else {
1601 float original = (float) ins->constants[component];
1602 scaled_constant = _mesa_float_to_half(original);
1603
1604 /* Check for loss of precision. If this is
1605 * mediump, we don't care, but for a highp
1606 * shader, we need to pay attention. NIR
1607 * doesn't yet tell us which mode we're in!
1608 * Practically this prevents most constants
1609 * from being inlined, sadly. */
1610
1611 float fp32 = _mesa_half_to_float(scaled_constant);
1612
1613 if (fp32 != original)
1614 continue;
1615 }
1616
1617 /* We don't know how to handle these with a constant */
1618
1619 if (src->mod || src->half || src->rep_low || src->rep_high) {
1620 DBG("Bailing inline constant...\n");
1621 continue;
1622 }
1623
1624 /* Make sure that the constant is not itself a
1625 * vector by checking if all accessed values
1626 * (by the swizzle) are the same. */
1627
1628 uint32_t *cons = (uint32_t *) ins->constants;
1629 uint32_t value = cons[component];
1630
1631 bool is_vector = false;
1632 unsigned mask = effective_writemask(&ins->alu);
1633
1634 for (int c = 1; c < 4; ++c) {
1635 /* We only care if this component is actually used */
1636 if (!(mask & (1 << c)))
1637 continue;
1638
1639 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
1640
1641 if (test != value) {
1642 is_vector = true;
1643 break;
1644 }
1645 }
1646
1647 if (is_vector)
1648 continue;
1649
1650 /* Get rid of the embedded constant */
1651 ins->has_constants = false;
1652 ins->ssa_args.src1 = SSA_UNUSED_0;
1653 ins->ssa_args.inline_constant = true;
1654 ins->inline_constant = scaled_constant;
1655 }
1656 }
1657 }
1658
1659 /* Map normal SSA sources to other SSA sources / fixed registers (like
1660 * uniforms) */
1661
1662 static void
1663 map_ssa_to_alias(compiler_context *ctx, int *ref)
1664 {
1665 /* Sign is used quite deliberately for unused */
1666 if (*ref < 0)
1667 return;
1668
1669 unsigned int alias = (uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_to_alias, *ref + 1);
1670
1671 if (alias) {
1672 /* Remove entry in leftovers to avoid a redunant fmov */
1673
1674 struct set_entry *leftover = _mesa_set_search(ctx->leftover_ssa_to_alias, ((void *) (uintptr_t) (*ref + 1)));
1675
1676 if (leftover)
1677 _mesa_set_remove(ctx->leftover_ssa_to_alias, leftover);
1678
1679 /* Assign the alias map */
1680 *ref = alias - 1;
1681 return;
1682 }
1683 }
1684
1685 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1686 * texture pipeline */
1687
1688 static bool
1689 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
1690 {
1691 bool progress = false;
1692
1693 mir_foreach_instr_in_block_safe(block, ins) {
1694 if (ins->type != TAG_ALU_4) continue;
1695 if (ins->compact_branch) continue;
1696
1697 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
1698 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
1699
1700 mir_remove_instruction(ins);
1701 progress = true;
1702 }
1703
1704 return progress;
1705 }
1706
1707 /* Dead code elimination for branches at the end of a block - only one branch
1708 * per block is legal semantically */
1709
1710 static void
1711 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
1712 {
1713 bool branched = false;
1714
1715 mir_foreach_instr_in_block_safe(block, ins) {
1716 if (!midgard_is_branch_unit(ins->unit)) continue;
1717
1718 /* We ignore prepacked branches since the fragment epilogue is
1719 * just generally special */
1720 if (ins->prepacked_branch) continue;
1721
1722 /* Discards are similarly special and may not correspond to the
1723 * end of a block */
1724
1725 if (ins->branch.target_type == TARGET_DISCARD) continue;
1726
1727 if (branched) {
1728 /* We already branched, so this is dead */
1729 mir_remove_instruction(ins);
1730 }
1731
1732 branched = true;
1733 }
1734 }
1735
1736 static bool
1737 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
1738 {
1739 /* abs or neg */
1740 if (!is_int && src.mod) return true;
1741
1742 /* swizzle */
1743 for (unsigned c = 0; c < 4; ++c) {
1744 if (!(mask & (1 << c))) continue;
1745 if (((src.swizzle >> (2*c)) & 3) != c) return true;
1746 }
1747
1748 return false;
1749 }
1750
1751 static bool
1752 mir_nontrivial_source2_mod(midgard_instruction *ins)
1753 {
1754 unsigned mask = squeeze_writemask(ins->alu.mask);
1755 bool is_int = midgard_is_integer_op(ins->alu.op);
1756
1757 midgard_vector_alu_src src2 =
1758 vector_alu_from_unsigned(ins->alu.src2);
1759
1760 return mir_nontrivial_mod(src2, is_int, mask);
1761 }
1762
1763 static bool
1764 mir_nontrivial_outmod(midgard_instruction *ins)
1765 {
1766 bool is_int = midgard_is_integer_op(ins->alu.op);
1767 unsigned mod = ins->alu.outmod;
1768
1769 if (is_int)
1770 return mod != midgard_outmod_int_wrap;
1771 else
1772 return mod != midgard_outmod_none;
1773 }
1774
1775 static bool
1776 midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
1777 {
1778 bool progress = false;
1779
1780 mir_foreach_instr_in_block_safe(block, ins) {
1781 if (ins->type != TAG_ALU_4) continue;
1782 if (!OP_IS_MOVE(ins->alu.op)) continue;
1783
1784 unsigned from = ins->ssa_args.src1;
1785 unsigned to = ins->ssa_args.dest;
1786
1787 /* We only work on pure SSA */
1788
1789 if (to >= SSA_FIXED_MINIMUM) continue;
1790 if (from >= SSA_FIXED_MINIMUM) continue;
1791 if (to >= ctx->func->impl->ssa_alloc) continue;
1792 if (from >= ctx->func->impl->ssa_alloc) continue;
1793
1794 /* Constant propagation is not handled here, either */
1795 if (ins->ssa_args.inline_constant) continue;
1796 if (ins->has_constants) continue;
1797
1798 if (mir_nontrivial_source2_mod(ins)) continue;
1799 if (mir_nontrivial_outmod(ins)) continue;
1800
1801 /* We're clear -- rewrite */
1802 mir_rewrite_index_src(ctx, to, from);
1803 mir_remove_instruction(ins);
1804 progress |= true;
1805 }
1806
1807 return progress;
1808 }
1809
1810 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1811 * the move can be propagated away entirely */
1812
1813 static bool
1814 mir_compose_float_outmod(midgard_outmod_float *outmod, midgard_outmod_float comp)
1815 {
1816 /* Nothing to do */
1817 if (comp == midgard_outmod_none)
1818 return true;
1819
1820 if (*outmod == midgard_outmod_none) {
1821 *outmod = comp;
1822 return true;
1823 }
1824
1825 /* TODO: Compose rules */
1826 return false;
1827 }
1828
1829 static bool
1830 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
1831 {
1832 bool progress = false;
1833
1834 mir_foreach_instr_in_block_safe(block, ins) {
1835 if (ins->type != TAG_ALU_4) continue;
1836 if (ins->alu.op != midgard_alu_op_fmov) continue;
1837 if (ins->alu.outmod != midgard_outmod_pos) continue;
1838
1839 /* TODO: Registers? */
1840 unsigned src = ins->ssa_args.src1;
1841 if (src >= ctx->func->impl->ssa_alloc) continue;
1842 assert(!mir_has_multiple_writes(ctx, src));
1843
1844 /* There might be a source modifier, too */
1845 if (mir_nontrivial_source2_mod(ins)) continue;
1846
1847 /* Backpropagate the modifier */
1848 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1849 if (v->type != TAG_ALU_4) continue;
1850 if (v->ssa_args.dest != src) continue;
1851
1852 /* Can we even take a float outmod? */
1853 if (midgard_is_integer_out_op(v->alu.op)) continue;
1854
1855 midgard_outmod_float temp = v->alu.outmod;
1856 progress |= mir_compose_float_outmod(&temp, ins->alu.outmod);
1857
1858 /* Throw in the towel.. */
1859 if (!progress) break;
1860
1861 /* Otherwise, transfer the modifier */
1862 v->alu.outmod = temp;
1863 ins->alu.outmod = midgard_outmod_none;
1864
1865 break;
1866 }
1867 }
1868
1869 return progress;
1870 }
1871
1872 static bool
1873 midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
1874 {
1875 bool progress = false;
1876
1877 mir_foreach_instr_in_block_safe(block, ins) {
1878 if (ins->type != TAG_ALU_4) continue;
1879 if (!OP_IS_MOVE(ins->alu.op)) continue;
1880
1881 unsigned from = ins->ssa_args.src1;
1882 unsigned to = ins->ssa_args.dest;
1883
1884 /* Make sure it's simple enough for us to handle */
1885
1886 if (from >= SSA_FIXED_MINIMUM) continue;
1887 if (from >= ctx->func->impl->ssa_alloc) continue;
1888 if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
1889 if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
1890
1891 bool eliminated = false;
1892
1893 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1894 /* The texture registers are not SSA so be careful.
1895 * Conservatively, just stop if we hit a texture op
1896 * (even if it may not write) to where we are */
1897
1898 if (v->type != TAG_ALU_4)
1899 break;
1900
1901 if (v->ssa_args.dest == from) {
1902 /* We don't want to track partial writes ... */
1903 if (v->alu.mask == 0xF) {
1904 v->ssa_args.dest = to;
1905 eliminated = true;
1906 }
1907
1908 break;
1909 }
1910 }
1911
1912 if (eliminated)
1913 mir_remove_instruction(ins);
1914
1915 progress |= eliminated;
1916 }
1917
1918 return progress;
1919 }
1920
1921 /* The following passes reorder MIR instructions to enable better scheduling */
1922
1923 static void
1924 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
1925 {
1926 mir_foreach_instr_in_block_safe(block, ins) {
1927 if (ins->type != TAG_LOAD_STORE_4) continue;
1928
1929 /* We've found a load/store op. Check if next is also load/store. */
1930 midgard_instruction *next_op = mir_next_op(ins);
1931 if (&next_op->link != &block->instructions) {
1932 if (next_op->type == TAG_LOAD_STORE_4) {
1933 /* If so, we're done since we're a pair */
1934 ins = mir_next_op(ins);
1935 continue;
1936 }
1937
1938 /* Maximum search distance to pair, to avoid register pressure disasters */
1939 int search_distance = 8;
1940
1941 /* Otherwise, we have an orphaned load/store -- search for another load */
1942 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
1943 /* Terminate search if necessary */
1944 if (!(search_distance--)) break;
1945
1946 if (c->type != TAG_LOAD_STORE_4) continue;
1947
1948 /* Stores cannot be reordered, since they have
1949 * dependencies. For the same reason, indirect
1950 * loads cannot be reordered as their index is
1951 * loaded in r27.w */
1952
1953 if (OP_IS_STORE(c->load_store.op)) continue;
1954
1955 /* It appears the 0x800 bit is set whenever a
1956 * load is direct, unset when it is indirect.
1957 * Skip indirect loads. */
1958
1959 if (!(c->load_store.unknown & 0x800)) continue;
1960
1961 /* We found one! Move it up to pair and remove it from the old location */
1962
1963 mir_insert_instruction_before(ins, *c);
1964 mir_remove_instruction(c);
1965
1966 break;
1967 }
1968 }
1969 }
1970 }
1971
1972 /* If there are leftovers after the below pass, emit actual fmov
1973 * instructions for the slow-but-correct path */
1974
1975 static void
1976 emit_leftover_move(compiler_context *ctx)
1977 {
1978 set_foreach(ctx->leftover_ssa_to_alias, leftover) {
1979 int base = ((uintptr_t) leftover->key) - 1;
1980 int mapped = base;
1981
1982 map_ssa_to_alias(ctx, &mapped);
1983 EMIT(fmov, mapped, blank_alu_src, base);
1984 }
1985 }
1986
1987 static void
1988 actualise_ssa_to_alias(compiler_context *ctx)
1989 {
1990 mir_foreach_instr(ctx, ins) {
1991 map_ssa_to_alias(ctx, &ins->ssa_args.src0);
1992 map_ssa_to_alias(ctx, &ins->ssa_args.src1);
1993 }
1994
1995 emit_leftover_move(ctx);
1996 }
1997
1998 static void
1999 emit_fragment_epilogue(compiler_context *ctx)
2000 {
2001 /* Special case: writing out constants requires us to include the move
2002 * explicitly now, so shove it into r0 */
2003
2004 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, ctx->fragment_output + 1);
2005
2006 if (constant_value) {
2007 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(0));
2008 attach_constants(ctx, &ins, constant_value, ctx->fragment_output + 1);
2009 emit_mir_instruction(ctx, ins);
2010 }
2011
2012 /* Perform the actual fragment writeout. We have two writeout/branch
2013 * instructions, forming a loop until writeout is successful as per the
2014 * docs. TODO: gl_FragDepth */
2015
2016 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2017 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2018 }
2019
2020 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2021 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2022 * with the int8 analogue to the fragment epilogue */
2023
2024 static void
2025 emit_blend_epilogue(compiler_context *ctx)
2026 {
2027 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2028
2029 midgard_instruction scale = {
2030 .type = TAG_ALU_4,
2031 .unit = UNIT_VMUL,
2032 .inline_constant = _mesa_float_to_half(255.0),
2033 .ssa_args = {
2034 .src0 = SSA_FIXED_REGISTER(0),
2035 .src1 = SSA_UNUSED_0,
2036 .dest = SSA_FIXED_REGISTER(24),
2037 .inline_constant = true
2038 },
2039 .alu = {
2040 .op = midgard_alu_op_fmul,
2041 .reg_mode = midgard_reg_mode_32,
2042 .dest_override = midgard_dest_override_lower,
2043 .mask = 0xFF,
2044 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2045 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2046 }
2047 };
2048
2049 emit_mir_instruction(ctx, scale);
2050
2051 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2052
2053 midgard_vector_alu_src alu_src = blank_alu_src;
2054 alu_src.half = true;
2055
2056 midgard_instruction f2u8 = {
2057 .type = TAG_ALU_4,
2058 .ssa_args = {
2059 .src0 = SSA_FIXED_REGISTER(24),
2060 .src1 = SSA_UNUSED_0,
2061 .dest = SSA_FIXED_REGISTER(0),
2062 .inline_constant = true
2063 },
2064 .alu = {
2065 .op = midgard_alu_op_f2u8,
2066 .reg_mode = midgard_reg_mode_16,
2067 .dest_override = midgard_dest_override_lower,
2068 .outmod = midgard_outmod_pos,
2069 .mask = 0xF,
2070 .src1 = vector_alu_srco_unsigned(alu_src),
2071 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2072 }
2073 };
2074
2075 emit_mir_instruction(ctx, f2u8);
2076
2077 /* vmul.imov.quarter r0, r0, r0 */
2078
2079 midgard_instruction imov_8 = {
2080 .type = TAG_ALU_4,
2081 .ssa_args = {
2082 .src0 = SSA_UNUSED_1,
2083 .src1 = SSA_FIXED_REGISTER(0),
2084 .dest = SSA_FIXED_REGISTER(0),
2085 },
2086 .alu = {
2087 .op = midgard_alu_op_imov,
2088 .reg_mode = midgard_reg_mode_8,
2089 .dest_override = midgard_dest_override_none,
2090 .outmod = midgard_outmod_int_wrap,
2091 .mask = 0xFF,
2092 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2093 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2094 }
2095 };
2096
2097 /* Emit branch epilogue with the 8-bit move as the source */
2098
2099 emit_mir_instruction(ctx, imov_8);
2100 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2101
2102 emit_mir_instruction(ctx, imov_8);
2103 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2104 }
2105
2106 static midgard_block *
2107 emit_block(compiler_context *ctx, nir_block *block)
2108 {
2109 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2110 list_addtail(&this_block->link, &ctx->blocks);
2111
2112 this_block->is_scheduled = false;
2113 ++ctx->block_count;
2114
2115 ctx->texture_index[0] = -1;
2116 ctx->texture_index[1] = -1;
2117
2118 /* Add us as a successor to the block we are following */
2119 if (ctx->current_block)
2120 midgard_block_add_successor(ctx->current_block, this_block);
2121
2122 /* Set up current block */
2123 list_inithead(&this_block->instructions);
2124 ctx->current_block = this_block;
2125
2126 nir_foreach_instr(instr, block) {
2127 emit_instr(ctx, instr);
2128 ++ctx->instruction_count;
2129 }
2130
2131 inline_alu_constants(ctx);
2132 embedded_to_inline_constant(ctx);
2133
2134 /* Perform heavylifting for aliasing */
2135 actualise_ssa_to_alias(ctx);
2136
2137 midgard_pair_load_store(ctx, this_block);
2138
2139 /* Append fragment shader epilogue (value writeout) */
2140 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2141 if (block == nir_impl_last_block(ctx->func->impl)) {
2142 if (ctx->is_blend)
2143 emit_blend_epilogue(ctx);
2144 else
2145 emit_fragment_epilogue(ctx);
2146 }
2147 }
2148
2149 if (block == nir_start_block(ctx->func->impl))
2150 ctx->initial_block = this_block;
2151
2152 if (block == nir_impl_last_block(ctx->func->impl))
2153 ctx->final_block = this_block;
2154
2155 /* Allow the next control flow to access us retroactively, for
2156 * branching etc */
2157 ctx->current_block = this_block;
2158
2159 /* Document the fallthrough chain */
2160 ctx->previous_source_block = this_block;
2161
2162 return this_block;
2163 }
2164
2165 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2166
2167 static void
2168 emit_if(struct compiler_context *ctx, nir_if *nif)
2169 {
2170 /* Conditional branches expect the condition in r31.w; emit a move for
2171 * that in the _previous_ block (which is the current block). */
2172 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2173
2174 /* Speculatively emit the branch, but we can't fill it in until later */
2175 EMIT(branch, true, true);
2176 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2177
2178 /* Emit the two subblocks */
2179 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2180
2181 /* Emit a jump from the end of the then block to the end of the else */
2182 EMIT(branch, false, false);
2183 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2184
2185 /* Emit second block, and check if it's empty */
2186
2187 int else_idx = ctx->block_count;
2188 int count_in = ctx->instruction_count;
2189 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2190 int after_else_idx = ctx->block_count;
2191
2192 /* Now that we have the subblocks emitted, fix up the branches */
2193
2194 assert(then_block);
2195 assert(else_block);
2196
2197 if (ctx->instruction_count == count_in) {
2198 /* The else block is empty, so don't emit an exit jump */
2199 mir_remove_instruction(then_exit);
2200 then_branch->branch.target_block = after_else_idx;
2201 } else {
2202 then_branch->branch.target_block = else_idx;
2203 then_exit->branch.target_block = after_else_idx;
2204 }
2205 }
2206
2207 static void
2208 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2209 {
2210 /* Remember where we are */
2211 midgard_block *start_block = ctx->current_block;
2212
2213 /* Allocate a loop number, growing the current inner loop depth */
2214 int loop_idx = ++ctx->current_loop_depth;
2215
2216 /* Get index from before the body so we can loop back later */
2217 int start_idx = ctx->block_count;
2218
2219 /* Emit the body itself */
2220 emit_cf_list(ctx, &nloop->body);
2221
2222 /* Branch back to loop back */
2223 struct midgard_instruction br_back = v_branch(false, false);
2224 br_back.branch.target_block = start_idx;
2225 emit_mir_instruction(ctx, br_back);
2226
2227 /* Mark down that branch in the graph. Note that we're really branching
2228 * to the block *after* we started in. TODO: Why doesn't the branch
2229 * itself have an off-by-one then...? */
2230 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2231
2232 /* Find the index of the block about to follow us (note: we don't add
2233 * one; blocks are 0-indexed so we get a fencepost problem) */
2234 int break_block_idx = ctx->block_count;
2235
2236 /* Fix up the break statements we emitted to point to the right place,
2237 * now that we can allocate a block number for them */
2238
2239 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2240 mir_foreach_instr_in_block(block, ins) {
2241 if (ins->type != TAG_ALU_4) continue;
2242 if (!ins->compact_branch) continue;
2243 if (ins->prepacked_branch) continue;
2244
2245 /* We found a branch -- check the type to see if we need to do anything */
2246 if (ins->branch.target_type != TARGET_BREAK) continue;
2247
2248 /* It's a break! Check if it's our break */
2249 if (ins->branch.target_break != loop_idx) continue;
2250
2251 /* Okay, cool, we're breaking out of this loop.
2252 * Rewrite from a break to a goto */
2253
2254 ins->branch.target_type = TARGET_GOTO;
2255 ins->branch.target_block = break_block_idx;
2256 }
2257 }
2258
2259 /* Now that we've finished emitting the loop, free up the depth again
2260 * so we play nice with recursion amid nested loops */
2261 --ctx->current_loop_depth;
2262 }
2263
2264 static midgard_block *
2265 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2266 {
2267 midgard_block *start_block = NULL;
2268
2269 foreach_list_typed(nir_cf_node, node, node, list) {
2270 switch (node->type) {
2271 case nir_cf_node_block: {
2272 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2273
2274 if (!start_block)
2275 start_block = block;
2276
2277 break;
2278 }
2279
2280 case nir_cf_node_if:
2281 emit_if(ctx, nir_cf_node_as_if(node));
2282 break;
2283
2284 case nir_cf_node_loop:
2285 emit_loop(ctx, nir_cf_node_as_loop(node));
2286 break;
2287
2288 case nir_cf_node_function:
2289 assert(0);
2290 break;
2291 }
2292 }
2293
2294 return start_block;
2295 }
2296
2297 /* Due to lookahead, we need to report the first tag executed in the command
2298 * stream and in branch targets. An initial block might be empty, so iterate
2299 * until we find one that 'works' */
2300
2301 static unsigned
2302 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2303 {
2304 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2305
2306 unsigned first_tag = 0;
2307
2308 do {
2309 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
2310
2311 if (initial_bundle) {
2312 first_tag = initial_bundle->tag;
2313 break;
2314 }
2315
2316 /* Initial block is empty, try the next block */
2317 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
2318 } while(initial_block != NULL);
2319
2320 assert(first_tag);
2321 return first_tag;
2322 }
2323
2324 int
2325 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend)
2326 {
2327 struct util_dynarray *compiled = &program->compiled;
2328
2329 midgard_debug = debug_get_option_midgard_debug();
2330
2331 compiler_context ictx = {
2332 .nir = nir,
2333 .stage = nir->info.stage,
2334
2335 .is_blend = is_blend,
2336 .blend_constant_offset = -1,
2337
2338 .alpha_ref = program->alpha_ref
2339 };
2340
2341 compiler_context *ctx = &ictx;
2342
2343 /* TODO: Decide this at runtime */
2344 ctx->uniform_cutoff = 8;
2345
2346 /* Initialize at a global (not block) level hash tables */
2347
2348 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2349 ctx->ssa_to_alias = _mesa_hash_table_u64_create(NULL);
2350 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2351 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2352 ctx->leftover_ssa_to_alias = _mesa_set_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
2353
2354 /* Record the varying mapping for the command stream's bookkeeping */
2355
2356 struct exec_list *varyings =
2357 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2358
2359 unsigned max_varying = 0;
2360 nir_foreach_variable(var, varyings) {
2361 unsigned loc = var->data.driver_location;
2362 unsigned sz = glsl_type_size(var->type, FALSE);
2363
2364 for (int c = loc; c < (loc + sz); ++c) {
2365 program->varyings[c] = var->data.location;
2366 max_varying = MAX2(max_varying, c);
2367 }
2368 }
2369
2370 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2371 * (so we don't accidentally duplicate the epilogue since mesa/st has
2372 * messed with our I/O quite a bit already) */
2373
2374 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2375
2376 if (ctx->stage == MESA_SHADER_VERTEX)
2377 NIR_PASS_V(nir, nir_lower_viewport_transform);
2378
2379 NIR_PASS_V(nir, nir_lower_var_copies);
2380 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2381 NIR_PASS_V(nir, nir_split_var_copies);
2382 NIR_PASS_V(nir, nir_lower_var_copies);
2383 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2384 NIR_PASS_V(nir, nir_lower_var_copies);
2385 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2386
2387 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2388
2389 /* Optimisation passes */
2390
2391 optimise_nir(nir);
2392
2393 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2394 nir_print_shader(nir, stdout);
2395 }
2396
2397 /* Assign sysvals and counts, now that we're sure
2398 * (post-optimisation) */
2399
2400 midgard_nir_assign_sysvals(ctx, nir);
2401
2402 program->uniform_count = nir->num_uniforms;
2403 program->sysval_count = ctx->sysval_count;
2404 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2405
2406 program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_inputs : 0;
2407 program->varying_count = max_varying + 1; /* Fencepost off-by-one */
2408
2409 nir_foreach_function(func, nir) {
2410 if (!func->impl)
2411 continue;
2412
2413 list_inithead(&ctx->blocks);
2414 ctx->block_count = 0;
2415 ctx->func = func;
2416
2417 emit_cf_list(ctx, &func->impl->body);
2418 emit_block(ctx, func->impl->end_block);
2419
2420 break; /* TODO: Multi-function shaders */
2421 }
2422
2423 util_dynarray_init(compiled, NULL);
2424
2425 /* MIR-level optimizations */
2426
2427 bool progress = false;
2428
2429 do {
2430 progress = false;
2431
2432 mir_foreach_block(ctx, block) {
2433 progress |= midgard_opt_pos_propagate(ctx, block);
2434 progress |= midgard_opt_copy_prop(ctx, block);
2435 progress |= midgard_opt_copy_prop_tex(ctx, block);
2436 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2437 }
2438 } while (progress);
2439
2440 /* Nested control-flow can result in dead branches at the end of the
2441 * block. This messes with our analysis and is just dead code, so cull
2442 * them */
2443 mir_foreach_block(ctx, block) {
2444 midgard_opt_cull_dead_branch(ctx, block);
2445 }
2446
2447 /* Schedule! */
2448 schedule_program(ctx);
2449
2450 /* Now that all the bundles are scheduled and we can calculate block
2451 * sizes, emit actual branch instructions rather than placeholders */
2452
2453 int br_block_idx = 0;
2454
2455 mir_foreach_block(ctx, block) {
2456 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2457 for (int c = 0; c < bundle->instruction_count; ++c) {
2458 midgard_instruction *ins = bundle->instructions[c];
2459
2460 if (!midgard_is_branch_unit(ins->unit)) continue;
2461
2462 if (ins->prepacked_branch) continue;
2463
2464 /* Parse some basic branch info */
2465 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2466 bool is_conditional = ins->branch.conditional;
2467 bool is_inverted = ins->branch.invert_conditional;
2468 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2469
2470 /* Determine the block we're jumping to */
2471 int target_number = ins->branch.target_block;
2472
2473 /* Report the destination tag */
2474 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2475
2476 /* Count up the number of quadwords we're
2477 * jumping over = number of quadwords until
2478 * (br_block_idx, target_number) */
2479
2480 int quadword_offset = 0;
2481
2482 if (is_discard) {
2483 /* Jump to the end of the shader. We
2484 * need to include not only the
2485 * following blocks, but also the
2486 * contents of our current block (since
2487 * discard can come in the middle of
2488 * the block) */
2489
2490 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
2491
2492 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
2493 quadword_offset += quadword_size(bun->tag);
2494 }
2495
2496 mir_foreach_block_from(ctx, blk, b) {
2497 quadword_offset += b->quadword_count;
2498 }
2499
2500 } else if (target_number > br_block_idx) {
2501 /* Jump forward */
2502
2503 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2504 midgard_block *blk = mir_get_block(ctx, idx);
2505 assert(blk);
2506
2507 quadword_offset += blk->quadword_count;
2508 }
2509 } else {
2510 /* Jump backwards */
2511
2512 for (int idx = br_block_idx; idx >= target_number; --idx) {
2513 midgard_block *blk = mir_get_block(ctx, idx);
2514 assert(blk);
2515
2516 quadword_offset -= blk->quadword_count;
2517 }
2518 }
2519
2520 /* Unconditional extended branches (far jumps)
2521 * have issues, so we always use a conditional
2522 * branch, setting the condition to always for
2523 * unconditional. For compact unconditional
2524 * branches, cond isn't used so it doesn't
2525 * matter what we pick. */
2526
2527 midgard_condition cond =
2528 !is_conditional ? midgard_condition_always :
2529 is_inverted ? midgard_condition_false :
2530 midgard_condition_true;
2531
2532 midgard_jmp_writeout_op op =
2533 is_discard ? midgard_jmp_writeout_op_discard :
2534 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2535 midgard_jmp_writeout_op_branch_cond;
2536
2537 if (!is_compact) {
2538 midgard_branch_extended branch =
2539 midgard_create_branch_extended(
2540 cond, op,
2541 dest_tag,
2542 quadword_offset);
2543
2544 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2545 } else if (is_conditional || is_discard) {
2546 midgard_branch_cond branch = {
2547 .op = op,
2548 .dest_tag = dest_tag,
2549 .offset = quadword_offset,
2550 .cond = cond
2551 };
2552
2553 assert(branch.offset == quadword_offset);
2554
2555 memcpy(&ins->br_compact, &branch, sizeof(branch));
2556 } else {
2557 assert(op == midgard_jmp_writeout_op_branch_uncond);
2558
2559 midgard_branch_uncond branch = {
2560 .op = op,
2561 .dest_tag = dest_tag,
2562 .offset = quadword_offset,
2563 .unknown = 1
2564 };
2565
2566 assert(branch.offset == quadword_offset);
2567
2568 memcpy(&ins->br_compact, &branch, sizeof(branch));
2569 }
2570 }
2571 }
2572
2573 ++br_block_idx;
2574 }
2575
2576 /* Emit flat binary from the instruction arrays. Iterate each block in
2577 * sequence. Save instruction boundaries such that lookahead tags can
2578 * be assigned easily */
2579
2580 /* Cache _all_ bundles in source order for lookahead across failed branches */
2581
2582 int bundle_count = 0;
2583 mir_foreach_block(ctx, block) {
2584 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2585 }
2586 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2587 int bundle_idx = 0;
2588 mir_foreach_block(ctx, block) {
2589 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2590 source_order_bundles[bundle_idx++] = bundle;
2591 }
2592 }
2593
2594 int current_bundle = 0;
2595
2596 /* Midgard prefetches instruction types, so during emission we
2597 * need to lookahead. Unless this is the last instruction, in
2598 * which we return 1. Or if this is the second to last and the
2599 * last is an ALU, then it's also 1... */
2600
2601 mir_foreach_block(ctx, block) {
2602 mir_foreach_bundle_in_block(block, bundle) {
2603 int lookahead = 1;
2604
2605 if (current_bundle + 1 < bundle_count) {
2606 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2607
2608 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2609 lookahead = 1;
2610 } else {
2611 lookahead = next;
2612 }
2613 }
2614
2615 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2616 ++current_bundle;
2617 }
2618
2619 /* TODO: Free deeper */
2620 //util_dynarray_fini(&block->instructions);
2621 }
2622
2623 free(source_order_bundles);
2624
2625 /* Report the very first tag executed */
2626 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2627
2628 /* Deal with off-by-one related to the fencepost problem */
2629 program->work_register_count = ctx->work_registers + 1;
2630
2631 program->can_discard = ctx->can_discard;
2632 program->uniform_cutoff = ctx->uniform_cutoff;
2633
2634 program->blend_patch_offset = ctx->blend_constant_offset;
2635
2636 if (midgard_debug & MIDGARD_DBG_SHADERS)
2637 disassemble_midgard(program->compiled.data, program->compiled.size);
2638
2639 return 0;
2640 }