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panfrost/midgard: Use fancy iterator
[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value debug_options[] = {
54 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
56 DEBUG_NAMED_VALUE_END
57 };
58
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
60
61 int midgard_debug = 0;
62
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67
68 static bool
69 midgard_is_branch_unit(unsigned unit)
70 {
71 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
72 }
73
74 static void
75 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
76 {
77 block->successors[block->nr_successors++] = successor;
78 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
79 }
80
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
83
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
91 .ssa_args = { \
92 .rname = ssa, \
93 .uname = -1, \
94 .src1 = -1 \
95 }, \
96 .load_store = { \
97 .op = midgard_op_##name, \
98 .mask = 0xF, \
99 .swizzle = SWIZZLE_XYZW, \
100 .address = address \
101 } \
102 }; \
103 \
104 return i; \
105 }
106
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
109
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
112
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src *src, bool is_int)
115 {
116 if (!src) return blank_alu_src;
117
118 midgard_vector_alu_src alu_src = {
119 .rep_low = 0,
120 .rep_high = 0,
121 .half = 0, /* TODO */
122 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
123 };
124
125 if (is_int) {
126 /* TODO: sign-extend/zero-extend */
127 alu_src.mod = midgard_int_normal;
128
129 /* These should have been lowered away */
130 assert(!(src->abs || src->negate));
131 } else {
132 alu_src.mod = (src->abs << 0) | (src->negate << 1);
133 }
134
135 return alu_src;
136 }
137
138 /* load/store instructions have both 32-bit and 16-bit variants, depending on
139 * whether we are using vectors composed of highp or mediump. At the moment, we
140 * don't support half-floats -- this requires changes in other parts of the
141 * compiler -- therefore the 16-bit versions are commented out. */
142
143 //M_LOAD(ld_attr_16);
144 M_LOAD(ld_attr_32);
145 //M_LOAD(ld_vary_16);
146 M_LOAD(ld_vary_32);
147 //M_LOAD(ld_uniform_16);
148 M_LOAD(ld_uniform_32);
149 M_LOAD(ld_color_buffer_8);
150 //M_STORE(st_vary_16);
151 M_STORE(st_vary_32);
152 M_STORE(st_cubemap_coords);
153
154 static midgard_instruction
155 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
156 {
157 midgard_branch_cond branch = {
158 .op = op,
159 .dest_tag = tag,
160 .offset = offset,
161 .cond = cond
162 };
163
164 uint16_t compact;
165 memcpy(&compact, &branch, sizeof(branch));
166
167 midgard_instruction ins = {
168 .type = TAG_ALU_4,
169 .unit = ALU_ENAB_BR_COMPACT,
170 .prepacked_branch = true,
171 .compact_branch = true,
172 .br_compact = compact
173 };
174
175 if (op == midgard_jmp_writeout_op_writeout)
176 ins.writeout = true;
177
178 return ins;
179 }
180
181 static midgard_instruction
182 v_branch(bool conditional, bool invert)
183 {
184 midgard_instruction ins = {
185 .type = TAG_ALU_4,
186 .unit = ALU_ENAB_BRANCH,
187 .compact_branch = true,
188 .branch = {
189 .conditional = conditional,
190 .invert_conditional = invert
191 }
192 };
193
194 return ins;
195 }
196
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond,
199 midgard_jmp_writeout_op op,
200 unsigned dest_tag,
201 signed quadword_offset)
202 {
203 /* For unclear reasons, the condition code is repeated 8 times */
204 uint16_t duplicated_cond =
205 (cond << 14) |
206 (cond << 12) |
207 (cond << 10) |
208 (cond << 8) |
209 (cond << 6) |
210 (cond << 4) |
211 (cond << 2) |
212 (cond << 0);
213
214 midgard_branch_extended branch = {
215 .op = op,
216 .dest_tag = dest_tag,
217 .offset = quadword_offset,
218 .cond = duplicated_cond
219 };
220
221 return branch;
222 }
223
224 static void
225 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
226 {
227 ins->has_constants = true;
228 memcpy(&ins->constants, constants, 16);
229 }
230
231 static int
232 glsl_type_size(const struct glsl_type *type, bool bindless)
233 {
234 return glsl_count_attribute_slots(type, false);
235 }
236
237 /* Lower fdot2 to a vector multiplication followed by channel addition */
238 static void
239 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
240 {
241 if (alu->op != nir_op_fdot2)
242 return;
243
244 b->cursor = nir_before_instr(&alu->instr);
245
246 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
247 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
248
249 nir_ssa_def *product = nir_fmul(b, src0, src1);
250
251 nir_ssa_def *sum = nir_fadd(b,
252 nir_channel(b, product, 0),
253 nir_channel(b, product, 1));
254
255 /* Replace the fdot2 with this sum */
256 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
257 }
258
259 static int
260 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
261 {
262 switch (instr->intrinsic) {
263 case nir_intrinsic_load_viewport_scale:
264 return PAN_SYSVAL_VIEWPORT_SCALE;
265 case nir_intrinsic_load_viewport_offset:
266 return PAN_SYSVAL_VIEWPORT_OFFSET;
267 default:
268 return -1;
269 }
270 }
271
272 static void
273 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
274 {
275 int sysval = -1;
276
277 if (instr->type == nir_instr_type_intrinsic) {
278 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
279 sysval = midgard_nir_sysval_for_intrinsic(intr);
280 }
281
282 if (sysval < 0)
283 return;
284
285 /* We have a sysval load; check if it's already been assigned */
286
287 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
288 return;
289
290 /* It hasn't -- so assign it now! */
291
292 unsigned id = ctx->sysval_count++;
293 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
294 ctx->sysvals[id] = sysval;
295 }
296
297 static void
298 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
299 {
300 ctx->sysval_count = 0;
301
302 nir_foreach_function(function, shader) {
303 if (!function->impl) continue;
304
305 nir_foreach_block(block, function->impl) {
306 nir_foreach_instr_safe(instr, block) {
307 midgard_nir_assign_sysval_body(ctx, instr);
308 }
309 }
310 }
311 }
312
313 static bool
314 midgard_nir_lower_fdot2(nir_shader *shader)
315 {
316 bool progress = false;
317
318 nir_foreach_function(function, shader) {
319 if (!function->impl) continue;
320
321 nir_builder _b;
322 nir_builder *b = &_b;
323 nir_builder_init(b, function->impl);
324
325 nir_foreach_block(block, function->impl) {
326 nir_foreach_instr_safe(instr, block) {
327 if (instr->type != nir_instr_type_alu) continue;
328
329 nir_alu_instr *alu = nir_instr_as_alu(instr);
330 midgard_nir_lower_fdot2_body(b, alu);
331
332 progress |= true;
333 }
334 }
335
336 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
337
338 }
339
340 return progress;
341 }
342
343 static void
344 optimise_nir(nir_shader *nir)
345 {
346 bool progress;
347 unsigned lower_flrp =
348 (nir->options->lower_flrp16 ? 16 : 0) |
349 (nir->options->lower_flrp32 ? 32 : 0) |
350 (nir->options->lower_flrp64 ? 64 : 0);
351
352 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
353 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
354 NIR_PASS(progress, nir, nir_lower_idiv);
355
356 nir_lower_tex_options lower_tex_options = {
357 .lower_rect = true
358 };
359
360 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
361
362 do {
363 progress = false;
364
365 NIR_PASS(progress, nir, nir_lower_var_copies);
366 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
367
368 NIR_PASS(progress, nir, nir_copy_prop);
369 NIR_PASS(progress, nir, nir_opt_dce);
370 NIR_PASS(progress, nir, nir_opt_dead_cf);
371 NIR_PASS(progress, nir, nir_opt_cse);
372 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
373 NIR_PASS(progress, nir, nir_opt_algebraic);
374 NIR_PASS(progress, nir, nir_opt_constant_folding);
375
376 if (lower_flrp != 0) {
377 bool lower_flrp_progress = false;
378 NIR_PASS(lower_flrp_progress,
379 nir,
380 nir_lower_flrp,
381 lower_flrp,
382 false /* always_precise */,
383 nir->options->lower_ffma);
384 if (lower_flrp_progress) {
385 NIR_PASS(progress, nir,
386 nir_opt_constant_folding);
387 progress = true;
388 }
389
390 /* Nothing should rematerialize any flrps, so we only
391 * need to do this lowering once.
392 */
393 lower_flrp = 0;
394 }
395
396 NIR_PASS(progress, nir, nir_opt_undef);
397 NIR_PASS(progress, nir, nir_opt_loop_unroll,
398 nir_var_shader_in |
399 nir_var_shader_out |
400 nir_var_function_temp);
401
402 /* TODO: Enable vectorize when merged upstream */
403 // NIR_PASS(progress, nir, nir_opt_vectorize);
404 } while (progress);
405
406 /* Must be run at the end to prevent creation of fsin/fcos ops */
407 NIR_PASS(progress, nir, midgard_nir_scale_trig);
408
409 do {
410 progress = false;
411
412 NIR_PASS(progress, nir, nir_opt_dce);
413 NIR_PASS(progress, nir, nir_opt_algebraic);
414 NIR_PASS(progress, nir, nir_opt_constant_folding);
415 NIR_PASS(progress, nir, nir_copy_prop);
416 } while (progress);
417
418 NIR_PASS(progress, nir, nir_opt_algebraic_late);
419
420 /* We implement booleans as 32-bit 0/~0 */
421 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
422
423 /* Now that booleans are lowered, we can run out late opts */
424 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
425
426 /* Lower mods for float ops only. Integer ops don't support modifiers
427 * (saturate doesn't make sense on integers, neg/abs require dedicated
428 * instructions) */
429
430 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
431 NIR_PASS(progress, nir, nir_copy_prop);
432 NIR_PASS(progress, nir, nir_opt_dce);
433
434 /* Take us out of SSA */
435 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
436 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
437
438 /* We are a vector architecture; write combine where possible */
439 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
440 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
441
442 NIR_PASS(progress, nir, nir_opt_dce);
443 }
444
445 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
446 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
447 * r0. See the comments in compiler_context */
448
449 static void
450 alias_ssa(compiler_context *ctx, int dest, int src)
451 {
452 _mesa_hash_table_u64_insert(ctx->ssa_to_alias, dest + 1, (void *) ((uintptr_t) src + 1));
453 _mesa_set_add(ctx->leftover_ssa_to_alias, (void *) (uintptr_t) (dest + 1));
454 }
455
456 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
457
458 static void
459 unalias_ssa(compiler_context *ctx, int dest)
460 {
461 _mesa_hash_table_u64_remove(ctx->ssa_to_alias, dest + 1);
462 /* TODO: Remove from leftover or no? */
463 }
464
465 /* Do not actually emit a load; instead, cache the constant for inlining */
466
467 static void
468 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
469 {
470 nir_ssa_def def = instr->def;
471
472 float *v = rzalloc_array(NULL, float, 4);
473 nir_const_load_to_arr(v, instr, f32);
474 _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
475 }
476
477 static unsigned
478 nir_src_index(compiler_context *ctx, nir_src *src)
479 {
480 if (src->is_ssa)
481 return src->ssa->index;
482 else {
483 assert(!src->reg.indirect);
484 return ctx->func->impl->ssa_alloc + src->reg.reg->index;
485 }
486 }
487
488 static unsigned
489 nir_dest_index(compiler_context *ctx, nir_dest *dst)
490 {
491 if (dst->is_ssa)
492 return dst->ssa.index;
493 else {
494 assert(!dst->reg.indirect);
495 return ctx->func->impl->ssa_alloc + dst->reg.reg->index;
496 }
497 }
498
499 static unsigned
500 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
501 {
502 return nir_src_index(ctx, &src->src);
503 }
504
505 static bool
506 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
507 {
508 unsigned comp = src->swizzle[0];
509
510 for (unsigned c = 1; c < nr_components; ++c) {
511 if (src->swizzle[c] != comp)
512 return true;
513 }
514
515 return false;
516 }
517
518 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
519 * output of a conditional test) into that register */
520
521 static void
522 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
523 {
524 int condition = nir_src_index(ctx, src);
525
526 /* Source to swizzle the desired component into w */
527
528 const midgard_vector_alu_src alu_src = {
529 .swizzle = SWIZZLE(component, component, component, component),
530 };
531
532 /* There is no boolean move instruction. Instead, we simulate a move by
533 * ANDing the condition with itself to get it into r31.w */
534
535 midgard_instruction ins = {
536 .type = TAG_ALU_4,
537
538 /* We need to set the conditional as close as possible */
539 .precede_break = true,
540 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
541
542 .ssa_args = {
543
544 .src0 = condition,
545 .src1 = condition,
546 .dest = SSA_FIXED_REGISTER(31),
547 },
548 .alu = {
549 .op = midgard_alu_op_iand,
550 .outmod = midgard_outmod_int,
551 .reg_mode = midgard_reg_mode_32,
552 .dest_override = midgard_dest_override_none,
553 .mask = (0x3 << 6), /* w */
554 .src1 = vector_alu_srco_unsigned(alu_src),
555 .src2 = vector_alu_srco_unsigned(alu_src)
556 },
557 };
558
559 emit_mir_instruction(ctx, ins);
560 }
561
562 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
563 * r31 instead */
564
565 static void
566 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
567 {
568 int condition = nir_src_index(ctx, &src->src);
569
570 /* Source to swizzle the desired component into w */
571
572 const midgard_vector_alu_src alu_src = {
573 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
574 };
575
576 /* There is no boolean move instruction. Instead, we simulate a move by
577 * ANDing the condition with itself to get it into r31.w */
578
579 midgard_instruction ins = {
580 .type = TAG_ALU_4,
581 .precede_break = true,
582 .ssa_args = {
583 .src0 = condition,
584 .src1 = condition,
585 .dest = SSA_FIXED_REGISTER(31),
586 },
587 .alu = {
588 .op = midgard_alu_op_iand,
589 .outmod = midgard_outmod_int,
590 .reg_mode = midgard_reg_mode_32,
591 .dest_override = midgard_dest_override_none,
592 .mask = expand_writemask((1 << nr_comp) - 1),
593 .src1 = vector_alu_srco_unsigned(alu_src),
594 .src2 = vector_alu_srco_unsigned(alu_src)
595 },
596 };
597
598 emit_mir_instruction(ctx, ins);
599 }
600
601
602
603 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
604 * pinning to eliminate this move in all known cases */
605
606 static void
607 emit_indirect_offset(compiler_context *ctx, nir_src *src)
608 {
609 int offset = nir_src_index(ctx, src);
610
611 midgard_instruction ins = {
612 .type = TAG_ALU_4,
613 .ssa_args = {
614 .src0 = SSA_UNUSED_1,
615 .src1 = offset,
616 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
617 },
618 .alu = {
619 .op = midgard_alu_op_imov,
620 .outmod = midgard_outmod_int,
621 .reg_mode = midgard_reg_mode_32,
622 .dest_override = midgard_dest_override_none,
623 .mask = (0x3 << 6), /* w */
624 .src1 = vector_alu_srco_unsigned(zero_alu_src),
625 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
626 },
627 };
628
629 emit_mir_instruction(ctx, ins);
630 }
631
632 #define ALU_CASE(nir, _op) \
633 case nir_op_##nir: \
634 op = midgard_alu_op_##_op; \
635 break;
636 static bool
637 nir_is_fzero_constant(nir_src src)
638 {
639 if (!nir_src_is_const(src))
640 return false;
641
642 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
643 if (nir_src_comp_as_float(src, c) != 0.0)
644 return false;
645 }
646
647 return true;
648 }
649
650 static void
651 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
652 {
653 bool is_ssa = instr->dest.dest.is_ssa;
654
655 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
656 unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components;
657 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
658
659 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
660 * supported. A few do not and are commented for now. Also, there are a
661 * number of NIR ops which Midgard does not support and need to be
662 * lowered, also TODO. This switch block emits the opcode and calling
663 * convention of the Midgard instruction; actual packing is done in
664 * emit_alu below */
665
666 unsigned op;
667
668 switch (instr->op) {
669 ALU_CASE(fadd, fadd);
670 ALU_CASE(fmul, fmul);
671 ALU_CASE(fmin, fmin);
672 ALU_CASE(fmax, fmax);
673 ALU_CASE(imin, imin);
674 ALU_CASE(imax, imax);
675 ALU_CASE(umin, umin);
676 ALU_CASE(umax, umax);
677 ALU_CASE(ffloor, ffloor);
678 ALU_CASE(fround_even, froundeven);
679 ALU_CASE(ftrunc, ftrunc);
680 ALU_CASE(fceil, fceil);
681 ALU_CASE(fdot3, fdot3);
682 ALU_CASE(fdot4, fdot4);
683 ALU_CASE(iadd, iadd);
684 ALU_CASE(isub, isub);
685 ALU_CASE(imul, imul);
686
687 /* Zero shoved as second-arg */
688 ALU_CASE(iabs, iabsdiff);
689
690 ALU_CASE(mov, imov);
691
692 ALU_CASE(feq32, feq);
693 ALU_CASE(fne32, fne);
694 ALU_CASE(flt32, flt);
695 ALU_CASE(ieq32, ieq);
696 ALU_CASE(ine32, ine);
697 ALU_CASE(ilt32, ilt);
698 ALU_CASE(ult32, ult);
699
700 /* We don't have a native b2f32 instruction. Instead, like many
701 * GPUs, we exploit booleans as 0/~0 for false/true, and
702 * correspondingly AND
703 * by 1.0 to do the type conversion. For the moment, prime us
704 * to emit:
705 *
706 * iand [whatever], #0
707 *
708 * At the end of emit_alu (as MIR), we'll fix-up the constant
709 */
710
711 ALU_CASE(b2f32, iand);
712 ALU_CASE(b2i32, iand);
713
714 /* Likewise, we don't have a dedicated f2b32 instruction, but
715 * we can do a "not equal to 0.0" test. */
716
717 ALU_CASE(f2b32, fne);
718 ALU_CASE(i2b32, ine);
719
720 ALU_CASE(frcp, frcp);
721 ALU_CASE(frsq, frsqrt);
722 ALU_CASE(fsqrt, fsqrt);
723 ALU_CASE(fexp2, fexp2);
724 ALU_CASE(flog2, flog2);
725
726 ALU_CASE(f2i32, f2i);
727 ALU_CASE(f2u32, f2u);
728 ALU_CASE(i2f32, i2f);
729 ALU_CASE(u2f32, u2f);
730
731 ALU_CASE(fsin, fsin);
732 ALU_CASE(fcos, fcos);
733
734 ALU_CASE(iand, iand);
735 ALU_CASE(ior, ior);
736 ALU_CASE(ixor, ixor);
737 ALU_CASE(inot, inand);
738 ALU_CASE(ishl, ishl);
739 ALU_CASE(ishr, iasr);
740 ALU_CASE(ushr, ilsr);
741
742 ALU_CASE(b32all_fequal2, fball_eq);
743 ALU_CASE(b32all_fequal3, fball_eq);
744 ALU_CASE(b32all_fequal4, fball_eq);
745
746 ALU_CASE(b32any_fnequal2, fbany_neq);
747 ALU_CASE(b32any_fnequal3, fbany_neq);
748 ALU_CASE(b32any_fnequal4, fbany_neq);
749
750 ALU_CASE(b32all_iequal2, iball_eq);
751 ALU_CASE(b32all_iequal3, iball_eq);
752 ALU_CASE(b32all_iequal4, iball_eq);
753
754 ALU_CASE(b32any_inequal2, ibany_neq);
755 ALU_CASE(b32any_inequal3, ibany_neq);
756 ALU_CASE(b32any_inequal4, ibany_neq);
757
758 /* Source mods will be shoved in later */
759 ALU_CASE(fabs, fmov);
760 ALU_CASE(fneg, fmov);
761 ALU_CASE(fsat, fmov);
762
763 /* For greater-or-equal, we lower to less-or-equal and flip the
764 * arguments */
765
766 case nir_op_fge:
767 case nir_op_fge32:
768 case nir_op_ige32:
769 case nir_op_uge32: {
770 op =
771 instr->op == nir_op_fge ? midgard_alu_op_fle :
772 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
773 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
774 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
775 0;
776
777 /* Swap via temporary */
778 nir_alu_src temp = instr->src[1];
779 instr->src[1] = instr->src[0];
780 instr->src[0] = temp;
781
782 break;
783 }
784
785 case nir_op_b32csel: {
786 /* Midgard features both fcsel and icsel, depending on
787 * the type of the arguments/output. However, as long
788 * as we're careful we can _always_ use icsel and
789 * _never_ need fcsel, since the latter does additional
790 * floating-point-specific processing whereas the
791 * former just moves bits on the wire. It's not obvious
792 * why these are separate opcodes, save for the ability
793 * to do things like sat/pos/abs/neg for free */
794
795 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
796 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
797
798 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
799 nr_inputs = 2;
800
801 /* Emit the condition into r31 */
802
803 if (mixed)
804 emit_condition_mixed(ctx, &instr->src[0], nr_components);
805 else
806 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
807
808 /* The condition is the first argument; move the other
809 * arguments up one to be a binary instruction for
810 * Midgard */
811
812 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
813 break;
814 }
815
816 default:
817 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
818 assert(0);
819 return;
820 }
821
822 /* Midgard can perform certain modifiers on output of an ALU op */
823 midgard_outmod outmod =
824 midgard_is_integer_out_op(op) ? midgard_outmod_int :
825 instr->dest.saturate ? midgard_outmod_sat : midgard_outmod_none;
826
827 if (instr->op == nir_op_fsat)
828 outmod = midgard_outmod_sat;
829
830 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
831
832 if (instr->op == nir_op_fmax) {
833 if (nir_is_fzero_constant(instr->src[0].src)) {
834 op = midgard_alu_op_fmov;
835 nr_inputs = 1;
836 outmod = midgard_outmod_pos;
837 instr->src[0] = instr->src[1];
838 } else if (nir_is_fzero_constant(instr->src[1].src)) {
839 op = midgard_alu_op_fmov;
840 nr_inputs = 1;
841 outmod = midgard_outmod_pos;
842 }
843 }
844
845 /* Fetch unit, quirks, etc information */
846 unsigned opcode_props = alu_opcode_props[op].props;
847 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
848
849 /* src0 will always exist afaik, but src1 will not for 1-argument
850 * instructions. The latter can only be fetched if the instruction
851 * needs it, or else we may segfault. */
852
853 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
854 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
855
856 /* Rather than use the instruction generation helpers, we do it
857 * ourselves here to avoid the mess */
858
859 midgard_instruction ins = {
860 .type = TAG_ALU_4,
861 .ssa_args = {
862 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
863 .src1 = quirk_flipped_r24 ? src0 : src1,
864 .dest = dest,
865 }
866 };
867
868 nir_alu_src *nirmods[2] = { NULL };
869
870 if (nr_inputs == 2) {
871 nirmods[0] = &instr->src[0];
872 nirmods[1] = &instr->src[1];
873 } else if (nr_inputs == 1) {
874 nirmods[quirk_flipped_r24] = &instr->src[0];
875 } else {
876 assert(0);
877 }
878
879 /* These were lowered to a move, so apply the corresponding mod */
880
881 if (instr->op == nir_op_fneg || instr->op == nir_op_fabs) {
882 nir_alu_src *s = nirmods[quirk_flipped_r24];
883
884 if (instr->op == nir_op_fneg)
885 s->negate = !s->negate;
886
887 if (instr->op == nir_op_fabs)
888 s->abs = !s->abs;
889 }
890
891 bool is_int = midgard_is_integer_op(op);
892
893 midgard_vector_alu alu = {
894 .op = op,
895 .reg_mode = midgard_reg_mode_32,
896 .dest_override = midgard_dest_override_none,
897 .outmod = outmod,
898
899 /* Writemask only valid for non-SSA NIR */
900 .mask = expand_writemask((1 << nr_components) - 1),
901
902 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int)),
903 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int)),
904 };
905
906 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
907
908 if (!is_ssa)
909 alu.mask &= expand_writemask(instr->dest.write_mask);
910
911 ins.alu = alu;
912
913 /* Late fixup for emulated instructions */
914
915 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
916 /* Presently, our second argument is an inline #0 constant.
917 * Switch over to an embedded 1.0 constant (that can't fit
918 * inline, since we're 32-bit, not 16-bit like the inline
919 * constants) */
920
921 ins.ssa_args.inline_constant = false;
922 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
923 ins.has_constants = true;
924
925 if (instr->op == nir_op_b2f32) {
926 ins.constants[0] = 1.0f;
927 } else {
928 /* Type pun it into place */
929 uint32_t one = 0x1;
930 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
931 }
932
933 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
934 } else if (nr_inputs == 1 && !quirk_flipped_r24) {
935 /* Lots of instructions need a 0 plonked in */
936 ins.ssa_args.inline_constant = false;
937 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
938 ins.has_constants = true;
939 ins.constants[0] = 0.0f;
940 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
941 } else if (instr->op == nir_op_inot) {
942 /* ~b = ~(b & b), so duplicate the source */
943 ins.ssa_args.src1 = ins.ssa_args.src0;
944 ins.alu.src2 = ins.alu.src1;
945 }
946
947 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
948 /* To avoid duplicating the lookup tables (probably), true LUT
949 * instructions can only operate as if they were scalars. Lower
950 * them here by changing the component. */
951
952 uint8_t original_swizzle[4];
953 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
954
955 for (int i = 0; i < nr_components; ++i) {
956 ins.alu.mask = (0x3) << (2 * i); /* Mask the associated component */
957
958 for (int j = 0; j < 4; ++j)
959 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
960
961 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int));
962 emit_mir_instruction(ctx, ins);
963 }
964 } else {
965 emit_mir_instruction(ctx, ins);
966 }
967 }
968
969 #undef ALU_CASE
970
971 static void
972 emit_uniform_read(compiler_context *ctx, unsigned dest, unsigned offset, nir_src *indirect_offset)
973 {
974 /* TODO: half-floats */
975
976 if (!indirect_offset && offset < ctx->uniform_cutoff) {
977 /* Fast path: For the first 16 uniforms, direct accesses are
978 * 0-cycle, since they're just a register fetch in the usual
979 * case. So, we alias the registers while we're still in
980 * SSA-space */
981
982 int reg_slot = 23 - offset;
983 alias_ssa(ctx, dest, SSA_FIXED_REGISTER(reg_slot));
984 } else {
985 /* Otherwise, read from the 'special' UBO to access
986 * higher-indexed uniforms, at a performance cost. More
987 * generally, we're emitting a UBO read instruction. */
988
989 midgard_instruction ins = m_ld_uniform_32(dest, offset);
990
991 /* TODO: Don't split */
992 ins.load_store.varying_parameters = (offset & 7) << 7;
993 ins.load_store.address = offset >> 3;
994
995 if (indirect_offset) {
996 emit_indirect_offset(ctx, indirect_offset);
997 ins.load_store.unknown = 0x8700; /* xxx: what is this? */
998 } else {
999 ins.load_store.unknown = 0x1E00; /* xxx: what is this? */
1000 }
1001
1002 emit_mir_instruction(ctx, ins);
1003 }
1004 }
1005
1006 static void
1007 emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
1008 {
1009 /* First, pull out the destination */
1010 unsigned dest = nir_dest_index(ctx, &instr->dest);
1011
1012 /* Now, figure out which uniform this is */
1013 int sysval = midgard_nir_sysval_for_intrinsic(instr);
1014 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1015
1016 /* Sysvals are prefix uniforms */
1017 unsigned uniform = ((uintptr_t) val) - 1;
1018
1019 /* Emit the read itself -- this is never indirect */
1020 emit_uniform_read(ctx, dest, uniform, NULL);
1021 }
1022
1023 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1024 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1025 * generations have faster vectorized reads. This operation is for blend
1026 * shaders in particular; reading the tilebuffer from the fragment shader
1027 * remains an open problem. */
1028
1029 static void
1030 emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
1031 {
1032 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1033 ins.load_store.swizzle = 0; /* xxxx */
1034
1035 /* Read each component sequentially */
1036
1037 for (unsigned c = 0; c < 4; ++c) {
1038 ins.load_store.mask = (1 << c);
1039 ins.load_store.unknown = c;
1040 emit_mir_instruction(ctx, ins);
1041 }
1042
1043 /* vadd.u2f hr2, zext(hr2), #0 */
1044
1045 midgard_vector_alu_src alu_src = blank_alu_src;
1046 alu_src.mod = midgard_int_zero_extend;
1047 alu_src.half = true;
1048
1049 midgard_instruction u2f = {
1050 .type = TAG_ALU_4,
1051 .ssa_args = {
1052 .src0 = reg,
1053 .src1 = SSA_UNUSED_0,
1054 .dest = reg,
1055 .inline_constant = true
1056 },
1057 .alu = {
1058 .op = midgard_alu_op_u2f,
1059 .reg_mode = midgard_reg_mode_16,
1060 .dest_override = midgard_dest_override_none,
1061 .mask = 0xF,
1062 .src1 = vector_alu_srco_unsigned(alu_src),
1063 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1064 }
1065 };
1066
1067 emit_mir_instruction(ctx, u2f);
1068
1069 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1070
1071 alu_src.mod = 0;
1072
1073 midgard_instruction fmul = {
1074 .type = TAG_ALU_4,
1075 .inline_constant = _mesa_float_to_half(1.0 / 255.0),
1076 .ssa_args = {
1077 .src0 = reg,
1078 .dest = reg,
1079 .src1 = SSA_UNUSED_0,
1080 .inline_constant = true
1081 },
1082 .alu = {
1083 .op = midgard_alu_op_fmul,
1084 .reg_mode = midgard_reg_mode_32,
1085 .dest_override = midgard_dest_override_none,
1086 .outmod = midgard_outmod_sat,
1087 .mask = 0xFF,
1088 .src1 = vector_alu_srco_unsigned(alu_src),
1089 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1090 }
1091 };
1092
1093 emit_mir_instruction(ctx, fmul);
1094 }
1095
1096 static void
1097 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1098 {
1099 unsigned offset, reg;
1100
1101 switch (instr->intrinsic) {
1102 case nir_intrinsic_discard_if:
1103 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1104
1105 /* fallthrough */
1106
1107 case nir_intrinsic_discard: {
1108 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1109 struct midgard_instruction discard = v_branch(conditional, false);
1110 discard.branch.target_type = TARGET_DISCARD;
1111 emit_mir_instruction(ctx, discard);
1112
1113 ctx->can_discard = true;
1114 break;
1115 }
1116
1117 case nir_intrinsic_load_uniform:
1118 case nir_intrinsic_load_input:
1119 offset = nir_intrinsic_base(instr);
1120
1121 unsigned nr_comp = nir_intrinsic_dest_components(instr);
1122 bool direct = nir_src_is_const(instr->src[0]);
1123
1124 if (direct) {
1125 offset += nir_src_as_uint(instr->src[0]);
1126 }
1127
1128 /* We may need to apply a fractional offset */
1129 int component = instr->intrinsic == nir_intrinsic_load_input ?
1130 nir_intrinsic_component(instr) : 0;
1131 reg = nir_dest_index(ctx, &instr->dest);
1132
1133 if (instr->intrinsic == nir_intrinsic_load_uniform && !ctx->is_blend) {
1134 emit_uniform_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL);
1135 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1136 /* XXX: Half-floats? */
1137 /* TODO: swizzle, mask */
1138
1139 midgard_instruction ins = m_ld_vary_32(reg, offset);
1140 ins.load_store.mask = (1 << nr_comp) - 1;
1141 ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component);
1142
1143 midgard_varying_parameter p = {
1144 .is_varying = 1,
1145 .interpolation = midgard_interp_default,
1146 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1147 };
1148
1149 unsigned u;
1150 memcpy(&u, &p, sizeof(p));
1151 ins.load_store.varying_parameters = u;
1152
1153 if (direct) {
1154 /* We have the offset totally ready */
1155 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1156 } else {
1157 /* We have it partially ready, but we need to
1158 * add in the dynamic index, moved to r27.w */
1159 emit_indirect_offset(ctx, &instr->src[0]);
1160 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1161 }
1162
1163 emit_mir_instruction(ctx, ins);
1164 } else if (ctx->is_blend) {
1165 /* For blend shaders, load the input color, which is
1166 * preloaded to r0 */
1167
1168 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1169 emit_mir_instruction(ctx, move);
1170 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1171 midgard_instruction ins = m_ld_attr_32(reg, offset);
1172 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1173 ins.load_store.mask = (1 << nr_comp) - 1;
1174 emit_mir_instruction(ctx, ins);
1175 } else {
1176 DBG("Unknown load\n");
1177 assert(0);
1178 }
1179
1180 break;
1181
1182 case nir_intrinsic_load_output:
1183 assert(nir_src_is_const(instr->src[0]));
1184 reg = nir_dest_index(ctx, &instr->dest);
1185
1186 if (ctx->is_blend) {
1187 /* TODO: MRT */
1188 emit_fb_read_blend_scalar(ctx, reg);
1189 } else {
1190 DBG("Unknown output load\n");
1191 assert(0);
1192 }
1193
1194 break;
1195
1196 case nir_intrinsic_load_blend_const_color_rgba: {
1197 assert(ctx->is_blend);
1198 reg = nir_dest_index(ctx, &instr->dest);
1199
1200 /* Blend constants are embedded directly in the shader and
1201 * patched in, so we use some magic routing */
1202
1203 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1204 ins.has_constants = true;
1205 ins.has_blend_constant = true;
1206 emit_mir_instruction(ctx, ins);
1207 break;
1208 }
1209
1210 case nir_intrinsic_store_output:
1211 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1212
1213 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1214
1215 reg = nir_src_index(ctx, &instr->src[0]);
1216
1217 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1218 /* gl_FragColor is not emitted with load/store
1219 * instructions. Instead, it gets plonked into
1220 * r0 at the end of the shader and we do the
1221 * framebuffer writeout dance. TODO: Defer
1222 * writes */
1223
1224 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1225 emit_mir_instruction(ctx, move);
1226
1227 /* Save the index we're writing to for later reference
1228 * in the epilogue */
1229
1230 ctx->fragment_output = reg;
1231 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1232 /* Varyings are written into one of two special
1233 * varying register, r26 or r27. The register itself is
1234 * selected as the register in the st_vary instruction,
1235 * minus the base of 26. E.g. write into r27 and then
1236 * call st_vary(1) */
1237
1238 midgard_instruction ins = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(26));
1239 emit_mir_instruction(ctx, ins);
1240
1241 /* We should have been vectorized. That also lets us
1242 * ignore the mask. because the mask component on
1243 * st_vary is (as far as I can tell) ignored [the blob
1244 * sets it to zero] */
1245 assert(nir_intrinsic_component(instr) == 0);
1246
1247 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset);
1248 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1249 emit_mir_instruction(ctx, st);
1250 } else {
1251 DBG("Unknown store\n");
1252 assert(0);
1253 }
1254
1255 break;
1256
1257 case nir_intrinsic_load_alpha_ref_float:
1258 assert(instr->dest.is_ssa);
1259
1260 float ref_value = ctx->alpha_ref;
1261
1262 float *v = ralloc_array(NULL, float, 4);
1263 memcpy(v, &ref_value, sizeof(float));
1264 _mesa_hash_table_u64_insert(ctx->ssa_constants, instr->dest.ssa.index + 1, v);
1265 break;
1266
1267 case nir_intrinsic_load_viewport_scale:
1268 case nir_intrinsic_load_viewport_offset:
1269 emit_sysval_read(ctx, instr);
1270 break;
1271
1272 default:
1273 printf ("Unhandled intrinsic\n");
1274 assert(0);
1275 break;
1276 }
1277 }
1278
1279 static unsigned
1280 midgard_tex_format(enum glsl_sampler_dim dim)
1281 {
1282 switch (dim) {
1283 case GLSL_SAMPLER_DIM_2D:
1284 case GLSL_SAMPLER_DIM_EXTERNAL:
1285 return TEXTURE_2D;
1286
1287 case GLSL_SAMPLER_DIM_3D:
1288 return TEXTURE_3D;
1289
1290 case GLSL_SAMPLER_DIM_CUBE:
1291 return TEXTURE_CUBE;
1292
1293 default:
1294 DBG("Unknown sampler dim type\n");
1295 assert(0);
1296 return 0;
1297 }
1298 }
1299
1300 static void
1301 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1302 {
1303 /* TODO */
1304 //assert (!instr->sampler);
1305 //assert (!instr->texture_array_size);
1306 assert (instr->op == nir_texop_tex);
1307
1308 /* Allocate registers via a round robin scheme to alternate between the two registers */
1309 int reg = ctx->texture_op_count & 1;
1310 int in_reg = reg, out_reg = reg;
1311
1312 /* Make room for the reg */
1313
1314 if (ctx->texture_index[reg] > -1)
1315 unalias_ssa(ctx, ctx->texture_index[reg]);
1316
1317 int texture_index = instr->texture_index;
1318 int sampler_index = texture_index;
1319
1320 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1321 switch (instr->src[i].src_type) {
1322 case nir_tex_src_coord: {
1323 int index = nir_src_index(ctx, &instr->src[i].src);
1324
1325 midgard_vector_alu_src alu_src = blank_alu_src;
1326
1327 int reg = SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + in_reg);
1328
1329 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1330 /* For cubemaps, we need to load coords into
1331 * special r27, and then use a special ld/st op
1332 * to copy into the texture register */
1333
1334 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X);
1335
1336 midgard_instruction move = v_fmov(index, alu_src, SSA_FIXED_REGISTER(27));
1337 emit_mir_instruction(ctx, move);
1338
1339 midgard_instruction st = m_st_cubemap_coords(reg, 0);
1340 st.load_store.unknown = 0x24; /* XXX: What is this? */
1341 st.load_store.mask = 0x3; /* xy? */
1342 st.load_store.swizzle = alu_src.swizzle;
1343 emit_mir_instruction(ctx, st);
1344
1345 } else {
1346 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X);
1347
1348 midgard_instruction ins = v_fmov(index, alu_src, reg);
1349 emit_mir_instruction(ctx, ins);
1350 }
1351
1352 break;
1353 }
1354
1355 default: {
1356 DBG("Unknown source type\n");
1357 //assert(0);
1358 break;
1359 }
1360 }
1361 }
1362
1363 /* No helper to build texture words -- we do it all here */
1364 midgard_instruction ins = {
1365 .type = TAG_TEXTURE_4,
1366 .texture = {
1367 .op = TEXTURE_OP_NORMAL,
1368 .format = midgard_tex_format(instr->sampler_dim),
1369 .texture_handle = texture_index,
1370 .sampler_handle = sampler_index,
1371
1372 /* TODO: Don't force xyzw */
1373 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
1374 .mask = 0xF,
1375
1376 /* TODO: half */
1377 //.in_reg_full = 1,
1378 .out_full = 1,
1379
1380 .filter = 1,
1381
1382 /* Always 1 */
1383 .unknown7 = 1,
1384
1385 /* Assume we can continue; hint it out later */
1386 .cont = 1,
1387 }
1388 };
1389
1390 /* Set registers to read and write from the same place */
1391 ins.texture.in_reg_select = in_reg;
1392 ins.texture.out_reg_select = out_reg;
1393
1394 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1395 if (instr->sampler_dim == GLSL_SAMPLER_DIM_3D) {
1396 ins.texture.in_reg_swizzle_right = COMPONENT_X;
1397 ins.texture.in_reg_swizzle_left = COMPONENT_Y;
1398 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1399 } else {
1400 ins.texture.in_reg_swizzle_left = COMPONENT_X;
1401 ins.texture.in_reg_swizzle_right = COMPONENT_Y;
1402 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1403 }
1404
1405 emit_mir_instruction(ctx, ins);
1406
1407 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1408
1409 int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest);
1410 alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg));
1411 ctx->texture_index[reg] = o_index;
1412
1413 midgard_instruction ins2 = v_fmov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index);
1414 emit_mir_instruction(ctx, ins2);
1415
1416 /* Used for .cont and .last hinting */
1417 ctx->texture_op_count++;
1418 }
1419
1420 static void
1421 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1422 {
1423 switch (instr->type) {
1424 case nir_jump_break: {
1425 /* Emit a branch out of the loop */
1426 struct midgard_instruction br = v_branch(false, false);
1427 br.branch.target_type = TARGET_BREAK;
1428 br.branch.target_break = ctx->current_loop_depth;
1429 emit_mir_instruction(ctx, br);
1430
1431 DBG("break..\n");
1432 break;
1433 }
1434
1435 default:
1436 DBG("Unknown jump type %d\n", instr->type);
1437 break;
1438 }
1439 }
1440
1441 static void
1442 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1443 {
1444 switch (instr->type) {
1445 case nir_instr_type_load_const:
1446 emit_load_const(ctx, nir_instr_as_load_const(instr));
1447 break;
1448
1449 case nir_instr_type_intrinsic:
1450 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1451 break;
1452
1453 case nir_instr_type_alu:
1454 emit_alu(ctx, nir_instr_as_alu(instr));
1455 break;
1456
1457 case nir_instr_type_tex:
1458 emit_tex(ctx, nir_instr_as_tex(instr));
1459 break;
1460
1461 case nir_instr_type_jump:
1462 emit_jump(ctx, nir_instr_as_jump(instr));
1463 break;
1464
1465 case nir_instr_type_ssa_undef:
1466 /* Spurious */
1467 break;
1468
1469 default:
1470 DBG("Unhandled instruction type\n");
1471 break;
1472 }
1473 }
1474
1475
1476 /* ALU instructions can inline or embed constants, which decreases register
1477 * pressure and saves space. */
1478
1479 #define CONDITIONAL_ATTACH(src) { \
1480 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1481 \
1482 if (entry) { \
1483 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1484 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1485 } \
1486 }
1487
1488 static void
1489 inline_alu_constants(compiler_context *ctx)
1490 {
1491 mir_foreach_instr(ctx, alu) {
1492 /* Other instructions cannot inline constants */
1493 if (alu->type != TAG_ALU_4) continue;
1494
1495 /* If there is already a constant here, we can do nothing */
1496 if (alu->has_constants) continue;
1497
1498 /* It makes no sense to inline constants on a branch */
1499 if (alu->compact_branch || alu->prepacked_branch) continue;
1500
1501 CONDITIONAL_ATTACH(src0);
1502
1503 if (!alu->has_constants) {
1504 CONDITIONAL_ATTACH(src1)
1505 } else if (!alu->inline_constant) {
1506 /* Corner case: _two_ vec4 constants, for instance with a
1507 * csel. For this case, we can only use a constant
1508 * register for one, we'll have to emit a move for the
1509 * other. Note, if both arguments are constants, then
1510 * necessarily neither argument depends on the value of
1511 * any particular register. As the destination register
1512 * will be wiped, that means we can spill the constant
1513 * to the destination register.
1514 */
1515
1516 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
1517 unsigned scratch = alu->ssa_args.dest;
1518
1519 if (entry) {
1520 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
1521 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
1522
1523 /* Force a break XXX Defer r31 writes */
1524 ins.unit = UNIT_VLUT;
1525
1526 /* Set the source */
1527 alu->ssa_args.src1 = scratch;
1528
1529 /* Inject us -before- the last instruction which set r31 */
1530 mir_insert_instruction_before(mir_prev_op(alu), ins);
1531 }
1532 }
1533 }
1534 }
1535
1536 /* Midgard supports two types of constants, embedded constants (128-bit) and
1537 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1538 * constants can be demoted to inline constants, for space savings and
1539 * sometimes a performance boost */
1540
1541 static void
1542 embedded_to_inline_constant(compiler_context *ctx)
1543 {
1544 mir_foreach_instr(ctx, ins) {
1545 if (!ins->has_constants) continue;
1546
1547 if (ins->ssa_args.inline_constant) continue;
1548
1549 /* Blend constants must not be inlined by definition */
1550 if (ins->has_blend_constant) continue;
1551
1552 /* src1 cannot be an inline constant due to encoding
1553 * restrictions. So, if possible we try to flip the arguments
1554 * in that case */
1555
1556 int op = ins->alu.op;
1557
1558 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1559 switch (op) {
1560 /* These ops require an operational change to flip
1561 * their arguments TODO */
1562 case midgard_alu_op_flt:
1563 case midgard_alu_op_fle:
1564 case midgard_alu_op_ilt:
1565 case midgard_alu_op_ile:
1566 case midgard_alu_op_fcsel:
1567 case midgard_alu_op_icsel:
1568 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
1569 default:
1570 break;
1571 }
1572
1573 if (alu_opcode_props[op].props & OP_COMMUTES) {
1574 /* Flip the SSA numbers */
1575 ins->ssa_args.src0 = ins->ssa_args.src1;
1576 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1577
1578 /* And flip the modifiers */
1579
1580 unsigned src_temp;
1581
1582 src_temp = ins->alu.src2;
1583 ins->alu.src2 = ins->alu.src1;
1584 ins->alu.src1 = src_temp;
1585 }
1586 }
1587
1588 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
1589 /* Extract the source information */
1590
1591 midgard_vector_alu_src *src;
1592 int q = ins->alu.src2;
1593 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1594 src = m;
1595
1596 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1597 int component = src->swizzle & 3;
1598
1599 /* Scale constant appropriately, if we can legally */
1600 uint16_t scaled_constant = 0;
1601
1602 if (midgard_is_integer_op(op)) {
1603 unsigned int *iconstants = (unsigned int *) ins->constants;
1604 scaled_constant = (uint16_t) iconstants[component];
1605
1606 /* Constant overflow after resize */
1607 if (scaled_constant != iconstants[component])
1608 continue;
1609 } else {
1610 float original = (float) ins->constants[component];
1611 scaled_constant = _mesa_float_to_half(original);
1612
1613 /* Check for loss of precision. If this is
1614 * mediump, we don't care, but for a highp
1615 * shader, we need to pay attention. NIR
1616 * doesn't yet tell us which mode we're in!
1617 * Practically this prevents most constants
1618 * from being inlined, sadly. */
1619
1620 float fp32 = _mesa_half_to_float(scaled_constant);
1621
1622 if (fp32 != original)
1623 continue;
1624 }
1625
1626 /* We don't know how to handle these with a constant */
1627
1628 if (src->mod || src->half || src->rep_low || src->rep_high) {
1629 DBG("Bailing inline constant...\n");
1630 continue;
1631 }
1632
1633 /* Make sure that the constant is not itself a
1634 * vector by checking if all accessed values
1635 * (by the swizzle) are the same. */
1636
1637 uint32_t *cons = (uint32_t *) ins->constants;
1638 uint32_t value = cons[component];
1639
1640 bool is_vector = false;
1641 unsigned mask = effective_writemask(&ins->alu);
1642
1643 for (int c = 1; c < 4; ++c) {
1644 /* We only care if this component is actually used */
1645 if (!(mask & (1 << c)))
1646 continue;
1647
1648 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
1649
1650 if (test != value) {
1651 is_vector = true;
1652 break;
1653 }
1654 }
1655
1656 if (is_vector)
1657 continue;
1658
1659 /* Get rid of the embedded constant */
1660 ins->has_constants = false;
1661 ins->ssa_args.src1 = SSA_UNUSED_0;
1662 ins->ssa_args.inline_constant = true;
1663 ins->inline_constant = scaled_constant;
1664 }
1665 }
1666 }
1667
1668 /* Map normal SSA sources to other SSA sources / fixed registers (like
1669 * uniforms) */
1670
1671 static void
1672 map_ssa_to_alias(compiler_context *ctx, int *ref)
1673 {
1674 /* Sign is used quite deliberately for unused */
1675 if (*ref < 0)
1676 return;
1677
1678 unsigned int alias = (uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_to_alias, *ref + 1);
1679
1680 if (alias) {
1681 /* Remove entry in leftovers to avoid a redunant fmov */
1682
1683 struct set_entry *leftover = _mesa_set_search(ctx->leftover_ssa_to_alias, ((void *) (uintptr_t) (*ref + 1)));
1684
1685 if (leftover)
1686 _mesa_set_remove(ctx->leftover_ssa_to_alias, leftover);
1687
1688 /* Assign the alias map */
1689 *ref = alias - 1;
1690 return;
1691 }
1692 }
1693
1694 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1695 * texture pipeline */
1696
1697 static bool
1698 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
1699 {
1700 bool progress = false;
1701
1702 mir_foreach_instr_in_block_safe(block, ins) {
1703 if (ins->type != TAG_ALU_4) continue;
1704 if (ins->compact_branch) continue;
1705
1706 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
1707 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
1708
1709 mir_remove_instruction(ins);
1710 progress = true;
1711 }
1712
1713 return progress;
1714 }
1715
1716 /* Dead code elimination for branches at the end of a block - only one branch
1717 * per block is legal semantically */
1718
1719 static void
1720 midgard_opt_cull_dead_branch(compiler_context *ctx, midgard_block *block)
1721 {
1722 bool branched = false;
1723
1724 mir_foreach_instr_in_block_safe(block, ins) {
1725 if (!midgard_is_branch_unit(ins->unit)) continue;
1726
1727 /* We ignore prepacked branches since the fragment epilogue is
1728 * just generally special */
1729 if (ins->prepacked_branch) continue;
1730
1731 if (branched) {
1732 /* We already branched, so this is dead */
1733 mir_remove_instruction(ins);
1734 }
1735
1736 branched = true;
1737 }
1738 }
1739
1740 static bool
1741 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
1742 {
1743 /* abs or neg */
1744 if (!is_int && src.mod) return true;
1745
1746 /* swizzle */
1747 for (unsigned c = 0; c < 4; ++c) {
1748 if (!(mask & (1 << c))) continue;
1749 if (((src.swizzle >> (2*c)) & 3) != c) return true;
1750 }
1751
1752 return false;
1753 }
1754
1755 static bool
1756 mir_nontrivial_source2_mod(midgard_instruction *ins)
1757 {
1758 unsigned mask = squeeze_writemask(ins->alu.mask);
1759 bool is_int = midgard_is_integer_op(ins->alu.op);
1760
1761 midgard_vector_alu_src src2 =
1762 vector_alu_from_unsigned(ins->alu.src2);
1763
1764 return mir_nontrivial_mod(src2, is_int, mask);
1765 }
1766
1767 static bool
1768 midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
1769 {
1770 bool progress = false;
1771
1772 mir_foreach_instr_in_block_safe(block, ins) {
1773 if (ins->type != TAG_ALU_4) continue;
1774 if (!OP_IS_MOVE(ins->alu.op)) continue;
1775
1776 unsigned from = ins->ssa_args.src1;
1777 unsigned to = ins->ssa_args.dest;
1778
1779 /* We only work on pure SSA */
1780
1781 if (to >= SSA_FIXED_MINIMUM) continue;
1782 if (from >= SSA_FIXED_MINIMUM) continue;
1783 if (to >= ctx->func->impl->ssa_alloc) continue;
1784 if (from >= ctx->func->impl->ssa_alloc) continue;
1785
1786 /* Constant propagation is not handled here, either */
1787 if (ins->ssa_args.inline_constant) continue;
1788 if (ins->has_constants) continue;
1789
1790 if (mir_nontrivial_source2_mod(ins)) continue;
1791 if (ins->alu.outmod != midgard_outmod_none) continue;
1792
1793 /* We're clear -- rewrite */
1794 mir_rewrite_index_src(ctx, to, from);
1795 mir_remove_instruction(ins);
1796 progress |= true;
1797 }
1798
1799 return progress;
1800 }
1801
1802 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1803 * the move can be propagated away entirely */
1804
1805 static bool
1806 mir_compose_outmod(midgard_outmod *outmod, midgard_outmod comp)
1807 {
1808 /* Nothing to do */
1809 if (comp == midgard_outmod_none)
1810 return true;
1811
1812 if (*outmod == midgard_outmod_none) {
1813 *outmod = comp;
1814 return true;
1815 }
1816
1817 /* TODO: Compose rules */
1818 return false;
1819 }
1820
1821 static bool
1822 midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block)
1823 {
1824 bool progress = false;
1825
1826 mir_foreach_instr_in_block_safe(block, ins) {
1827 if (ins->type != TAG_ALU_4) continue;
1828 if (ins->alu.op != midgard_alu_op_fmov) continue;
1829 if (ins->alu.outmod != midgard_outmod_pos) continue;
1830
1831 /* TODO: Registers? */
1832 unsigned src = ins->ssa_args.src1;
1833 if (src >= ctx->func->impl->ssa_alloc) continue;
1834
1835 /* There might be a source modifier, too */
1836 if (mir_nontrivial_source2_mod(ins)) continue;
1837
1838 /* Backpropagate the modifier */
1839 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1840 if (v->type != TAG_ALU_4) continue;
1841 if (v->ssa_args.dest != src) continue;
1842
1843 midgard_outmod temp = v->alu.outmod;
1844 progress |= mir_compose_outmod(&temp, ins->alu.outmod);
1845
1846 /* Throw in the towel.. */
1847 if (!progress) break;
1848
1849 /* Otherwise, transfer the modifier */
1850 v->alu.outmod = temp;
1851 ins->alu.outmod = midgard_outmod_none;
1852
1853 break;
1854 }
1855 }
1856
1857 return progress;
1858 }
1859
1860 static bool
1861 midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
1862 {
1863 bool progress = false;
1864
1865 mir_foreach_instr_in_block_safe(block, ins) {
1866 if (ins->type != TAG_ALU_4) continue;
1867 if (!OP_IS_MOVE(ins->alu.op)) continue;
1868
1869 unsigned from = ins->ssa_args.src1;
1870 unsigned to = ins->ssa_args.dest;
1871
1872 /* Make sure it's simple enough for us to handle */
1873
1874 if (from >= SSA_FIXED_MINIMUM) continue;
1875 if (from >= ctx->func->impl->ssa_alloc) continue;
1876 if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
1877 if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
1878
1879 bool eliminated = false;
1880
1881 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
1882 /* The texture registers are not SSA so be careful.
1883 * Conservatively, just stop if we hit a texture op
1884 * (even if it may not write) to where we are */
1885
1886 if (v->type != TAG_ALU_4)
1887 break;
1888
1889 if (v->ssa_args.dest == from) {
1890 /* We don't want to track partial writes ... */
1891 if (v->alu.mask == 0xF) {
1892 v->ssa_args.dest = to;
1893 eliminated = true;
1894 }
1895
1896 break;
1897 }
1898 }
1899
1900 if (eliminated)
1901 mir_remove_instruction(ins);
1902
1903 progress |= eliminated;
1904 }
1905
1906 return progress;
1907 }
1908
1909 /* The following passes reorder MIR instructions to enable better scheduling */
1910
1911 static void
1912 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
1913 {
1914 mir_foreach_instr_in_block_safe(block, ins) {
1915 if (ins->type != TAG_LOAD_STORE_4) continue;
1916
1917 /* We've found a load/store op. Check if next is also load/store. */
1918 midgard_instruction *next_op = mir_next_op(ins);
1919 if (&next_op->link != &block->instructions) {
1920 if (next_op->type == TAG_LOAD_STORE_4) {
1921 /* If so, we're done since we're a pair */
1922 ins = mir_next_op(ins);
1923 continue;
1924 }
1925
1926 /* Maximum search distance to pair, to avoid register pressure disasters */
1927 int search_distance = 8;
1928
1929 /* Otherwise, we have an orphaned load/store -- search for another load */
1930 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
1931 /* Terminate search if necessary */
1932 if (!(search_distance--)) break;
1933
1934 if (c->type != TAG_LOAD_STORE_4) continue;
1935
1936 /* Stores cannot be reordered, since they have
1937 * dependencies. For the same reason, indirect
1938 * loads cannot be reordered as their index is
1939 * loaded in r27.w */
1940
1941 if (OP_IS_STORE(c->load_store.op)) continue;
1942
1943 /* It appears the 0x800 bit is set whenever a
1944 * load is direct, unset when it is indirect.
1945 * Skip indirect loads. */
1946
1947 if (!(c->load_store.unknown & 0x800)) continue;
1948
1949 /* We found one! Move it up to pair and remove it from the old location */
1950
1951 mir_insert_instruction_before(ins, *c);
1952 mir_remove_instruction(c);
1953
1954 break;
1955 }
1956 }
1957 }
1958 }
1959
1960 /* If there are leftovers after the below pass, emit actual fmov
1961 * instructions for the slow-but-correct path */
1962
1963 static void
1964 emit_leftover_move(compiler_context *ctx)
1965 {
1966 set_foreach(ctx->leftover_ssa_to_alias, leftover) {
1967 int base = ((uintptr_t) leftover->key) - 1;
1968 int mapped = base;
1969
1970 map_ssa_to_alias(ctx, &mapped);
1971 EMIT(fmov, mapped, blank_alu_src, base);
1972 }
1973 }
1974
1975 static void
1976 actualise_ssa_to_alias(compiler_context *ctx)
1977 {
1978 mir_foreach_instr(ctx, ins) {
1979 map_ssa_to_alias(ctx, &ins->ssa_args.src0);
1980 map_ssa_to_alias(ctx, &ins->ssa_args.src1);
1981 }
1982
1983 emit_leftover_move(ctx);
1984 }
1985
1986 static void
1987 emit_fragment_epilogue(compiler_context *ctx)
1988 {
1989 /* Special case: writing out constants requires us to include the move
1990 * explicitly now, so shove it into r0 */
1991
1992 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, ctx->fragment_output + 1);
1993
1994 if (constant_value) {
1995 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(0));
1996 attach_constants(ctx, &ins, constant_value, ctx->fragment_output + 1);
1997 emit_mir_instruction(ctx, ins);
1998 }
1999
2000 /* Perform the actual fragment writeout. We have two writeout/branch
2001 * instructions, forming a loop until writeout is successful as per the
2002 * docs. TODO: gl_FragDepth */
2003
2004 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2005 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2006 }
2007
2008 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2009 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2010 * with the int8 analogue to the fragment epilogue */
2011
2012 static void
2013 emit_blend_epilogue(compiler_context *ctx)
2014 {
2015 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2016
2017 midgard_instruction scale = {
2018 .type = TAG_ALU_4,
2019 .unit = UNIT_VMUL,
2020 .inline_constant = _mesa_float_to_half(255.0),
2021 .ssa_args = {
2022 .src0 = SSA_FIXED_REGISTER(0),
2023 .src1 = SSA_UNUSED_0,
2024 .dest = SSA_FIXED_REGISTER(24),
2025 .inline_constant = true
2026 },
2027 .alu = {
2028 .op = midgard_alu_op_fmul,
2029 .reg_mode = midgard_reg_mode_32,
2030 .dest_override = midgard_dest_override_lower,
2031 .mask = 0xFF,
2032 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2033 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2034 }
2035 };
2036
2037 emit_mir_instruction(ctx, scale);
2038
2039 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2040
2041 midgard_vector_alu_src alu_src = blank_alu_src;
2042 alu_src.half = true;
2043
2044 midgard_instruction f2u8 = {
2045 .type = TAG_ALU_4,
2046 .ssa_args = {
2047 .src0 = SSA_FIXED_REGISTER(24),
2048 .src1 = SSA_UNUSED_0,
2049 .dest = SSA_FIXED_REGISTER(0),
2050 .inline_constant = true
2051 },
2052 .alu = {
2053 .op = midgard_alu_op_f2u8,
2054 .reg_mode = midgard_reg_mode_16,
2055 .dest_override = midgard_dest_override_lower,
2056 .outmod = midgard_outmod_pos,
2057 .mask = 0xF,
2058 .src1 = vector_alu_srco_unsigned(alu_src),
2059 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2060 }
2061 };
2062
2063 emit_mir_instruction(ctx, f2u8);
2064
2065 /* vmul.imov.quarter r0, r0, r0 */
2066
2067 midgard_instruction imov_8 = {
2068 .type = TAG_ALU_4,
2069 .ssa_args = {
2070 .src0 = SSA_UNUSED_1,
2071 .src1 = SSA_FIXED_REGISTER(0),
2072 .dest = SSA_FIXED_REGISTER(0),
2073 },
2074 .alu = {
2075 .op = midgard_alu_op_imov,
2076 .reg_mode = midgard_reg_mode_8,
2077 .dest_override = midgard_dest_override_none,
2078 .outmod = midgard_outmod_int,
2079 .mask = 0xFF,
2080 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2081 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2082 }
2083 };
2084
2085 /* Emit branch epilogue with the 8-bit move as the source */
2086
2087 emit_mir_instruction(ctx, imov_8);
2088 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2089
2090 emit_mir_instruction(ctx, imov_8);
2091 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2092 }
2093
2094 static midgard_block *
2095 emit_block(compiler_context *ctx, nir_block *block)
2096 {
2097 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2098 list_addtail(&this_block->link, &ctx->blocks);
2099
2100 this_block->is_scheduled = false;
2101 ++ctx->block_count;
2102
2103 ctx->texture_index[0] = -1;
2104 ctx->texture_index[1] = -1;
2105
2106 /* Add us as a successor to the block we are following */
2107 if (ctx->current_block)
2108 midgard_block_add_successor(ctx->current_block, this_block);
2109
2110 /* Set up current block */
2111 list_inithead(&this_block->instructions);
2112 ctx->current_block = this_block;
2113
2114 nir_foreach_instr(instr, block) {
2115 emit_instr(ctx, instr);
2116 ++ctx->instruction_count;
2117 }
2118
2119 inline_alu_constants(ctx);
2120 embedded_to_inline_constant(ctx);
2121
2122 /* Perform heavylifting for aliasing */
2123 actualise_ssa_to_alias(ctx);
2124
2125 midgard_pair_load_store(ctx, this_block);
2126
2127 /* Append fragment shader epilogue (value writeout) */
2128 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2129 if (block == nir_impl_last_block(ctx->func->impl)) {
2130 if (ctx->is_blend)
2131 emit_blend_epilogue(ctx);
2132 else
2133 emit_fragment_epilogue(ctx);
2134 }
2135 }
2136
2137 if (block == nir_start_block(ctx->func->impl))
2138 ctx->initial_block = this_block;
2139
2140 if (block == nir_impl_last_block(ctx->func->impl))
2141 ctx->final_block = this_block;
2142
2143 /* Allow the next control flow to access us retroactively, for
2144 * branching etc */
2145 ctx->current_block = this_block;
2146
2147 /* Document the fallthrough chain */
2148 ctx->previous_source_block = this_block;
2149
2150 return this_block;
2151 }
2152
2153 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2154
2155 static void
2156 emit_if(struct compiler_context *ctx, nir_if *nif)
2157 {
2158 /* Conditional branches expect the condition in r31.w; emit a move for
2159 * that in the _previous_ block (which is the current block). */
2160 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2161
2162 /* Speculatively emit the branch, but we can't fill it in until later */
2163 EMIT(branch, true, true);
2164 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2165
2166 /* Emit the two subblocks */
2167 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2168
2169 /* Emit a jump from the end of the then block to the end of the else */
2170 EMIT(branch, false, false);
2171 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2172
2173 /* Emit second block, and check if it's empty */
2174
2175 int else_idx = ctx->block_count;
2176 int count_in = ctx->instruction_count;
2177 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2178 int after_else_idx = ctx->block_count;
2179
2180 /* Now that we have the subblocks emitted, fix up the branches */
2181
2182 assert(then_block);
2183 assert(else_block);
2184
2185 if (ctx->instruction_count == count_in) {
2186 /* The else block is empty, so don't emit an exit jump */
2187 mir_remove_instruction(then_exit);
2188 then_branch->branch.target_block = after_else_idx;
2189 } else {
2190 then_branch->branch.target_block = else_idx;
2191 then_exit->branch.target_block = after_else_idx;
2192 }
2193 }
2194
2195 static void
2196 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2197 {
2198 /* Remember where we are */
2199 midgard_block *start_block = ctx->current_block;
2200
2201 /* Allocate a loop number, growing the current inner loop depth */
2202 int loop_idx = ++ctx->current_loop_depth;
2203
2204 /* Get index from before the body so we can loop back later */
2205 int start_idx = ctx->block_count;
2206
2207 /* Emit the body itself */
2208 emit_cf_list(ctx, &nloop->body);
2209
2210 /* Branch back to loop back */
2211 struct midgard_instruction br_back = v_branch(false, false);
2212 br_back.branch.target_block = start_idx;
2213 emit_mir_instruction(ctx, br_back);
2214
2215 /* Mark down that branch in the graph. Note that we're really branching
2216 * to the block *after* we started in. TODO: Why doesn't the branch
2217 * itself have an off-by-one then...? */
2218 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2219
2220 /* Find the index of the block about to follow us (note: we don't add
2221 * one; blocks are 0-indexed so we get a fencepost problem) */
2222 int break_block_idx = ctx->block_count;
2223
2224 /* Fix up the break statements we emitted to point to the right place,
2225 * now that we can allocate a block number for them */
2226
2227 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2228 mir_foreach_instr_in_block(block, ins) {
2229 if (ins->type != TAG_ALU_4) continue;
2230 if (!ins->compact_branch) continue;
2231 if (ins->prepacked_branch) continue;
2232
2233 /* We found a branch -- check the type to see if we need to do anything */
2234 if (ins->branch.target_type != TARGET_BREAK) continue;
2235
2236 /* It's a break! Check if it's our break */
2237 if (ins->branch.target_break != loop_idx) continue;
2238
2239 /* Okay, cool, we're breaking out of this loop.
2240 * Rewrite from a break to a goto */
2241
2242 ins->branch.target_type = TARGET_GOTO;
2243 ins->branch.target_block = break_block_idx;
2244 }
2245 }
2246
2247 /* Now that we've finished emitting the loop, free up the depth again
2248 * so we play nice with recursion amid nested loops */
2249 --ctx->current_loop_depth;
2250 }
2251
2252 static midgard_block *
2253 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
2254 {
2255 midgard_block *start_block = NULL;
2256
2257 foreach_list_typed(nir_cf_node, node, node, list) {
2258 switch (node->type) {
2259 case nir_cf_node_block: {
2260 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
2261
2262 if (!start_block)
2263 start_block = block;
2264
2265 break;
2266 }
2267
2268 case nir_cf_node_if:
2269 emit_if(ctx, nir_cf_node_as_if(node));
2270 break;
2271
2272 case nir_cf_node_loop:
2273 emit_loop(ctx, nir_cf_node_as_loop(node));
2274 break;
2275
2276 case nir_cf_node_function:
2277 assert(0);
2278 break;
2279 }
2280 }
2281
2282 return start_block;
2283 }
2284
2285 /* Due to lookahead, we need to report the first tag executed in the command
2286 * stream and in branch targets. An initial block might be empty, so iterate
2287 * until we find one that 'works' */
2288
2289 static unsigned
2290 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
2291 {
2292 midgard_block *initial_block = mir_get_block(ctx, block_idx);
2293
2294 unsigned first_tag = 0;
2295
2296 do {
2297 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
2298
2299 if (initial_bundle) {
2300 first_tag = initial_bundle->tag;
2301 break;
2302 }
2303
2304 /* Initial block is empty, try the next block */
2305 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
2306 } while(initial_block != NULL);
2307
2308 assert(first_tag);
2309 return first_tag;
2310 }
2311
2312 int
2313 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend)
2314 {
2315 struct util_dynarray *compiled = &program->compiled;
2316
2317 midgard_debug = debug_get_option_midgard_debug();
2318
2319 compiler_context ictx = {
2320 .nir = nir,
2321 .stage = nir->info.stage,
2322
2323 .is_blend = is_blend,
2324 .blend_constant_offset = -1,
2325
2326 .alpha_ref = program->alpha_ref
2327 };
2328
2329 compiler_context *ctx = &ictx;
2330
2331 /* TODO: Decide this at runtime */
2332 ctx->uniform_cutoff = 8;
2333
2334 /* Initialize at a global (not block) level hash tables */
2335
2336 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
2337 ctx->ssa_to_alias = _mesa_hash_table_u64_create(NULL);
2338 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
2339 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
2340 ctx->leftover_ssa_to_alias = _mesa_set_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
2341
2342 /* Record the varying mapping for the command stream's bookkeeping */
2343
2344 struct exec_list *varyings =
2345 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
2346
2347 unsigned max_varying = 0;
2348 nir_foreach_variable(var, varyings) {
2349 unsigned loc = var->data.driver_location;
2350 unsigned sz = glsl_type_size(var->type, FALSE);
2351
2352 for (int c = loc; c < (loc + sz); ++c) {
2353 program->varyings[c] = var->data.location;
2354 max_varying = MAX2(max_varying, c);
2355 }
2356 }
2357
2358 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2359 * (so we don't accidentally duplicate the epilogue since mesa/st has
2360 * messed with our I/O quite a bit already) */
2361
2362 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2363
2364 if (ctx->stage == MESA_SHADER_VERTEX)
2365 NIR_PASS_V(nir, nir_lower_viewport_transform);
2366
2367 NIR_PASS_V(nir, nir_lower_var_copies);
2368 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2369 NIR_PASS_V(nir, nir_split_var_copies);
2370 NIR_PASS_V(nir, nir_lower_var_copies);
2371 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2372 NIR_PASS_V(nir, nir_lower_var_copies);
2373 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2374
2375 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
2376
2377 /* Optimisation passes */
2378
2379 optimise_nir(nir);
2380
2381 if (midgard_debug & MIDGARD_DBG_SHADERS) {
2382 nir_print_shader(nir, stdout);
2383 }
2384
2385 /* Assign sysvals and counts, now that we're sure
2386 * (post-optimisation) */
2387
2388 midgard_nir_assign_sysvals(ctx, nir);
2389
2390 program->uniform_count = nir->num_uniforms;
2391 program->sysval_count = ctx->sysval_count;
2392 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
2393
2394 program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_inputs : 0;
2395 program->varying_count = max_varying + 1; /* Fencepost off-by-one */
2396
2397 nir_foreach_function(func, nir) {
2398 if (!func->impl)
2399 continue;
2400
2401 list_inithead(&ctx->blocks);
2402 ctx->block_count = 0;
2403 ctx->func = func;
2404
2405 emit_cf_list(ctx, &func->impl->body);
2406 emit_block(ctx, func->impl->end_block);
2407
2408 break; /* TODO: Multi-function shaders */
2409 }
2410
2411 util_dynarray_init(compiled, NULL);
2412
2413 /* MIR-level optimizations */
2414
2415 bool progress = false;
2416
2417 do {
2418 progress = false;
2419
2420 mir_foreach_block(ctx, block) {
2421 progress |= midgard_opt_pos_propagate(ctx, block);
2422 progress |= midgard_opt_copy_prop(ctx, block);
2423 progress |= midgard_opt_copy_prop_tex(ctx, block);
2424 progress |= midgard_opt_dead_code_eliminate(ctx, block);
2425 }
2426 } while (progress);
2427
2428 /* Nested control-flow can result in dead branches at the end of the
2429 * block. This messes with our analysis and is just dead code, so cull
2430 * them */
2431 mir_foreach_block(ctx, block) {
2432 midgard_opt_cull_dead_branch(ctx, block);
2433 }
2434
2435 /* Schedule! */
2436 schedule_program(ctx);
2437
2438 /* Now that all the bundles are scheduled and we can calculate block
2439 * sizes, emit actual branch instructions rather than placeholders */
2440
2441 int br_block_idx = 0;
2442
2443 mir_foreach_block(ctx, block) {
2444 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2445 for (int c = 0; c < bundle->instruction_count; ++c) {
2446 midgard_instruction *ins = bundle->instructions[c];
2447
2448 if (!midgard_is_branch_unit(ins->unit)) continue;
2449
2450 if (ins->prepacked_branch) continue;
2451
2452 /* Parse some basic branch info */
2453 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
2454 bool is_conditional = ins->branch.conditional;
2455 bool is_inverted = ins->branch.invert_conditional;
2456 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
2457
2458 /* Determine the block we're jumping to */
2459 int target_number = ins->branch.target_block;
2460
2461 /* Report the destination tag */
2462 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
2463
2464 /* Count up the number of quadwords we're
2465 * jumping over = number of quadwords until
2466 * (br_block_idx, target_number) */
2467
2468 int quadword_offset = 0;
2469
2470 if (is_discard) {
2471 /* Jump to the end of the shader. We
2472 * need to include not only the
2473 * following blocks, but also the
2474 * contents of our current block (since
2475 * discard can come in the middle of
2476 * the block) */
2477
2478 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
2479
2480 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
2481 quadword_offset += quadword_size(bun->tag);
2482 }
2483
2484 mir_foreach_block_from(ctx, blk, b) {
2485 quadword_offset += b->quadword_count;
2486 }
2487
2488 } else if (target_number > br_block_idx) {
2489 /* Jump forward */
2490
2491 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
2492 midgard_block *blk = mir_get_block(ctx, idx);
2493 assert(blk);
2494
2495 quadword_offset += blk->quadword_count;
2496 }
2497 } else {
2498 /* Jump backwards */
2499
2500 for (int idx = br_block_idx; idx >= target_number; --idx) {
2501 midgard_block *blk = mir_get_block(ctx, idx);
2502 assert(blk);
2503
2504 quadword_offset -= blk->quadword_count;
2505 }
2506 }
2507
2508 /* Unconditional extended branches (far jumps)
2509 * have issues, so we always use a conditional
2510 * branch, setting the condition to always for
2511 * unconditional. For compact unconditional
2512 * branches, cond isn't used so it doesn't
2513 * matter what we pick. */
2514
2515 midgard_condition cond =
2516 !is_conditional ? midgard_condition_always :
2517 is_inverted ? midgard_condition_false :
2518 midgard_condition_true;
2519
2520 midgard_jmp_writeout_op op =
2521 is_discard ? midgard_jmp_writeout_op_discard :
2522 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
2523 midgard_jmp_writeout_op_branch_cond;
2524
2525 if (!is_compact) {
2526 midgard_branch_extended branch =
2527 midgard_create_branch_extended(
2528 cond, op,
2529 dest_tag,
2530 quadword_offset);
2531
2532 memcpy(&ins->branch_extended, &branch, sizeof(branch));
2533 } else if (is_conditional || is_discard) {
2534 midgard_branch_cond branch = {
2535 .op = op,
2536 .dest_tag = dest_tag,
2537 .offset = quadword_offset,
2538 .cond = cond
2539 };
2540
2541 assert(branch.offset == quadword_offset);
2542
2543 memcpy(&ins->br_compact, &branch, sizeof(branch));
2544 } else {
2545 assert(op == midgard_jmp_writeout_op_branch_uncond);
2546
2547 midgard_branch_uncond branch = {
2548 .op = op,
2549 .dest_tag = dest_tag,
2550 .offset = quadword_offset,
2551 .unknown = 1
2552 };
2553
2554 assert(branch.offset == quadword_offset);
2555
2556 memcpy(&ins->br_compact, &branch, sizeof(branch));
2557 }
2558 }
2559 }
2560
2561 ++br_block_idx;
2562 }
2563
2564 /* Emit flat binary from the instruction arrays. Iterate each block in
2565 * sequence. Save instruction boundaries such that lookahead tags can
2566 * be assigned easily */
2567
2568 /* Cache _all_ bundles in source order for lookahead across failed branches */
2569
2570 int bundle_count = 0;
2571 mir_foreach_block(ctx, block) {
2572 bundle_count += block->bundles.size / sizeof(midgard_bundle);
2573 }
2574 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
2575 int bundle_idx = 0;
2576 mir_foreach_block(ctx, block) {
2577 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
2578 source_order_bundles[bundle_idx++] = bundle;
2579 }
2580 }
2581
2582 int current_bundle = 0;
2583
2584 /* Midgard prefetches instruction types, so during emission we
2585 * need to lookahead. Unless this is the last instruction, in
2586 * which we return 1. Or if this is the second to last and the
2587 * last is an ALU, then it's also 1... */
2588
2589 mir_foreach_block(ctx, block) {
2590 mir_foreach_bundle_in_block(block, bundle) {
2591 int lookahead = 1;
2592
2593 if (current_bundle + 1 < bundle_count) {
2594 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
2595
2596 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
2597 lookahead = 1;
2598 } else {
2599 lookahead = next;
2600 }
2601 }
2602
2603 emit_binary_bundle(ctx, bundle, compiled, lookahead);
2604 ++current_bundle;
2605 }
2606
2607 /* TODO: Free deeper */
2608 //util_dynarray_fini(&block->instructions);
2609 }
2610
2611 free(source_order_bundles);
2612
2613 /* Report the very first tag executed */
2614 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
2615
2616 /* Deal with off-by-one related to the fencepost problem */
2617 program->work_register_count = ctx->work_registers + 1;
2618
2619 program->can_discard = ctx->can_discard;
2620 program->uniform_cutoff = ctx->uniform_cutoff;
2621
2622 program->blend_patch_offset = ctx->blend_constant_offset;
2623
2624 if (midgard_debug & MIDGARD_DBG_SHADERS)
2625 disassemble_midgard(program->compiled.data, program->compiled.size);
2626
2627 return 0;
2628 }