2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
110 /* Generic in-memory data type repesenting a single logical instruction, rather
111 * than a single instruction group. This is the preferred form for code gen.
112 * Multiple midgard_insturctions will later be combined during scheduling,
113 * though this is not represented in this structure. Its format bridges
114 * the low-level binary representation with the higher level semantic meaning.
116 * Notably, it allows registers to be specified as block local SSA, for code
117 * emitted before the register allocation pass.
120 typedef struct midgard_instruction
{
121 /* Must be first for casting */
122 struct list_head link
;
124 unsigned type
; /* ALU, load/store, texture */
126 /* If the register allocator has not run yet... */
129 /* Special fields for an ALU instruction */
130 midgard_reg_info registers
;
132 /* I.e. (1 << alu_bit) */
137 uint16_t inline_constant
;
138 bool has_blend_constant
;
142 bool prepacked_branch
;
145 midgard_load_store_word load_store
;
146 midgard_vector_alu alu
;
147 midgard_texture_word texture
;
148 midgard_branch_extended branch_extended
;
151 /* General branch, rather than packed br_compact. Higher level
152 * than the other components */
153 midgard_branch branch
;
155 } midgard_instruction
;
157 typedef struct midgard_block
{
158 /* Link to next block. Must be first for mir_get_block */
159 struct list_head link
;
161 /* List of midgard_instructions emitted for the current block */
162 struct list_head instructions
;
166 /* List of midgard_bundles emitted (after the scheduler has run) */
167 struct util_dynarray bundles
;
169 /* Number of quadwords _actually_ emitted, as determined after scheduling */
170 unsigned quadword_count
;
172 struct midgard_block
*next_fallthrough
;
175 /* Helpers to generate midgard_instruction's using macro magic, since every
176 * driver seems to do it that way */
178 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
180 #define M_LOAD_STORE(name, rname, uname) \
181 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
182 midgard_instruction i = { \
183 .type = TAG_LOAD_STORE_4, \
190 .op = midgard_op_##name, \
192 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
200 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
201 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
203 const midgard_vector_alu_src blank_alu_src
= {
204 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
207 const midgard_vector_alu_src blank_alu_src_xxxx
= {
208 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
211 const midgard_scalar_alu_src blank_scalar_alu_src
= {
215 /* Used for encoding the unused source of 1-op instructions */
216 const midgard_vector_alu_src zero_alu_src
= { 0 };
218 /* Coerce structs to integer */
221 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
224 memcpy(&u
, &src
, sizeof(src
));
228 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
229 * the corresponding Midgard source */
231 static midgard_vector_alu_src
232 vector_alu_modifiers(nir_alu_src
*src
)
234 if (!src
) return blank_alu_src
;
236 midgard_vector_alu_src alu_src
= {
238 .negate
= src
->negate
,
241 .half
= 0, /* TODO */
242 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
248 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
250 static midgard_instruction
251 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
253 midgard_instruction ins
= {
256 .src0
= SSA_UNUSED_1
,
261 .op
= midgard_alu_op_fmov
,
262 .reg_mode
= midgard_reg_mode_full
,
263 .dest_override
= midgard_dest_override_none
,
265 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
266 .src2
= vector_alu_srco_unsigned(mod
)
273 /* load/store instructions have both 32-bit and 16-bit variants, depending on
274 * whether we are using vectors composed of highp or mediump. At the moment, we
275 * don't support half-floats -- this requires changes in other parts of the
276 * compiler -- therefore the 16-bit versions are commented out. */
278 //M_LOAD(load_attr_16);
279 M_LOAD(load_attr_32
);
280 //M_LOAD(load_vary_16);
281 M_LOAD(load_vary_32
);
282 //M_LOAD(load_uniform_16);
283 M_LOAD(load_uniform_32
);
284 M_LOAD(load_color_buffer_8
);
285 //M_STORE(store_vary_16);
286 M_STORE(store_vary_32
);
288 static midgard_instruction
289 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
291 midgard_branch_cond branch
= {
299 memcpy(&compact
, &branch
, sizeof(branch
));
301 midgard_instruction ins
= {
303 .unit
= ALU_ENAB_BR_COMPACT
,
304 .prepacked_branch
= true,
305 .compact_branch
= true,
306 .br_compact
= compact
309 if (op
== midgard_jmp_writeout_op_writeout
)
315 static midgard_instruction
316 v_branch(bool conditional
, bool invert
)
318 midgard_instruction ins
= {
320 .unit
= ALU_ENAB_BRANCH
,
321 .compact_branch
= true,
323 .conditional
= conditional
,
324 .invert_conditional
= invert
331 static midgard_branch_extended
332 midgard_create_branch_extended( midgard_condition cond
,
333 midgard_jmp_writeout_op op
,
335 signed quadword_offset
)
337 /* For unclear reasons, the condition code is repeated 8 times */
338 uint16_t duplicated_cond
=
348 midgard_branch_extended branch
= {
350 .dest_tag
= dest_tag
,
351 .offset
= quadword_offset
,
352 .cond
= duplicated_cond
358 typedef struct midgard_bundle
{
359 /* Tag for the overall bundle */
362 /* Instructions contained by the bundle */
363 int instruction_count
;
364 midgard_instruction instructions
[5];
366 /* Bundle-wide ALU configuration */
369 bool has_embedded_constants
;
371 bool has_blend_constant
;
373 uint16_t register_words
[8];
374 int register_words_count
;
376 uint64_t body_words
[8];
378 int body_words_count
;
381 typedef struct compiler_context
{
383 gl_shader_stage stage
;
385 /* Is internally a blend shader? Depends on stage == FRAGMENT */
388 /* Tracking for blend constant patching */
389 int blend_constant_number
;
390 int blend_constant_offset
;
392 /* Current NIR function */
395 /* Unordered list of midgard_blocks */
397 struct list_head blocks
;
399 midgard_block
*initial_block
;
400 midgard_block
*previous_source_block
;
401 midgard_block
*final_block
;
403 /* List of midgard_instructions emitted for the current block */
404 midgard_block
*current_block
;
406 /* The index corresponding to the current loop, e.g. for breaks/contineus */
409 /* Constants which have been loaded, for later inlining */
410 struct hash_table_u64
*ssa_constants
;
412 /* SSA indices to be outputted to corresponding varying offset */
413 struct hash_table_u64
*ssa_varyings
;
415 /* SSA values / registers which have been aliased. Naively, these
416 * demand a fmov output; instead, we alias them in a later pass to
417 * avoid the wasted op.
419 * A note on encoding: to avoid dynamic memory management here, rather
420 * than ampping to a pointer, we map to the source index; the key
421 * itself is just the destination index. */
423 struct hash_table_u64
*ssa_to_alias
;
424 struct set
*leftover_ssa_to_alias
;
426 /* Actual SSA-to-register for RA */
427 struct hash_table_u64
*ssa_to_register
;
429 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
430 struct hash_table_u64
*hash_to_temp
;
434 /* Uniform IDs for mdg */
435 struct hash_table_u64
*uniform_nir_to_mdg
;
438 /* Just the count of the max register used. Higher count => higher
439 * register pressure */
442 /* Used for cont/last hinting. Increase when a tex op is added.
443 * Decrease when a tex op is removed. */
444 int texture_op_count
;
446 /* Mapping of texture register -> SSA index for unaliasing */
447 int texture_index
[2];
449 /* Count of special uniforms (viewport, etc) in vec4 units */
450 int special_uniforms
;
452 /* If any path hits a discard instruction */
455 /* The number of uniforms allowable for the fast path */
458 /* Count of instructions emitted from NIR overall, across all blocks */
459 int instruction_count
;
461 /* Alpha ref value passed in */
464 /* The index corresponding to the fragment output */
465 unsigned fragment_output
;
468 /* Append instruction to end of current block */
470 static midgard_instruction
*
471 mir_upload_ins(struct midgard_instruction ins
)
473 midgard_instruction
*heap
= malloc(sizeof(ins
));
474 memcpy(heap
, &ins
, sizeof(ins
));
479 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
481 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
485 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
487 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
491 mir_remove_instruction(struct midgard_instruction
*ins
)
493 list_del(&ins
->link
);
496 static midgard_instruction
*
497 mir_prev_op(struct midgard_instruction
*ins
)
499 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
502 static midgard_instruction
*
503 mir_next_op(struct midgard_instruction
*ins
)
505 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
508 static midgard_block
*
509 mir_next_block(struct midgard_block
*blk
)
511 return list_first_entry(&(blk
->link
), midgard_block
, link
);
515 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
516 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
518 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
519 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
520 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
521 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
522 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
523 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
526 static midgard_instruction
*
527 mir_last_in_block(struct midgard_block
*block
)
529 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
532 static midgard_block
*
533 mir_get_block(compiler_context
*ctx
, int idx
)
535 struct list_head
*lst
= &ctx
->blocks
;
540 return (struct midgard_block
*) lst
;
543 /* Pretty printer for internal Midgard IR */
546 print_mir_source(int source
)
548 if (source
>= SSA_FIXED_MINIMUM
) {
549 /* Specific register */
550 int reg
= SSA_REG_FROM_FIXED(source
);
552 /* TODO: Moving threshold */
553 if (reg
> 16 && reg
< 24)
554 printf("u%d", 23 - reg
);
558 printf("%d", source
);
563 print_mir_instruction(midgard_instruction
*ins
)
569 midgard_alu_op op
= ins
->alu
.op
;
570 const char *name
= alu_opcode_names
[op
];
573 printf("%d.", ins
->unit
);
575 printf("%s", name
? name
: "??");
579 case TAG_LOAD_STORE_4
: {
580 midgard_load_store_op op
= ins
->load_store
.op
;
581 const char *name
= load_store_opcode_names
[op
];
588 case TAG_TEXTURE_4
: {
597 ssa_args
*args
= &ins
->ssa_args
;
599 printf(" %d, ", args
->dest
);
601 print_mir_source(args
->src0
);
604 if (args
->inline_constant
)
605 printf("#%d", ins
->inline_constant
);
607 print_mir_source(args
->src1
);
609 if (ins
->has_constants
)
610 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
616 print_mir_block(midgard_block
*block
)
620 mir_foreach_instr_in_block(block
, ins
) {
621 print_mir_instruction(ins
);
630 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
632 ins
->has_constants
= true;
633 memcpy(&ins
->constants
, constants
, 16);
635 /* If this is the special blend constant, mark this instruction */
637 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
638 ins
->has_blend_constant
= true;
642 glsl_type_size(const struct glsl_type
*type
)
644 return glsl_count_attribute_slots(type
, false);
647 /* Lower fdot2 to a vector multiplication followed by channel addition */
649 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
651 if (alu
->op
!= nir_op_fdot2
)
654 b
->cursor
= nir_before_instr(&alu
->instr
);
656 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
657 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
659 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
661 nir_ssa_def
*sum
= nir_fadd(b
,
662 nir_channel(b
, product
, 0),
663 nir_channel(b
, product
, 1));
665 /* Replace the fdot2 with this sum */
666 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
670 midgard_nir_lower_fdot2(nir_shader
*shader
)
672 bool progress
= false;
674 nir_foreach_function(function
, shader
) {
675 if (!function
->impl
) continue;
678 nir_builder
*b
= &_b
;
679 nir_builder_init(b
, function
->impl
);
681 nir_foreach_block(block
, function
->impl
) {
682 nir_foreach_instr_safe(instr
, block
) {
683 if (instr
->type
!= nir_instr_type_alu
) continue;
685 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
686 midgard_nir_lower_fdot2_body(b
, alu
);
692 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
700 optimise_nir(nir_shader
*nir
)
704 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
705 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
707 nir_lower_tex_options lower_tex_options
= {
711 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
716 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
717 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
718 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
719 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
721 NIR_PASS(progress
, nir
, nir_copy_prop
);
722 NIR_PASS(progress
, nir
, nir_opt_dce
);
723 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
724 NIR_PASS(progress
, nir
, nir_opt_cse
);
725 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
726 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
727 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
728 NIR_PASS(progress
, nir
, nir_opt_undef
);
729 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
732 nir_var_function_temp
);
734 /* TODO: Enable vectorize when merged upstream */
735 // NIR_PASS(progress, nir, nir_opt_vectorize);
738 /* Must be run at the end to prevent creation of fsin/fcos ops */
739 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
744 NIR_PASS(progress
, nir
, nir_opt_dce
);
745 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
746 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
747 NIR_PASS(progress
, nir
, nir_copy_prop
);
750 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
751 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
753 /* Lower mods for float ops only. Integer ops don't support modifiers
754 * (saturate doesn't make sense on integers, neg/abs require dedicated
757 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
758 NIR_PASS(progress
, nir
, nir_copy_prop
);
759 NIR_PASS(progress
, nir
, nir_opt_dce
);
761 /* We implement booleans as 32-bit 0/~0 */
762 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
764 /* Take us out of SSA */
765 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
766 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
768 /* We are a vector architecture; write combine where possible */
769 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
770 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
772 NIR_PASS(progress
, nir
, nir_opt_dce
);
775 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
776 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
777 * r0. See the comments in compiler_context */
780 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
782 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
783 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
786 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
789 unalias_ssa(compiler_context
*ctx
, int dest
)
791 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
792 /* TODO: Remove from leftover or no? */
796 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
798 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
802 midgard_is_pinned(compiler_context
*ctx
, int index
)
804 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
807 /* Do not actually emit a load; instead, cache the constant for inlining */
810 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
812 nir_ssa_def def
= instr
->def
;
814 float *v
= ralloc_array(NULL
, float, 4);
815 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
816 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
819 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
823 expand_writemask(unsigned mask
)
827 for (int i
= 0; i
< 4; ++i
)
835 squeeze_writemask(unsigned mask
)
839 for (int i
= 0; i
< 4; ++i
)
840 if (mask
& (3 << (2 * i
)))
847 /* Determines effective writemask, taking quirks and expansion into account */
849 effective_writemask(midgard_vector_alu
*alu
)
851 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
854 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
856 /* If there is a fixed channel count, construct the appropriate mask */
859 return (1 << channel_count
) - 1;
861 /* Otherwise, just squeeze the existing mask */
862 return squeeze_writemask(alu
->mask
);
866 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
868 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
871 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
876 /* If no temp is find, allocate one */
877 temp
= ctx
->temp_count
++;
878 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
880 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
886 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
889 return src
->ssa
->index
;
891 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
895 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
898 return dst
->ssa
.index
;
900 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
904 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
906 return nir_src_index(ctx
, &src
->src
);
909 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
910 * a conditional test) into that register */
913 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
915 /* XXX: Force component correct */
916 int condition
= nir_src_index(ctx
, src
);
918 /* There is no boolean move instruction. Instead, we simulate a move by
919 * ANDing the condition with itself to get it into r31.w */
921 midgard_instruction ins
= {
923 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
927 .dest
= SSA_FIXED_REGISTER(31),
930 .op
= midgard_alu_op_iand
,
931 .reg_mode
= midgard_reg_mode_full
,
932 .dest_override
= midgard_dest_override_none
,
933 .mask
= (0x3 << 6), /* w */
934 .src1
= vector_alu_srco_unsigned(blank_alu_src_xxxx
),
935 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
939 emit_mir_instruction(ctx
, ins
);
942 #define ALU_CASE(nir, _op) \
944 op = midgard_alu_op_##_op; \
948 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
950 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
952 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
953 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
954 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
956 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
957 * supported. A few do not and are commented for now. Also, there are a
958 * number of NIR ops which Midgard does not support and need to be
959 * lowered, also TODO. This switch block emits the opcode and calling
960 * convention of the Midgard instruction; actual packing is done in
966 ALU_CASE(fadd
, fadd
);
967 ALU_CASE(fmul
, fmul
);
968 ALU_CASE(fmin
, fmin
);
969 ALU_CASE(fmax
, fmax
);
970 ALU_CASE(imin
, imin
);
971 ALU_CASE(imax
, imax
);
972 ALU_CASE(fmov
, fmov
);
973 ALU_CASE(ffloor
, ffloor
);
974 ALU_CASE(fround_even
, froundeven
);
975 ALU_CASE(ftrunc
, ftrunc
);
976 ALU_CASE(fceil
, fceil
);
977 ALU_CASE(fdot3
, fdot3
);
978 ALU_CASE(fdot4
, fdot4
);
979 ALU_CASE(iadd
, iadd
);
980 ALU_CASE(isub
, isub
);
981 ALU_CASE(imul
, imul
);
982 ALU_CASE(iabs
, iabs
);
984 /* XXX: Use fmov, not imov, since imov was causing major
985 * issues with texture precision? XXX research */
986 ALU_CASE(imov
, fmov
);
988 ALU_CASE(feq32
, feq
);
989 ALU_CASE(fne32
, fne
);
990 ALU_CASE(flt32
, flt
);
991 ALU_CASE(ieq32
, ieq
);
992 ALU_CASE(ine32
, ine
);
993 ALU_CASE(ilt32
, ilt
);
995 /* We don't have a native b2f32 instruction. Instead, like many
996 * GPUs, we exploit booleans as 0/~0 for false/true, and
997 * correspondingly AND
998 * by 1.0 to do the type conversion. For the moment, prime us
1001 * iand [whatever], #0
1003 * At the end of emit_alu (as MIR), we'll fix-up the constant
1006 ALU_CASE(b2f32
, iand
);
1007 ALU_CASE(b2i32
, iand
);
1009 /* Likewise, we don't have a dedicated f2b32 instruction, but
1010 * we can do a "not equal to 0.0" test. */
1012 ALU_CASE(f2b32
, fne
);
1013 ALU_CASE(i2b32
, ine
);
1015 ALU_CASE(frcp
, frcp
);
1016 ALU_CASE(frsq
, frsqrt
);
1017 ALU_CASE(fsqrt
, fsqrt
);
1018 ALU_CASE(fpow
, fpow
);
1019 ALU_CASE(fexp2
, fexp2
);
1020 ALU_CASE(flog2
, flog2
);
1022 ALU_CASE(f2i32
, f2i
);
1023 ALU_CASE(f2u32
, f2u
);
1024 ALU_CASE(i2f32
, i2f
);
1025 ALU_CASE(u2f32
, u2f
);
1027 ALU_CASE(fsin
, fsin
);
1028 ALU_CASE(fcos
, fcos
);
1030 ALU_CASE(iand
, iand
);
1032 ALU_CASE(ixor
, ixor
);
1033 ALU_CASE(inot
, inot
);
1034 ALU_CASE(ishl
, ishl
);
1035 ALU_CASE(ishr
, iasr
);
1036 ALU_CASE(ushr
, ilsr
);
1038 ALU_CASE(b32all_fequal2
, fball_eq
);
1039 ALU_CASE(b32all_fequal3
, fball_eq
);
1040 ALU_CASE(b32all_fequal4
, fball_eq
);
1042 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1043 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1044 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1046 ALU_CASE(b32all_iequal2
, iball_eq
);
1047 ALU_CASE(b32all_iequal3
, iball_eq
);
1048 ALU_CASE(b32all_iequal4
, iball_eq
);
1050 ALU_CASE(b32any_inequal2
, ibany_neq
);
1051 ALU_CASE(b32any_inequal3
, ibany_neq
);
1052 ALU_CASE(b32any_inequal4
, ibany_neq
);
1054 /* For greater-or-equal, we use less-or-equal and flip the
1057 case nir_op_ige32
: {
1058 op
= midgard_alu_op_ile
;
1060 /* Swap via temporary */
1061 nir_alu_src temp
= instr
->src
[1];
1062 instr
->src
[1] = instr
->src
[0];
1063 instr
->src
[0] = temp
;
1068 case nir_op_b32csel
: {
1069 op
= midgard_alu_op_fcsel
;
1071 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1074 emit_condition(ctx
, &instr
->src
[0].src
, false);
1076 /* The condition is the first argument; move the other
1077 * arguments up one to be a binary instruction for
1080 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1085 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1090 /* Fetch unit, quirks, etc information */
1091 unsigned opcode_props
= alu_opcode_props
[op
];
1092 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1094 /* Initialise fields common between scalar/vector instructions */
1095 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1097 /* src0 will always exist afaik, but src1 will not for 1-argument
1098 * instructions. The latter can only be fetched if the instruction
1099 * needs it, or else we may segfault. */
1101 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1102 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1104 /* Rather than use the instruction generation helpers, we do it
1105 * ourselves here to avoid the mess */
1107 midgard_instruction ins
= {
1110 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1111 .src1
= quirk_flipped_r24
? src0
: src1
,
1116 nir_alu_src
*nirmods
[2] = { NULL
};
1118 if (nr_inputs
== 2) {
1119 nirmods
[0] = &instr
->src
[0];
1120 nirmods
[1] = &instr
->src
[1];
1121 } else if (nr_inputs
== 1) {
1122 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1127 midgard_vector_alu alu
= {
1129 .reg_mode
= midgard_reg_mode_full
,
1130 .dest_override
= midgard_dest_override_none
,
1133 /* Writemask only valid for non-SSA NIR */
1134 .mask
= expand_writemask((1 << nr_components
) - 1),
1136 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1137 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1140 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1143 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1147 /* Late fixup for emulated instructions */
1149 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1150 /* Presently, our second argument is an inline #0 constant.
1151 * Switch over to an embedded 1.0 constant (that can't fit
1152 * inline, since we're 32-bit, not 16-bit like the inline
1155 ins
.ssa_args
.inline_constant
= false;
1156 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1157 ins
.has_constants
= true;
1159 if (instr
->op
== nir_op_b2f32
) {
1160 ins
.constants
[0] = 1.0f
;
1162 /* Type pun it into place */
1164 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1167 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1168 } else if (instr
->op
== nir_op_f2b32
) {
1169 ins
.ssa_args
.inline_constant
= false;
1170 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1171 ins
.has_constants
= true;
1172 ins
.constants
[0] = 0.0f
;
1173 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1176 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1177 /* To avoid duplicating the lookup tables (probably), true LUT
1178 * instructions can only operate as if they were scalars. Lower
1179 * them here by changing the component. */
1181 uint8_t original_swizzle
[4];
1182 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1184 for (int i
= 0; i
< nr_components
; ++i
) {
1185 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1187 for (int j
= 0; j
< 4; ++j
)
1188 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1190 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1191 emit_mir_instruction(ctx
, ins
);
1194 emit_mir_instruction(ctx
, ins
);
1201 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1203 nir_const_value
*const_offset
;
1204 unsigned offset
, reg
;
1206 switch (instr
->intrinsic
) {
1207 case nir_intrinsic_discard_if
:
1208 emit_condition(ctx
, &instr
->src
[0], true);
1212 case nir_intrinsic_discard
: {
1213 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1214 struct midgard_instruction discard
= v_branch(conditional
, false);
1215 discard
.branch
.target_type
= TARGET_DISCARD
;
1216 emit_mir_instruction(ctx
, discard
);
1218 ctx
->can_discard
= true;
1222 case nir_intrinsic_load_uniform
:
1223 case nir_intrinsic_load_input
:
1224 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1225 assert (const_offset
&& "no indirect inputs");
1227 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1229 reg
= nir_dest_index(ctx
, &instr
->dest
);
1231 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1232 /* TODO: half-floats */
1234 int uniform_offset
= 0;
1236 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1237 /* XXX: Resolve which uniform */
1240 /* Offset away from the special
1243 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1247 DBG("WARNING: Unknown uniform %d\n", offset
);
1251 uniform_offset
= (uintptr_t) (entry
) - 1;
1252 uniform_offset
+= ctx
->special_uniforms
;
1255 if (uniform_offset
< ctx
->uniform_cutoff
) {
1256 /* Fast path: For the first 16 uniform,
1257 * accesses are 0-cycle, since they're
1258 * just a register fetch in the usual
1259 * case. So, we alias the registers
1260 * while we're still in SSA-space */
1262 int reg_slot
= 23 - uniform_offset
;
1263 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1265 /* Otherwise, read from the 'special'
1266 * UBO to access higher-indexed
1267 * uniforms, at a performance cost */
1269 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1271 /* TODO: Don't split */
1272 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1273 ins
.load_store
.address
= uniform_offset
>> 3;
1275 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1276 emit_mir_instruction(ctx
, ins
);
1278 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1279 /* XXX: Half-floats? */
1280 /* TODO: swizzle, mask */
1282 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1284 midgard_varying_parameter p
= {
1286 .interpolation
= midgard_interp_default
,
1287 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1291 memcpy(&u
, &p
, sizeof(p
));
1292 ins
.load_store
.varying_parameters
= u
;
1294 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1295 emit_mir_instruction(ctx
, ins
);
1296 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1297 /* Constant encoded as a pinned constant */
1299 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1300 ins
.has_constants
= true;
1301 ins
.has_blend_constant
= true;
1302 emit_mir_instruction(ctx
, ins
);
1303 } else if (ctx
->is_blend
) {
1304 /* For blend shaders, a load might be
1305 * translated various ways depending on what
1306 * we're loading. Figure out how this is used */
1308 nir_variable
*out
= NULL
;
1310 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1311 int drvloc
= var
->data
.driver_location
;
1313 if (nir_intrinsic_base(instr
) == drvloc
) {
1321 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1322 /* Source color preloaded to r0 */
1324 midgard_pin_output(ctx
, reg
, 0);
1325 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1326 /* Destination color must be read from framebuffer */
1328 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1329 ins
.load_store
.swizzle
= 0; /* xxxx */
1331 /* Read each component sequentially */
1333 for (int c
= 0; c
< 4; ++c
) {
1334 ins
.load_store
.mask
= (1 << c
);
1335 ins
.load_store
.unknown
= c
;
1336 emit_mir_instruction(ctx
, ins
);
1339 /* vadd.u2f hr2, abs(hr2), #0 */
1341 midgard_vector_alu_src alu_src
= blank_alu_src
;
1343 alu_src
.half
= true;
1345 midgard_instruction u2f
= {
1349 .src1
= SSA_UNUSED_0
,
1351 .inline_constant
= true
1354 .op
= midgard_alu_op_u2f
,
1355 .reg_mode
= midgard_reg_mode_half
,
1356 .dest_override
= midgard_dest_override_none
,
1358 .src1
= vector_alu_srco_unsigned(alu_src
),
1359 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1363 emit_mir_instruction(ctx
, u2f
);
1365 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1367 alu_src
.abs
= false;
1369 midgard_instruction fmul
= {
1371 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1375 .src1
= SSA_UNUSED_0
,
1376 .inline_constant
= true
1379 .op
= midgard_alu_op_fmul
,
1380 .reg_mode
= midgard_reg_mode_full
,
1381 .dest_override
= midgard_dest_override_none
,
1382 .outmod
= midgard_outmod_sat
,
1384 .src1
= vector_alu_srco_unsigned(alu_src
),
1385 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1389 emit_mir_instruction(ctx
, fmul
);
1391 DBG("Unknown input in blend shader\n");
1394 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1395 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1396 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1397 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1398 emit_mir_instruction(ctx
, ins
);
1400 DBG("Unknown load\n");
1406 case nir_intrinsic_store_output
:
1407 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1408 assert(const_offset
&& "no indirect outputs");
1410 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1412 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1414 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1415 /* gl_FragColor is not emitted with load/store
1416 * instructions. Instead, it gets plonked into
1417 * r0 at the end of the shader and we do the
1418 * framebuffer writeout dance. TODO: Defer
1421 midgard_pin_output(ctx
, reg
, 0);
1423 /* Save the index we're writing to for later reference
1424 * in the epilogue */
1426 ctx
->fragment_output
= reg
;
1427 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1428 /* Varyings are written into one of two special
1429 * varying register, r26 or r27. The register itself is selected as the register
1430 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1432 * Normally emitting fmov's is frowned upon,
1433 * but due to unique constraints of
1434 * REGISTER_VARYING, fmov emission + a
1435 * dedicated cleanup pass is the only way to
1436 * guarantee correctness when considering some
1437 * (common) edge cases XXX: FIXME */
1439 /* If this varying corresponds to a constant (why?!),
1440 * emit that now since it won't get picked up by
1441 * hoisting (since there is no corresponding move
1442 * emitted otherwise) */
1444 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1446 if (constant_value
) {
1447 /* Special case: emit the varying write
1448 * directly to r26 (looks funny in asm but it's
1449 * fine) and emit the store _now_. Possibly
1450 * slightly slower, but this is a really stupid
1451 * special case anyway (why on earth would you
1452 * have a constant varying? Your own fault for
1453 * slightly worse perf :P) */
1455 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1456 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1457 emit_mir_instruction(ctx
, ins
);
1459 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1460 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1461 emit_mir_instruction(ctx
, st
);
1463 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1465 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1468 DBG("Unknown store\n");
1474 case nir_intrinsic_load_alpha_ref_float
:
1475 assert(instr
->dest
.is_ssa
);
1477 float ref_value
= ctx
->alpha_ref
;
1479 float *v
= ralloc_array(NULL
, float, 4);
1480 memcpy(v
, &ref_value
, sizeof(float));
1481 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1486 printf ("Unhandled intrinsic\n");
1493 midgard_tex_format(enum glsl_sampler_dim dim
)
1496 case GLSL_SAMPLER_DIM_2D
:
1497 case GLSL_SAMPLER_DIM_EXTERNAL
:
1500 case GLSL_SAMPLER_DIM_3D
:
1503 case GLSL_SAMPLER_DIM_CUBE
:
1504 return TEXTURE_CUBE
;
1507 DBG("Unknown sampler dim type\n");
1514 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1517 //assert (!instr->sampler);
1518 //assert (!instr->texture_array_size);
1519 assert (instr
->op
== nir_texop_tex
);
1521 /* Allocate registers via a round robin scheme to alternate between the two registers */
1522 int reg
= ctx
->texture_op_count
& 1;
1523 int in_reg
= reg
, out_reg
= reg
;
1525 /* Make room for the reg */
1527 if (ctx
->texture_index
[reg
] > -1)
1528 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1530 int texture_index
= instr
->texture_index
;
1531 int sampler_index
= texture_index
;
1533 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1534 switch (instr
->src
[i
].src_type
) {
1535 case nir_tex_src_coord
: {
1536 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1538 midgard_vector_alu_src alu_src
= blank_alu_src
;
1539 alu_src
.swizzle
= (COMPONENT_Y
<< 2);
1541 midgard_instruction ins
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
));
1542 emit_mir_instruction(ctx
, ins
);
1544 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1550 DBG("Unknown source type\n");
1557 /* No helper to build texture words -- we do it all here */
1558 midgard_instruction ins
= {
1559 .type
= TAG_TEXTURE_4
,
1561 .op
= TEXTURE_OP_NORMAL
,
1562 .format
= midgard_tex_format(instr
->sampler_dim
),
1563 .texture_handle
= texture_index
,
1564 .sampler_handle
= sampler_index
,
1566 /* TODO: Don't force xyzw */
1567 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1579 /* Assume we can continue; hint it out later */
1584 /* Set registers to read and write from the same place */
1585 ins
.texture
.in_reg_select
= in_reg
;
1586 ins
.texture
.out_reg_select
= out_reg
;
1588 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1589 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1590 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1591 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1592 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1594 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1595 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1596 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1599 emit_mir_instruction(ctx
, ins
);
1601 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1603 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1604 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1605 ctx
->texture_index
[reg
] = o_index
;
1607 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1608 emit_mir_instruction(ctx
, ins2
);
1610 /* Used for .cont and .last hinting */
1611 ctx
->texture_op_count
++;
1615 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1617 switch (instr
->type
) {
1618 case nir_jump_break
: {
1619 /* Emit a branch out of the loop */
1620 struct midgard_instruction br
= v_branch(false, false);
1621 br
.branch
.target_type
= TARGET_BREAK
;
1622 br
.branch
.target_break
= ctx
->current_loop
;
1623 emit_mir_instruction(ctx
, br
);
1630 DBG("Unknown jump type %d\n", instr
->type
);
1636 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1638 switch (instr
->type
) {
1639 case nir_instr_type_load_const
:
1640 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1643 case nir_instr_type_intrinsic
:
1644 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1647 case nir_instr_type_alu
:
1648 emit_alu(ctx
, nir_instr_as_alu(instr
));
1651 case nir_instr_type_tex
:
1652 emit_tex(ctx
, nir_instr_as_tex(instr
));
1655 case nir_instr_type_jump
:
1656 emit_jump(ctx
, nir_instr_as_jump(instr
));
1659 case nir_instr_type_ssa_undef
:
1664 DBG("Unhandled instruction type\n");
1669 /* Determine the actual hardware from the index based on the RA results or special values */
1672 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1674 if (reg
>= SSA_FIXED_MINIMUM
)
1675 return SSA_REG_FROM_FIXED(reg
);
1678 assert(reg
< maxreg
);
1679 int r
= ra_get_node_reg(g
, reg
);
1680 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1685 /* fmov style unused */
1687 return REGISTER_UNUSED
;
1689 /* lut style unused */
1691 return REGISTER_UNUSED
;
1694 DBG("Unknown SSA register alias %d\n", reg
);
1701 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1703 /* Choose the first available register to minimise reported register pressure */
1705 for (int i
= 0; i
< 16; ++i
) {
1706 if (BITSET_TEST(regs
, i
)) {
1716 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1718 if (ins
->ssa_args
.src0
== src
) return true;
1719 if (ins
->ssa_args
.src1
== src
) return true;
1725 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1727 /* Check the rest of the block for liveness */
1728 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1729 if (midgard_is_live_in_instr(ins
, src
))
1733 /* Check the rest of the blocks for liveness */
1734 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1735 mir_foreach_instr_in_block(b
, ins
) {
1736 if (midgard_is_live_in_instr(ins
, src
))
1741 /* TODO: How does control flow interact in complex shaders? */
1747 allocate_registers(compiler_context
*ctx
)
1749 /* First, initialize the RA */
1750 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1752 /* Create a primary (general purpose) class, as well as special purpose
1753 * pipeline register classes */
1755 int primary_class
= ra_alloc_reg_class(regs
);
1756 int varying_class
= ra_alloc_reg_class(regs
);
1758 /* Add the full set of work registers */
1759 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1760 for (int i
= 0; i
< work_count
; ++i
)
1761 ra_class_add_reg(regs
, primary_class
, i
);
1763 /* Add special registers */
1764 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1765 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1767 /* We're done setting up */
1768 ra_set_finalize(regs
, NULL
);
1770 /* Transform the MIR into squeezed index form */
1771 mir_foreach_block(ctx
, block
) {
1772 mir_foreach_instr_in_block(block
, ins
) {
1773 if (ins
->compact_branch
) continue;
1775 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1776 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1777 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1779 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
1780 print_mir_block(block
);
1783 /* Let's actually do register allocation */
1784 int nodes
= ctx
->temp_count
;
1785 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1787 /* Set everything to the work register class, unless it has somewhere
1790 mir_foreach_block(ctx
, block
) {
1791 mir_foreach_instr_in_block(block
, ins
) {
1792 if (ins
->compact_branch
) continue;
1794 if (ins
->ssa_args
.dest
< 0) continue;
1796 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1798 int class = primary_class
;
1800 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1804 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1805 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1808 unsigned reg
= temp
- 1;
1809 int t
= find_or_allocate_temp(ctx
, index
);
1810 ra_set_node_reg(g
, t
, reg
);
1814 /* Determine liveness */
1816 int *live_start
= malloc(nodes
* sizeof(int));
1817 int *live_end
= malloc(nodes
* sizeof(int));
1819 /* Initialize as non-existent */
1821 for (int i
= 0; i
< nodes
; ++i
) {
1822 live_start
[i
] = live_end
[i
] = -1;
1827 mir_foreach_block(ctx
, block
) {
1828 mir_foreach_instr_in_block(block
, ins
) {
1829 if (ins
->compact_branch
) continue;
1831 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1832 /* If this destination is not yet live, it is now since we just wrote it */
1834 int dest
= ins
->ssa_args
.dest
;
1836 if (live_start
[dest
] == -1)
1837 live_start
[dest
] = d
;
1840 /* Since we just used a source, the source might be
1841 * dead now. Scan the rest of the block for
1842 * invocations, and if there are none, the source dies
1845 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1847 for (int src
= 0; src
< 2; ++src
) {
1848 int s
= sources
[src
];
1850 if (s
< 0) continue;
1852 if (s
>= SSA_FIXED_MINIMUM
) continue;
1854 if (!is_live_after(ctx
, block
, ins
, s
)) {
1863 /* If a node still hasn't been killed, kill it now */
1865 for (int i
= 0; i
< nodes
; ++i
) {
1866 /* live_start == -1 most likely indicates a pinned output */
1868 if (live_end
[i
] == -1)
1872 /* Setup interference between nodes that are live at the same time */
1874 for (int i
= 0; i
< nodes
; ++i
) {
1875 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1876 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1877 ra_add_node_interference(g
, i
, j
);
1881 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1883 if (!ra_allocate(g
)) {
1884 DBG("Error allocating registers\n");
1892 mir_foreach_block(ctx
, block
) {
1893 mir_foreach_instr_in_block(block
, ins
) {
1894 if (ins
->compact_branch
) continue;
1896 ssa_args args
= ins
->ssa_args
;
1898 switch (ins
->type
) {
1900 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1902 ins
->registers
.src2_imm
= args
.inline_constant
;
1904 if (args
.inline_constant
) {
1905 /* Encode inline 16-bit constant as a vector by default */
1907 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1909 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1911 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1912 ins
->alu
.src2
= imm
<< 2;
1914 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1917 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1921 case TAG_LOAD_STORE_4
: {
1922 if (OP_IS_STORE(ins
->load_store
.op
)) {
1923 /* TODO: use ssa_args for store_vary */
1924 ins
->load_store
.reg
= 0;
1926 bool has_dest
= args
.dest
>= 0;
1927 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1929 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1942 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1943 * use scalar ALU instructions, for functional or performance reasons. To do
1944 * this, we just demote vector ALU payloads to scalar. */
1947 component_from_mask(unsigned mask
)
1949 for (int c
= 0; c
< 4; ++c
) {
1950 if (mask
& (3 << (2 * c
)))
1959 is_single_component_mask(unsigned mask
)
1963 for (int c
= 0; c
< 4; ++c
)
1964 if (mask
& (3 << (2 * c
)))
1967 return components
== 1;
1970 /* Create a mask of accessed components from a swizzle to figure out vector
1974 swizzle_to_access_mask(unsigned swizzle
)
1976 unsigned component_mask
= 0;
1978 for (int i
= 0; i
< 4; ++i
) {
1979 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1980 component_mask
|= (1 << c
);
1983 return component_mask
;
1987 vector_to_scalar_source(unsigned u
)
1989 midgard_vector_alu_src v
;
1990 memcpy(&v
, &u
, sizeof(v
));
1992 midgard_scalar_alu_src s
= {
1996 .component
= (v
.swizzle
& 3) << 1
2000 memcpy(&o
, &s
, sizeof(s
));
2002 return o
& ((1 << 6) - 1);
2005 static midgard_scalar_alu
2006 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2008 /* The output component is from the mask */
2009 midgard_scalar_alu s
= {
2011 .src1
= vector_to_scalar_source(v
.src1
),
2012 .src2
= vector_to_scalar_source(v
.src2
),
2015 .output_full
= 1, /* TODO: Half */
2016 .output_component
= component_from_mask(v
.mask
) << 1,
2019 /* Inline constant is passed along rather than trying to extract it
2022 if (ins
->ssa_args
.inline_constant
) {
2024 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2025 imm
|= (lower_11
>> 9) & 3;
2026 imm
|= (lower_11
>> 6) & 4;
2027 imm
|= (lower_11
>> 2) & 0x38;
2028 imm
|= (lower_11
& 63) << 6;
2036 /* Midgard prefetches instruction types, so during emission we need to
2037 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2038 * if this is the second to last and the last is an ALU, then it's also 1... */
2040 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2041 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2043 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2044 bytes_emitted += sizeof(type)
2047 emit_binary_vector_instruction(midgard_instruction
*ains
,
2048 uint16_t *register_words
, int *register_words_count
,
2049 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2050 size_t *bytes_emitted
)
2052 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2053 *bytes_emitted
+= sizeof(midgard_reg_info
);
2055 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2056 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2057 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2060 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2061 * mind that we are a vector architecture and we can write to different
2062 * components simultaneously */
2065 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2067 /* Each instruction reads some registers and writes to a register. See
2068 * where the first writes */
2070 /* Figure out where exactly we wrote to */
2071 int source
= first
->ssa_args
.dest
;
2072 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2074 /* As long as the second doesn't read from the first, we're okay */
2075 if (second
->ssa_args
.src0
== source
) {
2076 if (first
->type
== TAG_ALU_4
) {
2077 /* Figure out which components we just read from */
2079 int q
= second
->alu
.src1
;
2080 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2082 /* Check if there are components in common, and fail if so */
2083 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2090 if (second
->ssa_args
.src1
== source
)
2093 /* Otherwise, it's safe in that regard. Another data hazard is both
2094 * writing to the same place, of course */
2096 if (second
->ssa_args
.dest
== source
) {
2097 /* ...but only if the components overlap */
2098 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2100 if (dest_mask
& source_mask
)
2110 midgard_instruction
**segment
, unsigned segment_size
,
2111 midgard_instruction
*ains
)
2113 for (int s
= 0; s
< segment_size
; ++s
)
2114 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2122 /* Schedules, but does not emit, a single basic block. After scheduling, the
2123 * final tag and size of the block are known, which are necessary for branching
2126 static midgard_bundle
2127 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2129 int instructions_emitted
= 0, instructions_consumed
= -1;
2130 midgard_bundle bundle
= { 0 };
2132 uint8_t tag
= ins
->type
;
2134 /* Default to the instruction's tag */
2137 switch (ins
->type
) {
2139 uint32_t control
= 0;
2140 size_t bytes_emitted
= sizeof(control
);
2142 /* TODO: Constant combining */
2143 int index
= 0, last_unit
= 0;
2145 /* Previous instructions, for the purpose of parallelism */
2146 midgard_instruction
*segment
[4] = {0};
2147 int segment_size
= 0;
2149 instructions_emitted
= -1;
2150 midgard_instruction
*pins
= ins
;
2153 midgard_instruction
*ains
= pins
;
2155 /* Advance instruction pointer */
2157 ains
= mir_next_op(pins
);
2161 /* Out-of-work condition */
2162 if ((struct list_head
*) ains
== &block
->instructions
)
2165 /* Ensure that the chain can continue */
2166 if (ains
->type
!= TAG_ALU_4
) break;
2168 /* According to the presentation "The ARM
2169 * Mali-T880 Mobile GPU" from HotChips 27,
2170 * there are two pipeline stages. Branching
2171 * position determined experimentally. Lines
2172 * are executed in parallel:
2175 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2177 * Verify that there are no ordering dependencies here.
2179 * TODO: Allow for parallelism!!!
2182 /* Pick a unit for it if it doesn't force a particular unit */
2184 int unit
= ains
->unit
;
2187 int op
= ains
->alu
.op
;
2188 int units
= alu_opcode_props
[op
];
2190 /* TODO: Promotion of scalars to vectors */
2191 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2194 assert(units
& UNITS_SCALAR
);
2197 if (last_unit
>= UNIT_VADD
) {
2198 if (units
& UNIT_VLUT
)
2203 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2205 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2207 else if (units
& UNIT_VLUT
)
2213 if (last_unit
>= UNIT_VADD
) {
2214 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2216 else if (units
& UNIT_VLUT
)
2221 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2223 else if (units
& UNIT_SMUL
)
2224 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2225 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2232 assert(unit
& units
);
2235 /* Late unit check, this time for encoding (not parallelism) */
2236 if (unit
<= last_unit
) break;
2238 /* Clear the segment */
2239 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2242 if (midgard_has_hazard(segment
, segment_size
, ains
))
2245 /* We're good to go -- emit the instruction */
2248 segment
[segment_size
++] = ains
;
2250 /* Only one set of embedded constants per
2251 * bundle possible; if we have more, we must
2252 * break the chain early, unfortunately */
2254 if (ains
->has_constants
) {
2255 if (bundle
.has_embedded_constants
) {
2256 /* ...but if there are already
2257 * constants but these are the
2258 * *same* constants, we let it
2261 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2264 bundle
.has_embedded_constants
= true;
2265 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2267 /* If this is a blend shader special constant, track it for patching */
2268 if (ains
->has_blend_constant
)
2269 bundle
.has_blend_constant
= true;
2273 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2274 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2275 &bundle
.register_words_count
, bundle
.body_words
,
2276 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2277 } else if (ains
->compact_branch
) {
2278 /* All of r0 has to be written out
2279 * along with the branch writeout.
2282 if (ains
->writeout
) {
2284 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2285 ins
.unit
= UNIT_VMUL
;
2287 control
|= ins
.unit
;
2289 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2290 &bundle
.register_words_count
, bundle
.body_words
,
2291 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2293 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2294 bool written_late
= false;
2295 bool components
[4] = { 0 };
2296 uint16_t register_dep_mask
= 0;
2297 uint16_t written_mask
= 0;
2299 midgard_instruction
*qins
= ins
;
2300 for (int t
= 0; t
< index
; ++t
) {
2301 if (qins
->registers
.out_reg
!= 0) {
2302 /* Mark down writes */
2304 written_mask
|= (1 << qins
->registers
.out_reg
);
2306 /* Mark down the register dependencies for errata check */
2308 if (qins
->registers
.src1_reg
< 16)
2309 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2311 if (qins
->registers
.src2_reg
< 16)
2312 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2314 int mask
= qins
->alu
.mask
;
2316 for (int c
= 0; c
< 4; ++c
)
2317 if (mask
& (0x3 << (2 * c
)))
2318 components
[c
] = true;
2320 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2322 if (qins
->unit
== UNIT_VLUT
)
2323 written_late
= true;
2326 /* Advance instruction pointer */
2327 qins
= mir_next_op(qins
);
2331 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2332 if (register_dep_mask
& written_mask
) {
2333 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2340 /* If even a single component is not written, break it up (conservative check). */
2341 bool breakup
= false;
2343 for (int c
= 0; c
< 4; ++c
)
2350 /* Otherwise, we're free to proceed */
2354 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2355 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2356 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2357 bytes_emitted
+= sizeof(midgard_branch_extended
);
2359 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2360 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2361 bytes_emitted
+= sizeof(ains
->br_compact
);
2364 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2365 bytes_emitted
+= sizeof(midgard_reg_info
);
2367 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2368 bundle
.body_words_count
++;
2369 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2372 /* Defer marking until after writing to allow for break */
2373 control
|= ains
->unit
;
2374 last_unit
= ains
->unit
;
2375 ++instructions_emitted
;
2379 /* Bubble up the number of instructions for skipping */
2380 instructions_consumed
= index
- 1;
2384 /* Pad ALU op to nearest word */
2386 if (bytes_emitted
& 15) {
2387 padding
= 16 - (bytes_emitted
& 15);
2388 bytes_emitted
+= padding
;
2391 /* Constants must always be quadwords */
2392 if (bundle
.has_embedded_constants
)
2393 bytes_emitted
+= 16;
2395 /* Size ALU instruction for tag */
2396 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2397 bundle
.padding
= padding
;
2398 bundle
.control
= bundle
.tag
| control
;
2403 case TAG_LOAD_STORE_4
: {
2404 /* Load store instructions have two words at once. If
2405 * we only have one queued up, we need to NOP pad.
2406 * Otherwise, we store both in succession to save space
2407 * and cycles -- letting them go in parallel -- skip
2408 * the next. The usefulness of this optimisation is
2409 * greatly dependent on the quality of the instruction
2413 midgard_instruction
*next_op
= mir_next_op(ins
);
2415 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2416 /* As the two operate concurrently, make sure
2417 * they are not dependent */
2419 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2420 /* Skip ahead, since it's redundant with the pair */
2421 instructions_consumed
= 1 + (instructions_emitted
++);
2429 /* Texture ops default to single-op-per-bundle scheduling */
2433 /* Copy the instructions into the bundle */
2434 bundle
.instruction_count
= instructions_emitted
+ 1;
2438 midgard_instruction
*uins
= ins
;
2439 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2440 bundle
.instructions
[used_idx
++] = *uins
;
2441 uins
= mir_next_op(uins
);
2444 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2450 quadword_size(int tag
)
2465 case TAG_LOAD_STORE_4
:
2477 /* Schedule a single block by iterating its instruction to create bundles.
2478 * While we go, tally about the bundle sizes to compute the block size. */
2481 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2483 util_dynarray_init(&block
->bundles
, NULL
);
2485 block
->quadword_count
= 0;
2487 mir_foreach_instr_in_block(block
, ins
) {
2489 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2490 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2492 if (bundle
.has_blend_constant
) {
2493 /* TODO: Multiblock? */
2494 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2495 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2499 ins
= mir_next_op(ins
);
2501 block
->quadword_count
+= quadword_size(bundle
.tag
);
2504 block
->is_scheduled
= true;
2508 schedule_program(compiler_context
*ctx
)
2510 allocate_registers(ctx
);
2512 mir_foreach_block(ctx
, block
) {
2513 schedule_block(ctx
, block
);
2517 /* After everything is scheduled, emit whole bundles at a time */
2520 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2522 int lookahead
= next_tag
<< 4;
2524 switch (bundle
->tag
) {
2529 /* Actually emit each component */
2530 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2532 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2533 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2535 /* Emit body words based on the instructions bundled */
2536 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2537 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2539 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2540 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2541 } else if (ins
->compact_branch
) {
2542 /* Dummy move, XXX DRY */
2543 if ((i
== 0) && ins
->writeout
) {
2544 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2545 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2548 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2549 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2551 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2555 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2556 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2560 /* Emit padding (all zero) */
2561 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2563 /* Tack on constants */
2565 if (bundle
->has_embedded_constants
) {
2566 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2567 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2568 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2569 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2575 case TAG_LOAD_STORE_4
: {
2576 /* One or two composing instructions */
2578 uint64_t current64
, next64
= LDST_NOP
;
2580 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2582 if (bundle
->instruction_count
== 2)
2583 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2585 midgard_load_store instruction
= {
2586 .type
= bundle
->tag
,
2587 .next_type
= next_tag
,
2592 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2597 case TAG_TEXTURE_4
: {
2598 /* Texture instructions are easy, since there is no
2599 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2601 midgard_instruction
*ins
= &bundle
->instructions
[0];
2603 ins
->texture
.type
= TAG_TEXTURE_4
;
2604 ins
->texture
.next_type
= next_tag
;
2606 ctx
->texture_op_count
--;
2608 if (!ctx
->texture_op_count
) {
2609 ins
->texture
.cont
= 0;
2610 ins
->texture
.last
= 1;
2613 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2618 DBG("Unknown midgard instruction type\n");
2625 /* ALU instructions can inline or embed constants, which decreases register
2626 * pressure and saves space. */
2628 #define CONDITIONAL_ATTACH(src) { \
2629 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2632 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2633 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2638 inline_alu_constants(compiler_context
*ctx
)
2640 mir_foreach_instr(ctx
, alu
) {
2641 /* Other instructions cannot inline constants */
2642 if (alu
->type
!= TAG_ALU_4
) continue;
2644 /* If there is already a constant here, we can do nothing */
2645 if (alu
->has_constants
) continue;
2647 CONDITIONAL_ATTACH(src0
);
2649 if (!alu
->has_constants
) {
2650 CONDITIONAL_ATTACH(src1
)
2651 } else if (!alu
->inline_constant
) {
2652 /* Corner case: _two_ vec4 constants, for instance with a
2653 * csel. For this case, we can only use a constant
2654 * register for one, we'll have to emit a move for the
2655 * other. Note, if both arguments are constants, then
2656 * necessarily neither argument depends on the value of
2657 * any particular register. As the destination register
2658 * will be wiped, that means we can spill the constant
2659 * to the destination register.
2662 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2663 unsigned scratch
= alu
->ssa_args
.dest
;
2666 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2667 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2669 /* Force a break XXX Defer r31 writes */
2670 ins
.unit
= UNIT_VLUT
;
2672 /* Set the source */
2673 alu
->ssa_args
.src1
= scratch
;
2675 /* Inject us -before- the last instruction which set r31 */
2676 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2682 /* Midgard supports two types of constants, embedded constants (128-bit) and
2683 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2684 * constants can be demoted to inline constants, for space savings and
2685 * sometimes a performance boost */
2688 embedded_to_inline_constant(compiler_context
*ctx
)
2690 mir_foreach_instr(ctx
, ins
) {
2691 if (!ins
->has_constants
) continue;
2693 if (ins
->ssa_args
.inline_constant
) continue;
2695 /* Blend constants must not be inlined by definition */
2696 if (ins
->has_blend_constant
) continue;
2698 /* src1 cannot be an inline constant due to encoding
2699 * restrictions. So, if possible we try to flip the arguments
2702 int op
= ins
->alu
.op
;
2704 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2705 /* Flip based on op. Fallthrough intentional */
2708 /* These ops require an operational change to flip their arguments TODO */
2709 case midgard_alu_op_flt
:
2710 case midgard_alu_op_fle
:
2711 case midgard_alu_op_ilt
:
2712 case midgard_alu_op_ile
:
2713 case midgard_alu_op_fcsel
:
2714 case midgard_alu_op_icsel
:
2715 case midgard_alu_op_isub
:
2716 DBG("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2719 /* These ops are commutative and Just Flip */
2720 case midgard_alu_op_fne
:
2721 case midgard_alu_op_fadd
:
2722 case midgard_alu_op_fmul
:
2723 case midgard_alu_op_fmin
:
2724 case midgard_alu_op_fmax
:
2725 case midgard_alu_op_iadd
:
2726 case midgard_alu_op_imul
:
2727 case midgard_alu_op_feq
:
2728 case midgard_alu_op_ieq
:
2729 case midgard_alu_op_ine
:
2730 case midgard_alu_op_iand
:
2731 case midgard_alu_op_ior
:
2732 case midgard_alu_op_ixor
:
2733 /* Flip the SSA numbers */
2734 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2735 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2737 /* And flip the modifiers */
2741 src_temp
= ins
->alu
.src2
;
2742 ins
->alu
.src2
= ins
->alu
.src1
;
2743 ins
->alu
.src1
= src_temp
;
2750 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2751 /* Extract the source information */
2753 midgard_vector_alu_src
*src
;
2754 int q
= ins
->alu
.src2
;
2755 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2758 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2759 int component
= src
->swizzle
& 3;
2761 /* Scale constant appropriately, if we can legally */
2762 uint16_t scaled_constant
= 0;
2764 /* XXX: Check legality */
2765 if (midgard_is_integer_op(op
)) {
2766 /* TODO: Inline integer */
2769 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2770 scaled_constant
= (uint16_t) iconstants
[component
];
2772 /* Constant overflow after resize */
2773 if (scaled_constant
!= iconstants
[component
])
2776 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2779 /* We don't know how to handle these with a constant */
2781 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2782 DBG("Bailing inline constant...\n");
2786 /* Make sure that the constant is not itself a
2787 * vector by checking if all accessed values
2788 * (by the swizzle) are the same. */
2790 uint32_t *cons
= (uint32_t *) ins
->constants
;
2791 uint32_t value
= cons
[component
];
2793 bool is_vector
= false;
2794 unsigned mask
= effective_writemask(&ins
->alu
);
2796 for (int c
= 1; c
< 4; ++c
) {
2797 /* We only care if this component is actually used */
2798 if (!(mask
& (1 << c
)))
2801 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2803 if (test
!= value
) {
2812 /* Get rid of the embedded constant */
2813 ins
->has_constants
= false;
2814 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2815 ins
->ssa_args
.inline_constant
= true;
2816 ins
->inline_constant
= scaled_constant
;
2821 /* Map normal SSA sources to other SSA sources / fixed registers (like
2825 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2827 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2830 /* Remove entry in leftovers to avoid a redunant fmov */
2832 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2835 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2837 /* Assign the alias map */
2843 #define AS_SRC(to, u) \
2844 int q##to = ins->alu.src2; \
2845 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2847 /* Removing unused moves is necessary to clean up the texture pipeline results.
2849 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2852 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2854 mir_foreach_instr_in_block_safe(block
, ins
) {
2855 if (ins
->type
!= TAG_ALU_4
) continue;
2857 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2859 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2861 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2863 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2865 mir_remove_instruction(ins
);
2869 /* The following passes reorder MIR instructions to enable better scheduling */
2872 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2874 mir_foreach_instr_in_block_safe(block
, ins
) {
2875 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2877 /* We've found a load/store op. Check if next is also load/store. */
2878 midgard_instruction
*next_op
= mir_next_op(ins
);
2879 if (&next_op
->link
!= &block
->instructions
) {
2880 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2881 /* If so, we're done since we're a pair */
2882 ins
= mir_next_op(ins
);
2886 /* Maximum search distance to pair, to avoid register pressure disasters */
2887 int search_distance
= 8;
2889 /* Otherwise, we have an orphaned load/store -- search for another load */
2890 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2891 /* Terminate search if necessary */
2892 if (!(search_distance
--)) break;
2894 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2896 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2898 /* We found one! Move it up to pair and remove it from the old location */
2900 mir_insert_instruction_before(ins
, *c
);
2901 mir_remove_instruction(c
);
2909 /* Emit varying stores late */
2912 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2913 /* Iterate in reverse to get the final write, rather than the first */
2915 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2916 /* Check if what we just wrote needs a store */
2917 int idx
= ins
->ssa_args
.dest
;
2918 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2920 if (!varying
) continue;
2924 /* We need to store to the appropriate varying, so emit the
2927 /* TODO: Integrate with special purpose RA (and scheduler?) */
2928 bool high_varying_register
= false;
2930 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2932 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2933 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2935 mir_insert_instruction_before(mir_next_op(ins
), st
);
2936 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2938 /* We no longer need to store this varying */
2939 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2943 /* If there are leftovers after the below pass, emit actual fmov
2944 * instructions for the slow-but-correct path */
2947 emit_leftover_move(compiler_context
*ctx
)
2949 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2950 int base
= ((uintptr_t) leftover
->key
) - 1;
2953 map_ssa_to_alias(ctx
, &mapped
);
2954 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2959 actualise_ssa_to_alias(compiler_context
*ctx
)
2961 mir_foreach_instr(ctx
, ins
) {
2962 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2963 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2966 emit_leftover_move(ctx
);
2969 /* Vertex shaders do not write gl_Position as is; instead, they write a
2970 * transformed screen space position as a varying. See section 12.5 "Coordinate
2971 * Transformation" of the ES 3.2 full specification for details.
2973 * This transformation occurs early on, as NIR and prior to optimisation, in
2974 * order to take advantage of NIR optimisation passes of the transform itself.
2978 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
2980 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
2982 /* Get viewport from the uniforms */
2983 nir_intrinsic_instr
*load
;
2984 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
2985 load
->num_components
= 4;
2986 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
2987 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
2988 nir_builder_instr_insert(b
, &load
->instr
);
2990 /* Formatted as <width, height, centerx, centery> */
2991 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
2992 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
2993 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
2994 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
2996 /* XXX: From uniforms? */
2997 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
2998 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
3000 /* World space to normalised device coordinates */
3002 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
3003 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
3005 /* Normalised device coordinates to screen space */
3007 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
3008 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
3010 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
3011 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
3012 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
3014 /* gl_Position will be written out in screenspace xyz, with w set to
3015 * the reciprocal we computed earlier. The transformed w component is
3016 * then used for perspective-correct varying interpolation. The
3017 * transformed w component must preserve its original sign; this is
3018 * used in depth clipping computations */
3020 nir_ssa_def
*screen_space
= nir_vec4(b
,
3021 nir_channel(b
, viewport_xy
, 0),
3022 nir_channel(b
, viewport_xy
, 1),
3026 /* Finally, write out the transformed values to the varying */
3028 nir_intrinsic_instr
*store
;
3029 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
3030 store
->num_components
= 4;
3031 nir_intrinsic_set_base(store
, 0);
3032 nir_intrinsic_set_write_mask(store
, 0xf);
3033 store
->src
[0].ssa
= screen_space
;
3034 store
->src
[0].is_ssa
= true;
3035 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
3036 nir_builder_instr_insert(b
, &store
->instr
);
3040 transform_position_writes(nir_shader
*shader
)
3042 nir_foreach_function(func
, shader
) {
3043 nir_foreach_block(block
, func
->impl
) {
3044 nir_foreach_instr_safe(instr
, block
) {
3045 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
3047 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
3048 nir_variable
*out
= NULL
;
3050 switch (intr
->intrinsic
) {
3051 case nir_intrinsic_store_output
:
3052 /* already had i/o lowered.. lookup the matching output var: */
3053 nir_foreach_variable(var
, &shader
->outputs
) {
3054 int drvloc
= var
->data
.driver_location
;
3056 if (nir_intrinsic_base(intr
) == drvloc
) {
3070 if (out
->data
.mode
!= nir_var_shader_out
)
3073 if (out
->data
.location
!= VARYING_SLOT_POS
)
3077 nir_builder_init(&b
, func
->impl
);
3078 b
.cursor
= nir_before_instr(instr
);
3080 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
3081 nir_instr_remove(instr
);
3088 emit_fragment_epilogue(compiler_context
*ctx
)
3090 /* Special case: writing out constants requires us to include the move
3091 * explicitly now, so shove it into r0 */
3093 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3095 if (constant_value
) {
3096 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3097 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3098 emit_mir_instruction(ctx
, ins
);
3101 /* Perform the actual fragment writeout. We have two writeout/branch
3102 * instructions, forming a loop until writeout is successful as per the
3103 * docs. TODO: gl_FragDepth */
3105 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3106 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3109 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3110 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3111 * with the int8 analogue to the fragment epilogue */
3114 emit_blend_epilogue(compiler_context
*ctx
)
3116 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3118 midgard_instruction scale
= {
3121 .inline_constant
= _mesa_float_to_half(255.0),
3123 .src0
= SSA_FIXED_REGISTER(0),
3124 .src1
= SSA_UNUSED_0
,
3125 .dest
= SSA_FIXED_REGISTER(24),
3126 .inline_constant
= true
3129 .op
= midgard_alu_op_fmul
,
3130 .reg_mode
= midgard_reg_mode_full
,
3131 .dest_override
= midgard_dest_override_lower
,
3133 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3134 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3138 emit_mir_instruction(ctx
, scale
);
3140 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3142 midgard_vector_alu_src alu_src
= blank_alu_src
;
3143 alu_src
.half
= true;
3145 midgard_instruction f2u8
= {
3148 .src0
= SSA_FIXED_REGISTER(24),
3149 .src1
= SSA_UNUSED_0
,
3150 .dest
= SSA_FIXED_REGISTER(0),
3151 .inline_constant
= true
3154 .op
= midgard_alu_op_f2u8
,
3155 .reg_mode
= midgard_reg_mode_half
,
3156 .dest_override
= midgard_dest_override_lower
,
3157 .outmod
= midgard_outmod_pos
,
3159 .src1
= vector_alu_srco_unsigned(alu_src
),
3160 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3164 emit_mir_instruction(ctx
, f2u8
);
3166 /* vmul.imov.quarter r0, r0, r0 */
3168 midgard_instruction imov_8
= {
3171 .src0
= SSA_UNUSED_1
,
3172 .src1
= SSA_FIXED_REGISTER(0),
3173 .dest
= SSA_FIXED_REGISTER(0),
3176 .op
= midgard_alu_op_imov
,
3177 .reg_mode
= midgard_reg_mode_quarter
,
3178 .dest_override
= midgard_dest_override_none
,
3180 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3181 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3185 /* Emit branch epilogue with the 8-bit move as the source */
3187 emit_mir_instruction(ctx
, imov_8
);
3188 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3190 emit_mir_instruction(ctx
, imov_8
);
3191 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3194 static midgard_block
*
3195 emit_block(compiler_context
*ctx
, nir_block
*block
)
3197 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3198 list_addtail(&this_block
->link
, &ctx
->blocks
);
3200 this_block
->is_scheduled
= false;
3203 ctx
->texture_index
[0] = -1;
3204 ctx
->texture_index
[1] = -1;
3206 /* Set up current block */
3207 list_inithead(&this_block
->instructions
);
3208 ctx
->current_block
= this_block
;
3210 nir_foreach_instr(instr
, block
) {
3211 emit_instr(ctx
, instr
);
3212 ++ctx
->instruction_count
;
3215 inline_alu_constants(ctx
);
3216 embedded_to_inline_constant(ctx
);
3218 /* Perform heavylifting for aliasing */
3219 actualise_ssa_to_alias(ctx
);
3221 midgard_emit_store(ctx
, this_block
);
3222 midgard_eliminate_orphan_moves(ctx
, this_block
);
3223 midgard_pair_load_store(ctx
, this_block
);
3225 /* Append fragment shader epilogue (value writeout) */
3226 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3227 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3229 emit_blend_epilogue(ctx
);
3231 emit_fragment_epilogue(ctx
);
3235 /* Fallthrough save */
3236 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3238 if (block
== nir_start_block(ctx
->func
->impl
))
3239 ctx
->initial_block
= this_block
;
3241 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3242 ctx
->final_block
= this_block
;
3244 /* Allow the next control flow to access us retroactively, for
3246 ctx
->current_block
= this_block
;
3248 /* Document the fallthrough chain */
3249 ctx
->previous_source_block
= this_block
;
3254 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3257 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3259 /* Conditional branches expect the condition in r31.w; emit a move for
3260 * that in the _previous_ block (which is the current block). */
3261 emit_condition(ctx
, &nif
->condition
, true);
3263 /* Speculatively emit the branch, but we can't fill it in until later */
3264 EMIT(branch
, true, true);
3265 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3267 /* Emit the two subblocks */
3268 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3270 /* Emit a jump from the end of the then block to the end of the else */
3271 EMIT(branch
, false, false);
3272 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3274 /* Emit second block, and check if it's empty */
3276 int else_idx
= ctx
->block_count
;
3277 int count_in
= ctx
->instruction_count
;
3278 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3279 int after_else_idx
= ctx
->block_count
;
3281 /* Now that we have the subblocks emitted, fix up the branches */
3286 if (ctx
->instruction_count
== count_in
) {
3287 /* The else block is empty, so don't emit an exit jump */
3288 mir_remove_instruction(then_exit
);
3289 then_branch
->branch
.target_block
= after_else_idx
;
3291 then_branch
->branch
.target_block
= else_idx
;
3292 then_exit
->branch
.target_block
= after_else_idx
;
3297 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3299 /* Remember where we are */
3300 midgard_block
*start_block
= ctx
->current_block
;
3302 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3303 * single current_loop variable, maybe we need a stack */
3305 int loop_idx
= ++ctx
->current_loop
;
3307 /* Get index from before the body so we can loop back later */
3308 int start_idx
= ctx
->block_count
;
3310 /* Emit the body itself */
3311 emit_cf_list(ctx
, &nloop
->body
);
3313 /* Branch back to loop back */
3314 struct midgard_instruction br_back
= v_branch(false, false);
3315 br_back
.branch
.target_block
= start_idx
;
3316 emit_mir_instruction(ctx
, br_back
);
3318 /* Find the index of the block about to follow us (note: we don't add
3319 * one; blocks are 0-indexed so we get a fencepost problem) */
3320 int break_block_idx
= ctx
->block_count
;
3322 /* Fix up the break statements we emitted to point to the right place,
3323 * now that we can allocate a block number for them */
3325 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3326 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3327 print_mir_block(block
);
3328 mir_foreach_instr_in_block(block
, ins
) {
3329 if (ins
->type
!= TAG_ALU_4
) continue;
3330 if (!ins
->compact_branch
) continue;
3331 if (ins
->prepacked_branch
) continue;
3333 /* We found a branch -- check the type to see if we need to do anything */
3334 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3336 /* It's a break! Check if it's our break */
3337 if (ins
->branch
.target_break
!= loop_idx
) continue;
3339 /* Okay, cool, we're breaking out of this loop.
3340 * Rewrite from a break to a goto */
3342 ins
->branch
.target_type
= TARGET_GOTO
;
3343 ins
->branch
.target_block
= break_block_idx
;
3348 static midgard_block
*
3349 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3351 midgard_block
*start_block
= NULL
;
3353 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3354 switch (node
->type
) {
3355 case nir_cf_node_block
: {
3356 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3359 start_block
= block
;
3364 case nir_cf_node_if
:
3365 emit_if(ctx
, nir_cf_node_as_if(node
));
3368 case nir_cf_node_loop
:
3369 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3372 case nir_cf_node_function
:
3381 /* Due to lookahead, we need to report the first tag executed in the command
3382 * stream and in branch targets. An initial block might be empty, so iterate
3383 * until we find one that 'works' */
3386 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3388 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3390 unsigned first_tag
= 0;
3393 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3395 if (initial_bundle
) {
3396 first_tag
= initial_bundle
->tag
;
3400 /* Initial block is empty, try the next block */
3401 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3402 } while(initial_block
!= NULL
);
3409 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3411 struct util_dynarray
*compiled
= &program
->compiled
;
3413 midgard_debug
= debug_get_option_midgard_debug();
3415 compiler_context ictx
= {
3417 .stage
= nir
->info
.stage
,
3419 .is_blend
= is_blend
,
3420 .blend_constant_offset
= -1,
3422 .alpha_ref
= program
->alpha_ref
3425 compiler_context
*ctx
= &ictx
;
3427 /* TODO: Decide this at runtime */
3428 ctx
->uniform_cutoff
= 8;
3430 switch (ctx
->stage
) {
3431 case MESA_SHADER_VERTEX
:
3432 ctx
->special_uniforms
= 1;
3436 ctx
->special_uniforms
= 0;
3440 /* Append epilogue uniforms if necessary. The cmdstream depends on
3441 * these being at the -end-; see assign_var_locations. */
3443 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3444 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3447 /* Assign var locations early, so the epilogue can use them if necessary */
3449 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3450 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3451 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3453 /* Initialize at a global (not block) level hash tables */
3455 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3456 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3457 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3458 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3459 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3460 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3462 /* Assign actual uniform location, skipping over samplers */
3464 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3466 nir_foreach_variable(var
, &nir
->uniforms
) {
3467 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3469 unsigned length
= glsl_get_aoa_size(var
->type
);
3472 length
= glsl_get_length(var
->type
);
3476 length
= glsl_get_matrix_columns(var
->type
);
3479 for (int col
= 0; col
< length
; ++col
) {
3480 int id
= ctx
->uniform_count
++;
3481 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3485 /* Record the varying mapping for the command stream's bookkeeping */
3487 struct exec_list
*varyings
=
3488 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3490 nir_foreach_variable(var
, varyings
) {
3491 unsigned loc
= var
->data
.driver_location
;
3492 program
->varyings
[loc
] = var
->data
.location
;
3495 /* Lower vars -- not I/O -- before epilogue */
3497 NIR_PASS_V(nir
, nir_lower_var_copies
);
3498 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3499 NIR_PASS_V(nir
, nir_split_var_copies
);
3500 NIR_PASS_V(nir
, nir_lower_var_copies
);
3501 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3502 NIR_PASS_V(nir
, nir_lower_var_copies
);
3503 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3504 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3506 /* Append vertex epilogue before optimisation, so the epilogue itself
3509 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3510 transform_position_writes(nir
);
3512 /* Optimisation passes */
3516 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3517 nir_print_shader(nir
, stdout
);
3520 /* Assign counts, now that we're sure (post-optimisation) */
3521 program
->uniform_count
= nir
->num_uniforms
;
3523 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3524 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3527 nir_foreach_function(func
, nir
) {
3531 list_inithead(&ctx
->blocks
);
3532 ctx
->block_count
= 0;
3535 emit_cf_list(ctx
, &func
->impl
->body
);
3536 emit_block(ctx
, func
->impl
->end_block
);
3538 break; /* TODO: Multi-function shaders */
3541 util_dynarray_init(compiled
, NULL
);
3544 schedule_program(ctx
);
3546 /* Now that all the bundles are scheduled and we can calculate block
3547 * sizes, emit actual branch instructions rather than placeholders */
3549 int br_block_idx
= 0;
3551 mir_foreach_block(ctx
, block
) {
3552 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3553 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3554 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3556 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3558 if (ins
->prepacked_branch
) continue;
3560 /* Parse some basic branch info */
3561 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3562 bool is_conditional
= ins
->branch
.conditional
;
3563 bool is_inverted
= ins
->branch
.invert_conditional
;
3564 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3566 /* Determine the block we're jumping to */
3567 int target_number
= ins
->branch
.target_block
;
3569 /* Report the destination tag. Discards don't need this */
3570 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3572 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3573 int quadword_offset
= 0;
3576 /* Jump to the end of the shader. We
3577 * need to include not only the
3578 * following blocks, but also the
3579 * contents of our current block (since
3580 * discard can come in the middle of
3583 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3585 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3586 quadword_offset
+= quadword_size(bun
->tag
);
3589 mir_foreach_block_from(ctx
, blk
, b
) {
3590 quadword_offset
+= b
->quadword_count
;
3593 } else if (target_number
> br_block_idx
) {
3596 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3597 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3600 quadword_offset
+= blk
->quadword_count
;
3603 /* Jump backwards */
3605 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3606 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3609 quadword_offset
-= blk
->quadword_count
;
3613 /* Unconditional extended branches (far jumps)
3614 * have issues, so we always use a conditional
3615 * branch, setting the condition to always for
3616 * unconditional. For compact unconditional
3617 * branches, cond isn't used so it doesn't
3618 * matter what we pick. */
3620 midgard_condition cond
=
3621 !is_conditional
? midgard_condition_always
:
3622 is_inverted
? midgard_condition_false
:
3623 midgard_condition_true
;
3625 midgard_jmp_writeout_op op
=
3626 is_discard
? midgard_jmp_writeout_op_discard
:
3627 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3628 midgard_jmp_writeout_op_branch_cond
;
3631 midgard_branch_extended branch
=
3632 midgard_create_branch_extended(
3637 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3638 } else if (is_conditional
|| is_discard
) {
3639 midgard_branch_cond branch
= {
3641 .dest_tag
= dest_tag
,
3642 .offset
= quadword_offset
,
3646 assert(branch
.offset
== quadword_offset
);
3648 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3650 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3652 midgard_branch_uncond branch
= {
3654 .dest_tag
= dest_tag
,
3655 .offset
= quadword_offset
,
3659 assert(branch
.offset
== quadword_offset
);
3661 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3669 /* Emit flat binary from the instruction arrays. Iterate each block in
3670 * sequence. Save instruction boundaries such that lookahead tags can
3671 * be assigned easily */
3673 /* Cache _all_ bundles in source order for lookahead across failed branches */
3675 int bundle_count
= 0;
3676 mir_foreach_block(ctx
, block
) {
3677 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3679 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3681 mir_foreach_block(ctx
, block
) {
3682 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3683 source_order_bundles
[bundle_idx
++] = bundle
;
3687 int current_bundle
= 0;
3689 mir_foreach_block(ctx
, block
) {
3690 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3693 if (current_bundle
+ 1 < bundle_count
) {
3694 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3696 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3703 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3707 /* TODO: Free deeper */
3708 //util_dynarray_fini(&block->instructions);
3711 free(source_order_bundles
);
3713 /* Report the very first tag executed */
3714 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3716 /* Deal with off-by-one related to the fencepost problem */
3717 program
->work_register_count
= ctx
->work_registers
+ 1;
3719 program
->can_discard
= ctx
->can_discard
;
3720 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3722 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3724 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3725 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);