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nir: Drop imov/fmov in favor of one mov instruction
[mesa.git] / src / gallium / drivers / panfrost / midgard / midgard_compile.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <sys/mman.h>
27 #include <fcntl.h>
28 #include <stdint.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <err.h>
32
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
43
44 #include "midgard.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
48 #include "helpers.h"
49 #include "compiler.h"
50
51 #include "disassemble.h"
52
53 static const struct debug_named_value debug_options[] = {
54 {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"},
56 DEBUG_NAMED_VALUE_END
57 };
58
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0)
60
61 int midgard_debug = 0;
62
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67
68 static bool
69 midgard_is_branch_unit(unsigned unit)
70 {
71 return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
72 }
73
74 static void
75 midgard_block_add_successor(midgard_block *block, midgard_block *successor)
76 {
77 block->successors[block->nr_successors++] = successor;
78 assert(block->nr_successors <= ARRAY_SIZE(block->successors));
79 }
80
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
83
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
91 .ssa_args = { \
92 .rname = ssa, \
93 .uname = -1, \
94 .src1 = -1 \
95 }, \
96 .load_store = { \
97 .op = midgard_op_##name, \
98 .mask = 0xF, \
99 .swizzle = SWIZZLE_XYZW, \
100 .address = address \
101 } \
102 }; \
103 \
104 return i; \
105 }
106
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
109
110 const midgard_vector_alu_src blank_alu_src = {
111 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
112 };
113
114 const midgard_vector_alu_src blank_alu_src_xxxx = {
115 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
116 };
117
118 const midgard_scalar_alu_src blank_scalar_alu_src = {
119 .full = true
120 };
121
122 /* Used for encoding the unused source of 1-op instructions */
123 const midgard_vector_alu_src zero_alu_src = { 0 };
124
125 /* Coerce structs to integer */
126
127 static unsigned
128 vector_alu_srco_unsigned(midgard_vector_alu_src src)
129 {
130 unsigned u;
131 memcpy(&u, &src, sizeof(src));
132 return u;
133 }
134
135 static midgard_vector_alu_src
136 vector_alu_from_unsigned(unsigned u)
137 {
138 midgard_vector_alu_src s;
139 memcpy(&s, &u, sizeof(s));
140 return s;
141 }
142
143 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
144 * the corresponding Midgard source */
145
146 static midgard_vector_alu_src
147 vector_alu_modifiers(nir_alu_src *src, bool is_int)
148 {
149 if (!src) return blank_alu_src;
150
151 midgard_vector_alu_src alu_src = {
152 .rep_low = 0,
153 .rep_high = 0,
154 .half = 0, /* TODO */
155 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
156 };
157
158 if (is_int) {
159 /* TODO: sign-extend/zero-extend */
160 alu_src.mod = midgard_int_normal;
161
162 /* These should have been lowered away */
163 assert(!(src->abs || src->negate));
164 } else {
165 alu_src.mod = (src->abs << 0) | (src->negate << 1);
166 }
167
168 return alu_src;
169 }
170
171 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
172
173 static midgard_instruction
174 v_fmov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
175 {
176 midgard_instruction ins = {
177 .type = TAG_ALU_4,
178 .ssa_args = {
179 .src0 = SSA_UNUSED_1,
180 .src1 = src,
181 .dest = dest,
182 },
183 .alu = {
184 .op = midgard_alu_op_fmov,
185 .reg_mode = midgard_reg_mode_32,
186 .dest_override = midgard_dest_override_none,
187 .mask = 0xFF,
188 .src1 = vector_alu_srco_unsigned(zero_alu_src),
189 .src2 = vector_alu_srco_unsigned(mod)
190 },
191 };
192
193 return ins;
194 }
195
196 /* load/store instructions have both 32-bit and 16-bit variants, depending on
197 * whether we are using vectors composed of highp or mediump. At the moment, we
198 * don't support half-floats -- this requires changes in other parts of the
199 * compiler -- therefore the 16-bit versions are commented out. */
200
201 //M_LOAD(ld_attr_16);
202 M_LOAD(ld_attr_32);
203 //M_LOAD(ld_vary_16);
204 M_LOAD(ld_vary_32);
205 //M_LOAD(ld_uniform_16);
206 M_LOAD(ld_uniform_32);
207 M_LOAD(ld_color_buffer_8);
208 //M_STORE(st_vary_16);
209 M_STORE(st_vary_32);
210 M_STORE(st_cubemap_coords);
211
212 static midgard_instruction
213 v_alu_br_compact_cond(midgard_jmp_writeout_op op, unsigned tag, signed offset, unsigned cond)
214 {
215 midgard_branch_cond branch = {
216 .op = op,
217 .dest_tag = tag,
218 .offset = offset,
219 .cond = cond
220 };
221
222 uint16_t compact;
223 memcpy(&compact, &branch, sizeof(branch));
224
225 midgard_instruction ins = {
226 .type = TAG_ALU_4,
227 .unit = ALU_ENAB_BR_COMPACT,
228 .prepacked_branch = true,
229 .compact_branch = true,
230 .br_compact = compact
231 };
232
233 if (op == midgard_jmp_writeout_op_writeout)
234 ins.writeout = true;
235
236 return ins;
237 }
238
239 static midgard_instruction
240 v_branch(bool conditional, bool invert)
241 {
242 midgard_instruction ins = {
243 .type = TAG_ALU_4,
244 .unit = ALU_ENAB_BRANCH,
245 .compact_branch = true,
246 .branch = {
247 .conditional = conditional,
248 .invert_conditional = invert
249 }
250 };
251
252 return ins;
253 }
254
255 static midgard_branch_extended
256 midgard_create_branch_extended( midgard_condition cond,
257 midgard_jmp_writeout_op op,
258 unsigned dest_tag,
259 signed quadword_offset)
260 {
261 /* For unclear reasons, the condition code is repeated 8 times */
262 uint16_t duplicated_cond =
263 (cond << 14) |
264 (cond << 12) |
265 (cond << 10) |
266 (cond << 8) |
267 (cond << 6) |
268 (cond << 4) |
269 (cond << 2) |
270 (cond << 0);
271
272 midgard_branch_extended branch = {
273 .op = op,
274 .dest_tag = dest_tag,
275 .offset = quadword_offset,
276 .cond = duplicated_cond
277 };
278
279 return branch;
280 }
281
282 static void
283 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
284 {
285 ins->has_constants = true;
286 memcpy(&ins->constants, constants, 16);
287 }
288
289 static int
290 glsl_type_size(const struct glsl_type *type, bool bindless)
291 {
292 return glsl_count_attribute_slots(type, false);
293 }
294
295 /* Lower fdot2 to a vector multiplication followed by channel addition */
296 static void
297 midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu)
298 {
299 if (alu->op != nir_op_fdot2)
300 return;
301
302 b->cursor = nir_before_instr(&alu->instr);
303
304 nir_ssa_def *src0 = nir_ssa_for_alu_src(b, alu, 0);
305 nir_ssa_def *src1 = nir_ssa_for_alu_src(b, alu, 1);
306
307 nir_ssa_def *product = nir_fmul(b, src0, src1);
308
309 nir_ssa_def *sum = nir_fadd(b,
310 nir_channel(b, product, 0),
311 nir_channel(b, product, 1));
312
313 /* Replace the fdot2 with this sum */
314 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum));
315 }
316
317 static int
318 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
319 {
320 switch (instr->intrinsic) {
321 case nir_intrinsic_load_viewport_scale:
322 return PAN_SYSVAL_VIEWPORT_SCALE;
323 case nir_intrinsic_load_viewport_offset:
324 return PAN_SYSVAL_VIEWPORT_OFFSET;
325 default:
326 return -1;
327 }
328 }
329
330 static void
331 midgard_nir_assign_sysval_body(compiler_context *ctx, nir_instr *instr)
332 {
333 int sysval = -1;
334
335 if (instr->type == nir_instr_type_intrinsic) {
336 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
337 sysval = midgard_nir_sysval_for_intrinsic(intr);
338 }
339
340 if (sysval < 0)
341 return;
342
343 /* We have a sysval load; check if it's already been assigned */
344
345 if (_mesa_hash_table_u64_search(ctx->sysval_to_id, sysval))
346 return;
347
348 /* It hasn't -- so assign it now! */
349
350 unsigned id = ctx->sysval_count++;
351 _mesa_hash_table_u64_insert(ctx->sysval_to_id, sysval, (void *) ((uintptr_t) id + 1));
352 ctx->sysvals[id] = sysval;
353 }
354
355 static void
356 midgard_nir_assign_sysvals(compiler_context *ctx, nir_shader *shader)
357 {
358 ctx->sysval_count = 0;
359
360 nir_foreach_function(function, shader) {
361 if (!function->impl) continue;
362
363 nir_foreach_block(block, function->impl) {
364 nir_foreach_instr_safe(instr, block) {
365 midgard_nir_assign_sysval_body(ctx, instr);
366 }
367 }
368 }
369 }
370
371 static bool
372 midgard_nir_lower_fdot2(nir_shader *shader)
373 {
374 bool progress = false;
375
376 nir_foreach_function(function, shader) {
377 if (!function->impl) continue;
378
379 nir_builder _b;
380 nir_builder *b = &_b;
381 nir_builder_init(b, function->impl);
382
383 nir_foreach_block(block, function->impl) {
384 nir_foreach_instr_safe(instr, block) {
385 if (instr->type != nir_instr_type_alu) continue;
386
387 nir_alu_instr *alu = nir_instr_as_alu(instr);
388 midgard_nir_lower_fdot2_body(b, alu);
389
390 progress |= true;
391 }
392 }
393
394 nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance);
395
396 }
397
398 return progress;
399 }
400
401 static void
402 optimise_nir(nir_shader *nir)
403 {
404 bool progress;
405 unsigned lower_flrp =
406 (nir->options->lower_flrp16 ? 16 : 0) |
407 (nir->options->lower_flrp32 ? 32 : 0) |
408 (nir->options->lower_flrp64 ? 64 : 0);
409
410 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
411 NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
412
413 nir_lower_tex_options lower_tex_options = {
414 .lower_rect = true
415 };
416
417 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
418
419 do {
420 progress = false;
421
422 NIR_PASS(progress, nir, nir_lower_var_copies);
423 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
424
425 NIR_PASS(progress, nir, nir_copy_prop);
426 NIR_PASS(progress, nir, nir_opt_dce);
427 NIR_PASS(progress, nir, nir_opt_dead_cf);
428 NIR_PASS(progress, nir, nir_opt_cse);
429 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
430 NIR_PASS(progress, nir, nir_opt_algebraic);
431 NIR_PASS(progress, nir, nir_opt_constant_folding);
432
433 if (lower_flrp != 0) {
434 bool lower_flrp_progress = false;
435 NIR_PASS(lower_flrp_progress,
436 nir,
437 nir_lower_flrp,
438 lower_flrp,
439 false /* always_precise */,
440 nir->options->lower_ffma);
441 if (lower_flrp_progress) {
442 NIR_PASS(progress, nir,
443 nir_opt_constant_folding);
444 progress = true;
445 }
446
447 /* Nothing should rematerialize any flrps, so we only
448 * need to do this lowering once.
449 */
450 lower_flrp = 0;
451 }
452
453 NIR_PASS(progress, nir, nir_opt_undef);
454 NIR_PASS(progress, nir, nir_opt_loop_unroll,
455 nir_var_shader_in |
456 nir_var_shader_out |
457 nir_var_function_temp);
458
459 /* TODO: Enable vectorize when merged upstream */
460 // NIR_PASS(progress, nir, nir_opt_vectorize);
461 } while (progress);
462
463 /* Must be run at the end to prevent creation of fsin/fcos ops */
464 NIR_PASS(progress, nir, midgard_nir_scale_trig);
465
466 do {
467 progress = false;
468
469 NIR_PASS(progress, nir, nir_opt_dce);
470 NIR_PASS(progress, nir, nir_opt_algebraic);
471 NIR_PASS(progress, nir, nir_opt_constant_folding);
472 NIR_PASS(progress, nir, nir_copy_prop);
473 } while (progress);
474
475 NIR_PASS(progress, nir, nir_opt_algebraic_late);
476
477 /* We implement booleans as 32-bit 0/~0 */
478 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
479
480 /* Now that booleans are lowered, we can run out late opts */
481 NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
482
483 /* Lower mods for float ops only. Integer ops don't support modifiers
484 * (saturate doesn't make sense on integers, neg/abs require dedicated
485 * instructions) */
486
487 NIR_PASS(progress, nir, nir_lower_to_source_mods, nir_lower_float_source_mods);
488 NIR_PASS(progress, nir, nir_copy_prop);
489 NIR_PASS(progress, nir, nir_opt_dce);
490
491 /* Take us out of SSA */
492 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
493 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
494
495 /* We are a vector architecture; write combine where possible */
496 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
497 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
498
499 NIR_PASS(progress, nir, nir_opt_dce);
500 }
501
502 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
503 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
504 * r0. See the comments in compiler_context */
505
506 static void
507 alias_ssa(compiler_context *ctx, int dest, int src)
508 {
509 _mesa_hash_table_u64_insert(ctx->ssa_to_alias, dest + 1, (void *) ((uintptr_t) src + 1));
510 _mesa_set_add(ctx->leftover_ssa_to_alias, (void *) (uintptr_t) (dest + 1));
511 }
512
513 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
514
515 static void
516 unalias_ssa(compiler_context *ctx, int dest)
517 {
518 _mesa_hash_table_u64_remove(ctx->ssa_to_alias, dest + 1);
519 /* TODO: Remove from leftover or no? */
520 }
521
522 static void
523 midgard_pin_output(compiler_context *ctx, int index, int reg)
524 {
525 _mesa_hash_table_u64_insert(ctx->ssa_to_register, index + 1, (void *) ((uintptr_t) reg + 1));
526 }
527
528 static bool
529 midgard_is_pinned(compiler_context *ctx, int index)
530 {
531 return _mesa_hash_table_u64_search(ctx->ssa_to_register, index + 1) != NULL;
532 }
533
534 /* Do not actually emit a load; instead, cache the constant for inlining */
535
536 static void
537 emit_load_const(compiler_context *ctx, nir_load_const_instr *instr)
538 {
539 nir_ssa_def def = instr->def;
540
541 float *v = rzalloc_array(NULL, float, 4);
542 nir_const_load_to_arr(v, instr, f32);
543 _mesa_hash_table_u64_insert(ctx->ssa_constants, def.index + 1, v);
544 }
545
546 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
547 * do the inverse) */
548
549 static unsigned
550 expand_writemask(unsigned mask)
551 {
552 unsigned o = 0;
553
554 for (int i = 0; i < 4; ++i)
555 if (mask & (1 << i))
556 o |= (3 << (2 * i));
557
558 return o;
559 }
560
561 static unsigned
562 squeeze_writemask(unsigned mask)
563 {
564 unsigned o = 0;
565
566 for (int i = 0; i < 4; ++i)
567 if (mask & (3 << (2 * i)))
568 o |= (1 << i);
569
570 return o;
571
572 }
573
574 /* Determines effective writemask, taking quirks and expansion into account */
575 static unsigned
576 effective_writemask(midgard_vector_alu *alu)
577 {
578 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
579 * sense) */
580
581 unsigned channel_count = GET_CHANNEL_COUNT(alu_opcode_props[alu->op].props);
582
583 /* If there is a fixed channel count, construct the appropriate mask */
584
585 if (channel_count)
586 return (1 << channel_count) - 1;
587
588 /* Otherwise, just squeeze the existing mask */
589 return squeeze_writemask(alu->mask);
590 }
591
592 static unsigned
593 nir_src_index(compiler_context *ctx, nir_src *src)
594 {
595 if (src->is_ssa)
596 return src->ssa->index;
597 else {
598 assert(!src->reg.indirect);
599 return ctx->func->impl->ssa_alloc + src->reg.reg->index;
600 }
601 }
602
603 static unsigned
604 nir_dest_index(compiler_context *ctx, nir_dest *dst)
605 {
606 if (dst->is_ssa)
607 return dst->ssa.index;
608 else {
609 assert(!dst->reg.indirect);
610 return ctx->func->impl->ssa_alloc + dst->reg.reg->index;
611 }
612 }
613
614 static unsigned
615 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
616 {
617 return nir_src_index(ctx, &src->src);
618 }
619
620 static bool
621 nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
622 {
623 unsigned comp = src->swizzle[0];
624
625 for (unsigned c = 1; c < nr_components; ++c) {
626 if (src->swizzle[c] != comp)
627 return true;
628 }
629
630 return false;
631 }
632
633 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
634 * output of a conditional test) into that register */
635
636 static void
637 emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned component)
638 {
639 int condition = nir_src_index(ctx, src);
640
641 /* Source to swizzle the desired component into w */
642
643 const midgard_vector_alu_src alu_src = {
644 .swizzle = SWIZZLE(component, component, component, component),
645 };
646
647 /* There is no boolean move instruction. Instead, we simulate a move by
648 * ANDing the condition with itself to get it into r31.w */
649
650 midgard_instruction ins = {
651 .type = TAG_ALU_4,
652
653 /* We need to set the conditional as close as possible */
654 .precede_break = true,
655 .unit = for_branch ? UNIT_SMUL : UNIT_SADD,
656
657 .ssa_args = {
658
659 .src0 = condition,
660 .src1 = condition,
661 .dest = SSA_FIXED_REGISTER(31),
662 },
663 .alu = {
664 .op = midgard_alu_op_iand,
665 .reg_mode = midgard_reg_mode_32,
666 .dest_override = midgard_dest_override_none,
667 .mask = (0x3 << 6), /* w */
668 .src1 = vector_alu_srco_unsigned(alu_src),
669 .src2 = vector_alu_srco_unsigned(alu_src)
670 },
671 };
672
673 emit_mir_instruction(ctx, ins);
674 }
675
676 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
677 * r31 instead */
678
679 static void
680 emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
681 {
682 int condition = nir_src_index(ctx, &src->src);
683
684 /* Source to swizzle the desired component into w */
685
686 const midgard_vector_alu_src alu_src = {
687 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle),
688 };
689
690 /* There is no boolean move instruction. Instead, we simulate a move by
691 * ANDing the condition with itself to get it into r31.w */
692
693 midgard_instruction ins = {
694 .type = TAG_ALU_4,
695 .precede_break = true,
696 .ssa_args = {
697 .src0 = condition,
698 .src1 = condition,
699 .dest = SSA_FIXED_REGISTER(31),
700 },
701 .alu = {
702 .op = midgard_alu_op_iand,
703 .reg_mode = midgard_reg_mode_32,
704 .dest_override = midgard_dest_override_none,
705 .mask = expand_writemask((1 << nr_comp) - 1),
706 .src1 = vector_alu_srco_unsigned(alu_src),
707 .src2 = vector_alu_srco_unsigned(alu_src)
708 },
709 };
710
711 emit_mir_instruction(ctx, ins);
712 }
713
714
715
716 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
717 * pinning to eliminate this move in all known cases */
718
719 static void
720 emit_indirect_offset(compiler_context *ctx, nir_src *src)
721 {
722 int offset = nir_src_index(ctx, src);
723
724 midgard_instruction ins = {
725 .type = TAG_ALU_4,
726 .ssa_args = {
727 .src0 = SSA_UNUSED_1,
728 .src1 = offset,
729 .dest = SSA_FIXED_REGISTER(REGISTER_OFFSET),
730 },
731 .alu = {
732 .op = midgard_alu_op_imov,
733 .reg_mode = midgard_reg_mode_32,
734 .dest_override = midgard_dest_override_none,
735 .mask = (0x3 << 6), /* w */
736 .src1 = vector_alu_srco_unsigned(zero_alu_src),
737 .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
738 },
739 };
740
741 emit_mir_instruction(ctx, ins);
742 }
743
744 #define ALU_CASE(nir, _op) \
745 case nir_op_##nir: \
746 op = midgard_alu_op_##_op; \
747 break;
748 static bool
749 nir_is_fzero_constant(nir_src src)
750 {
751 if (!nir_src_is_const(src))
752 return false;
753
754 for (unsigned c = 0; c < nir_src_num_components(src); ++c) {
755 if (nir_src_comp_as_float(src, c) != 0.0)
756 return false;
757 }
758
759 return true;
760 }
761
762 static void
763 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
764 {
765 bool is_ssa = instr->dest.dest.is_ssa;
766
767 unsigned dest = nir_dest_index(ctx, &instr->dest.dest);
768 unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components;
769 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
770
771 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
772 * supported. A few do not and are commented for now. Also, there are a
773 * number of NIR ops which Midgard does not support and need to be
774 * lowered, also TODO. This switch block emits the opcode and calling
775 * convention of the Midgard instruction; actual packing is done in
776 * emit_alu below */
777
778 unsigned op;
779
780 switch (instr->op) {
781 ALU_CASE(fadd, fadd);
782 ALU_CASE(fmul, fmul);
783 ALU_CASE(fmin, fmin);
784 ALU_CASE(fmax, fmax);
785 ALU_CASE(imin, imin);
786 ALU_CASE(imax, imax);
787 ALU_CASE(umin, umin);
788 ALU_CASE(umax, umax);
789 ALU_CASE(ffloor, ffloor);
790 ALU_CASE(fround_even, froundeven);
791 ALU_CASE(ftrunc, ftrunc);
792 ALU_CASE(fceil, fceil);
793 ALU_CASE(fdot3, fdot3);
794 ALU_CASE(fdot4, fdot4);
795 ALU_CASE(iadd, iadd);
796 ALU_CASE(isub, isub);
797 ALU_CASE(imul, imul);
798 ALU_CASE(iabs, iabs);
799 ALU_CASE(mov, imov);
800
801 ALU_CASE(feq32, feq);
802 ALU_CASE(fne32, fne);
803 ALU_CASE(flt32, flt);
804 ALU_CASE(ieq32, ieq);
805 ALU_CASE(ine32, ine);
806 ALU_CASE(ilt32, ilt);
807 ALU_CASE(ult32, ult);
808
809 /* We don't have a native b2f32 instruction. Instead, like many
810 * GPUs, we exploit booleans as 0/~0 for false/true, and
811 * correspondingly AND
812 * by 1.0 to do the type conversion. For the moment, prime us
813 * to emit:
814 *
815 * iand [whatever], #0
816 *
817 * At the end of emit_alu (as MIR), we'll fix-up the constant
818 */
819
820 ALU_CASE(b2f32, iand);
821 ALU_CASE(b2i32, iand);
822
823 /* Likewise, we don't have a dedicated f2b32 instruction, but
824 * we can do a "not equal to 0.0" test. */
825
826 ALU_CASE(f2b32, fne);
827 ALU_CASE(i2b32, ine);
828
829 ALU_CASE(frcp, frcp);
830 ALU_CASE(frsq, frsqrt);
831 ALU_CASE(fsqrt, fsqrt);
832 ALU_CASE(fexp2, fexp2);
833 ALU_CASE(flog2, flog2);
834
835 ALU_CASE(f2i32, f2i);
836 ALU_CASE(f2u32, f2u);
837 ALU_CASE(i2f32, i2f);
838 ALU_CASE(u2f32, u2f);
839
840 ALU_CASE(fsin, fsin);
841 ALU_CASE(fcos, fcos);
842
843 ALU_CASE(iand, iand);
844 ALU_CASE(ior, ior);
845 ALU_CASE(ixor, ixor);
846 ALU_CASE(inot, inand);
847 ALU_CASE(ishl, ishl);
848 ALU_CASE(ishr, iasr);
849 ALU_CASE(ushr, ilsr);
850
851 ALU_CASE(b32all_fequal2, fball_eq);
852 ALU_CASE(b32all_fequal3, fball_eq);
853 ALU_CASE(b32all_fequal4, fball_eq);
854
855 ALU_CASE(b32any_fnequal2, fbany_neq);
856 ALU_CASE(b32any_fnequal3, fbany_neq);
857 ALU_CASE(b32any_fnequal4, fbany_neq);
858
859 ALU_CASE(b32all_iequal2, iball_eq);
860 ALU_CASE(b32all_iequal3, iball_eq);
861 ALU_CASE(b32all_iequal4, iball_eq);
862
863 ALU_CASE(b32any_inequal2, ibany_neq);
864 ALU_CASE(b32any_inequal3, ibany_neq);
865 ALU_CASE(b32any_inequal4, ibany_neq);
866
867 /* For greater-or-equal, we lower to less-or-equal and flip the
868 * arguments */
869
870 case nir_op_fge:
871 case nir_op_fge32:
872 case nir_op_ige32:
873 case nir_op_uge32: {
874 op =
875 instr->op == nir_op_fge ? midgard_alu_op_fle :
876 instr->op == nir_op_fge32 ? midgard_alu_op_fle :
877 instr->op == nir_op_ige32 ? midgard_alu_op_ile :
878 instr->op == nir_op_uge32 ? midgard_alu_op_ule :
879 0;
880
881 /* Swap via temporary */
882 nir_alu_src temp = instr->src[1];
883 instr->src[1] = instr->src[0];
884 instr->src[0] = temp;
885
886 break;
887 }
888
889 case nir_op_b32csel: {
890 /* Midgard features both fcsel and icsel, depending on
891 * the type of the arguments/output. However, as long
892 * as we're careful we can _always_ use icsel and
893 * _never_ need fcsel, since the latter does additional
894 * floating-point-specific processing whereas the
895 * former just moves bits on the wire. It's not obvious
896 * why these are separate opcodes, save for the ability
897 * to do things like sat/pos/abs/neg for free */
898
899 bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
900 op = mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel;
901
902 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
903 nr_inputs = 2;
904
905 /* Emit the condition into r31 */
906
907 if (mixed)
908 emit_condition_mixed(ctx, &instr->src[0], nr_components);
909 else
910 emit_condition(ctx, &instr->src[0].src, false, instr->src[0].swizzle[0]);
911
912 /* The condition is the first argument; move the other
913 * arguments up one to be a binary instruction for
914 * Midgard */
915
916 memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src));
917 break;
918 }
919
920 default:
921 DBG("Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
922 assert(0);
923 return;
924 }
925
926 /* Midgard can perform certain modifiers on output of an ALU op */
927 midgard_outmod outmod =
928 midgard_is_integer_out_op(op) ? midgard_outmod_int :
929 instr->dest.saturate ? midgard_outmod_sat : midgard_outmod_none;
930
931 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
932
933 if (instr->op == nir_op_fmax) {
934 if (nir_is_fzero_constant(instr->src[0].src)) {
935 op = midgard_alu_op_fmov;
936 nr_inputs = 1;
937 outmod = midgard_outmod_pos;
938 instr->src[0] = instr->src[1];
939 } else if (nir_is_fzero_constant(instr->src[1].src)) {
940 op = midgard_alu_op_fmov;
941 nr_inputs = 1;
942 outmod = midgard_outmod_pos;
943 }
944 }
945
946 /* Fetch unit, quirks, etc information */
947 unsigned opcode_props = alu_opcode_props[op].props;
948 bool quirk_flipped_r24 = opcode_props & QUIRK_FLIPPED_R24;
949
950 /* src0 will always exist afaik, but src1 will not for 1-argument
951 * instructions. The latter can only be fetched if the instruction
952 * needs it, or else we may segfault. */
953
954 unsigned src0 = nir_alu_src_index(ctx, &instr->src[0]);
955 unsigned src1 = nr_inputs == 2 ? nir_alu_src_index(ctx, &instr->src[1]) : SSA_UNUSED_0;
956
957 /* Rather than use the instruction generation helpers, we do it
958 * ourselves here to avoid the mess */
959
960 midgard_instruction ins = {
961 .type = TAG_ALU_4,
962 .ssa_args = {
963 .src0 = quirk_flipped_r24 ? SSA_UNUSED_1 : src0,
964 .src1 = quirk_flipped_r24 ? src0 : src1,
965 .dest = dest,
966 }
967 };
968
969 nir_alu_src *nirmods[2] = { NULL };
970
971 if (nr_inputs == 2) {
972 nirmods[0] = &instr->src[0];
973 nirmods[1] = &instr->src[1];
974 } else if (nr_inputs == 1) {
975 nirmods[quirk_flipped_r24] = &instr->src[0];
976 } else {
977 assert(0);
978 }
979
980 bool is_int = midgard_is_integer_op(op);
981
982 midgard_vector_alu alu = {
983 .op = op,
984 .reg_mode = midgard_reg_mode_32,
985 .dest_override = midgard_dest_override_none,
986 .outmod = outmod,
987
988 /* Writemask only valid for non-SSA NIR */
989 .mask = expand_writemask((1 << nr_components) - 1),
990
991 .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int)),
992 .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int)),
993 };
994
995 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
996
997 if (!is_ssa)
998 alu.mask &= expand_writemask(instr->dest.write_mask);
999
1000 ins.alu = alu;
1001
1002 /* Late fixup for emulated instructions */
1003
1004 if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
1005 /* Presently, our second argument is an inline #0 constant.
1006 * Switch over to an embedded 1.0 constant (that can't fit
1007 * inline, since we're 32-bit, not 16-bit like the inline
1008 * constants) */
1009
1010 ins.ssa_args.inline_constant = false;
1011 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1012 ins.has_constants = true;
1013
1014 if (instr->op == nir_op_b2f32) {
1015 ins.constants[0] = 1.0f;
1016 } else {
1017 /* Type pun it into place */
1018 uint32_t one = 0x1;
1019 memcpy(&ins.constants[0], &one, sizeof(uint32_t));
1020 }
1021
1022 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
1023 } else if (instr->op == nir_op_f2b32 || instr->op == nir_op_i2b32) {
1024 ins.ssa_args.inline_constant = false;
1025 ins.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1026 ins.has_constants = true;
1027 ins.constants[0] = 0.0f;
1028 ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx);
1029 } else if (instr->op == nir_op_inot) {
1030 /* ~b = ~(b & b), so duplicate the source */
1031 ins.ssa_args.src1 = ins.ssa_args.src0;
1032 ins.alu.src2 = ins.alu.src1;
1033 }
1034
1035 if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
1036 /* To avoid duplicating the lookup tables (probably), true LUT
1037 * instructions can only operate as if they were scalars. Lower
1038 * them here by changing the component. */
1039
1040 uint8_t original_swizzle[4];
1041 memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
1042
1043 for (int i = 0; i < nr_components; ++i) {
1044 ins.alu.mask = (0x3) << (2 * i); /* Mask the associated component */
1045
1046 for (int j = 0; j < 4; ++j)
1047 nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */
1048
1049 ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int));
1050 emit_mir_instruction(ctx, ins);
1051 }
1052 } else {
1053 emit_mir_instruction(ctx, ins);
1054 }
1055 }
1056
1057 #undef ALU_CASE
1058
1059 static void
1060 emit_uniform_read(compiler_context *ctx, unsigned dest, unsigned offset, nir_src *indirect_offset)
1061 {
1062 /* TODO: half-floats */
1063
1064 if (!indirect_offset && offset < ctx->uniform_cutoff) {
1065 /* Fast path: For the first 16 uniforms, direct accesses are
1066 * 0-cycle, since they're just a register fetch in the usual
1067 * case. So, we alias the registers while we're still in
1068 * SSA-space */
1069
1070 int reg_slot = 23 - offset;
1071 alias_ssa(ctx, dest, SSA_FIXED_REGISTER(reg_slot));
1072 } else {
1073 /* Otherwise, read from the 'special' UBO to access
1074 * higher-indexed uniforms, at a performance cost. More
1075 * generally, we're emitting a UBO read instruction. */
1076
1077 midgard_instruction ins = m_ld_uniform_32(dest, offset);
1078
1079 /* TODO: Don't split */
1080 ins.load_store.varying_parameters = (offset & 7) << 7;
1081 ins.load_store.address = offset >> 3;
1082
1083 if (indirect_offset) {
1084 emit_indirect_offset(ctx, indirect_offset);
1085 ins.load_store.unknown = 0x8700; /* xxx: what is this? */
1086 } else {
1087 ins.load_store.unknown = 0x1E00; /* xxx: what is this? */
1088 }
1089
1090 emit_mir_instruction(ctx, ins);
1091 }
1092 }
1093
1094 static void
1095 emit_sysval_read(compiler_context *ctx, nir_intrinsic_instr *instr)
1096 {
1097 /* First, pull out the destination */
1098 unsigned dest = nir_dest_index(ctx, &instr->dest);
1099
1100 /* Now, figure out which uniform this is */
1101 int sysval = midgard_nir_sysval_for_intrinsic(instr);
1102 void *val = _mesa_hash_table_u64_search(ctx->sysval_to_id, sysval);
1103
1104 /* Sysvals are prefix uniforms */
1105 unsigned uniform = ((uintptr_t) val) - 1;
1106
1107 /* Emit the read itself -- this is never indirect */
1108 emit_uniform_read(ctx, dest, uniform, NULL);
1109 }
1110
1111 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1112 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1113 * generations have faster vectorized reads. This operation is for blend
1114 * shaders in particular; reading the tilebuffer from the fragment shader
1115 * remains an open problem. */
1116
1117 static void
1118 emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
1119 {
1120 midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
1121 ins.load_store.swizzle = 0; /* xxxx */
1122
1123 /* Read each component sequentially */
1124
1125 for (unsigned c = 0; c < 4; ++c) {
1126 ins.load_store.mask = (1 << c);
1127 ins.load_store.unknown = c;
1128 emit_mir_instruction(ctx, ins);
1129 }
1130
1131 /* vadd.u2f hr2, zext(hr2), #0 */
1132
1133 midgard_vector_alu_src alu_src = blank_alu_src;
1134 alu_src.mod = midgard_int_zero_extend;
1135 alu_src.half = true;
1136
1137 midgard_instruction u2f = {
1138 .type = TAG_ALU_4,
1139 .ssa_args = {
1140 .src0 = reg,
1141 .src1 = SSA_UNUSED_0,
1142 .dest = reg,
1143 .inline_constant = true
1144 },
1145 .alu = {
1146 .op = midgard_alu_op_u2f,
1147 .reg_mode = midgard_reg_mode_16,
1148 .dest_override = midgard_dest_override_none,
1149 .mask = 0xF,
1150 .src1 = vector_alu_srco_unsigned(alu_src),
1151 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1152 }
1153 };
1154
1155 emit_mir_instruction(ctx, u2f);
1156
1157 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1158
1159 alu_src.mod = 0;
1160
1161 midgard_instruction fmul = {
1162 .type = TAG_ALU_4,
1163 .inline_constant = _mesa_float_to_half(1.0 / 255.0),
1164 .ssa_args = {
1165 .src0 = reg,
1166 .dest = reg,
1167 .src1 = SSA_UNUSED_0,
1168 .inline_constant = true
1169 },
1170 .alu = {
1171 .op = midgard_alu_op_fmul,
1172 .reg_mode = midgard_reg_mode_32,
1173 .dest_override = midgard_dest_override_none,
1174 .outmod = midgard_outmod_sat,
1175 .mask = 0xFF,
1176 .src1 = vector_alu_srco_unsigned(alu_src),
1177 .src2 = vector_alu_srco_unsigned(blank_alu_src),
1178 }
1179 };
1180
1181 emit_mir_instruction(ctx, fmul);
1182 }
1183
1184 static void
1185 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
1186 {
1187 unsigned offset, reg;
1188
1189 switch (instr->intrinsic) {
1190 case nir_intrinsic_discard_if:
1191 emit_condition(ctx, &instr->src[0], true, COMPONENT_X);
1192
1193 /* fallthrough */
1194
1195 case nir_intrinsic_discard: {
1196 bool conditional = instr->intrinsic == nir_intrinsic_discard_if;
1197 struct midgard_instruction discard = v_branch(conditional, false);
1198 discard.branch.target_type = TARGET_DISCARD;
1199 emit_mir_instruction(ctx, discard);
1200
1201 ctx->can_discard = true;
1202 break;
1203 }
1204
1205 case nir_intrinsic_load_uniform:
1206 case nir_intrinsic_load_input:
1207 offset = nir_intrinsic_base(instr);
1208
1209 bool direct = nir_src_is_const(instr->src[0]);
1210
1211 if (direct) {
1212 offset += nir_src_as_uint(instr->src[0]);
1213 }
1214
1215 reg = nir_dest_index(ctx, &instr->dest);
1216
1217 if (instr->intrinsic == nir_intrinsic_load_uniform && !ctx->is_blend) {
1218 emit_uniform_read(ctx, reg, ctx->sysval_count + offset, !direct ? &instr->src[0] : NULL);
1219 } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) {
1220 /* XXX: Half-floats? */
1221 /* TODO: swizzle, mask */
1222
1223 midgard_instruction ins = m_ld_vary_32(reg, offset);
1224
1225 midgard_varying_parameter p = {
1226 .is_varying = 1,
1227 .interpolation = midgard_interp_default,
1228 .flat = /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1229 };
1230
1231 unsigned u;
1232 memcpy(&u, &p, sizeof(p));
1233 ins.load_store.varying_parameters = u;
1234
1235 if (direct) {
1236 /* We have the offset totally ready */
1237 ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */
1238 } else {
1239 /* We have it partially ready, but we need to
1240 * add in the dynamic index, moved to r27.w */
1241 emit_indirect_offset(ctx, &instr->src[0]);
1242 ins.load_store.unknown = 0x79e; /* xxx: what is this? */
1243 }
1244
1245 emit_mir_instruction(ctx, ins);
1246 } else if (ctx->is_blend) {
1247 /* For blend shaders, load the input color, which is
1248 * preloaded to r0 */
1249
1250 midgard_pin_output(ctx, reg, 0);
1251 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1252 midgard_instruction ins = m_ld_attr_32(reg, offset);
1253 ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
1254 ins.load_store.mask = (1 << instr->num_components) - 1;
1255 emit_mir_instruction(ctx, ins);
1256 } else {
1257 DBG("Unknown load\n");
1258 assert(0);
1259 }
1260
1261 break;
1262
1263 case nir_intrinsic_load_output:
1264 assert(nir_src_is_const(instr->src[0]));
1265 reg = nir_dest_index(ctx, &instr->dest);
1266
1267 if (ctx->is_blend) {
1268 /* TODO: MRT */
1269 emit_fb_read_blend_scalar(ctx, reg);
1270 } else {
1271 DBG("Unknown output load\n");
1272 assert(0);
1273 }
1274
1275 break;
1276
1277 case nir_intrinsic_load_blend_const_color_rgba: {
1278 assert(ctx->is_blend);
1279 reg = nir_dest_index(ctx, &instr->dest);
1280
1281 /* Blend constants are embedded directly in the shader and
1282 * patched in, so we use some magic routing */
1283
1284 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, reg);
1285 ins.has_constants = true;
1286 ins.has_blend_constant = true;
1287 emit_mir_instruction(ctx, ins);
1288 break;
1289 }
1290
1291 case nir_intrinsic_store_output:
1292 assert(nir_src_is_const(instr->src[1]) && "no indirect outputs");
1293
1294 offset = nir_intrinsic_base(instr) + nir_src_as_uint(instr->src[1]);
1295
1296 reg = nir_src_index(ctx, &instr->src[0]);
1297
1298 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1299 /* gl_FragColor is not emitted with load/store
1300 * instructions. Instead, it gets plonked into
1301 * r0 at the end of the shader and we do the
1302 * framebuffer writeout dance. TODO: Defer
1303 * writes */
1304
1305 midgard_instruction move = v_fmov(reg, blank_alu_src, SSA_FIXED_REGISTER(0));
1306 emit_mir_instruction(ctx, move);
1307
1308 //midgard_pin_output(ctx, reg, 0);
1309
1310 /* Save the index we're writing to for later reference
1311 * in the epilogue */
1312
1313 ctx->fragment_output = reg;
1314 } else if (ctx->stage == MESA_SHADER_VERTEX) {
1315 /* Varyings are written into one of two special
1316 * varying register, r26 or r27. The register itself is selected as the register
1317 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1318 *
1319 * Normally emitting fmov's is frowned upon,
1320 * but due to unique constraints of
1321 * REGISTER_VARYING, fmov emission + a
1322 * dedicated cleanup pass is the only way to
1323 * guarantee correctness when considering some
1324 * (common) edge cases XXX: FIXME */
1325
1326 /* If this varying corresponds to a constant (why?!),
1327 * emit that now since it won't get picked up by
1328 * hoisting (since there is no corresponding move
1329 * emitted otherwise) */
1330
1331 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, reg + 1);
1332
1333 if (constant_value) {
1334 /* Special case: emit the varying write
1335 * directly to r26 (looks funny in asm but it's
1336 * fine) and emit the store _now_. Possibly
1337 * slightly slower, but this is a really stupid
1338 * special case anyway (why on earth would you
1339 * have a constant varying? Your own fault for
1340 * slightly worse perf :P) */
1341
1342 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(26));
1343 attach_constants(ctx, &ins, constant_value, reg + 1);
1344 emit_mir_instruction(ctx, ins);
1345
1346 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(0), offset);
1347 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
1348 emit_mir_instruction(ctx, st);
1349 } else {
1350 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1351
1352 _mesa_hash_table_u64_insert(ctx->ssa_varyings, reg + 1, (void *) ((uintptr_t) (offset + 1)));
1353 }
1354 } else {
1355 DBG("Unknown store\n");
1356 assert(0);
1357 }
1358
1359 break;
1360
1361 case nir_intrinsic_load_alpha_ref_float:
1362 assert(instr->dest.is_ssa);
1363
1364 float ref_value = ctx->alpha_ref;
1365
1366 float *v = ralloc_array(NULL, float, 4);
1367 memcpy(v, &ref_value, sizeof(float));
1368 _mesa_hash_table_u64_insert(ctx->ssa_constants, instr->dest.ssa.index + 1, v);
1369 break;
1370
1371 case nir_intrinsic_load_viewport_scale:
1372 case nir_intrinsic_load_viewport_offset:
1373 emit_sysval_read(ctx, instr);
1374 break;
1375
1376 default:
1377 printf ("Unhandled intrinsic\n");
1378 assert(0);
1379 break;
1380 }
1381 }
1382
1383 static unsigned
1384 midgard_tex_format(enum glsl_sampler_dim dim)
1385 {
1386 switch (dim) {
1387 case GLSL_SAMPLER_DIM_2D:
1388 case GLSL_SAMPLER_DIM_EXTERNAL:
1389 return TEXTURE_2D;
1390
1391 case GLSL_SAMPLER_DIM_3D:
1392 return TEXTURE_3D;
1393
1394 case GLSL_SAMPLER_DIM_CUBE:
1395 return TEXTURE_CUBE;
1396
1397 default:
1398 DBG("Unknown sampler dim type\n");
1399 assert(0);
1400 return 0;
1401 }
1402 }
1403
1404 static void
1405 emit_tex(compiler_context *ctx, nir_tex_instr *instr)
1406 {
1407 /* TODO */
1408 //assert (!instr->sampler);
1409 //assert (!instr->texture_array_size);
1410 assert (instr->op == nir_texop_tex);
1411
1412 /* Allocate registers via a round robin scheme to alternate between the two registers */
1413 int reg = ctx->texture_op_count & 1;
1414 int in_reg = reg, out_reg = reg;
1415
1416 /* Make room for the reg */
1417
1418 if (ctx->texture_index[reg] > -1)
1419 unalias_ssa(ctx, ctx->texture_index[reg]);
1420
1421 int texture_index = instr->texture_index;
1422 int sampler_index = texture_index;
1423
1424 for (unsigned i = 0; i < instr->num_srcs; ++i) {
1425 switch (instr->src[i].src_type) {
1426 case nir_tex_src_coord: {
1427 int index = nir_src_index(ctx, &instr->src[i].src);
1428
1429 midgard_vector_alu_src alu_src = blank_alu_src;
1430
1431 int reg = SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + in_reg);
1432
1433 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
1434 /* For cubemaps, we need to load coords into
1435 * special r27, and then use a special ld/st op
1436 * to copy into the texture register */
1437
1438 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X);
1439
1440 midgard_instruction move = v_fmov(index, alu_src, SSA_FIXED_REGISTER(27));
1441 emit_mir_instruction(ctx, move);
1442
1443 midgard_instruction st = m_st_cubemap_coords(reg, 0);
1444 st.load_store.unknown = 0x24; /* XXX: What is this? */
1445 st.load_store.mask = 0x3; /* xy? */
1446 st.load_store.swizzle = alu_src.swizzle;
1447 emit_mir_instruction(ctx, st);
1448
1449 } else {
1450 alu_src.swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X);
1451
1452 midgard_instruction ins = v_fmov(index, alu_src, reg);
1453 emit_mir_instruction(ctx, ins);
1454 }
1455
1456 break;
1457 }
1458
1459 default: {
1460 DBG("Unknown source type\n");
1461 //assert(0);
1462 break;
1463 }
1464 }
1465 }
1466
1467 /* No helper to build texture words -- we do it all here */
1468 midgard_instruction ins = {
1469 .type = TAG_TEXTURE_4,
1470 .texture = {
1471 .op = TEXTURE_OP_NORMAL,
1472 .format = midgard_tex_format(instr->sampler_dim),
1473 .texture_handle = texture_index,
1474 .sampler_handle = sampler_index,
1475
1476 /* TODO: Don't force xyzw */
1477 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
1478 .mask = 0xF,
1479
1480 /* TODO: half */
1481 //.in_reg_full = 1,
1482 .out_full = 1,
1483
1484 .filter = 1,
1485
1486 /* Always 1 */
1487 .unknown7 = 1,
1488
1489 /* Assume we can continue; hint it out later */
1490 .cont = 1,
1491 }
1492 };
1493
1494 /* Set registers to read and write from the same place */
1495 ins.texture.in_reg_select = in_reg;
1496 ins.texture.out_reg_select = out_reg;
1497
1498 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1499 if (instr->sampler_dim == GLSL_SAMPLER_DIM_3D) {
1500 ins.texture.in_reg_swizzle_right = COMPONENT_X;
1501 ins.texture.in_reg_swizzle_left = COMPONENT_Y;
1502 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1503 } else {
1504 ins.texture.in_reg_swizzle_left = COMPONENT_X;
1505 ins.texture.in_reg_swizzle_right = COMPONENT_Y;
1506 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1507 }
1508
1509 emit_mir_instruction(ctx, ins);
1510
1511 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1512
1513 int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest);
1514 alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg));
1515 ctx->texture_index[reg] = o_index;
1516
1517 midgard_instruction ins2 = v_fmov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index);
1518 emit_mir_instruction(ctx, ins2);
1519
1520 /* Used for .cont and .last hinting */
1521 ctx->texture_op_count++;
1522 }
1523
1524 static void
1525 emit_jump(compiler_context *ctx, nir_jump_instr *instr)
1526 {
1527 switch (instr->type) {
1528 case nir_jump_break: {
1529 /* Emit a branch out of the loop */
1530 struct midgard_instruction br = v_branch(false, false);
1531 br.branch.target_type = TARGET_BREAK;
1532 br.branch.target_break = ctx->current_loop_depth;
1533 emit_mir_instruction(ctx, br);
1534
1535 DBG("break..\n");
1536 break;
1537 }
1538
1539 default:
1540 DBG("Unknown jump type %d\n", instr->type);
1541 break;
1542 }
1543 }
1544
1545 static void
1546 emit_instr(compiler_context *ctx, struct nir_instr *instr)
1547 {
1548 switch (instr->type) {
1549 case nir_instr_type_load_const:
1550 emit_load_const(ctx, nir_instr_as_load_const(instr));
1551 break;
1552
1553 case nir_instr_type_intrinsic:
1554 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
1555 break;
1556
1557 case nir_instr_type_alu:
1558 emit_alu(ctx, nir_instr_as_alu(instr));
1559 break;
1560
1561 case nir_instr_type_tex:
1562 emit_tex(ctx, nir_instr_as_tex(instr));
1563 break;
1564
1565 case nir_instr_type_jump:
1566 emit_jump(ctx, nir_instr_as_jump(instr));
1567 break;
1568
1569 case nir_instr_type_ssa_undef:
1570 /* Spurious */
1571 break;
1572
1573 default:
1574 DBG("Unhandled instruction type\n");
1575 break;
1576 }
1577 }
1578
1579 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1580 * use scalar ALU instructions, for functional or performance reasons. To do
1581 * this, we just demote vector ALU payloads to scalar. */
1582
1583 static int
1584 component_from_mask(unsigned mask)
1585 {
1586 for (int c = 0; c < 4; ++c) {
1587 if (mask & (3 << (2 * c)))
1588 return c;
1589 }
1590
1591 assert(0);
1592 return 0;
1593 }
1594
1595 static bool
1596 is_single_component_mask(unsigned mask)
1597 {
1598 int components = 0;
1599
1600 for (int c = 0; c < 4; ++c)
1601 if (mask & (3 << (2 * c)))
1602 components++;
1603
1604 return components == 1;
1605 }
1606
1607 /* Create a mask of accessed components from a swizzle to figure out vector
1608 * dependencies */
1609
1610 static unsigned
1611 swizzle_to_access_mask(unsigned swizzle)
1612 {
1613 unsigned component_mask = 0;
1614
1615 for (int i = 0; i < 4; ++i) {
1616 unsigned c = (swizzle >> (2 * i)) & 3;
1617 component_mask |= (1 << c);
1618 }
1619
1620 return component_mask;
1621 }
1622
1623 static unsigned
1624 vector_to_scalar_source(unsigned u, bool is_int)
1625 {
1626 midgard_vector_alu_src v;
1627 memcpy(&v, &u, sizeof(v));
1628
1629 /* TODO: Integers */
1630
1631 midgard_scalar_alu_src s = {
1632 .full = !v.half,
1633 .component = (v.swizzle & 3) << 1
1634 };
1635
1636 if (is_int) {
1637 /* TODO */
1638 } else {
1639 s.abs = v.mod & MIDGARD_FLOAT_MOD_ABS;
1640 s.negate = v.mod & MIDGARD_FLOAT_MOD_NEG;
1641 }
1642
1643 unsigned o;
1644 memcpy(&o, &s, sizeof(s));
1645
1646 return o & ((1 << 6) - 1);
1647 }
1648
1649 static midgard_scalar_alu
1650 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
1651 {
1652 bool is_int = midgard_is_integer_op(v.op);
1653
1654 /* The output component is from the mask */
1655 midgard_scalar_alu s = {
1656 .op = v.op,
1657 .src1 = vector_to_scalar_source(v.src1, is_int),
1658 .src2 = vector_to_scalar_source(v.src2, is_int),
1659 .unknown = 0,
1660 .outmod = v.outmod,
1661 .output_full = 1, /* TODO: Half */
1662 .output_component = component_from_mask(v.mask) << 1,
1663 };
1664
1665 /* Inline constant is passed along rather than trying to extract it
1666 * from v */
1667
1668 if (ins->ssa_args.inline_constant) {
1669 uint16_t imm = 0;
1670 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
1671 imm |= (lower_11 >> 9) & 3;
1672 imm |= (lower_11 >> 6) & 4;
1673 imm |= (lower_11 >> 2) & 0x38;
1674 imm |= (lower_11 & 63) << 6;
1675
1676 s.src2 = imm;
1677 }
1678
1679 return s;
1680 }
1681
1682 /* Midgard prefetches instruction types, so during emission we need to
1683 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1684 * if this is the second to last and the last is an ALU, then it's also 1... */
1685
1686 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1687 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1688
1689 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
1690 bytes_emitted += sizeof(type)
1691
1692 static void
1693 emit_binary_vector_instruction(midgard_instruction *ains,
1694 uint16_t *register_words, int *register_words_count,
1695 uint64_t *body_words, size_t *body_size, int *body_words_count,
1696 size_t *bytes_emitted)
1697 {
1698 memcpy(&register_words[(*register_words_count)++], &ains->registers, sizeof(ains->registers));
1699 *bytes_emitted += sizeof(midgard_reg_info);
1700
1701 body_size[*body_words_count] = sizeof(midgard_vector_alu);
1702 memcpy(&body_words[(*body_words_count)++], &ains->alu, sizeof(ains->alu));
1703 *bytes_emitted += sizeof(midgard_vector_alu);
1704 }
1705
1706 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
1707 * mind that we are a vector architecture and we can write to different
1708 * components simultaneously */
1709
1710 static bool
1711 can_run_concurrent_ssa(midgard_instruction *first, midgard_instruction *second)
1712 {
1713 /* Each instruction reads some registers and writes to a register. See
1714 * where the first writes */
1715
1716 /* Figure out where exactly we wrote to */
1717 int source = first->ssa_args.dest;
1718 int source_mask = first->type == TAG_ALU_4 ? squeeze_writemask(first->alu.mask) : 0xF;
1719
1720 /* As long as the second doesn't read from the first, we're okay */
1721 if (second->ssa_args.src0 == source) {
1722 if (first->type == TAG_ALU_4) {
1723 /* Figure out which components we just read from */
1724
1725 int q = second->alu.src1;
1726 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
1727
1728 /* Check if there are components in common, and fail if so */
1729 if (swizzle_to_access_mask(m->swizzle) & source_mask)
1730 return false;
1731 } else
1732 return false;
1733
1734 }
1735
1736 if (second->ssa_args.src1 == source)
1737 return false;
1738
1739 /* Otherwise, it's safe in that regard. Another data hazard is both
1740 * writing to the same place, of course */
1741
1742 if (second->ssa_args.dest == source) {
1743 /* ...but only if the components overlap */
1744 int dest_mask = second->type == TAG_ALU_4 ? squeeze_writemask(second->alu.mask) : 0xF;
1745
1746 if (dest_mask & source_mask)
1747 return false;
1748 }
1749
1750 /* ...That's it */
1751 return true;
1752 }
1753
1754 static bool
1755 midgard_has_hazard(
1756 midgard_instruction **segment, unsigned segment_size,
1757 midgard_instruction *ains)
1758 {
1759 for (int s = 0; s < segment_size; ++s)
1760 if (!can_run_concurrent_ssa(segment[s], ains))
1761 return true;
1762
1763 return false;
1764
1765
1766 }
1767
1768 /* Schedules, but does not emit, a single basic block. After scheduling, the
1769 * final tag and size of the block are known, which are necessary for branching
1770 * */
1771
1772 static midgard_bundle
1773 schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction *ins, int *skip)
1774 {
1775 int instructions_emitted = 0, instructions_consumed = -1;
1776 midgard_bundle bundle = { 0 };
1777
1778 uint8_t tag = ins->type;
1779
1780 /* Default to the instruction's tag */
1781 bundle.tag = tag;
1782
1783 switch (ins->type) {
1784 case TAG_ALU_4: {
1785 uint32_t control = 0;
1786 size_t bytes_emitted = sizeof(control);
1787
1788 /* TODO: Constant combining */
1789 int index = 0, last_unit = 0;
1790
1791 /* Previous instructions, for the purpose of parallelism */
1792 midgard_instruction *segment[4] = {0};
1793 int segment_size = 0;
1794
1795 instructions_emitted = -1;
1796 midgard_instruction *pins = ins;
1797
1798 for (;;) {
1799 midgard_instruction *ains = pins;
1800
1801 /* Advance instruction pointer */
1802 if (index) {
1803 ains = mir_next_op(pins);
1804 pins = ains;
1805 }
1806
1807 /* Out-of-work condition */
1808 if ((struct list_head *) ains == &block->instructions)
1809 break;
1810
1811 /* Ensure that the chain can continue */
1812 if (ains->type != TAG_ALU_4) break;
1813
1814 /* If there's already something in the bundle and we
1815 * have weird scheduler constraints, break now */
1816 if (ains->precede_break && index) break;
1817
1818 /* According to the presentation "The ARM
1819 * Mali-T880 Mobile GPU" from HotChips 27,
1820 * there are two pipeline stages. Branching
1821 * position determined experimentally. Lines
1822 * are executed in parallel:
1823 *
1824 * [ VMUL ] [ SADD ]
1825 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
1826 *
1827 * Verify that there are no ordering dependencies here.
1828 *
1829 * TODO: Allow for parallelism!!!
1830 */
1831
1832 /* Pick a unit for it if it doesn't force a particular unit */
1833
1834 int unit = ains->unit;
1835
1836 if (!unit) {
1837 int op = ains->alu.op;
1838 int units = alu_opcode_props[op].props;
1839
1840 /* TODO: Promotion of scalars to vectors */
1841 int vector = ((!is_single_component_mask(ains->alu.mask)) || ((units & UNITS_SCALAR) == 0)) && (units & UNITS_ANY_VECTOR);
1842
1843 if (!vector)
1844 assert(units & UNITS_SCALAR);
1845
1846 if (vector) {
1847 if (last_unit >= UNIT_VADD) {
1848 if (units & UNIT_VLUT)
1849 unit = UNIT_VLUT;
1850 else
1851 break;
1852 } else {
1853 if ((units & UNIT_VMUL) && !(control & UNIT_VMUL))
1854 unit = UNIT_VMUL;
1855 else if ((units & UNIT_VADD) && !(control & UNIT_VADD))
1856 unit = UNIT_VADD;
1857 else if (units & UNIT_VLUT)
1858 unit = UNIT_VLUT;
1859 else
1860 break;
1861 }
1862 } else {
1863 if (last_unit >= UNIT_VADD) {
1864 if ((units & UNIT_SMUL) && !(control & UNIT_SMUL))
1865 unit = UNIT_SMUL;
1866 else if (units & UNIT_VLUT)
1867 unit = UNIT_VLUT;
1868 else
1869 break;
1870 } else {
1871 if ((units & UNIT_SADD) && !(control & UNIT_SADD) && !midgard_has_hazard(segment, segment_size, ains))
1872 unit = UNIT_SADD;
1873 else if (units & UNIT_SMUL)
1874 unit = ((units & UNIT_VMUL) && !(control & UNIT_VMUL)) ? UNIT_VMUL : UNIT_SMUL;
1875 else if ((units & UNIT_VADD) && !(control & UNIT_VADD))
1876 unit = UNIT_VADD;
1877 else
1878 break;
1879 }
1880 }
1881
1882 assert(unit & units);
1883 }
1884
1885 /* Late unit check, this time for encoding (not parallelism) */
1886 if (unit <= last_unit) break;
1887
1888 /* Clear the segment */
1889 if (last_unit < UNIT_VADD && unit >= UNIT_VADD)
1890 segment_size = 0;
1891
1892 if (midgard_has_hazard(segment, segment_size, ains))
1893 break;
1894
1895 /* We're good to go -- emit the instruction */
1896 ains->unit = unit;
1897
1898 segment[segment_size++] = ains;
1899
1900 /* Only one set of embedded constants per
1901 * bundle possible; if we have more, we must
1902 * break the chain early, unfortunately */
1903
1904 if (ains->has_constants) {
1905 if (bundle.has_embedded_constants) {
1906 /* The blend constant needs to be
1907 * alone, since it conflicts with
1908 * everything by definition*/
1909
1910 if (ains->has_blend_constant || bundle.has_blend_constant)
1911 break;
1912
1913 /* ...but if there are already
1914 * constants but these are the
1915 * *same* constants, we let it
1916 * through */
1917
1918 if (memcmp(bundle.constants, ains->constants, sizeof(bundle.constants)))
1919 break;
1920 } else {
1921 bundle.has_embedded_constants = true;
1922 memcpy(bundle.constants, ains->constants, sizeof(bundle.constants));
1923
1924 /* If this is a blend shader special constant, track it for patching */
1925 bundle.has_blend_constant |= ains->has_blend_constant;
1926 }
1927 }
1928
1929 if (ains->unit & UNITS_ANY_VECTOR) {
1930 emit_binary_vector_instruction(ains, bundle.register_words,
1931 &bundle.register_words_count, bundle.body_words,
1932 bundle.body_size, &bundle.body_words_count, &bytes_emitted);
1933 } else if (ains->compact_branch) {
1934 /* All of r0 has to be written out
1935 * along with the branch writeout.
1936 * (slow!) */
1937
1938 if (ains->writeout) {
1939 if (index == 0) {
1940 midgard_instruction ins = v_fmov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
1941 ins.unit = UNIT_VMUL;
1942
1943 control |= ins.unit;
1944
1945 emit_binary_vector_instruction(&ins, bundle.register_words,
1946 &bundle.register_words_count, bundle.body_words,
1947 bundle.body_size, &bundle.body_words_count, &bytes_emitted);
1948 } else {
1949 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
1950 bool written_late = false;
1951 bool components[4] = { 0 };
1952 uint16_t register_dep_mask = 0;
1953 uint16_t written_mask = 0;
1954
1955 midgard_instruction *qins = ins;
1956 for (int t = 0; t < index; ++t) {
1957 if (qins->registers.out_reg != 0) {
1958 /* Mark down writes */
1959
1960 written_mask |= (1 << qins->registers.out_reg);
1961 } else {
1962 /* Mark down the register dependencies for errata check */
1963
1964 if (qins->registers.src1_reg < 16)
1965 register_dep_mask |= (1 << qins->registers.src1_reg);
1966
1967 if (qins->registers.src2_reg < 16)
1968 register_dep_mask |= (1 << qins->registers.src2_reg);
1969
1970 int mask = qins->alu.mask;
1971
1972 for (int c = 0; c < 4; ++c)
1973 if (mask & (0x3 << (2 * c)))
1974 components[c] = true;
1975
1976 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
1977
1978 if (qins->unit == UNIT_VLUT)
1979 written_late = true;
1980 }
1981
1982 /* Advance instruction pointer */
1983 qins = mir_next_op(qins);
1984 }
1985
1986
1987 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
1988 if (register_dep_mask & written_mask) {
1989 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask, written_mask, register_dep_mask & written_mask);
1990 break;
1991 }
1992
1993 if (written_late)
1994 break;
1995
1996 /* If even a single component is not written, break it up (conservative check). */
1997 bool breakup = false;
1998
1999 for (int c = 0; c < 4; ++c)
2000 if (!components[c])
2001 breakup = true;
2002
2003 if (breakup)
2004 break;
2005
2006 /* Otherwise, we're free to proceed */
2007 }
2008 }
2009
2010 if (ains->unit == ALU_ENAB_BRANCH) {
2011 bundle.body_size[bundle.body_words_count] = sizeof(midgard_branch_extended);
2012 memcpy(&bundle.body_words[bundle.body_words_count++], &ains->branch_extended, sizeof(midgard_branch_extended));
2013 bytes_emitted += sizeof(midgard_branch_extended);
2014 } else {
2015 bundle.body_size[bundle.body_words_count] = sizeof(ains->br_compact);
2016 memcpy(&bundle.body_words[bundle.body_words_count++], &ains->br_compact, sizeof(ains->br_compact));
2017 bytes_emitted += sizeof(ains->br_compact);
2018 }
2019 } else {
2020 memcpy(&bundle.register_words[bundle.register_words_count++], &ains->registers, sizeof(ains->registers));
2021 bytes_emitted += sizeof(midgard_reg_info);
2022
2023 bundle.body_size[bundle.body_words_count] = sizeof(midgard_scalar_alu);
2024 bundle.body_words_count++;
2025 bytes_emitted += sizeof(midgard_scalar_alu);
2026 }
2027
2028 /* Defer marking until after writing to allow for break */
2029 control |= ains->unit;
2030 last_unit = ains->unit;
2031 ++instructions_emitted;
2032 ++index;
2033 }
2034
2035 /* Bubble up the number of instructions for skipping */
2036 instructions_consumed = index - 1;
2037
2038 int padding = 0;
2039
2040 /* Pad ALU op to nearest word */
2041
2042 if (bytes_emitted & 15) {
2043 padding = 16 - (bytes_emitted & 15);
2044 bytes_emitted += padding;
2045 }
2046
2047 /* Constants must always be quadwords */
2048 if (bundle.has_embedded_constants)
2049 bytes_emitted += 16;
2050
2051 /* Size ALU instruction for tag */
2052 bundle.tag = (TAG_ALU_4) + (bytes_emitted / 16) - 1;
2053 bundle.padding = padding;
2054 bundle.control = bundle.tag | control;
2055
2056 break;
2057 }
2058
2059 case TAG_LOAD_STORE_4: {
2060 /* Load store instructions have two words at once. If
2061 * we only have one queued up, we need to NOP pad.
2062 * Otherwise, we store both in succession to save space
2063 * and cycles -- letting them go in parallel -- skip
2064 * the next. The usefulness of this optimisation is
2065 * greatly dependent on the quality of the instruction
2066 * scheduler.
2067 */
2068
2069 midgard_instruction *next_op = mir_next_op(ins);
2070
2071 if ((struct list_head *) next_op != &block->instructions && next_op->type == TAG_LOAD_STORE_4) {
2072 /* As the two operate concurrently, make sure
2073 * they are not dependent */
2074
2075 if (can_run_concurrent_ssa(ins, next_op) || true) {
2076 /* Skip ahead, since it's redundant with the pair */
2077 instructions_consumed = 1 + (instructions_emitted++);
2078 }
2079 }
2080
2081 break;
2082 }
2083
2084 default:
2085 /* Texture ops default to single-op-per-bundle scheduling */
2086 break;
2087 }
2088
2089 /* Copy the instructions into the bundle */
2090 bundle.instruction_count = instructions_emitted + 1;
2091
2092 int used_idx = 0;
2093
2094 midgard_instruction *uins = ins;
2095 for (int i = 0; used_idx < bundle.instruction_count; ++i) {
2096 bundle.instructions[used_idx++] = *uins;
2097 uins = mir_next_op(uins);
2098 }
2099
2100 *skip = (instructions_consumed == -1) ? instructions_emitted : instructions_consumed;
2101
2102 return bundle;
2103 }
2104
2105 static int
2106 quadword_size(int tag)
2107 {
2108 switch (tag) {
2109 case TAG_ALU_4:
2110 return 1;
2111
2112 case TAG_ALU_8:
2113 return 2;
2114
2115 case TAG_ALU_12:
2116 return 3;
2117
2118 case TAG_ALU_16:
2119 return 4;
2120
2121 case TAG_LOAD_STORE_4:
2122 return 1;
2123
2124 case TAG_TEXTURE_4:
2125 return 1;
2126
2127 default:
2128 assert(0);
2129 return 0;
2130 }
2131 }
2132
2133 /* Schedule a single block by iterating its instruction to create bundles.
2134 * While we go, tally about the bundle sizes to compute the block size. */
2135
2136 static void
2137 schedule_block(compiler_context *ctx, midgard_block *block)
2138 {
2139 util_dynarray_init(&block->bundles, NULL);
2140
2141 block->quadword_count = 0;
2142
2143 mir_foreach_instr_in_block(block, ins) {
2144 int skip;
2145 midgard_bundle bundle = schedule_bundle(ctx, block, ins, &skip);
2146 util_dynarray_append(&block->bundles, midgard_bundle, bundle);
2147
2148 if (bundle.has_blend_constant) {
2149 /* TODO: Multiblock? */
2150 int quadwords_within_block = block->quadword_count + quadword_size(bundle.tag) - 1;
2151 ctx->blend_constant_offset = quadwords_within_block * 0x10;
2152 }
2153
2154 while(skip--)
2155 ins = mir_next_op(ins);
2156
2157 block->quadword_count += quadword_size(bundle.tag);
2158 }
2159
2160 block->is_scheduled = true;
2161 }
2162
2163 static void
2164 schedule_program(compiler_context *ctx)
2165 {
2166 /* We run RA prior to scheduling */
2167 struct ra_graph *g = allocate_registers(ctx);
2168 install_registers(ctx, g);
2169
2170 mir_foreach_block(ctx, block) {
2171 schedule_block(ctx, block);
2172 }
2173 }
2174
2175 /* After everything is scheduled, emit whole bundles at a time */
2176
2177 static void
2178 emit_binary_bundle(compiler_context *ctx, midgard_bundle *bundle, struct util_dynarray *emission, int next_tag)
2179 {
2180 int lookahead = next_tag << 4;
2181
2182 switch (bundle->tag) {
2183 case TAG_ALU_4:
2184 case TAG_ALU_8:
2185 case TAG_ALU_12:
2186 case TAG_ALU_16: {
2187 /* Actually emit each component */
2188 util_dynarray_append(emission, uint32_t, bundle->control | lookahead);
2189
2190 for (int i = 0; i < bundle->register_words_count; ++i)
2191 util_dynarray_append(emission, uint16_t, bundle->register_words[i]);
2192
2193 /* Emit body words based on the instructions bundled */
2194 for (int i = 0; i < bundle->instruction_count; ++i) {
2195 midgard_instruction *ins = &bundle->instructions[i];
2196
2197 if (ins->unit & UNITS_ANY_VECTOR) {
2198 memcpy(util_dynarray_grow(emission, sizeof(midgard_vector_alu)), &ins->alu, sizeof(midgard_vector_alu));
2199 } else if (ins->compact_branch) {
2200 /* Dummy move, XXX DRY */
2201 if ((i == 0) && ins->writeout) {
2202 midgard_instruction ins = v_fmov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
2203 memcpy(util_dynarray_grow(emission, sizeof(midgard_vector_alu)), &ins.alu, sizeof(midgard_vector_alu));
2204 }
2205
2206 if (ins->unit == ALU_ENAB_BR_COMPACT) {
2207 memcpy(util_dynarray_grow(emission, sizeof(ins->br_compact)), &ins->br_compact, sizeof(ins->br_compact));
2208 } else {
2209 memcpy(util_dynarray_grow(emission, sizeof(ins->branch_extended)), &ins->branch_extended, sizeof(ins->branch_extended));
2210 }
2211 } else {
2212 /* Scalar */
2213 midgard_scalar_alu scalarised = vector_to_scalar_alu(ins->alu, ins);
2214 memcpy(util_dynarray_grow(emission, sizeof(scalarised)), &scalarised, sizeof(scalarised));
2215 }
2216 }
2217
2218 /* Emit padding (all zero) */
2219 memset(util_dynarray_grow(emission, bundle->padding), 0, bundle->padding);
2220
2221 /* Tack on constants */
2222
2223 if (bundle->has_embedded_constants) {
2224 util_dynarray_append(emission, float, bundle->constants[0]);
2225 util_dynarray_append(emission, float, bundle->constants[1]);
2226 util_dynarray_append(emission, float, bundle->constants[2]);
2227 util_dynarray_append(emission, float, bundle->constants[3]);
2228 }
2229
2230 break;
2231 }
2232
2233 case TAG_LOAD_STORE_4: {
2234 /* One or two composing instructions */
2235
2236 uint64_t current64, next64 = LDST_NOP;
2237
2238 memcpy(&current64, &bundle->instructions[0].load_store, sizeof(current64));
2239
2240 if (bundle->instruction_count == 2)
2241 memcpy(&next64, &bundle->instructions[1].load_store, sizeof(next64));
2242
2243 midgard_load_store instruction = {
2244 .type = bundle->tag,
2245 .next_type = next_tag,
2246 .word1 = current64,
2247 .word2 = next64
2248 };
2249
2250 util_dynarray_append(emission, midgard_load_store, instruction);
2251
2252 break;
2253 }
2254
2255 case TAG_TEXTURE_4: {
2256 /* Texture instructions are easy, since there is no
2257 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2258
2259 midgard_instruction *ins = &bundle->instructions[0];
2260
2261 ins->texture.type = TAG_TEXTURE_4;
2262 ins->texture.next_type = next_tag;
2263
2264 ctx->texture_op_count--;
2265
2266 if (!ctx->texture_op_count) {
2267 ins->texture.cont = 0;
2268 ins->texture.last = 1;
2269 }
2270
2271 util_dynarray_append(emission, midgard_texture_word, ins->texture);
2272 break;
2273 }
2274
2275 default:
2276 DBG("Unknown midgard instruction type\n");
2277 assert(0);
2278 break;
2279 }
2280 }
2281
2282
2283 /* ALU instructions can inline or embed constants, which decreases register
2284 * pressure and saves space. */
2285
2286 #define CONDITIONAL_ATTACH(src) { \
2287 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2288 \
2289 if (entry) { \
2290 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2291 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2292 } \
2293 }
2294
2295 static void
2296 inline_alu_constants(compiler_context *ctx)
2297 {
2298 mir_foreach_instr(ctx, alu) {
2299 /* Other instructions cannot inline constants */
2300 if (alu->type != TAG_ALU_4) continue;
2301
2302 /* If there is already a constant here, we can do nothing */
2303 if (alu->has_constants) continue;
2304
2305 /* It makes no sense to inline constants on a branch */
2306 if (alu->compact_branch || alu->prepacked_branch) continue;
2307
2308 CONDITIONAL_ATTACH(src0);
2309
2310 if (!alu->has_constants) {
2311 CONDITIONAL_ATTACH(src1)
2312 } else if (!alu->inline_constant) {
2313 /* Corner case: _two_ vec4 constants, for instance with a
2314 * csel. For this case, we can only use a constant
2315 * register for one, we'll have to emit a move for the
2316 * other. Note, if both arguments are constants, then
2317 * necessarily neither argument depends on the value of
2318 * any particular register. As the destination register
2319 * will be wiped, that means we can spill the constant
2320 * to the destination register.
2321 */
2322
2323 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src1 + 1);
2324 unsigned scratch = alu->ssa_args.dest;
2325
2326 if (entry) {
2327 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, scratch);
2328 attach_constants(ctx, &ins, entry, alu->ssa_args.src1 + 1);
2329
2330 /* Force a break XXX Defer r31 writes */
2331 ins.unit = UNIT_VLUT;
2332
2333 /* Set the source */
2334 alu->ssa_args.src1 = scratch;
2335
2336 /* Inject us -before- the last instruction which set r31 */
2337 mir_insert_instruction_before(mir_prev_op(alu), ins);
2338 }
2339 }
2340 }
2341 }
2342
2343 /* Midgard supports two types of constants, embedded constants (128-bit) and
2344 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2345 * constants can be demoted to inline constants, for space savings and
2346 * sometimes a performance boost */
2347
2348 static void
2349 embedded_to_inline_constant(compiler_context *ctx)
2350 {
2351 mir_foreach_instr(ctx, ins) {
2352 if (!ins->has_constants) continue;
2353
2354 if (ins->ssa_args.inline_constant) continue;
2355
2356 /* Blend constants must not be inlined by definition */
2357 if (ins->has_blend_constant) continue;
2358
2359 /* src1 cannot be an inline constant due to encoding
2360 * restrictions. So, if possible we try to flip the arguments
2361 * in that case */
2362
2363 int op = ins->alu.op;
2364
2365 if (ins->ssa_args.src0 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2366 switch (op) {
2367 /* These ops require an operational change to flip
2368 * their arguments TODO */
2369 case midgard_alu_op_flt:
2370 case midgard_alu_op_fle:
2371 case midgard_alu_op_ilt:
2372 case midgard_alu_op_ile:
2373 case midgard_alu_op_fcsel:
2374 case midgard_alu_op_icsel:
2375 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props[op].name);
2376 default:
2377 break;
2378 }
2379
2380 if (alu_opcode_props[op].props & OP_COMMUTES) {
2381 /* Flip the SSA numbers */
2382 ins->ssa_args.src0 = ins->ssa_args.src1;
2383 ins->ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
2384
2385 /* And flip the modifiers */
2386
2387 unsigned src_temp;
2388
2389 src_temp = ins->alu.src2;
2390 ins->alu.src2 = ins->alu.src1;
2391 ins->alu.src1 = src_temp;
2392 }
2393 }
2394
2395 if (ins->ssa_args.src1 == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2396 /* Extract the source information */
2397
2398 midgard_vector_alu_src *src;
2399 int q = ins->alu.src2;
2400 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
2401 src = m;
2402
2403 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2404 int component = src->swizzle & 3;
2405
2406 /* Scale constant appropriately, if we can legally */
2407 uint16_t scaled_constant = 0;
2408
2409 if (midgard_is_integer_op(op)) {
2410 unsigned int *iconstants = (unsigned int *) ins->constants;
2411 scaled_constant = (uint16_t) iconstants[component];
2412
2413 /* Constant overflow after resize */
2414 if (scaled_constant != iconstants[component])
2415 continue;
2416 } else {
2417 float original = (float) ins->constants[component];
2418 scaled_constant = _mesa_float_to_half(original);
2419
2420 /* Check for loss of precision. If this is
2421 * mediump, we don't care, but for a highp
2422 * shader, we need to pay attention. NIR
2423 * doesn't yet tell us which mode we're in!
2424 * Practically this prevents most constants
2425 * from being inlined, sadly. */
2426
2427 float fp32 = _mesa_half_to_float(scaled_constant);
2428
2429 if (fp32 != original)
2430 continue;
2431 }
2432
2433 /* We don't know how to handle these with a constant */
2434
2435 if (src->mod || src->half || src->rep_low || src->rep_high) {
2436 DBG("Bailing inline constant...\n");
2437 continue;
2438 }
2439
2440 /* Make sure that the constant is not itself a
2441 * vector by checking if all accessed values
2442 * (by the swizzle) are the same. */
2443
2444 uint32_t *cons = (uint32_t *) ins->constants;
2445 uint32_t value = cons[component];
2446
2447 bool is_vector = false;
2448 unsigned mask = effective_writemask(&ins->alu);
2449
2450 for (int c = 1; c < 4; ++c) {
2451 /* We only care if this component is actually used */
2452 if (!(mask & (1 << c)))
2453 continue;
2454
2455 uint32_t test = cons[(src->swizzle >> (2 * c)) & 3];
2456
2457 if (test != value) {
2458 is_vector = true;
2459 break;
2460 }
2461 }
2462
2463 if (is_vector)
2464 continue;
2465
2466 /* Get rid of the embedded constant */
2467 ins->has_constants = false;
2468 ins->ssa_args.src1 = SSA_UNUSED_0;
2469 ins->ssa_args.inline_constant = true;
2470 ins->inline_constant = scaled_constant;
2471 }
2472 }
2473 }
2474
2475 /* Map normal SSA sources to other SSA sources / fixed registers (like
2476 * uniforms) */
2477
2478 static void
2479 map_ssa_to_alias(compiler_context *ctx, int *ref)
2480 {
2481 unsigned int alias = (uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_to_alias, *ref + 1);
2482
2483 if (alias) {
2484 /* Remove entry in leftovers to avoid a redunant fmov */
2485
2486 struct set_entry *leftover = _mesa_set_search(ctx->leftover_ssa_to_alias, ((void *) (uintptr_t) (*ref + 1)));
2487
2488 if (leftover)
2489 _mesa_set_remove(ctx->leftover_ssa_to_alias, leftover);
2490
2491 /* Assign the alias map */
2492 *ref = alias - 1;
2493 return;
2494 }
2495 }
2496
2497 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
2498 * texture pipeline */
2499
2500 static bool
2501 midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block)
2502 {
2503 bool progress = false;
2504
2505 mir_foreach_instr_in_block_safe(block, ins) {
2506 if (ins->type != TAG_ALU_4) continue;
2507 if (ins->compact_branch) continue;
2508
2509 if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
2510 if (midgard_is_pinned(ctx, ins->ssa_args.dest)) continue;
2511 if (mir_is_live_after(ctx, block, ins, ins->ssa_args.dest)) continue;
2512
2513 mir_remove_instruction(ins);
2514 progress = true;
2515 }
2516
2517 return progress;
2518 }
2519
2520 static bool
2521 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
2522 {
2523 /* abs or neg */
2524 if (!is_int && src.mod) return true;
2525
2526 /* swizzle */
2527 for (unsigned c = 0; c < 4; ++c) {
2528 if (!(mask & (1 << c))) continue;
2529 if (((src.swizzle >> (2*c)) & 3) != c) return true;
2530 }
2531
2532 return false;
2533 }
2534
2535 static bool
2536 midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
2537 {
2538 bool progress = false;
2539
2540 mir_foreach_instr_in_block_safe(block, ins) {
2541 if (ins->type != TAG_ALU_4) continue;
2542 if (!OP_IS_MOVE(ins->alu.op)) continue;
2543
2544 unsigned from = ins->ssa_args.src1;
2545 unsigned to = ins->ssa_args.dest;
2546
2547 /* We only work on pure SSA */
2548
2549 if (to >= SSA_FIXED_MINIMUM) continue;
2550 if (from >= SSA_FIXED_MINIMUM) continue;
2551 if (to >= ctx->func->impl->ssa_alloc) continue;
2552 if (from >= ctx->func->impl->ssa_alloc) continue;
2553
2554 /* Constant propagation is not handled here, either */
2555 if (ins->ssa_args.inline_constant) continue;
2556 if (ins->has_constants) continue;
2557
2558 /* Also, if the move has side effects, we're helpless */
2559
2560 midgard_vector_alu_src src =
2561 vector_alu_from_unsigned(ins->alu.src2);
2562 unsigned mask = squeeze_writemask(ins->alu.mask);
2563 bool is_int = midgard_is_integer_op(ins->alu.op);
2564
2565 if (mir_nontrivial_mod(src, is_int, mask)) continue;
2566 if (ins->alu.outmod != midgard_outmod_none) continue;
2567
2568 mir_foreach_instr_in_block_from(block, v, mir_next_op(ins)) {
2569 if (v->ssa_args.src0 == to) {
2570 v->ssa_args.src0 = from;
2571 progress = true;
2572 }
2573
2574 if (v->ssa_args.src1 == to && !v->ssa_args.inline_constant) {
2575 v->ssa_args.src1 = from;
2576 progress = true;
2577 }
2578 }
2579 }
2580
2581 return progress;
2582 }
2583
2584 static bool
2585 midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
2586 {
2587 bool progress = false;
2588
2589 mir_foreach_instr_in_block_safe(block, ins) {
2590 if (ins->type != TAG_ALU_4) continue;
2591 if (!OP_IS_MOVE(ins->alu.op)) continue;
2592
2593 unsigned from = ins->ssa_args.src1;
2594 unsigned to = ins->ssa_args.dest;
2595
2596 /* Make sure it's simple enough for us to handle */
2597
2598 if (from >= SSA_FIXED_MINIMUM) continue;
2599 if (from >= ctx->func->impl->ssa_alloc) continue;
2600 if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
2601 if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
2602
2603 bool eliminated = false;
2604
2605 mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
2606 /* The texture registers are not SSA so be careful.
2607 * Conservatively, just stop if we hit a texture op
2608 * (even if it may not write) to where we are */
2609
2610 if (v->type != TAG_ALU_4)
2611 break;
2612
2613 if (v->ssa_args.dest == from) {
2614 /* We don't want to track partial writes ... */
2615 if (v->alu.mask == 0xF) {
2616 v->ssa_args.dest = to;
2617 eliminated = true;
2618 }
2619
2620 break;
2621 }
2622 }
2623
2624 if (eliminated)
2625 mir_remove_instruction(ins);
2626
2627 progress |= eliminated;
2628 }
2629
2630 return progress;
2631 }
2632
2633 /* The following passes reorder MIR instructions to enable better scheduling */
2634
2635 static void
2636 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
2637 {
2638 mir_foreach_instr_in_block_safe(block, ins) {
2639 if (ins->type != TAG_LOAD_STORE_4) continue;
2640
2641 /* We've found a load/store op. Check if next is also load/store. */
2642 midgard_instruction *next_op = mir_next_op(ins);
2643 if (&next_op->link != &block->instructions) {
2644 if (next_op->type == TAG_LOAD_STORE_4) {
2645 /* If so, we're done since we're a pair */
2646 ins = mir_next_op(ins);
2647 continue;
2648 }
2649
2650 /* Maximum search distance to pair, to avoid register pressure disasters */
2651 int search_distance = 8;
2652
2653 /* Otherwise, we have an orphaned load/store -- search for another load */
2654 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
2655 /* Terminate search if necessary */
2656 if (!(search_distance--)) break;
2657
2658 if (c->type != TAG_LOAD_STORE_4) continue;
2659
2660 /* Stores cannot be reordered, since they have
2661 * dependencies. For the same reason, indirect
2662 * loads cannot be reordered as their index is
2663 * loaded in r27.w */
2664
2665 if (OP_IS_STORE(c->load_store.op)) continue;
2666
2667 /* It appears the 0x800 bit is set whenever a
2668 * load is direct, unset when it is indirect.
2669 * Skip indirect loads. */
2670
2671 if (!(c->load_store.unknown & 0x800)) continue;
2672
2673 /* We found one! Move it up to pair and remove it from the old location */
2674
2675 mir_insert_instruction_before(ins, *c);
2676 mir_remove_instruction(c);
2677
2678 break;
2679 }
2680 }
2681 }
2682 }
2683
2684 /* Emit varying stores late */
2685
2686 static void
2687 midgard_emit_store(compiler_context *ctx, midgard_block *block) {
2688 /* Iterate in reverse to get the final write, rather than the first */
2689
2690 mir_foreach_instr_in_block_safe_rev(block, ins) {
2691 /* Check if what we just wrote needs a store */
2692 int idx = ins->ssa_args.dest;
2693 uintptr_t varying = ((uintptr_t) _mesa_hash_table_u64_search(ctx->ssa_varyings, idx + 1));
2694
2695 if (!varying) continue;
2696
2697 varying -= 1;
2698
2699 /* We need to store to the appropriate varying, so emit the
2700 * move/store */
2701
2702 /* TODO: Integrate with special purpose RA (and scheduler?) */
2703 bool high_varying_register = false;
2704
2705 midgard_instruction mov = v_fmov(idx, blank_alu_src, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE + high_varying_register));
2706
2707 midgard_instruction st = m_st_vary_32(SSA_FIXED_REGISTER(high_varying_register), varying);
2708 st.load_store.unknown = 0x1E9E; /* XXX: What is this? */
2709
2710 mir_insert_instruction_before(mir_next_op(ins), st);
2711 mir_insert_instruction_before(mir_next_op(ins), mov);
2712
2713 /* We no longer need to store this varying */
2714 _mesa_hash_table_u64_remove(ctx->ssa_varyings, idx + 1);
2715 }
2716 }
2717
2718 /* If there are leftovers after the below pass, emit actual fmov
2719 * instructions for the slow-but-correct path */
2720
2721 static void
2722 emit_leftover_move(compiler_context *ctx)
2723 {
2724 set_foreach(ctx->leftover_ssa_to_alias, leftover) {
2725 int base = ((uintptr_t) leftover->key) - 1;
2726 int mapped = base;
2727
2728 map_ssa_to_alias(ctx, &mapped);
2729 EMIT(fmov, mapped, blank_alu_src, base);
2730 }
2731 }
2732
2733 static void
2734 actualise_ssa_to_alias(compiler_context *ctx)
2735 {
2736 mir_foreach_instr(ctx, ins) {
2737 map_ssa_to_alias(ctx, &ins->ssa_args.src0);
2738 map_ssa_to_alias(ctx, &ins->ssa_args.src1);
2739 }
2740
2741 emit_leftover_move(ctx);
2742 }
2743
2744 static void
2745 emit_fragment_epilogue(compiler_context *ctx)
2746 {
2747 /* Special case: writing out constants requires us to include the move
2748 * explicitly now, so shove it into r0 */
2749
2750 void *constant_value = _mesa_hash_table_u64_search(ctx->ssa_constants, ctx->fragment_output + 1);
2751
2752 if (constant_value) {
2753 midgard_instruction ins = v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), blank_alu_src, SSA_FIXED_REGISTER(0));
2754 attach_constants(ctx, &ins, constant_value, ctx->fragment_output + 1);
2755 emit_mir_instruction(ctx, ins);
2756 }
2757
2758 /* Perform the actual fragment writeout. We have two writeout/branch
2759 * instructions, forming a loop until writeout is successful as per the
2760 * docs. TODO: gl_FragDepth */
2761
2762 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2763 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2764 }
2765
2766 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2767 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2768 * with the int8 analogue to the fragment epilogue */
2769
2770 static void
2771 emit_blend_epilogue(compiler_context *ctx)
2772 {
2773 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2774
2775 midgard_instruction scale = {
2776 .type = TAG_ALU_4,
2777 .unit = UNIT_VMUL,
2778 .inline_constant = _mesa_float_to_half(255.0),
2779 .ssa_args = {
2780 .src0 = SSA_FIXED_REGISTER(0),
2781 .src1 = SSA_UNUSED_0,
2782 .dest = SSA_FIXED_REGISTER(24),
2783 .inline_constant = true
2784 },
2785 .alu = {
2786 .op = midgard_alu_op_fmul,
2787 .reg_mode = midgard_reg_mode_32,
2788 .dest_override = midgard_dest_override_lower,
2789 .mask = 0xFF,
2790 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2791 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2792 }
2793 };
2794
2795 emit_mir_instruction(ctx, scale);
2796
2797 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2798
2799 midgard_vector_alu_src alu_src = blank_alu_src;
2800 alu_src.half = true;
2801
2802 midgard_instruction f2u8 = {
2803 .type = TAG_ALU_4,
2804 .ssa_args = {
2805 .src0 = SSA_FIXED_REGISTER(24),
2806 .src1 = SSA_UNUSED_0,
2807 .dest = SSA_FIXED_REGISTER(0),
2808 .inline_constant = true
2809 },
2810 .alu = {
2811 .op = midgard_alu_op_f2u8,
2812 .reg_mode = midgard_reg_mode_16,
2813 .dest_override = midgard_dest_override_lower,
2814 .outmod = midgard_outmod_pos,
2815 .mask = 0xF,
2816 .src1 = vector_alu_srco_unsigned(alu_src),
2817 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2818 }
2819 };
2820
2821 emit_mir_instruction(ctx, f2u8);
2822
2823 /* vmul.imov.quarter r0, r0, r0 */
2824
2825 midgard_instruction imov_8 = {
2826 .type = TAG_ALU_4,
2827 .ssa_args = {
2828 .src0 = SSA_UNUSED_1,
2829 .src1 = SSA_FIXED_REGISTER(0),
2830 .dest = SSA_FIXED_REGISTER(0),
2831 },
2832 .alu = {
2833 .op = midgard_alu_op_imov,
2834 .reg_mode = midgard_reg_mode_8,
2835 .dest_override = midgard_dest_override_none,
2836 .mask = 0xFF,
2837 .src1 = vector_alu_srco_unsigned(blank_alu_src),
2838 .src2 = vector_alu_srco_unsigned(blank_alu_src),
2839 }
2840 };
2841
2842 /* Emit branch epilogue with the 8-bit move as the source */
2843
2844 emit_mir_instruction(ctx, imov_8);
2845 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always);
2846
2847 emit_mir_instruction(ctx, imov_8);
2848 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always);
2849 }
2850
2851 static midgard_block *
2852 emit_block(compiler_context *ctx, nir_block *block)
2853 {
2854 midgard_block *this_block = calloc(sizeof(midgard_block), 1);
2855 list_addtail(&this_block->link, &ctx->blocks);
2856
2857 this_block->is_scheduled = false;
2858 ++ctx->block_count;
2859
2860 ctx->texture_index[0] = -1;
2861 ctx->texture_index[1] = -1;
2862
2863 /* Add us as a successor to the block we are following */
2864 if (ctx->current_block)
2865 midgard_block_add_successor(ctx->current_block, this_block);
2866
2867 /* Set up current block */
2868 list_inithead(&this_block->instructions);
2869 ctx->current_block = this_block;
2870
2871 nir_foreach_instr(instr, block) {
2872 emit_instr(ctx, instr);
2873 ++ctx->instruction_count;
2874 }
2875
2876 inline_alu_constants(ctx);
2877 embedded_to_inline_constant(ctx);
2878
2879 /* Perform heavylifting for aliasing */
2880 actualise_ssa_to_alias(ctx);
2881
2882 midgard_emit_store(ctx, this_block);
2883 midgard_pair_load_store(ctx, this_block);
2884
2885 /* Append fragment shader epilogue (value writeout) */
2886 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2887 if (block == nir_impl_last_block(ctx->func->impl)) {
2888 if (ctx->is_blend)
2889 emit_blend_epilogue(ctx);
2890 else
2891 emit_fragment_epilogue(ctx);
2892 }
2893 }
2894
2895 if (block == nir_start_block(ctx->func->impl))
2896 ctx->initial_block = this_block;
2897
2898 if (block == nir_impl_last_block(ctx->func->impl))
2899 ctx->final_block = this_block;
2900
2901 /* Allow the next control flow to access us retroactively, for
2902 * branching etc */
2903 ctx->current_block = this_block;
2904
2905 /* Document the fallthrough chain */
2906 ctx->previous_source_block = this_block;
2907
2908 return this_block;
2909 }
2910
2911 static midgard_block *emit_cf_list(struct compiler_context *ctx, struct exec_list *list);
2912
2913 static void
2914 emit_if(struct compiler_context *ctx, nir_if *nif)
2915 {
2916 /* Conditional branches expect the condition in r31.w; emit a move for
2917 * that in the _previous_ block (which is the current block). */
2918 emit_condition(ctx, &nif->condition, true, COMPONENT_X);
2919
2920 /* Speculatively emit the branch, but we can't fill it in until later */
2921 EMIT(branch, true, true);
2922 midgard_instruction *then_branch = mir_last_in_block(ctx->current_block);
2923
2924 /* Emit the two subblocks */
2925 midgard_block *then_block = emit_cf_list(ctx, &nif->then_list);
2926
2927 /* Emit a jump from the end of the then block to the end of the else */
2928 EMIT(branch, false, false);
2929 midgard_instruction *then_exit = mir_last_in_block(ctx->current_block);
2930
2931 /* Emit second block, and check if it's empty */
2932
2933 int else_idx = ctx->block_count;
2934 int count_in = ctx->instruction_count;
2935 midgard_block *else_block = emit_cf_list(ctx, &nif->else_list);
2936 int after_else_idx = ctx->block_count;
2937
2938 /* Now that we have the subblocks emitted, fix up the branches */
2939
2940 assert(then_block);
2941 assert(else_block);
2942
2943 if (ctx->instruction_count == count_in) {
2944 /* The else block is empty, so don't emit an exit jump */
2945 mir_remove_instruction(then_exit);
2946 then_branch->branch.target_block = after_else_idx;
2947 } else {
2948 then_branch->branch.target_block = else_idx;
2949 then_exit->branch.target_block = after_else_idx;
2950 }
2951 }
2952
2953 static void
2954 emit_loop(struct compiler_context *ctx, nir_loop *nloop)
2955 {
2956 /* Remember where we are */
2957 midgard_block *start_block = ctx->current_block;
2958
2959 /* Allocate a loop number, growing the current inner loop depth */
2960 int loop_idx = ++ctx->current_loop_depth;
2961
2962 /* Get index from before the body so we can loop back later */
2963 int start_idx = ctx->block_count;
2964
2965 /* Emit the body itself */
2966 emit_cf_list(ctx, &nloop->body);
2967
2968 /* Branch back to loop back */
2969 struct midgard_instruction br_back = v_branch(false, false);
2970 br_back.branch.target_block = start_idx;
2971 emit_mir_instruction(ctx, br_back);
2972
2973 /* Mark down that branch in the graph. Note that we're really branching
2974 * to the block *after* we started in. TODO: Why doesn't the branch
2975 * itself have an off-by-one then...? */
2976 midgard_block_add_successor(ctx->current_block, start_block->successors[0]);
2977
2978 /* Find the index of the block about to follow us (note: we don't add
2979 * one; blocks are 0-indexed so we get a fencepost problem) */
2980 int break_block_idx = ctx->block_count;
2981
2982 /* Fix up the break statements we emitted to point to the right place,
2983 * now that we can allocate a block number for them */
2984
2985 list_for_each_entry_from(struct midgard_block, block, start_block, &ctx->blocks, link) {
2986 mir_foreach_instr_in_block(block, ins) {
2987 if (ins->type != TAG_ALU_4) continue;
2988 if (!ins->compact_branch) continue;
2989 if (ins->prepacked_branch) continue;
2990
2991 /* We found a branch -- check the type to see if we need to do anything */
2992 if (ins->branch.target_type != TARGET_BREAK) continue;
2993
2994 /* It's a break! Check if it's our break */
2995 if (ins->branch.target_break != loop_idx) continue;
2996
2997 /* Okay, cool, we're breaking out of this loop.
2998 * Rewrite from a break to a goto */
2999
3000 ins->branch.target_type = TARGET_GOTO;
3001 ins->branch.target_block = break_block_idx;
3002 }
3003 }
3004
3005 /* Now that we've finished emitting the loop, free up the depth again
3006 * so we play nice with recursion amid nested loops */
3007 --ctx->current_loop_depth;
3008 }
3009
3010 static midgard_block *
3011 emit_cf_list(struct compiler_context *ctx, struct exec_list *list)
3012 {
3013 midgard_block *start_block = NULL;
3014
3015 foreach_list_typed(nir_cf_node, node, node, list) {
3016 switch (node->type) {
3017 case nir_cf_node_block: {
3018 midgard_block *block = emit_block(ctx, nir_cf_node_as_block(node));
3019
3020 if (!start_block)
3021 start_block = block;
3022
3023 break;
3024 }
3025
3026 case nir_cf_node_if:
3027 emit_if(ctx, nir_cf_node_as_if(node));
3028 break;
3029
3030 case nir_cf_node_loop:
3031 emit_loop(ctx, nir_cf_node_as_loop(node));
3032 break;
3033
3034 case nir_cf_node_function:
3035 assert(0);
3036 break;
3037 }
3038 }
3039
3040 return start_block;
3041 }
3042
3043 /* Due to lookahead, we need to report the first tag executed in the command
3044 * stream and in branch targets. An initial block might be empty, so iterate
3045 * until we find one that 'works' */
3046
3047 static unsigned
3048 midgard_get_first_tag_from_block(compiler_context *ctx, unsigned block_idx)
3049 {
3050 midgard_block *initial_block = mir_get_block(ctx, block_idx);
3051
3052 unsigned first_tag = 0;
3053
3054 do {
3055 midgard_bundle *initial_bundle = util_dynarray_element(&initial_block->bundles, midgard_bundle, 0);
3056
3057 if (initial_bundle) {
3058 first_tag = initial_bundle->tag;
3059 break;
3060 }
3061
3062 /* Initial block is empty, try the next block */
3063 initial_block = list_first_entry(&(initial_block->link), midgard_block, link);
3064 } while(initial_block != NULL);
3065
3066 assert(first_tag);
3067 return first_tag;
3068 }
3069
3070 int
3071 midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_blend)
3072 {
3073 struct util_dynarray *compiled = &program->compiled;
3074
3075 midgard_debug = debug_get_option_midgard_debug();
3076
3077 compiler_context ictx = {
3078 .nir = nir,
3079 .stage = nir->info.stage,
3080
3081 .is_blend = is_blend,
3082 .blend_constant_offset = -1,
3083
3084 .alpha_ref = program->alpha_ref
3085 };
3086
3087 compiler_context *ctx = &ictx;
3088
3089 /* TODO: Decide this at runtime */
3090 ctx->uniform_cutoff = 8;
3091
3092 /* Assign var locations early, so the epilogue can use them if necessary */
3093
3094 nir_assign_var_locations(&nir->outputs, &nir->num_outputs, glsl_type_size);
3095 nir_assign_var_locations(&nir->inputs, &nir->num_inputs, glsl_type_size);
3096 nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms, glsl_type_size);
3097
3098 /* Initialize at a global (not block) level hash tables */
3099
3100 ctx->ssa_constants = _mesa_hash_table_u64_create(NULL);
3101 ctx->ssa_varyings = _mesa_hash_table_u64_create(NULL);
3102 ctx->ssa_to_alias = _mesa_hash_table_u64_create(NULL);
3103 ctx->ssa_to_register = _mesa_hash_table_u64_create(NULL);
3104 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
3105 ctx->sysval_to_id = _mesa_hash_table_u64_create(NULL);
3106 ctx->leftover_ssa_to_alias = _mesa_set_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
3107
3108 /* Record the varying mapping for the command stream's bookkeeping */
3109
3110 struct exec_list *varyings =
3111 ctx->stage == MESA_SHADER_VERTEX ? &nir->outputs : &nir->inputs;
3112
3113 nir_foreach_variable(var, varyings) {
3114 unsigned loc = var->data.driver_location;
3115 unsigned sz = glsl_type_size(var->type, FALSE);
3116
3117 for (int c = 0; c < sz; ++c) {
3118 program->varyings[loc + c] = var->data.location;
3119 }
3120 }
3121
3122 /* Lower gl_Position pre-optimisation */
3123
3124 if (ctx->stage == MESA_SHADER_VERTEX)
3125 NIR_PASS_V(nir, nir_lower_viewport_transform);
3126
3127 NIR_PASS_V(nir, nir_lower_var_copies);
3128 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
3129 NIR_PASS_V(nir, nir_split_var_copies);
3130 NIR_PASS_V(nir, nir_lower_var_copies);
3131 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
3132 NIR_PASS_V(nir, nir_lower_var_copies);
3133 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
3134
3135 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
3136
3137 /* Optimisation passes */
3138
3139 optimise_nir(nir);
3140
3141 if (midgard_debug & MIDGARD_DBG_SHADERS) {
3142 nir_print_shader(nir, stdout);
3143 }
3144
3145 /* Assign sysvals and counts, now that we're sure
3146 * (post-optimisation) */
3147
3148 midgard_nir_assign_sysvals(ctx, nir);
3149
3150 program->uniform_count = nir->num_uniforms;
3151 program->sysval_count = ctx->sysval_count;
3152 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * ctx->sysval_count);
3153
3154 program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_inputs : 0;
3155 program->varying_count = (ctx->stage == MESA_SHADER_VERTEX) ? nir->num_outputs : ((ctx->stage == MESA_SHADER_FRAGMENT) ? nir->num_inputs : 0);
3156
3157 nir_foreach_function(func, nir) {
3158 if (!func->impl)
3159 continue;
3160
3161 list_inithead(&ctx->blocks);
3162 ctx->block_count = 0;
3163 ctx->func = func;
3164
3165 emit_cf_list(ctx, &func->impl->body);
3166 emit_block(ctx, func->impl->end_block);
3167
3168 break; /* TODO: Multi-function shaders */
3169 }
3170
3171 util_dynarray_init(compiled, NULL);
3172
3173 /* MIR-level optimizations */
3174
3175 bool progress = false;
3176
3177 do {
3178 progress = false;
3179
3180 mir_foreach_block(ctx, block) {
3181 progress |= midgard_opt_copy_prop(ctx, block);
3182 progress |= midgard_opt_copy_prop_tex(ctx, block);
3183 progress |= midgard_opt_dead_code_eliminate(ctx, block);
3184 }
3185 } while (progress);
3186
3187 /* Schedule! */
3188 schedule_program(ctx);
3189
3190 /* Now that all the bundles are scheduled and we can calculate block
3191 * sizes, emit actual branch instructions rather than placeholders */
3192
3193 int br_block_idx = 0;
3194
3195 mir_foreach_block(ctx, block) {
3196 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3197 for (int c = 0; c < bundle->instruction_count; ++c) {
3198 midgard_instruction *ins = &bundle->instructions[c];
3199
3200 if (!midgard_is_branch_unit(ins->unit)) continue;
3201
3202 if (ins->prepacked_branch) continue;
3203
3204 /* Parse some basic branch info */
3205 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
3206 bool is_conditional = ins->branch.conditional;
3207 bool is_inverted = ins->branch.invert_conditional;
3208 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
3209
3210 /* Determine the block we're jumping to */
3211 int target_number = ins->branch.target_block;
3212
3213 /* Report the destination tag. Discards don't need this */
3214 int dest_tag = is_discard ? 0 : midgard_get_first_tag_from_block(ctx, target_number);
3215
3216 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3217 int quadword_offset = 0;
3218
3219 if (is_discard) {
3220 /* Jump to the end of the shader. We
3221 * need to include not only the
3222 * following blocks, but also the
3223 * contents of our current block (since
3224 * discard can come in the middle of
3225 * the block) */
3226
3227 midgard_block *blk = mir_get_block(ctx, br_block_idx + 1);
3228
3229 for (midgard_bundle *bun = bundle + 1; bun < (midgard_bundle *)((char*) block->bundles.data + block->bundles.size); ++bun) {
3230 quadword_offset += quadword_size(bun->tag);
3231 }
3232
3233 mir_foreach_block_from(ctx, blk, b) {
3234 quadword_offset += b->quadword_count;
3235 }
3236
3237 } else if (target_number > br_block_idx) {
3238 /* Jump forward */
3239
3240 for (int idx = br_block_idx + 1; idx < target_number; ++idx) {
3241 midgard_block *blk = mir_get_block(ctx, idx);
3242 assert(blk);
3243
3244 quadword_offset += blk->quadword_count;
3245 }
3246 } else {
3247 /* Jump backwards */
3248
3249 for (int idx = br_block_idx; idx >= target_number; --idx) {
3250 midgard_block *blk = mir_get_block(ctx, idx);
3251 assert(blk);
3252
3253 quadword_offset -= blk->quadword_count;
3254 }
3255 }
3256
3257 /* Unconditional extended branches (far jumps)
3258 * have issues, so we always use a conditional
3259 * branch, setting the condition to always for
3260 * unconditional. For compact unconditional
3261 * branches, cond isn't used so it doesn't
3262 * matter what we pick. */
3263
3264 midgard_condition cond =
3265 !is_conditional ? midgard_condition_always :
3266 is_inverted ? midgard_condition_false :
3267 midgard_condition_true;
3268
3269 midgard_jmp_writeout_op op =
3270 is_discard ? midgard_jmp_writeout_op_discard :
3271 (is_compact && !is_conditional) ? midgard_jmp_writeout_op_branch_uncond :
3272 midgard_jmp_writeout_op_branch_cond;
3273
3274 if (!is_compact) {
3275 midgard_branch_extended branch =
3276 midgard_create_branch_extended(
3277 cond, op,
3278 dest_tag,
3279 quadword_offset);
3280
3281 memcpy(&ins->branch_extended, &branch, sizeof(branch));
3282 } else if (is_conditional || is_discard) {
3283 midgard_branch_cond branch = {
3284 .op = op,
3285 .dest_tag = dest_tag,
3286 .offset = quadword_offset,
3287 .cond = cond
3288 };
3289
3290 assert(branch.offset == quadword_offset);
3291
3292 memcpy(&ins->br_compact, &branch, sizeof(branch));
3293 } else {
3294 assert(op == midgard_jmp_writeout_op_branch_uncond);
3295
3296 midgard_branch_uncond branch = {
3297 .op = op,
3298 .dest_tag = dest_tag,
3299 .offset = quadword_offset,
3300 .unknown = 1
3301 };
3302
3303 assert(branch.offset == quadword_offset);
3304
3305 memcpy(&ins->br_compact, &branch, sizeof(branch));
3306 }
3307 }
3308 }
3309
3310 ++br_block_idx;
3311 }
3312
3313 /* Emit flat binary from the instruction arrays. Iterate each block in
3314 * sequence. Save instruction boundaries such that lookahead tags can
3315 * be assigned easily */
3316
3317 /* Cache _all_ bundles in source order for lookahead across failed branches */
3318
3319 int bundle_count = 0;
3320 mir_foreach_block(ctx, block) {
3321 bundle_count += block->bundles.size / sizeof(midgard_bundle);
3322 }
3323 midgard_bundle **source_order_bundles = malloc(sizeof(midgard_bundle *) * bundle_count);
3324 int bundle_idx = 0;
3325 mir_foreach_block(ctx, block) {
3326 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3327 source_order_bundles[bundle_idx++] = bundle;
3328 }
3329 }
3330
3331 int current_bundle = 0;
3332
3333 mir_foreach_block(ctx, block) {
3334 util_dynarray_foreach(&block->bundles, midgard_bundle, bundle) {
3335 int lookahead = 1;
3336
3337 if (current_bundle + 1 < bundle_count) {
3338 uint8_t next = source_order_bundles[current_bundle + 1]->tag;
3339
3340 if (!(current_bundle + 2 < bundle_count) && IS_ALU(next)) {
3341 lookahead = 1;
3342 } else {
3343 lookahead = next;
3344 }
3345 }
3346
3347 emit_binary_bundle(ctx, bundle, compiled, lookahead);
3348 ++current_bundle;
3349 }
3350
3351 /* TODO: Free deeper */
3352 //util_dynarray_fini(&block->instructions);
3353 }
3354
3355 free(source_order_bundles);
3356
3357 /* Report the very first tag executed */
3358 program->first_tag = midgard_get_first_tag_from_block(ctx, 0);
3359
3360 /* Deal with off-by-one related to the fencepost problem */
3361 program->work_register_count = ctx->work_registers + 1;
3362
3363 program->can_discard = ctx->can_discard;
3364 program->uniform_cutoff = ctx->uniform_cutoff;
3365
3366 program->blend_patch_offset = ctx->blend_constant_offset;
3367
3368 if (midgard_debug & MIDGARD_DBG_SHADERS)
3369 disassemble_midgard(program->compiled.data, program->compiled.size);
3370
3371 return 0;
3372 }