src/gallium/drivers/panfrost/midgard/midgard_emit.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
  28  * use scalar ALU instructions, for functional or performance reasons. To do
  29  * this, we just demote vector ALU payloads to scalar. */
  30
  31 static int
  32 component_from_mask(unsigned mask)
  33 {
  34         for (int c = 0; c < 8; ++c) {
  35                 if (mask & (1 << c))
  36                         return c;
  37         }
  38
  39         assert(0);
  40         return 0;
  41 }
  42
  43 static unsigned
  44 vector_to_scalar_source(unsigned u, bool is_int, bool is_full)
  45 {
  46         midgard_vector_alu_src v;
  47         memcpy(&v, &u, sizeof(v));
  48
  49         /* TODO: Integers */
  50
  51         unsigned component = v.swizzle & 3;
  52         bool upper = false; /* TODO */
  53
  54         midgard_scalar_alu_src s = { 0 };
  55
  56         if (is_full) {
  57                 /* For a 32-bit op, just check the source half flag */
  58                 s.full = !v.half;
  59         } else if (!v.half) {
  60                 /* For a 16-bit op that's not subdivided, never full */
  61                 s.full = false;
  62         } else {
  63                 /* We can't do 8-bit scalar, abort! */
  64                 assert(0);
  65         }
  66
  67         /* Component indexing takes size into account */
  68
  69         if (s.full)
  70                 s.component = component << 1;
  71         else
  72                 s.component = component + (upper << 2);
  73
  74         if (is_int) {
  75                 /* TODO */
  76         } else {
  77                 s.abs = v.mod & MIDGARD_FLOAT_MOD_ABS;
  78                 s.negate = v.mod & MIDGARD_FLOAT_MOD_NEG;
  79         }
  80
  81         unsigned o;
  82         memcpy(&o, &s, sizeof(s));
  83
  84         return o & ((1 << 6) - 1);
  85 }
  86
  87 static midgard_scalar_alu
  88 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
  89 {
  90         bool is_int = midgard_is_integer_op(v.op);
  91         bool is_full = v.reg_mode == midgard_reg_mode_32;
  92         bool is_inline_constant = ins->ssa_args.inline_constant;
  93
  94         /* The output component is from the mask */
  95         midgard_scalar_alu s = {
  96                 .op = v.op,
  97                 .src1 = vector_to_scalar_source(v.src1, is_int, is_full),
  98                 .src2 = !is_inline_constant ? vector_to_scalar_source(v.src2, is_int, is_full) : 0,
  99                 .unknown = 0,
 100                 .outmod = v.outmod,
 101                 .output_full = is_full,
 102                 .output_component = component_from_mask(ins->mask),
 103         };
 104
 105         /* Full components are physically spaced out */
 106         if (is_full) {
 107                 assert(s.output_component < 4);
 108                 s.output_component <<= 1;
 109         }
 110
 111         /* Inline constant is passed along rather than trying to extract it
 112          * from v */
 113
 114         if (ins->ssa_args.inline_constant) {
 115                 uint16_t imm = 0;
 116                 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
 117                 imm |= (lower_11 >> 9) & 3;
 118                 imm |= (lower_11 >> 6) & 4;
 119                 imm |= (lower_11 >> 2) & 0x38;
 120                 imm |= (lower_11 & 63) << 6;
 121
 122                 s.src2 = imm;
 123         }
 124
 125         return s;
 126 }
 127
 128 static void
 129 emit_alu_bundle(compiler_context *ctx,
 130                 midgard_bundle *bundle,
 131                 struct util_dynarray *emission,
 132                 unsigned lookahead)
 133 {
 134         /* Emit the control word */
 135         util_dynarray_append(emission, uint32_t, bundle->control | lookahead);
 136
 137         /* Next up, emit register words */
 138         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 139                 midgard_instruction *ins = bundle->instructions[i];
 140
 141                 /* Check if this instruction has registers */
 142                 if (ins->compact_branch || ins->prepacked_branch) continue;
 143
 144                 /* Otherwise, just emit the registers */
 145                 uint16_t reg_word = 0;
 146                 memcpy(&reg_word, &ins->registers, sizeof(uint16_t));
 147                 util_dynarray_append(emission, uint16_t, reg_word);
 148         }
 149
 150         /* Now, we emit the body itself */
 151         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 152                 midgard_instruction *ins = bundle->instructions[i];
 153
 154                 /* Where is this body */
 155                 unsigned size = 0;
 156                 void *source = NULL;
 157
 158                 /* In case we demote to a scalar */
 159                 midgard_scalar_alu scalarized;
 160
 161                 if (ins->unit & UNITS_ANY_VECTOR) {
 162                         if (ins->alu.reg_mode == midgard_reg_mode_32)
 163                                 ins->alu.mask = expand_writemask_32(ins->mask);
 164                         else
 165                                 ins->alu.mask = ins->mask;
 166
 167                         size = sizeof(midgard_vector_alu);
 168                         source = &ins->alu;
 169                 } else if (ins->unit == ALU_ENAB_BR_COMPACT) {
 170                         size = sizeof(midgard_branch_cond);
 171                         source = &ins->br_compact;
 172                 } else if (ins->compact_branch) { /* misnomer */
 173                         size = sizeof(midgard_branch_extended);
 174                         source = &ins->branch_extended;
 175                 } else {
 176                         size = sizeof(midgard_scalar_alu);
 177                         scalarized = vector_to_scalar_alu(ins->alu, ins);
 178                         source = &scalarized;
 179                 }
 180
 181                 memcpy(util_dynarray_grow_bytes(emission, 1, size), source, size);
 182         }
 183
 184         /* Emit padding (all zero) */
 185         memset(util_dynarray_grow_bytes(emission, 1, bundle->padding), 0, bundle->padding);
 186
 187         /* Tack on constants */
 188
 189         if (bundle->has_embedded_constants) {
 190                 util_dynarray_append(emission, float, bundle->constants[0]);
 191                 util_dynarray_append(emission, float, bundle->constants[1]);
 192                 util_dynarray_append(emission, float, bundle->constants[2]);
 193                 util_dynarray_append(emission, float, bundle->constants[3]);
 194         }
 195 }
 196
 197 /* After everything is scheduled, emit whole bundles at a time */
 198
 199 void
 200 emit_binary_bundle(compiler_context *ctx,
 201                 midgard_bundle *bundle,
 202                 struct util_dynarray *emission,
 203                 int next_tag)
 204 {
 205         int lookahead = next_tag << 4;
 206
 207         switch (bundle->tag) {
 208         case TAG_ALU_4:
 209         case TAG_ALU_8:
 210         case TAG_ALU_12:
 211         case TAG_ALU_16:
 212                 emit_alu_bundle(ctx, bundle, emission, lookahead);
 213                 break;
 214
 215         case TAG_LOAD_STORE_4: {
 216                 /* One or two composing instructions */
 217
 218                 uint64_t current64, next64 = LDST_NOP;
 219
 220                 /* Copy masks */
 221
 222                 for (unsigned i = 0; i < bundle->instruction_count; ++i) {
 223                         bundle->instructions[i]->load_store.mask =
 224                                 bundle->instructions[i]->mask;
 225                 }
 226
 227                 memcpy(&current64, &bundle->instructions[0]->load_store, sizeof(current64));
 228
 229                 if (bundle->instruction_count == 2)
 230                         memcpy(&next64, &bundle->instructions[1]->load_store, sizeof(next64));
 231
 232                 midgard_load_store instruction = {
 233                         .type = bundle->tag,
 234                         .next_type = next_tag,
 235                         .word1 = current64,
 236                         .word2 = next64
 237                 };
 238
 239                 util_dynarray_append(emission, midgard_load_store, instruction);
 240
 241                 break;
 242         }
 243
 244         case TAG_TEXTURE_4:
 245         case TAG_TEXTURE_4_VTX: {
 246                 /* Texture instructions are easy, since there is no pipelining
 247                  * nor VLIW to worry about. We may need to set .cont/.last
 248                  * flags. */
 249
 250                 midgard_instruction *ins = bundle->instructions[0];
 251
 252                 ins->texture.type = bundle->tag;
 253                 ins->texture.next_type = next_tag;
 254                 ins->texture.mask = ins->mask;
 255
 256                 ctx->texture_op_count--;
 257
 258                 if (ins->texture.op == TEXTURE_OP_NORMAL) {
 259                         bool continues = ctx->texture_op_count > 0;
 260                         ins->texture.cont = continues;
 261                         ins->texture.last = !continues;
 262                 } else {
 263                         ins->texture.cont = ins->texture.last = 1;
 264                 }
 265
 266                 util_dynarray_append(emission, midgard_texture_word, ins->texture);
 267                 break;
 268         }
 269
 270         default:
 271                 unreachable("Unknown midgard instruction type\n");
 272         }
 273 }