2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
27 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
28 * use scalar ALU instructions, for functional or performance reasons. To do
29 * this, we just demote vector ALU payloads to scalar. */
32 component_from_mask(unsigned mask
)
34 for (int c
= 0; c
< 8; ++c
) {
44 vector_to_scalar_source(unsigned u
, bool is_int
, bool is_full
)
46 midgard_vector_alu_src v
;
47 memcpy(&v
, &u
, sizeof(v
));
51 unsigned component
= v
.swizzle
& 3;
52 bool upper
= false; /* TODO */
54 midgard_scalar_alu_src s
= { 0 };
57 /* For a 32-bit op, just check the source half flag */
60 /* For a 16-bit op that's not subdivided, never full */
63 /* We can't do 8-bit scalar, abort! */
67 /* Component indexing takes size into account */
70 s
.component
= component
<< 1;
72 s
.component
= component
+ (upper
<< 2);
77 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
78 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
82 memcpy(&o
, &s
, sizeof(s
));
84 return o
& ((1 << 6) - 1);
87 static midgard_scalar_alu
88 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
90 bool is_int
= midgard_is_integer_op(v
.op
);
91 bool is_full
= v
.reg_mode
== midgard_reg_mode_32
;
93 /* The output component is from the mask */
94 midgard_scalar_alu s
= {
96 .src1
= vector_to_scalar_source(v
.src1
, is_int
, is_full
),
97 .src2
= vector_to_scalar_source(v
.src2
, is_int
, is_full
),
100 .output_full
= is_full
,
101 .output_component
= component_from_mask(ins
->mask
),
104 /* Full components are physically spaced out */
106 assert(s
.output_component
< 4);
107 s
.output_component
<<= 1;
110 /* Inline constant is passed along rather than trying to extract it
113 if (ins
->ssa_args
.inline_constant
) {
115 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
116 imm
|= (lower_11
>> 9) & 3;
117 imm
|= (lower_11
>> 6) & 4;
118 imm
|= (lower_11
>> 2) & 0x38;
119 imm
|= (lower_11
& 63) << 6;
128 emit_alu_bundle(compiler_context
*ctx
,
129 midgard_bundle
*bundle
,
130 struct util_dynarray
*emission
,
133 /* Emit the control word */
134 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
136 /* Next up, emit register words */
137 for (unsigned i
= 0; i
< bundle
->instruction_count
; ++i
) {
138 midgard_instruction
*ins
= bundle
->instructions
[i
];
140 /* Check if this instruction has registers */
141 if (ins
->compact_branch
|| ins
->prepacked_branch
) continue;
143 /* Otherwise, just emit the registers */
144 uint16_t reg_word
= 0;
145 memcpy(®_word
, &ins
->registers
, sizeof(uint16_t));
146 util_dynarray_append(emission
, uint16_t, reg_word
);
149 /* Now, we emit the body itself */
150 for (unsigned i
= 0; i
< bundle
->instruction_count
; ++i
) {
151 midgard_instruction
*ins
= bundle
->instructions
[i
];
153 /* Where is this body */
157 /* In case we demote to a scalar */
158 midgard_scalar_alu scalarized
;
160 if (ins
->unit
& UNITS_ANY_VECTOR
) {
161 if (ins
->alu
.reg_mode
== midgard_reg_mode_32
)
162 ins
->alu
.mask
= expand_writemask_32(ins
->mask
);
164 ins
->alu
.mask
= ins
->mask
;
166 size
= sizeof(midgard_vector_alu
);
168 } else if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
169 size
= sizeof(midgard_branch_cond
);
170 source
= &ins
->br_compact
;
171 } else if (ins
->compact_branch
) { /* misnomer */
172 size
= sizeof(midgard_branch_extended
);
173 source
= &ins
->branch_extended
;
175 size
= sizeof(midgard_scalar_alu
);
176 scalarized
= vector_to_scalar_alu(ins
->alu
, ins
);
177 source
= &scalarized
;
180 memcpy(util_dynarray_grow_bytes(emission
, 1, size
), source
, size
);
183 /* Emit padding (all zero) */
184 memset(util_dynarray_grow_bytes(emission
, 1, bundle
->padding
), 0, bundle
->padding
);
186 /* Tack on constants */
188 if (bundle
->has_embedded_constants
) {
189 util_dynarray_append(emission
, float, bundle
->constants
[0]);
190 util_dynarray_append(emission
, float, bundle
->constants
[1]);
191 util_dynarray_append(emission
, float, bundle
->constants
[2]);
192 util_dynarray_append(emission
, float, bundle
->constants
[3]);
196 /* After everything is scheduled, emit whole bundles at a time */
199 emit_binary_bundle(compiler_context
*ctx
,
200 midgard_bundle
*bundle
,
201 struct util_dynarray
*emission
,
204 int lookahead
= next_tag
<< 4;
206 switch (bundle
->tag
) {
211 emit_alu_bundle(ctx
, bundle
, emission
, lookahead
);
214 case TAG_LOAD_STORE_4
: {
215 /* One or two composing instructions */
217 uint64_t current64
, next64
= LDST_NOP
;
221 for (unsigned i
= 0; i
< bundle
->instruction_count
; ++i
) {
222 bundle
->instructions
[i
]->load_store
.mask
=
223 bundle
->instructions
[i
]->mask
;
226 memcpy(¤t64
, &bundle
->instructions
[0]->load_store
, sizeof(current64
));
228 if (bundle
->instruction_count
== 2)
229 memcpy(&next64
, &bundle
->instructions
[1]->load_store
, sizeof(next64
));
231 midgard_load_store instruction
= {
233 .next_type
= next_tag
,
238 util_dynarray_append(emission
, midgard_load_store
, instruction
);
244 case TAG_TEXTURE_4_VTX
: {
245 /* Texture instructions are easy, since there is no pipelining
246 * nor VLIW to worry about. We may need to set .cont/.last
249 midgard_instruction
*ins
= bundle
->instructions
[0];
251 ins
->texture
.type
= bundle
->tag
;
252 ins
->texture
.next_type
= next_tag
;
253 ins
->texture
.mask
= ins
->mask
;
255 ctx
->texture_op_count
--;
257 if (ins
->texture
.op
== TEXTURE_OP_NORMAL
) {
258 bool continues
= ctx
->texture_op_count
> 0;
259 ins
->texture
.cont
= continues
;
260 ins
->texture
.last
= !continues
;
262 ins
->texture
.cont
= ins
->texture
.last
= 1;
265 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
270 unreachable("Unknown midgard instruction type\n");