src/gallium/drivers/panfrost/pan_assemble.c

   1 /*
   2  * © Copyright 2018 Alyssa Rosenzweig
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24
  25 #include <stdio.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include "pan_bo.h"
  29 #include "pan_context.h"
  30 #include "pan_util.h"
  31
  32 #include "compiler/nir/nir.h"
  33 #include "nir/tgsi_to_nir.h"
  34 #include "midgard/midgard_compile.h"
  35 #include "util/u_dynarray.h"
  36
  37 #include "tgsi/tgsi_dump.h"
  38
  39 void
  40 panfrost_shader_compile(
  41                 struct panfrost_context *ctx,
  42                 struct mali_shader_meta *meta,
  43                 enum pipe_shader_ir ir_type,
  44                 const void *ir,
  45                 gl_shader_stage stage,
  46                 struct panfrost_shader_state *state,
  47                 uint64_t *outputs_written)
  48 {
  49         struct panfrost_screen *screen = pan_screen(ctx->base.screen);
  50         uint8_t *dst;
  51
  52         nir_shader *s;
  53
  54         if (ir_type == PIPE_SHADER_IR_NIR) {
  55                 s = nir_shader_clone(NULL, ir);
  56         } else {
  57                 assert (ir_type == PIPE_SHADER_IR_TGSI);
  58                 s = tgsi_to_nir(ir, ctx->base.screen);
  59         }
  60
  61         s->info.stage = stage;
  62
  63         /* Call out to Midgard compiler given the above NIR */
  64
  65         midgard_program program = {
  66                 .alpha_ref = state->alpha_state.ref_value
  67         };
  68
  69         midgard_compile_shader_nir(s, &program, false, 0, screen->gpu_id,
  70                         pan_debug & PAN_DBG_PRECOMPILE);
  71
  72         /* Prepare the compiled binary for upload */
  73         int size = program.compiled.size;
  74         dst = program.compiled.data;
  75
  76         /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
  77          * I bet someone just thought that would be a cute pun. At least,
  78          * that's how I'd do it. */
  79
  80         if (size) {
  81                 state->bo = panfrost_bo_create(screen, size, PAN_BO_EXECUTE);
  82                 memcpy(state->bo->cpu, dst, size);
  83                 meta->shader = state->bo->gpu | program.first_tag;
  84         } else {
  85                 /* no shader */
  86                 meta->shader = 0x0;
  87         }
  88
  89         util_dynarray_fini(&program.compiled);
  90
  91         /* Sysvals are prepended */
  92         program.uniform_count += program.sysval_count;
  93         state->sysval_count = program.sysval_count;
  94         memcpy(state->sysval, program.sysvals, sizeof(state->sysval[0]) * state->sysval_count);
  95
  96         meta->midgard1.uniform_count = MIN2(program.uniform_count, program.uniform_cutoff);
  97         meta->midgard1.work_count = program.work_register_count;
  98
  99         bool vertex_id = s->info.system_values_read & (1 << SYSTEM_VALUE_VERTEX_ID);
 100         bool instance_id = s->info.system_values_read & (1 << SYSTEM_VALUE_INSTANCE_ID);
 101
 102         switch (stage) {
 103         case MESA_SHADER_VERTEX:
 104                 meta->attribute_count = util_bitcount64(s->info.inputs_read);
 105                 meta->varying_count = util_bitcount64(s->info.outputs_written);
 106
 107                 if (vertex_id)
 108                         meta->attribute_count = MAX2(meta->attribute_count, PAN_VERTEX_ID + 1);
 109
 110                 if (instance_id)
 111                         meta->attribute_count = MAX2(meta->attribute_count, PAN_INSTANCE_ID + 1);
 112
 113                 break;
 114         case MESA_SHADER_FRAGMENT:
 115                 meta->attribute_count = 0;
 116                 meta->varying_count = util_bitcount64(s->info.inputs_read);
 117                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 118                         state->writes_depth = true;
 119                 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL))
 120                         state->writes_stencil = true;
 121                 break;
 122         case MESA_SHADER_COMPUTE:
 123                 /* TODO: images */
 124                 meta->attribute_count = 0;
 125                 meta->varying_count = 0;
 126                 break;
 127         default:
 128                 unreachable("Unknown shader state");
 129         }
 130
 131         state->can_discard = s->info.fs.uses_discard;
 132         state->writes_point_size = program.writes_point_size;
 133         state->reads_point_coord = false;
 134         state->helper_invocations = s->info.fs.needs_helper_invocations;
 135         state->stack_size = program.tls_size;
 136
 137         if (outputs_written)
 138                 *outputs_written = s->info.outputs_written;
 139
 140         /* Separate as primary uniform count is truncated */
 141         state->uniform_count = program.uniform_count;
 142
 143         meta->midgard1.flags_hi = 8; /* XXX */
 144
 145         unsigned default_vec1_swizzle = panfrost_get_default_swizzle(1);
 146         unsigned default_vec2_swizzle = panfrost_get_default_swizzle(2);
 147         unsigned default_vec4_swizzle = panfrost_get_default_swizzle(4);
 148
 149         /* Iterate the varyings and emit the corresponding descriptor */
 150         for (unsigned i = 0; i < meta->varying_count; ++i) {
 151                 unsigned location = program.varyings[i];
 152
 153                 /* Default to a vec4 varying */
 154                 struct mali_attr_meta v = {
 155                         .format = program.varying_type[i],
 156                         .swizzle = default_vec4_swizzle,
 157                         .unknown1 = 0x2,
 158                 };
 159
 160                 /* Check for special cases, otherwise assume general varying */
 161
 162                 if (location == VARYING_SLOT_POS) {
 163                         if (stage == MESA_SHADER_FRAGMENT)
 164                                 state->reads_frag_coord = true;
 165                         else
 166                                 v.format = MALI_VARYING_POS;
 167                 } else if (location == VARYING_SLOT_PSIZ) {
 168                         v.format = MALI_R16F;
 169                         v.swizzle = default_vec1_swizzle;
 170
 171                         state->writes_point_size = true;
 172                 } else if (location == VARYING_SLOT_PNTC) {
 173                         v.format = MALI_RG16F;
 174                         v.swizzle = default_vec2_swizzle;
 175
 176                         state->reads_point_coord = true;
 177                 } else if (location == VARYING_SLOT_FACE) {
 178                         v.format = MALI_R32I;
 179                         v.swizzle = default_vec1_swizzle;
 180
 181                         state->reads_face = true;
 182                 }
 183
 184                 state->varyings[i] = v;
 185                 state->varyings_loc[i] = location;
 186         }
 187 }