cc4822a2361536a66161e78dde525c715488767e
2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
30 #include "compiler/nir/nir.h"
31 #include "nir/tgsi_to_nir.h"
32 #include "midgard/midgard_compile.h"
33 #include "util/u_dynarray.h"
35 #include "tgsi/tgsi_dump.h"
38 panfrost_shader_compile(
39 struct panfrost_context
*ctx
,
40 struct mali_shader_meta
*meta
,
41 enum pipe_shader_ir ir_type
,
43 gl_shader_stage stage
,
44 struct panfrost_shader_state
*state
,
45 uint64_t *outputs_written
)
47 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
52 if (ir_type
== PIPE_SHADER_IR_NIR
) {
53 s
= nir_shader_clone(NULL
, ir
);
55 assert (ir_type
== PIPE_SHADER_IR_TGSI
);
56 s
= tgsi_to_nir(ir
, ctx
->base
.screen
);
59 s
->info
.stage
= stage
;
61 if (stage
== MESA_SHADER_FRAGMENT
) {
62 /* Inject the alpha test now if we need to */
64 if (state
->alpha_state
.enabled
) {
65 NIR_PASS_V(s
, nir_lower_alpha_test
, state
->alpha_state
.func
, false);
69 /* Call out to Midgard compiler given the above NIR */
71 midgard_program program
= {
72 .alpha_ref
= state
->alpha_state
.ref_value
75 midgard_compile_shader_nir(&ctx
->compiler
, s
, &program
, false);
77 /* Prepare the compiled binary for upload */
78 int size
= program
.compiled
.size
;
79 dst
= program
.compiled
.data
;
81 /* Upload the shader. The lookahead tag is ORed on as a tagged pointer.
82 * I bet someone just thought that would be a cute pun. At least,
83 * that's how I'd do it. */
85 state
->bo
= panfrost_bo_create(screen
, size
, PAN_BO_EXECUTE
);
86 memcpy(state
->bo
->cpu
, dst
, size
);
87 meta
->shader
= state
->bo
->gpu
| program
.first_tag
;
89 util_dynarray_fini(&program
.compiled
);
91 /* Sysvals are prepended */
92 program
.uniform_count
+= program
.sysval_count
;
93 state
->sysval_count
= program
.sysval_count
;
94 memcpy(state
->sysval
, program
.sysvals
, sizeof(state
->sysval
[0]) * state
->sysval_count
);
96 meta
->midgard1
.uniform_count
= MIN2(program
.uniform_count
, program
.uniform_cutoff
);
97 meta
->midgard1
.work_count
= program
.work_register_count
;
100 case MESA_SHADER_VERTEX
:
101 meta
->attribute_count
= util_bitcount64(s
->info
.inputs_read
);
102 meta
->varying_count
= util_bitcount64(s
->info
.outputs_written
);
104 case MESA_SHADER_FRAGMENT
:
105 meta
->attribute_count
= 0;
106 meta
->varying_count
= util_bitcount64(s
->info
.inputs_read
);
108 case MESA_SHADER_COMPUTE
:
110 meta
->attribute_count
= 0;
111 meta
->varying_count
= 0;
114 unreachable("Unknown shader state");
117 state
->can_discard
= s
->info
.fs
.uses_discard
;
118 state
->writes_point_size
= program
.writes_point_size
;
119 state
->reads_point_coord
= false;
120 state
->helper_invocations
= s
->info
.fs
.needs_helper_invocations
;
123 *outputs_written
= s
->info
.outputs_written
;
125 /* Separate as primary uniform count is truncated */
126 state
->uniform_count
= program
.uniform_count
;
128 meta
->midgard1
.unknown2
= 8; /* XXX */
130 unsigned default_vec1_swizzle
= panfrost_get_default_swizzle(1);
131 unsigned default_vec2_swizzle
= panfrost_get_default_swizzle(2);
132 unsigned default_vec4_swizzle
= panfrost_get_default_swizzle(4);
134 /* Iterate the varyings and emit the corresponding descriptor */
135 for (unsigned i
= 0; i
< meta
->varying_count
; ++i
) {
136 unsigned location
= program
.varyings
[i
];
138 /* Default to a vec4 varying */
139 struct mali_attr_meta v
= {
140 .format
= MALI_RGBA32F
,
141 .swizzle
= default_vec4_swizzle
,
145 /* Check for special cases, otherwise assume general varying */
147 if (location
== VARYING_SLOT_POS
) {
148 if (stage
== MESA_SHADER_FRAGMENT
)
149 state
->reads_frag_coord
= true;
151 v
.format
= MALI_VARYING_POS
;
152 } else if (location
== VARYING_SLOT_PSIZ
) {
153 v
.format
= MALI_R16F
;
154 v
.swizzle
= default_vec1_swizzle
;
156 state
->writes_point_size
= true;
157 } else if (location
== VARYING_SLOT_PNTC
) {
158 v
.format
= MALI_RG16F
;
159 v
.swizzle
= default_vec2_swizzle
;
161 state
->reads_point_coord
= true;
162 } else if (location
== VARYING_SLOT_FACE
) {
163 v
.format
= MALI_R32I
;
164 v
.swizzle
= default_vec1_swizzle
;
166 state
->reads_face
= true;
169 state
->varyings
[i
] = v
;
170 state
->varyings_loc
[i
] = location
;