2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_format.h"
31 #include "util/macros.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_memory.h"
36 #include "util/u_vbuf.h"
37 #include "util/half_float.h"
38 #include "util/u_helpers.h"
39 #include "util/u_format.h"
40 #include "util/u_prim_restart.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
49 #include "pan_tiler.h"
51 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
54 static enum mali_job_type
55 panfrost_job_type_for_pipe(enum pipe_shader_type type
) {
58 case PIPE_SHADER_VERTEX
:
59 return JOB_TYPE_VERTEX
;
61 case PIPE_SHADER_FRAGMENT
:
62 /* Note: JOB_TYPE_FRAGMENT is different.
63 * JOB_TYPE_FRAGMENT actually executes the
64 * fragment shader, but JOB_TYPE_TILER is how you
66 return JOB_TYPE_TILER
;
68 case PIPE_SHADER_GEOMETRY
:
69 return JOB_TYPE_GEOMETRY
;
71 case PIPE_SHADER_COMPUTE
:
72 return JOB_TYPE_COMPUTE
;
75 unreachable("Unsupported shader stage");
79 /* Framebuffer descriptor */
81 static struct midgard_tiler_descriptor
82 panfrost_emit_midg_tiler(
83 struct panfrost_context
*ctx
,
86 unsigned vertex_count
)
88 struct midgard_tiler_descriptor t
= {};
91 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
93 /* Compute the polygon header size and use that to offset the body */
95 unsigned header_size
= panfrost_tiler_header_size(
96 width
, height
, t
.hierarchy_mask
);
98 unsigned body_size
= panfrost_tiler_body_size(
99 width
, height
, t
.hierarchy_mask
);
103 if (t
.hierarchy_mask
) {
104 assert(ctx
->tiler_polygon_list
.bo
->size
>= (header_size
+ body_size
));
106 /* Specify allocated tiler structures */
107 t
.polygon_list
= ctx
->tiler_polygon_list
.bo
->gpu
;
109 /* Allow the entire tiler heap */
110 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
112 ctx
->tiler_heap
.bo
->gpu
+ ctx
->tiler_heap
.bo
->size
;
114 /* The tiler is disabled, so don't allow the tiler heap */
115 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
116 t
.heap_end
= t
.heap_start
;
118 /* Use a dummy polygon list */
119 t
.polygon_list
= ctx
->tiler_dummy
.bo
->gpu
;
121 /* Also, set a "tiler disabled?" flag? */
122 t
.hierarchy_mask
|= 0x1000;
125 t
.polygon_list_body
=
126 t
.polygon_list
+ header_size
;
128 t
.polygon_list_size
=
129 header_size
+ body_size
;
134 struct mali_single_framebuffer
135 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
137 unsigned width
= ctx
->pipe_framebuffer
.width
;
138 unsigned height
= ctx
->pipe_framebuffer
.height
;
140 struct mali_single_framebuffer framebuffer
= {
141 .width
= MALI_POSITIVE(width
),
142 .height
= MALI_POSITIVE(height
),
144 .format
= 0x30000000,
145 .clear_flags
= 0x1000,
146 .unknown_address_0
= ctx
->scratchpad
.bo
->gpu
,
147 .tiler
= panfrost_emit_midg_tiler(ctx
,
148 width
, height
, vertex_count
),
154 struct bifrost_framebuffer
155 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
157 unsigned width
= ctx
->pipe_framebuffer
.width
;
158 unsigned height
= ctx
->pipe_framebuffer
.height
;
160 struct bifrost_framebuffer framebuffer
= {
161 .unk0
= 0x1e5, /* 1e4 if no spill */
162 .width1
= MALI_POSITIVE(width
),
163 .height1
= MALI_POSITIVE(height
),
164 .width2
= MALI_POSITIVE(width
),
165 .height2
= MALI_POSITIVE(height
),
169 .rt_count_1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.nr_cbufs
),
174 .scratchpad
= ctx
->scratchpad
.bo
->gpu
,
175 .tiler
= panfrost_emit_midg_tiler(ctx
,
176 width
, height
, vertex_count
)
182 /* Are we currently rendering to the screen (rather than an FBO)? */
185 panfrost_is_scanout(struct panfrost_context
*ctx
)
187 /* If there is no color buffer, it's an FBO */
188 if (ctx
->pipe_framebuffer
.nr_cbufs
!= 1)
191 /* If we're too early that no framebuffer was sent, it's scanout */
192 if (!ctx
->pipe_framebuffer
.cbufs
[0])
195 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
196 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
197 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
202 struct pipe_context
*pipe
,
204 const union pipe_color_union
*color
,
205 double depth
, unsigned stencil
)
207 struct panfrost_context
*ctx
= pan_context(pipe
);
208 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
210 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
214 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
216 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
220 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
222 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
226 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
, bool skippable
)
228 /* Skip the attach if we can */
230 if (skippable
&& ctx
->payload_vertex
.postfix
.framebuffer
) {
231 assert(ctx
->payload_tiler
.postfix
.framebuffer
);
235 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
236 mali_ptr framebuffer
= screen
->require_sfbd
?
237 panfrost_attach_vt_sfbd(ctx
) :
238 panfrost_attach_vt_mfbd(ctx
);
240 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
241 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
244 /* Reset per-frame context, called on context initialisation as well as after
245 * flushing a frame */
248 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
250 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
252 if (screen
->require_sfbd
)
253 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
255 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
257 /* The reference is now invalid */
258 ctx
->payload_vertex
.postfix
.framebuffer
= 0;
259 ctx
->payload_tiler
.postfix
.framebuffer
= 0;
262 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
265 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
268 /* In practice, every field of these payloads should be configurable
269 * arbitrarily, which means these functions are basically catch-all's for
270 * as-of-yet unwavering unknowns */
273 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
275 /* 0x2 bit clear on 32-bit T6XX */
277 struct midgard_payload_vertex_tiler payload
= {
278 .gl_enables
= 0x4 | 0x2,
281 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
285 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
287 struct midgard_payload_vertex_tiler payload
= {
289 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
293 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
297 translate_tex_wrap(enum pipe_tex_wrap w
)
300 case PIPE_TEX_WRAP_REPEAT
:
301 return MALI_WRAP_REPEAT
;
303 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
304 return MALI_WRAP_CLAMP_TO_EDGE
;
306 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
307 return MALI_WRAP_CLAMP_TO_BORDER
;
309 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
310 return MALI_WRAP_MIRRORED_REPEAT
;
313 unreachable("Invalid wrap");
318 translate_tex_filter(enum pipe_tex_filter f
)
321 case PIPE_TEX_FILTER_NEAREST
:
324 case PIPE_TEX_FILTER_LINEAR
:
328 unreachable("Invalid filter");
333 translate_mip_filter(enum pipe_tex_mipfilter f
)
335 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
339 panfrost_translate_compare_func(enum pipe_compare_func in
)
342 case PIPE_FUNC_NEVER
:
343 return MALI_FUNC_NEVER
;
346 return MALI_FUNC_LESS
;
348 case PIPE_FUNC_EQUAL
:
349 return MALI_FUNC_EQUAL
;
351 case PIPE_FUNC_LEQUAL
:
352 return MALI_FUNC_LEQUAL
;
354 case PIPE_FUNC_GREATER
:
355 return MALI_FUNC_GREATER
;
357 case PIPE_FUNC_NOTEQUAL
:
358 return MALI_FUNC_NOTEQUAL
;
360 case PIPE_FUNC_GEQUAL
:
361 return MALI_FUNC_GEQUAL
;
363 case PIPE_FUNC_ALWAYS
:
364 return MALI_FUNC_ALWAYS
;
367 unreachable("Invalid func");
372 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
375 case PIPE_FUNC_NEVER
:
376 return MALI_ALT_FUNC_NEVER
;
379 return MALI_ALT_FUNC_LESS
;
381 case PIPE_FUNC_EQUAL
:
382 return MALI_ALT_FUNC_EQUAL
;
384 case PIPE_FUNC_LEQUAL
:
385 return MALI_ALT_FUNC_LEQUAL
;
387 case PIPE_FUNC_GREATER
:
388 return MALI_ALT_FUNC_GREATER
;
390 case PIPE_FUNC_NOTEQUAL
:
391 return MALI_ALT_FUNC_NOTEQUAL
;
393 case PIPE_FUNC_GEQUAL
:
394 return MALI_ALT_FUNC_GEQUAL
;
396 case PIPE_FUNC_ALWAYS
:
397 return MALI_ALT_FUNC_ALWAYS
;
400 unreachable("Invalid alt func");
405 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
408 case PIPE_STENCIL_OP_KEEP
:
409 return MALI_STENCIL_KEEP
;
411 case PIPE_STENCIL_OP_ZERO
:
412 return MALI_STENCIL_ZERO
;
414 case PIPE_STENCIL_OP_REPLACE
:
415 return MALI_STENCIL_REPLACE
;
417 case PIPE_STENCIL_OP_INCR
:
418 return MALI_STENCIL_INCR
;
420 case PIPE_STENCIL_OP_DECR
:
421 return MALI_STENCIL_DECR
;
423 case PIPE_STENCIL_OP_INCR_WRAP
:
424 return MALI_STENCIL_INCR_WRAP
;
426 case PIPE_STENCIL_OP_DECR_WRAP
:
427 return MALI_STENCIL_DECR_WRAP
;
429 case PIPE_STENCIL_OP_INVERT
:
430 return MALI_STENCIL_INVERT
;
433 unreachable("Invalid stencil op");
438 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
440 out
->ref
= 0; /* Gallium gets it from elsewhere */
442 out
->mask
= in
->valuemask
;
443 out
->func
= panfrost_translate_compare_func(in
->func
);
444 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
445 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
446 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
450 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
452 struct mali_shader_meta shader
= {
453 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
455 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
456 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
459 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
460 * required (independent of 32-bit/64-bit descriptors), or why it's not
461 * used on later GPU revisions. Otherwise, all shader jobs fault on
462 * these earlier chips (perhaps this is a chicken bit of some kind).
463 * More investigation is needed. */
466 shader
.unknown2_4
|= 0x10;
469 struct pipe_stencil_state default_stencil
= {
471 .func
= PIPE_FUNC_ALWAYS
,
472 .fail_op
= MALI_STENCIL_KEEP
,
473 .zfail_op
= MALI_STENCIL_KEEP
,
474 .zpass_op
= MALI_STENCIL_KEEP
,
479 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
480 shader
.stencil_mask_front
= default_stencil
.writemask
;
482 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
483 shader
.stencil_mask_back
= default_stencil
.writemask
;
485 if (default_stencil
.enabled
)
486 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
488 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
491 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
492 * graphics command stream. It should be called once per draw, accordding to
493 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
494 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
497 struct panfrost_transfer
498 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
500 struct mali_job_descriptor_header job
= {
501 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
502 .job_descriptor_size
= 1,
505 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
507 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
508 memcpy(transfer
.cpu
, &job
, sizeof(job
));
509 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
514 panfrost_emit_varyings(
515 struct panfrost_context
*ctx
,
516 union mali_attr
*slot
,
520 /* Fill out the descriptor */
521 slot
->stride
= stride
;
522 slot
->size
= stride
* count
;
523 slot
->shift
= slot
->extra_flags
= 0;
525 struct panfrost_transfer transfer
=
526 panfrost_allocate_transient(ctx
, slot
->size
);
528 slot
->elements
= transfer
.gpu
| MALI_ATTR_LINEAR
;
534 panfrost_emit_point_coord(union mali_attr
*slot
)
536 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
537 slot
->stride
= slot
->size
= slot
->shift
= slot
->extra_flags
= 0;
541 panfrost_emit_varying_descriptor(
542 struct panfrost_context
*ctx
,
543 unsigned vertex_count
)
545 /* Load the shaders */
547 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
548 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
549 unsigned int num_gen_varyings
= 0;
551 /* Allocate the varying descriptor */
553 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
554 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
556 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
560 * Assign ->src_offset now that we know about all the general purpose
561 * varyings that will be used by the fragment and vertex shaders.
563 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
565 * General purpose varyings have ->index set to 0, skip other
568 if (vs
->varyings
[i
].index
)
571 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
574 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
577 /* If we have a point sprite replacement, handle that here. We
578 * have to translate location first. TODO: Flip y in shader.
579 * We're already keying ... just time crunch .. */
581 unsigned loc
= fs
->varyings_loc
[i
];
583 (loc
>= VARYING_SLOT_VAR0
) ? (loc
- VARYING_SLOT_VAR0
) :
584 (loc
== VARYING_SLOT_PNTC
) ? 8 :
587 if (~pnt_loc
&& fs
->point_sprite_mask
& (1 << pnt_loc
)) {
588 /* gl_PointCoord index by convention */
589 fs
->varyings
[i
].index
= 3;
590 fs
->reads_point_coord
= true;
592 /* Swizzle out the z/w to 0/1 */
593 fs
->varyings
[i
].format
= MALI_RG16F
;
594 fs
->varyings
[i
].swizzle
=
595 panfrost_get_default_swizzle(2);
600 if (fs
->varyings
[i
].index
)
604 * Re-use the VS general purpose varying pos if it exists,
605 * create a new one otherwise.
607 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
608 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
612 if (j
< vs
->tripipe
->varying_count
)
613 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
615 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
618 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
619 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
621 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
622 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
624 /* Buffer indices must be in this order per our convention */
625 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
628 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
631 /* fp32 vec4 gl_Position */
632 ctx
->payload_tiler
.postfix
.position_varying
=
633 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
634 sizeof(float) * 4, vertex_count
);
637 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
638 /* fp16 vec1 gl_PointSize */
639 ctx
->payload_tiler
.primitive_size
.pointer
=
640 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
644 if (fs
->reads_point_coord
) {
645 /* Special descriptor */
646 panfrost_emit_point_coord(&varyings
[idx
++]);
649 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
650 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
651 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
655 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
657 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
658 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
660 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
664 panfrost_writes_point_size(struct panfrost_context
*ctx
)
667 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
669 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
672 /* Stage the attribute descriptors so we can adjust src_offset
673 * to let BOs align nicely */
676 panfrost_stage_attributes(struct panfrost_context
*ctx
)
678 struct panfrost_vertex_state
*so
= ctx
->vertex
;
680 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
681 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
682 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
684 /* Copy as-is for the first pass */
685 memcpy(target
, so
->hw
, sz
);
687 /* Fixup offsets for the second pass. Recall that the hardware
688 * calculates attribute addresses as:
690 * addr = base + (stride * vtx) + src_offset;
692 * However, on Mali, base must be aligned to 64-bytes, so we
695 * base' = base & ~63 = base - (base & 63)
697 * To compensate when using base' (see emit_vertex_data), we have
698 * to adjust src_offset by the masked off piece:
700 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
701 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
702 * = base + (stride * vtx) + src_offset
708 unsigned start
= ctx
->payload_vertex
.draw_start
;
710 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
711 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
712 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
713 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
715 /* Adjust by the masked off bits of the offset */
716 target
[i
].src_offset
+= (addr
& 63);
718 /* Also, somewhat obscurely per-instance data needs to be
719 * offset in response to a delayed start in an indexed draw */
721 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
722 target
[i
].src_offset
-= buf
->stride
* start
;
728 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
732 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
734 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
736 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
739 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
740 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
742 struct panfrost_transfer transfer
=
743 panfrost_allocate_transient(ctx
, transfer_size
);
745 struct mali_sampler_descriptor
*desc
=
746 (struct mali_sampler_descriptor
*) transfer
.cpu
;
748 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
749 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
751 upload
= transfer
.gpu
;
754 if (t
== PIPE_SHADER_FRAGMENT
)
755 ctx
->payload_tiler
.postfix
.sampler_descriptor
= upload
;
756 else if (t
== PIPE_SHADER_VERTEX
)
757 ctx
->payload_vertex
.postfix
.sampler_descriptor
= upload
;
764 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
, bool manual_stride
)
766 /* TODO: other linear depth textures */
767 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
769 unsigned usage2_layout
= 0x10;
771 switch (rsrc
->layout
) {
773 usage2_layout
|= 0x8 | 0x4;
776 usage2_layout
|= 0x1;
779 usage2_layout
|= is_depth
? 0x1 : 0x2;
787 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
789 return usage2_layout
;
794 struct panfrost_context
*ctx
,
795 struct panfrost_sampler_view
*view
)
800 struct pipe_sampler_view
*pview
= &view
->base
;
801 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
803 /* Do we interleave an explicit stride with every element? */
805 bool has_manual_stride
= view
->manual_stride
;
807 /* For easy access */
809 assert(pview
->target
!= PIPE_BUFFER
);
810 unsigned first_level
= pview
->u
.tex
.first_level
;
811 unsigned last_level
= pview
->u
.tex
.last_level
;
812 unsigned first_layer
= pview
->u
.tex
.first_layer
;
813 unsigned last_layer
= pview
->u
.tex
.last_layer
;
815 /* Lower-bit is set when sampling from colour AFBC */
816 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
817 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
818 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
820 /* Add the BO to the job so it's retained until the job is done. */
821 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
822 panfrost_job_add_bo(job
, rsrc
->bo
);
824 /* Add the usage flags in, since they can change across the CSO
825 * lifetime due to layout switches */
827 view
->hw
.format
.usage2
= panfrost_layout_for_texture(rsrc
, has_manual_stride
);
829 /* Inject the addresses in, interleaving mip levels, cube faces, and
830 * strides in that order */
834 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
835 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
837 view
->hw
.payload
[idx
++] =
838 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
840 if (has_manual_stride
) {
841 view
->hw
.payload
[idx
++] =
842 rsrc
->slices
[l
].stride
;
847 return panfrost_upload_transient(ctx
, &view
->hw
,
848 sizeof(struct mali_texture_descriptor
));
852 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
854 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
855 mali_ptr trampoline
= 0;
857 if (ctx
->sampler_view_count
[t
]) {
858 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
860 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
862 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
864 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
867 if (t
== PIPE_SHADER_FRAGMENT
)
868 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
869 else if (t
== PIPE_SHADER_VERTEX
)
870 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
876 struct sysval_uniform
{
884 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
885 struct sysval_uniform
*uniform
)
887 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
889 uniform
->f
[0] = vp
->scale
[0];
890 uniform
->f
[1] = vp
->scale
[1];
891 uniform
->f
[2] = vp
->scale
[2];
894 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
895 struct sysval_uniform
*uniform
)
897 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
899 uniform
->f
[0] = vp
->translate
[0];
900 uniform
->f
[1] = vp
->translate
[1];
901 uniform
->f
[2] = vp
->translate
[2];
904 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
905 enum pipe_shader_type st
,
906 unsigned int sysvalid
,
907 struct sysval_uniform
*uniform
)
909 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
910 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
911 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
912 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
915 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
918 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
919 tex
->u
.tex
.first_level
);
922 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
923 tex
->u
.tex
.first_level
);
926 uniform
->i
[dim
] = tex
->texture
->array_size
;
929 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
930 struct panfrost_shader_state
*ss
,
931 enum pipe_shader_type st
)
933 struct sysval_uniform
*uniforms
= (void *)buf
;
935 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
936 int sysval
= ss
->sysval
[i
];
938 switch (PAN_SYSVAL_TYPE(sysval
)) {
939 case PAN_SYSVAL_VIEWPORT_SCALE
:
940 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
942 case PAN_SYSVAL_VIEWPORT_OFFSET
:
943 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
945 case PAN_SYSVAL_TEXTURE_SIZE
:
946 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
956 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
958 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
959 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
962 return rsrc
->bo
->cpu
;
963 else if (cb
->user_buffer
)
964 return cb
->user_buffer
;
966 unreachable("No constant buffer");
970 panfrost_map_constant_buffer_gpu(
971 struct panfrost_context
*ctx
,
972 struct panfrost_constant_buffer
*buf
,
975 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
976 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
979 return rsrc
->bo
->gpu
;
980 else if (cb
->user_buffer
)
981 return panfrost_upload_transient(ctx
, cb
->user_buffer
, cb
->buffer_size
);
983 unreachable("No constant buffer");
986 /* Compute number of UBOs active (more specifically, compute the highest UBO
987 * number addressable -- if there are gaps, include them in the count anyway).
988 * We always include UBO #0 in the count, since we *need* uniforms enabled for
992 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
994 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
995 return 32 - __builtin_clz(mask
);
998 /* Fixes up a shader state with current state, returning a GPU address to the
1002 panfrost_patch_shader_state(
1003 struct panfrost_context
*ctx
,
1004 struct panfrost_shader_state
*ss
,
1005 enum pipe_shader_type stage
,
1008 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
1009 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
1011 ss
->tripipe
->midgard1
.flags
= 0x220;
1013 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
1014 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
1016 /* We can't reuse over frames; that's not safe. The descriptor must be
1017 * transient uploaded */
1019 if (should_upload
) {
1020 return panfrost_upload_transient(ctx
,
1022 sizeof(struct mali_shader_meta
));
1025 /* If we don't need an upload, don't bother */
1030 /* Go through dirty flags and actualise them in the cmdstream. */
1033 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1035 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1036 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
1038 panfrost_attach_vt_framebuffer(ctx
, true);
1040 if (with_vertex_data
) {
1041 panfrost_emit_vertex_data(job
);
1043 /* Varyings emitted for -all- geometry */
1044 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
1045 panfrost_emit_varying_descriptor(ctx
, total_count
);
1048 bool msaa
= ctx
->rasterizer
->base
.multisample
;
1050 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1051 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1053 /* TODO: Sample size */
1054 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1055 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1058 panfrost_job_set_requirements(ctx
, job
);
1060 if (ctx
->occlusion_query
) {
1061 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1062 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1065 /* TODO: Does it make sense to dirty track VS? We need the transient
1067 ctx
->dirty
|= PAN_DIRTY_VS
;
1068 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1071 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1073 ctx
->payload_vertex
.postfix
._shader_upper
=
1074 panfrost_patch_shader_state(ctx
, vs
, PIPE_SHADER_VERTEX
, true) >> 4;
1077 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1078 /* Check if we need to link the gl_PointSize varying */
1079 if (!panfrost_writes_point_size(ctx
)) {
1080 /* If the size is constant, write it out. Otherwise,
1081 * don't touch primitive_size (since we would clobber
1082 * the pointer there) */
1084 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1088 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1090 ctx
->dirty
|= PAN_DIRTY_FS
;
1092 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1094 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1096 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
1098 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1101 COPY(attribute_count
);
1102 COPY(varying_count
);
1103 COPY(texture_count
);
1104 COPY(sampler_count
);
1105 COPY(sampler_count
);
1106 COPY(midgard1
.uniform_count
);
1107 COPY(midgard1
.uniform_buffer_count
);
1108 COPY(midgard1
.work_count
);
1109 COPY(midgard1
.flags
);
1110 COPY(midgard1
.unknown2
);
1114 /* Get blending setup */
1115 struct panfrost_blend_final blend
=
1116 panfrost_get_blend_for_context(ctx
, 0);
1118 /* If there is a blend shader, work registers are shared */
1120 if (blend
.is_shader
)
1121 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1123 /* Set late due to depending on render state */
1124 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
1126 /* Depending on whether it's legal to in the given shader, we
1127 * try to enable early-z testing (or forward-pixel kill?) */
1129 if (!variant
->can_discard
)
1130 flags
|= MALI_EARLY_Z
;
1132 /* Any time texturing is used, derivatives are implicitly
1133 * calculated, so we need to enable helper invocations */
1135 if (ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
])
1136 flags
|= MALI_HELPER_INVOCATIONS
;
1138 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1140 /* Assign the stencil refs late */
1142 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
1143 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
1144 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
1146 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
1147 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
1149 /* CAN_DISCARD should be set if the fragment shader possibly
1150 * contains a 'discard' instruction. It is likely this is
1151 * related to optimizations related to forward-pixel kill, as
1152 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1153 * thing?" by Peter Harris
1156 if (variant
->can_discard
) {
1157 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1158 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1161 /* Check if we're using the default blend descriptor (fast path) */
1165 (blend
.equation
.equation
->rgb_mode
== 0x122) &&
1166 (blend
.equation
.equation
->alpha_mode
== 0x122) &&
1167 (blend
.equation
.equation
->color_mask
== 0xf);
1169 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1170 * *also* copied to the blend_meta appended (by convention),
1171 * but this is the field actually read by the hardware. (Or
1172 * maybe both are read...?) */
1174 if (blend
.is_shader
) {
1175 ctx
->fragment_shader_core
.blend
.shader
=
1178 ctx
->fragment_shader_core
.blend
.shader
= 0;
1181 if (screen
->require_sfbd
) {
1182 /* When only a single render target platform is used, the blend
1183 * information is inside the shader meta itself. We
1184 * additionally need to signal CAN_DISCARD for nontrivial blend
1185 * modes (so we're able to read back the destination buffer) */
1187 if (!blend
.is_shader
) {
1188 ctx
->fragment_shader_core
.blend
.equation
=
1189 *blend
.equation
.equation
;
1190 ctx
->fragment_shader_core
.blend
.constant
=
1191 blend
.equation
.constant
;
1195 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1199 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1200 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1201 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1203 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1205 if (!screen
->require_sfbd
) {
1206 /* Additional blend descriptor tacked on for jobs using MFBD */
1208 unsigned blend_count
= 0x200;
1210 if (blend
.is_shader
) {
1211 /* For a blend shader, the bottom nibble corresponds to
1212 * the number of work registers used, which signals the
1213 * -existence- of a blend shader */
1215 assert(blend
.shader
.work_count
>= 2);
1216 blend_count
|= MIN2(blend
.shader
.work_count
, 3);
1218 /* Otherwise, the bottom bit simply specifies if
1219 * blending (anything other than REPLACE) is enabled */
1226 struct midgard_blend_rt rts
[4];
1228 for (unsigned i
= 0; i
< ctx
->pipe_framebuffer
.nr_cbufs
; ++i
) {
1230 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1231 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1232 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1234 rts
[i
].flags
= blend_count
;
1237 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1239 if (!ctx
->blend
->base
.dither
)
1240 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1242 /* TODO: sRGB in blend shaders is currently
1243 * unimplemented. Contact me (Alyssa) if you're
1244 * interested in working on this. We have
1245 * native Midgard ops for helping here, but
1246 * they're not well-understood yet. */
1248 assert(!(is_srgb
&& blend
.is_shader
));
1250 if (blend
.is_shader
) {
1251 rts
[i
].blend
.shader
= blend
.shader
.gpu
;
1253 rts
[i
].blend
.equation
= *blend
.equation
.equation
;
1254 rts
[i
].blend
.constant
= blend
.equation
.constant
;
1258 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1262 /* We stage to transient, so always dirty.. */
1263 panfrost_stage_attributes(ctx
);
1265 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1266 panfrost_upload_sampler_descriptors(ctx
);
1268 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1269 panfrost_upload_texture_descriptors(ctx
);
1271 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1273 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1274 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1276 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1277 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1278 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1280 /* Uniforms are implicitly UBO #0 */
1281 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1283 /* Allocate room for the sysval and the uniforms */
1284 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1285 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1286 size_t size
= sys_size
+ uniform_size
;
1287 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1289 /* Upload sysvals requested by the shader */
1290 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1292 /* Upload uniforms */
1294 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1295 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1298 int uniform_count
= 0;
1300 struct mali_vertex_tiler_postfix
*postfix
;
1303 case PIPE_SHADER_VERTEX
:
1304 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1305 postfix
= &ctx
->payload_vertex
.postfix
;
1308 case PIPE_SHADER_FRAGMENT
:
1309 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1310 postfix
= &ctx
->payload_tiler
.postfix
;
1314 unreachable("Invalid shader stage\n");
1317 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1320 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1321 assert(ubo_count
>= 1);
1323 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1324 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1326 /* Upload uniforms as a UBO */
1327 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1328 ubos
[0].ptr
= transfer
.gpu
>> 2;
1330 /* The rest are honest-to-goodness UBOs */
1332 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1333 size_t sz
= buf
->cb
[ubo
].buffer_size
;
1335 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1336 bool empty
= sz
== 0;
1338 if (!enabled
|| empty
) {
1339 /* Stub out disabled UBOs to catch accesses */
1342 ubos
[ubo
].ptr
= 0xDEAD0000;
1346 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1348 unsigned bytes_per_field
= 16;
1349 unsigned aligned
= ALIGN_POT(sz
, bytes_per_field
);
1350 unsigned fields
= aligned
/ bytes_per_field
;
1352 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1353 ubos
[ubo
].ptr
= gpu
>> 2;
1356 mali_ptr ubufs
= panfrost_upload_transient(ctx
, ubos
, sz
);
1357 postfix
->uniforms
= transfer
.gpu
;
1358 postfix
->uniform_buffers
= ubufs
;
1360 buf
->dirty_mask
= 0;
1363 /* TODO: Upload the viewport somewhere more appropriate */
1365 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1366 * (somewhat) asymmetric ints. */
1367 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1369 struct mali_viewport view
= {
1370 /* By default, do no viewport clipping, i.e. clip to (-inf,
1371 * inf) in each direction. Clipping to the viewport in theory
1372 * should work, but in practice causes issues when we're not
1373 * explicitly trying to scissor */
1375 .clip_minx
= -INFINITY
,
1376 .clip_miny
= -INFINITY
,
1377 .clip_maxx
= INFINITY
,
1378 .clip_maxy
= INFINITY
,
1384 /* Always scissor to the viewport by default. */
1385 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1386 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1388 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1389 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1391 /* Apply the scissor test */
1393 unsigned minx
, miny
, maxx
, maxy
;
1395 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1396 minx
= MAX2(ss
->minx
, vp_minx
);
1397 miny
= MAX2(ss
->miny
, vp_miny
);
1398 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1399 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1407 /* Hardware needs the min/max to be strictly ordered, so flip if we
1408 * need to. The viewport transformation in the vertex shader will
1409 * handle the negatives if we don't */
1423 /* Clamp everything positive, just in case */
1425 maxx
= MAX2(0, maxx
);
1426 maxy
= MAX2(0, maxy
);
1427 minx
= MAX2(0, minx
);
1428 miny
= MAX2(0, miny
);
1430 /* Clamp to the framebuffer size as a last check */
1432 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1433 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1435 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1436 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1438 /* Update the job, unless we're doing wallpapering (whose lack of
1439 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1440 * just... be faster :) */
1442 if (!ctx
->wallpaper_batch
)
1443 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1447 view
.viewport0
[0] = minx
;
1448 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1450 view
.viewport0
[1] = miny
;
1451 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1453 ctx
->payload_tiler
.postfix
.viewport
=
1454 panfrost_upload_transient(ctx
,
1456 sizeof(struct mali_viewport
));
1461 /* Corresponds to exactly one draw, but does not submit anything */
1464 panfrost_queue_draw(struct panfrost_context
*ctx
)
1466 /* Handle dirty flags now */
1467 panfrost_emit_for_draw(ctx
, true);
1469 /* If rasterizer discard is enable, only submit the vertex */
1471 bool rasterizer_discard
= ctx
->rasterizer
1472 && ctx
->rasterizer
->base
.rasterizer_discard
;
1474 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1475 struct panfrost_transfer tiler
;
1477 if (!rasterizer_discard
)
1478 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1480 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1482 if (rasterizer_discard
)
1483 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1484 else if (ctx
->wallpaper_batch
)
1485 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1487 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1490 /* The entire frame is in memory -- send it off to the kernel! */
1493 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1494 struct pipe_fence_handle
**fence
,
1495 struct panfrost_job
*job
)
1497 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1498 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1502 panfrost_job_submit(ctx
, job
);
1504 /* If visual, we can stall a frame */
1506 if (!flush_immediate
)
1507 panfrost_drm_force_flush_fragment(ctx
, fence
);
1509 screen
->last_fragment_flushed
= false;
1510 screen
->last_job
= job
;
1512 /* If readback, flush now (hurts the pipelined performance) */
1513 if (flush_immediate
)
1514 panfrost_drm_force_flush_fragment(ctx
, fence
);
1519 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1521 struct panfrost_context
*ctx
= pan_context(pipe
);
1523 /* Nothing to reload? TODO: MRT wallpapers */
1524 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1527 /* Check if the buffer has any content on it worth preserving */
1529 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1530 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1531 unsigned level
= surf
->u
.tex
.level
;
1533 if (!rsrc
->slices
[level
].initialized
)
1536 /* Save the batch */
1537 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1539 ctx
->wallpaper_batch
= batch
;
1540 panfrost_blit_wallpaper(ctx
);
1541 ctx
->wallpaper_batch
= NULL
;
1546 struct pipe_context
*pipe
,
1547 struct pipe_fence_handle
**fence
,
1550 struct panfrost_context
*ctx
= pan_context(pipe
);
1551 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1553 /* Nothing to do! */
1554 if (!job
->last_job
.gpu
&& !job
->clear
) return;
1557 panfrost_draw_wallpaper(&ctx
->base
);
1559 /* Whether to stall the pipeline for immediately correct results. Since
1560 * pipelined rendering is quite broken right now (to be fixed by the
1561 * panfrost_job refactor, just take the perf hit for correctness) */
1562 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1564 /* Submit the frame itself */
1565 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1567 /* Prepare for the next frame */
1568 panfrost_invalidate_frame(ctx
);
1571 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1574 g2m_draw_mode(enum pipe_prim_type mode
)
1577 DEFINE_CASE(POINTS
);
1579 DEFINE_CASE(LINE_LOOP
);
1580 DEFINE_CASE(LINE_STRIP
);
1581 DEFINE_CASE(TRIANGLES
);
1582 DEFINE_CASE(TRIANGLE_STRIP
);
1583 DEFINE_CASE(TRIANGLE_FAN
);
1585 DEFINE_CASE(QUAD_STRIP
);
1586 DEFINE_CASE(POLYGON
);
1589 unreachable("Invalid draw mode");
1596 panfrost_translate_index_size(unsigned size
)
1600 return MALI_DRAW_INDEXED_UINT8
;
1603 return MALI_DRAW_INDEXED_UINT16
;
1606 return MALI_DRAW_INDEXED_UINT32
;
1609 unreachable("Invalid index size");
1613 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1614 * good for the duration of the draw (transient), could last longer */
1617 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1619 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1621 off_t offset
= info
->start
* info
->index_size
;
1622 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1624 if (!info
->has_user_indices
) {
1625 /* Only resources can be directly mapped */
1626 panfrost_job_add_bo(batch
, rsrc
->bo
);
1627 return rsrc
->bo
->gpu
+ offset
;
1629 /* Otherwise, we need to upload to transient memory */
1630 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1631 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1636 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1638 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1640 /* Check if we're scissoring at all */
1642 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1645 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1650 struct pipe_context
*pipe
,
1651 const struct pipe_draw_info
*info
)
1653 struct panfrost_context
*ctx
= pan_context(pipe
);
1655 /* First of all, check the scissor to see if anything is drawn at all.
1656 * If it's not, we drop the draw (mostly a conformance issue;
1657 * well-behaved apps shouldn't hit this) */
1659 if (panfrost_scissor_culls_everything(ctx
))
1662 ctx
->payload_vertex
.draw_start
= info
->start
;
1663 ctx
->payload_tiler
.draw_start
= info
->start
;
1665 int mode
= info
->mode
;
1667 /* Fallback unsupported restart index */
1668 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1670 if (info
->primitive_restart
&& info
->index_size
1671 && info
->restart_index
!= primitive_index
) {
1672 util_draw_vbo_without_prim_restart(pipe
, info
);
1676 /* Fallback for unsupported modes */
1678 if (!(ctx
->draw_modes
& (1 << mode
))) {
1679 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1680 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1682 if (info
->count
< 4) {
1683 /* Degenerate case? */
1687 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1688 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1693 /* Now that we have a guaranteed terminating path, find the job.
1694 * Assignment commented out to prevent unused warning */
1696 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1698 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1700 ctx
->vertex_count
= info
->count
;
1701 ctx
->instance_count
= info
->instance_count
;
1703 /* For non-indexed draws, they're the same */
1704 unsigned vertex_count
= ctx
->vertex_count
;
1706 unsigned draw_flags
= 0;
1708 /* The draw flags interpret how primitive size is interpreted */
1710 if (panfrost_writes_point_size(ctx
))
1711 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1713 if (info
->primitive_restart
)
1714 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1716 /* For higher amounts of vertices (greater than what fits in a 16-bit
1717 * short), the other value is needed, otherwise there will be bizarre
1718 * rendering artefacts. It's not clear what these values mean yet. This
1719 * change is also needed for instancing and sometimes points (perhaps
1720 * related to dynamically setting gl_PointSize) */
1722 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1723 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1724 bool instanced
= ctx
->instance_count
> 1;
1726 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1728 /* This doesn't make much sense */
1729 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1730 draw_flags
|= 0x800;
1733 if (info
->index_size
) {
1734 /* Calculate the min/max index used so we can figure out how
1735 * many times to invoke the vertex shader */
1737 /* Fetch / calculate index bounds */
1738 unsigned min_index
= 0, max_index
= 0;
1740 if (info
->max_index
== ~0u) {
1741 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1743 min_index
= info
->min_index
;
1744 max_index
= info
->max_index
;
1747 /* Use the corresponding values */
1748 vertex_count
= max_index
- min_index
+ 1;
1749 ctx
->payload_vertex
.draw_start
= min_index
;
1750 ctx
->payload_tiler
.draw_start
= min_index
;
1752 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1753 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1755 //assert(!info->restart_index); /* TODO: Research */
1756 assert(!info
->index_bias
);
1758 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1759 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1761 /* Index count == vertex count, if no indexing is applied, as
1762 * if it is internally indexed in the expected order */
1764 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1765 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1767 /* Reverse index state */
1768 ctx
->payload_tiler
.prefix
.indices
= (u64
) NULL
;
1771 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1772 * vertex_count, 1) */
1774 panfrost_pack_work_groups_fused(
1775 &ctx
->payload_vertex
.prefix
,
1776 &ctx
->payload_tiler
.prefix
,
1777 1, vertex_count
, info
->instance_count
,
1780 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1782 /* Encode the padded vertex count */
1784 if (info
->instance_count
> 1) {
1785 /* Triangles have non-even vertex counts so they change how
1786 * padding works internally */
1789 mode
== PIPE_PRIM_TRIANGLES
||
1790 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1791 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1793 struct pan_shift_odd so
=
1794 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1796 ctx
->payload_vertex
.instance_shift
= so
.shift
;
1797 ctx
->payload_tiler
.instance_shift
= so
.shift
;
1799 ctx
->payload_vertex
.instance_odd
= so
.odd
;
1800 ctx
->payload_tiler
.instance_odd
= so
.odd
;
1802 ctx
->padded_count
= pan_expand_shift_odd(so
);
1804 ctx
->padded_count
= ctx
->vertex_count
;
1806 /* Reset instancing state */
1807 ctx
->payload_vertex
.instance_shift
= 0;
1808 ctx
->payload_vertex
.instance_odd
= 0;
1809 ctx
->payload_tiler
.instance_shift
= 0;
1810 ctx
->payload_tiler
.instance_odd
= 0;
1813 /* Fire off the draw itself */
1814 panfrost_queue_draw(ctx
);
1820 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1826 panfrost_create_rasterizer_state(
1827 struct pipe_context
*pctx
,
1828 const struct pipe_rasterizer_state
*cso
)
1830 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1834 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1835 so
->tiler_gl_enables
= 0x7;
1838 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1840 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1841 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1843 if (cso
->cull_face
& PIPE_FACE_BACK
)
1844 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1850 panfrost_bind_rasterizer_state(
1851 struct pipe_context
*pctx
,
1854 struct panfrost_context
*ctx
= pan_context(pctx
);
1856 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1860 ctx
->rasterizer
= hwcso
;
1861 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1863 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1864 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1866 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1867 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1869 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1871 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1872 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1874 /* Point sprites are emulated */
1876 struct panfrost_shader_state
*variant
=
1877 ctx
->fs
? &ctx
->fs
->variants
[ctx
->fs
->active_variant
] : NULL
;
1879 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1880 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
1884 panfrost_create_vertex_elements_state(
1885 struct pipe_context
*pctx
,
1886 unsigned num_elements
,
1887 const struct pipe_vertex_element
*elements
)
1889 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1891 so
->num_elements
= num_elements
;
1892 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1894 for (int i
= 0; i
< num_elements
; ++i
) {
1895 so
->hw
[i
].index
= i
;
1897 enum pipe_format fmt
= elements
[i
].src_format
;
1898 const struct util_format_description
*desc
= util_format_description(fmt
);
1899 so
->hw
[i
].unknown1
= 0x2;
1900 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1902 so
->hw
[i
].format
= panfrost_find_format(desc
);
1904 /* The field itself should probably be shifted over */
1905 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1912 panfrost_bind_vertex_elements_state(
1913 struct pipe_context
*pctx
,
1916 struct panfrost_context
*ctx
= pan_context(pctx
);
1918 ctx
->vertex
= hwcso
;
1919 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1923 panfrost_create_shader_state(
1924 struct pipe_context
*pctx
,
1925 const struct pipe_shader_state
*cso
)
1927 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1930 /* Token deep copy to prevent memory corruption */
1932 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1933 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1939 panfrost_delete_shader_state(
1940 struct pipe_context
*pctx
,
1943 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1945 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1946 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1953 panfrost_create_sampler_state(
1954 struct pipe_context
*pctx
,
1955 const struct pipe_sampler_state
*cso
)
1957 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1960 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1962 struct mali_sampler_descriptor sampler_descriptor
= {
1963 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1964 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1965 | translate_mip_filter(cso
->min_mip_filter
)
1968 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1969 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1970 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1971 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1973 cso
->border_color
.f
[0],
1974 cso
->border_color
.f
[1],
1975 cso
->border_color
.f
[2],
1976 cso
->border_color
.f
[3]
1978 .min_lod
= FIXED_16(cso
->min_lod
),
1979 .max_lod
= FIXED_16(cso
->max_lod
),
1980 .seamless_cube_map
= cso
->seamless_cube_map
,
1983 /* If necessary, we disable mipmapping in the sampler descriptor by
1984 * clamping the LOD as tight as possible (from 0 to epsilon,
1985 * essentially -- remember these are fixed point numbers, so
1988 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1989 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1991 /* Enforce that there is something in the middle by adding epsilon*/
1993 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1994 sampler_descriptor
.max_lod
++;
1997 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1999 so
->hw
= sampler_descriptor
;
2005 panfrost_bind_sampler_states(
2006 struct pipe_context
*pctx
,
2007 enum pipe_shader_type shader
,
2008 unsigned start_slot
, unsigned num_sampler
,
2011 assert(start_slot
== 0);
2013 struct panfrost_context
*ctx
= pan_context(pctx
);
2015 /* XXX: Should upload, not just copy? */
2016 ctx
->sampler_count
[shader
] = num_sampler
;
2017 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
2019 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
2023 panfrost_variant_matches(
2024 struct panfrost_context
*ctx
,
2025 struct panfrost_shader_state
*variant
,
2026 enum pipe_shader_type type
)
2028 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
2029 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
2031 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
2033 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
2034 /* Make sure enable state is at least the same */
2035 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
2039 /* Check that the contents of the test are the same */
2040 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
2041 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
2043 if (!(same_func
&& same_ref
)) {
2048 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
2049 variant
->point_sprite_mask
)) {
2050 /* Ensure the same varyings are turned to point sprites */
2051 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
2054 /* Ensure the orientation is correct */
2056 rasterizer
->sprite_coord_mode
==
2057 PIPE_SPRITE_COORD_UPPER_LEFT
;
2059 if (variant
->point_sprite_upper_left
!= upper_left
)
2063 /* Otherwise, we're good to go */
2068 panfrost_bind_shader_state(
2069 struct pipe_context
*pctx
,
2071 enum pipe_shader_type type
)
2073 struct panfrost_context
*ctx
= pan_context(pctx
);
2075 if (type
== PIPE_SHADER_FRAGMENT
) {
2077 ctx
->dirty
|= PAN_DIRTY_FS
;
2079 assert(type
== PIPE_SHADER_VERTEX
);
2081 ctx
->dirty
|= PAN_DIRTY_VS
;
2086 /* Match the appropriate variant */
2088 signed variant
= -1;
2089 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2091 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2092 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2098 if (variant
== -1) {
2099 /* No variant matched, so create a new one */
2100 variant
= variants
->variant_count
++;
2101 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2103 struct panfrost_shader_state
*v
=
2104 &variants
->variants
[variant
];
2108 if (type
== PIPE_SHADER_FRAGMENT
) {
2109 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2111 if (ctx
->rasterizer
) {
2112 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2113 v
->point_sprite_upper_left
=
2114 ctx
->rasterizer
->base
.sprite_coord_mode
==
2115 PIPE_SPRITE_COORD_UPPER_LEFT
;
2119 variants
->variants
[variant
].tripipe
= malloc(sizeof(struct mali_shader_meta
));
2123 /* Select this variant */
2124 variants
->active_variant
= variant
;
2126 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2127 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2129 /* We finally have a variant, so compile it */
2131 if (!shader_state
->compiled
) {
2132 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
2133 panfrost_job_type_for_pipe(type
), shader_state
);
2135 shader_state
->compiled
= true;
2140 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2142 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2146 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2148 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2152 panfrost_set_vertex_buffers(
2153 struct pipe_context
*pctx
,
2154 unsigned start_slot
,
2155 unsigned num_buffers
,
2156 const struct pipe_vertex_buffer
*buffers
)
2158 struct panfrost_context
*ctx
= pan_context(pctx
);
2160 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2164 panfrost_set_constant_buffer(
2165 struct pipe_context
*pctx
,
2166 enum pipe_shader_type shader
, uint index
,
2167 const struct pipe_constant_buffer
*buf
)
2169 struct panfrost_context
*ctx
= pan_context(pctx
);
2170 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2172 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2174 unsigned mask
= (1 << index
);
2176 if (unlikely(!buf
)) {
2177 pbuf
->enabled_mask
&= ~mask
;
2178 pbuf
->dirty_mask
&= ~mask
;
2182 pbuf
->enabled_mask
|= mask
;
2183 pbuf
->dirty_mask
|= mask
;
2187 panfrost_set_stencil_ref(
2188 struct pipe_context
*pctx
,
2189 const struct pipe_stencil_ref
*ref
)
2191 struct panfrost_context
*ctx
= pan_context(pctx
);
2192 ctx
->stencil_ref
= *ref
;
2194 /* Shader core dirty */
2195 ctx
->dirty
|= PAN_DIRTY_FS
;
2198 static enum mali_texture_type
2199 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2203 case PIPE_TEXTURE_1D
:
2204 case PIPE_TEXTURE_1D_ARRAY
:
2207 case PIPE_TEXTURE_2D
:
2208 case PIPE_TEXTURE_2D_ARRAY
:
2209 case PIPE_TEXTURE_RECT
:
2212 case PIPE_TEXTURE_3D
:
2215 case PIPE_TEXTURE_CUBE
:
2216 case PIPE_TEXTURE_CUBE_ARRAY
:
2217 return MALI_TEX_CUBE
;
2220 unreachable("Unknown target");
2224 static struct pipe_sampler_view
*
2225 panfrost_create_sampler_view(
2226 struct pipe_context
*pctx
,
2227 struct pipe_resource
*texture
,
2228 const struct pipe_sampler_view
*template)
2230 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2231 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2233 pipe_reference(NULL
, &texture
->reference
);
2235 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2238 so
->base
= *template;
2239 so
->base
.texture
= texture
;
2240 so
->base
.reference
.count
= 1;
2241 so
->base
.context
= pctx
;
2243 /* sampler_views correspond to texture descriptors, minus the texture
2244 * (data) itself. So, we serialise the descriptor here and cache it for
2247 /* TODO: Detect from format better */
2248 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2250 unsigned char user_swizzle
[4] = {
2251 template->swizzle_r
,
2252 template->swizzle_g
,
2253 template->swizzle_b
,
2257 enum mali_format format
= panfrost_find_format(desc
);
2259 /* Check if we need to set a custom stride by computing the "expected"
2260 * stride and comparing it to what the BO actually wants. Only applies
2261 * to linear textures, since tiled/compressed textures have strict
2262 * alignment requirements for their strides as it is */
2264 unsigned first_level
= template->u
.tex
.first_level
;
2265 unsigned last_level
= template->u
.tex
.last_level
;
2267 if (prsrc
->layout
== PAN_LINEAR
) {
2268 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2269 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2270 unsigned width
= u_minify(texture
->width0
, l
);
2271 unsigned comp_stride
= width
* bytes_per_pixel
;
2273 if (comp_stride
!= actual_stride
) {
2274 so
->manual_stride
= true;
2280 /* In the hardware, array_size refers specifically to array textures,
2281 * whereas in Gallium, it also covers cubemaps */
2283 unsigned array_size
= texture
->array_size
;
2285 if (template->target
== PIPE_TEXTURE_CUBE
) {
2286 /* TODO: Cubemap arrays */
2287 assert(array_size
== 6);
2291 struct mali_texture_descriptor texture_descriptor
= {
2292 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2293 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2294 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2295 .array_size
= MALI_POSITIVE(array_size
),
2299 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2302 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2303 .type
= panfrost_translate_texture_type(template->target
),
2306 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2309 texture_descriptor
.nr_mipmap_levels
= last_level
- first_level
;
2311 so
->hw
= texture_descriptor
;
2313 return (struct pipe_sampler_view
*) so
;
2317 panfrost_set_sampler_views(
2318 struct pipe_context
*pctx
,
2319 enum pipe_shader_type shader
,
2320 unsigned start_slot
, unsigned num_views
,
2321 struct pipe_sampler_view
**views
)
2323 struct panfrost_context
*ctx
= pan_context(pctx
);
2325 assert(start_slot
== 0);
2327 unsigned new_nr
= 0;
2328 for (unsigned i
= 0; i
< num_views
; ++i
) {
2333 ctx
->sampler_view_count
[shader
] = new_nr
;
2334 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2336 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2340 panfrost_sampler_view_destroy(
2341 struct pipe_context
*pctx
,
2342 struct pipe_sampler_view
*view
)
2344 pipe_resource_reference(&view
->texture
, NULL
);
2348 /* Hints that a framebuffer should use AFBC where possible */
2352 struct panfrost_screen
*screen
,
2353 const struct pipe_framebuffer_state
*fb
)
2355 /* AFBC implemenation incomplete; hide it */
2356 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2358 /* Hint AFBC to the resources bound to each color buffer */
2360 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2361 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2362 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2363 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2366 /* Also hint it to the depth buffer */
2369 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2370 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2375 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2376 const struct pipe_framebuffer_state
*fb
)
2378 struct panfrost_context
*ctx
= pan_context(pctx
);
2380 /* Flush when switching framebuffers, but not if the framebuffer
2381 * state is being restored by u_blitter
2384 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
2385 bool is_scanout
= panfrost_is_scanout(ctx
);
2386 bool has_draws
= job
->last_job
.gpu
;
2388 if (!ctx
->wallpaper_batch
&& (!is_scanout
|| has_draws
)) {
2389 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2392 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2394 /* Given that we're rendering, we'd love to have compression */
2395 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2397 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2399 if (screen
->require_sfbd
)
2400 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2402 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2404 panfrost_attach_vt_framebuffer(ctx
, false);
2408 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2409 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2411 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2415 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2418 struct panfrost_context
*ctx
= pan_context(pipe
);
2419 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2420 ctx
->depth_stencil
= depth_stencil
;
2425 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2426 * emulated in the fragment shader */
2428 if (depth_stencil
->alpha
.enabled
) {
2429 /* We need to trigger a new shader (maybe) */
2430 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2434 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2436 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2437 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2439 /* If back-stencil is not enabled, use the front values */
2440 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2441 unsigned back_index
= back_enab
? 1 : 0;
2443 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2444 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2446 /* Depth state (TODO: Refactor) */
2447 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2449 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2451 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2452 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2454 /* Bounds test not implemented */
2455 assert(!depth_stencil
->depth
.bounds_test
);
2457 ctx
->dirty
|= PAN_DIRTY_FS
;
2461 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2467 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2468 unsigned sample_mask
)
2473 panfrost_set_clip_state(struct pipe_context
*pipe
,
2474 const struct pipe_clip_state
*clip
)
2476 //struct panfrost_context *panfrost = pan_context(pipe);
2480 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2481 unsigned start_slot
,
2482 unsigned num_viewports
,
2483 const struct pipe_viewport_state
*viewports
)
2485 struct panfrost_context
*ctx
= pan_context(pipe
);
2487 assert(start_slot
== 0);
2488 assert(num_viewports
== 1);
2490 ctx
->pipe_viewport
= *viewports
;
2494 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2495 unsigned start_slot
,
2496 unsigned num_scissors
,
2497 const struct pipe_scissor_state
*scissors
)
2499 struct panfrost_context
*ctx
= pan_context(pipe
);
2501 assert(start_slot
== 0);
2502 assert(num_scissors
== 1);
2504 ctx
->scissor
= *scissors
;
2508 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2509 const struct pipe_poly_stipple
*stipple
)
2511 //struct panfrost_context *panfrost = pan_context(pipe);
2515 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2518 //struct panfrost_context *panfrost = pan_context(pipe);
2522 panfrost_destroy(struct pipe_context
*pipe
)
2524 struct panfrost_context
*panfrost
= pan_context(pipe
);
2525 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2527 if (panfrost
->blitter
)
2528 util_blitter_destroy(panfrost
->blitter
);
2530 if (panfrost
->blitter_wallpaper
)
2531 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2533 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2534 panfrost_drm_free_slab(screen
, &panfrost
->shaders
);
2535 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2536 panfrost_drm_free_slab(screen
, &panfrost
->tiler_polygon_list
);
2537 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2542 static struct pipe_query
*
2543 panfrost_create_query(struct pipe_context
*pipe
,
2547 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2552 return (struct pipe_query
*) q
;
2556 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2562 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2564 struct panfrost_context
*ctx
= pan_context(pipe
);
2565 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2567 switch (query
->type
) {
2568 case PIPE_QUERY_OCCLUSION_COUNTER
:
2569 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2570 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2571 /* Allocate a word for the query results to be stored */
2572 query
->transfer
= panfrost_allocate_transient(ctx
, sizeof(unsigned));
2574 ctx
->occlusion_query
= query
;
2580 DBG("Skipping query %d\n", query
->type
);
2588 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2590 struct panfrost_context
*ctx
= pan_context(pipe
);
2591 ctx
->occlusion_query
= NULL
;
2596 panfrost_get_query_result(struct pipe_context
*pipe
,
2597 struct pipe_query
*q
,
2599 union pipe_query_result
*vresult
)
2602 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2604 /* We need to flush out the jobs to actually run the counter, TODO
2605 * check wait, TODO wallpaper after if needed */
2607 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2609 switch (query
->type
) {
2610 case PIPE_QUERY_OCCLUSION_COUNTER
:
2611 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2612 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2613 /* Read back the query results */
2614 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2615 unsigned passed
= *result
;
2617 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2618 vresult
->u64
= passed
;
2620 vresult
->b
= !!passed
;
2626 DBG("Skipped query get %d\n", query
->type
);
2633 static struct pipe_stream_output_target
*
2634 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2635 struct pipe_resource
*prsc
,
2636 unsigned buffer_offset
,
2637 unsigned buffer_size
)
2639 struct pipe_stream_output_target
*target
;
2641 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2646 pipe_reference_init(&target
->reference
, 1);
2647 pipe_resource_reference(&target
->buffer
, prsc
);
2649 target
->context
= pctx
;
2650 target
->buffer_offset
= buffer_offset
;
2651 target
->buffer_size
= buffer_size
;
2657 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2658 struct pipe_stream_output_target
*target
)
2660 pipe_resource_reference(&target
->buffer
, NULL
);
2661 ralloc_free(target
);
2665 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2666 unsigned num_targets
,
2667 struct pipe_stream_output_target
**targets
,
2668 const unsigned *offsets
)
2674 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2676 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2677 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2679 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64*4, false, 0, 0, 0);
2680 panfrost_drm_allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2681 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 4096, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2682 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2683 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2686 /* New context creation, which also does hardware initialisation since I don't
2687 * know the better way to structure this :smirk: */
2689 struct pipe_context
*
2690 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2692 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2693 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2694 memset(ctx
, 0, sizeof(*ctx
));
2695 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2697 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2699 gallium
->screen
= screen
;
2701 gallium
->destroy
= panfrost_destroy
;
2703 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2705 gallium
->flush
= panfrost_flush
;
2706 gallium
->clear
= panfrost_clear
;
2707 gallium
->draw_vbo
= panfrost_draw_vbo
;
2709 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2710 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2712 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2714 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2715 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2716 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2718 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2719 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2720 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2722 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2723 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2724 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2726 gallium
->create_fs_state
= panfrost_create_shader_state
;
2727 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2728 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2730 gallium
->create_vs_state
= panfrost_create_shader_state
;
2731 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2732 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2734 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2735 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2736 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2738 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2739 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2740 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2742 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2744 gallium
->set_clip_state
= panfrost_set_clip_state
;
2745 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2746 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2747 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2748 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2750 gallium
->create_query
= panfrost_create_query
;
2751 gallium
->destroy_query
= panfrost_destroy_query
;
2752 gallium
->begin_query
= panfrost_begin_query
;
2753 gallium
->end_query
= panfrost_end_query
;
2754 gallium
->get_query_result
= panfrost_get_query_result
;
2756 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2757 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2758 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2760 panfrost_resource_context_init(gallium
);
2761 panfrost_blend_context_init(gallium
);
2763 panfrost_drm_init_context(ctx
);
2765 panfrost_setup_hardware(ctx
);
2768 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2769 gallium
->const_uploader
= gallium
->stream_uploader
;
2770 assert(gallium
->stream_uploader
);
2772 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2773 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2775 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2777 ctx
->blitter
= util_blitter_create(gallium
);
2778 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2780 assert(ctx
->blitter
);
2781 assert(ctx
->blitter_wallpaper
);
2783 /* Prepare for render! */
2785 panfrost_job_init(ctx
);
2786 panfrost_emit_vertex_payload(ctx
);
2787 panfrost_emit_tiler_payload(ctx
);
2788 panfrost_invalidate_frame(ctx
);
2789 panfrost_default_shader_backend(ctx
);