2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
45 #include "pan_wallpaper.h"
47 static int performance_counter_number
= 0;
48 extern const char *pan_counters_base
;
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 #define SET_BIT(lval, bit, cond) \
59 /* TODO: Sample size, etc */
62 panfrost_set_framebuffer_msaa(struct panfrost_context
*ctx
, bool enabled
)
64 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, enabled
);
65 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !enabled
);
67 if (ctx
->require_sfbd
) {
68 SET_BIT(ctx
->fragment_sfbd
.format
, MALI_FRAMEBUFFER_MSAA_A
| MALI_FRAMEBUFFER_MSAA_B
, enabled
);
70 SET_BIT(ctx
->fragment_rts
[0].format
.flags
, MALI_MFBD_FORMAT_MSAA
, enabled
);
72 SET_BIT(ctx
->fragment_mfbd
.unk1
, (1 << 4) | (1 << 1), enabled
);
75 ctx
->fragment_mfbd
.rt_count_2
= enabled
? 4 : 1;
79 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
80 * indepdent between color buffers and depth/stencil). To enable, we allocate
81 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
82 * edit the fragment job here. This routine should be called ONCE per
83 * AFBC-compressed buffer, rather than on every frame. */
86 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
88 if (ctx
->require_sfbd
) {
89 DBG("AFBC not supported yet on SFBD\n");
93 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
94 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
95 /* AFBC metadata is 16 bytes per tile */
96 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
97 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
98 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
99 int stride
= bytes_per_pixel
* rsrc
->base
.width0
; /* TODO: Alignment? */
101 stride
*= 2; /* TODO: Should this be carried over? */
102 int main_size
= stride
* rsrc
->base
.height0
;
103 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
105 /* Allocate the AFBC slab itself, large enough to hold the above */
106 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
107 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
110 rsrc
->bo
->has_afbc
= true;
111 rsrc
->bo
->gem_handle
= rsrc
->bo
->afbc_slab
.gem_handle
;
113 /* Compressed textured reads use a tagged pointer to the metadata */
115 rsrc
->bo
->gpu
[0] = rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
116 rsrc
->bo
->cpu
[0] = rsrc
->bo
->afbc_slab
.cpu
;
120 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
122 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
123 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
124 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
125 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
127 /* 8 byte checksum per tile */
128 rsrc
->bo
->checksum_stride
= tile_w
* 8;
129 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
130 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
132 rsrc
->bo
->has_checksum
= true;
135 /* ..by contrast, this routine runs for every FRAGMENT job, but does no
136 * allocation. AFBC is enabled on a per-surface basis */
139 panfrost_set_fragment_afbc(struct panfrost_context
*ctx
)
141 for (int cb
= 0; cb
< ctx
->pipe_framebuffer
.nr_cbufs
; ++cb
) {
142 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[cb
]->texture
;
144 /* Non-AFBC is the default */
145 if (!rsrc
->bo
->has_afbc
)
148 if (ctx
->require_sfbd
) {
149 DBG("Color AFBC not supported on SFBD\n");
153 /* Enable AFBC for the render target */
154 ctx
->fragment_rts
[0].afbc
.metadata
= rsrc
->bo
->afbc_slab
.gpu
;
155 ctx
->fragment_rts
[0].afbc
.stride
= 0;
156 ctx
->fragment_rts
[0].afbc
.unk
= 0x30009;
158 ctx
->fragment_rts
[0].format
.flags
|= MALI_MFBD_FORMAT_AFBC
;
160 /* Point rendering to our special framebuffer */
161 ctx
->fragment_rts
[0].framebuffer
= rsrc
->bo
->afbc_slab
.gpu
+ rsrc
->bo
->afbc_metadata_size
;
163 /* WAT? Stride is diff from the scanout case */
164 ctx
->fragment_rts
[0].framebuffer_stride
= ctx
->pipe_framebuffer
.width
* 2 * 4;
167 /* Enable depth/stencil AFBC for the framebuffer (not the render target) */
168 if (ctx
->pipe_framebuffer
.zsbuf
) {
169 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
;
171 if (rsrc
->bo
->has_afbc
) {
172 if (ctx
->require_sfbd
) {
173 DBG("Depth AFBC not supported on SFBD\n");
177 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
179 ctx
->fragment_extra
.ds_afbc
.depth_stencil_afbc_metadata
= rsrc
->bo
->afbc_slab
.gpu
;
180 ctx
->fragment_extra
.ds_afbc
.depth_stencil_afbc_stride
= 0;
182 ctx
->fragment_extra
.ds_afbc
.depth_stencil
= rsrc
->bo
->afbc_slab
.gpu
+ rsrc
->bo
->afbc_metadata_size
;
184 ctx
->fragment_extra
.ds_afbc
.zero1
= 0x10009;
185 ctx
->fragment_extra
.ds_afbc
.padding
= 0x1000;
187 ctx
->fragment_extra
.unk
= 0x435; /* General 0x400 in all unks. 0x5 for depth/stencil. 0x10 for AFBC encoded depth stencil. Unclear where the 0x20 is from */
189 ctx
->fragment_mfbd
.unk3
|= 0x400;
193 /* For the special case of a depth-only FBO, we need to attach a dummy render target */
195 if (ctx
->pipe_framebuffer
.nr_cbufs
== 0) {
196 if (ctx
->require_sfbd
) {
197 DBG("Depth-only FBO not supported on SFBD\n");
201 struct mali_rt_format null_rt
= {
206 ctx
->fragment_rts
[0].format
= null_rt
;
207 ctx
->fragment_rts
[0].framebuffer
= 0;
208 ctx
->fragment_rts
[0].framebuffer_stride
= 0;
212 /* Framebuffer descriptor */
215 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
217 fb
->width
= MALI_POSITIVE(w
);
218 fb
->height
= MALI_POSITIVE(h
);
220 /* No idea why this is needed, but it's how resolution_check is
221 * calculated. It's not clear to us yet why the hardware wants this.
222 * The formula itself was discovered mostly by manual bruteforce and
223 * aggressive algebraic simplification. */
225 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
228 static struct mali_single_framebuffer
229 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
231 struct mali_single_framebuffer framebuffer
= {
233 .format
= 0x30000000,
234 .clear_flags
= 0x1000,
235 .unknown_address_0
= ctx
->scratchpad
.gpu
,
236 .unknown_address_1
= ctx
->misc_0
.gpu
,
237 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
239 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
240 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
243 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
248 static struct bifrost_framebuffer
249 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
251 struct bifrost_framebuffer framebuffer
= {
252 /* It is not yet clear what tiler_meta means or how it's
253 * calculated, but we can tell the lower 32-bits are a
254 * (monotonically increasing?) function of tile count and
255 * geometry complexity; I suspect it defines a memory size of
256 * some kind? for the tiler. It's really unclear at the
257 * moment... but to add to the confusion, the hardware is happy
258 * enough to accept a zero in this field, so we don't even have
259 * to worry about it right now.
261 * The byte (just after the 32-bit mark) is much more
262 * interesting. The higher nibble I've only ever seen as 0xF,
263 * but the lower one I've seen as 0x0 or 0xF, and it's not
264 * obvious what the difference is. But what -is- obvious is
265 * that when the lower nibble is zero, performance is severely
266 * degraded compared to when the lower nibble is set.
267 * Evidently, that nibble enables some sort of fast path,
268 * perhaps relating to caching or tile flush? Regardless, at
269 * this point there's no clear reason not to set it, aside from
270 * substantially increased memory requirements (of the misc_0
273 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
275 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
276 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
277 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
278 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
283 .rt_count_1
= MALI_POSITIVE(1),
288 /* Corresponds to unknown_address_X of SFBD */
289 .scratchpad
= ctx
->scratchpad
.gpu
,
290 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
292 /* The constant added here is, like the lower word of
293 * tiler_meta, (loosely) another product of framebuffer size
294 * and geometry complexity. It must be sufficiently large for
295 * the tiler_meta fast path to work; if it's too small, there
296 * will be DATA_INVALID_FAULTs. Conversely, it must be less
297 * than the total size of misc_0, or else there's no room. It's
298 * possible this constant configures a partition between two
299 * parts of misc_0? We haven't investigated the functionality,
300 * as these buffers are internally used by the hardware
301 * (presumably by the tiler) but not seemingly touched by the driver
304 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
306 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
307 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
313 /* Are we currently rendering to the screen (rather than an FBO)? */
316 panfrost_is_scanout(struct panfrost_context
*ctx
)
318 /* If there is no color buffer, it's an FBO */
319 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
322 /* If we're too early that no framebuffer was sent, it's scanout */
323 if (!ctx
->pipe_framebuffer
.cbufs
[0])
326 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
327 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
328 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
331 /* The above function is for generalised fbd emission, used in both fragment as
332 * well as vertex/tiler payloads. This payload is specific to fragment
336 panfrost_new_frag_framebuffer(struct panfrost_context
*ctx
)
338 mali_ptr framebuffer
;
341 if (ctx
->pipe_framebuffer
.nr_cbufs
> 0) {
342 framebuffer
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[0]->texture
)->bo
->gpu
[0];
343 stride
= util_format_get_stride(ctx
->pipe_framebuffer
.cbufs
[0]->format
, ctx
->pipe_framebuffer
.width
);
345 /* Depth-only framebuffer -> dummy RT */
350 /* The default is upside down from OpenGL's perspective. */
351 if (panfrost_is_scanout(ctx
)) {
352 framebuffer
+= stride
* (ctx
->pipe_framebuffer
.height
- 1);
356 if (ctx
->require_sfbd
) {
357 struct mali_single_framebuffer fb
= panfrost_emit_sfbd(ctx
);
359 fb
.framebuffer
= framebuffer
;
362 fb
.format
= 0xb84e0281; /* RGB32, no MSAA */
363 memcpy(&ctx
->fragment_sfbd
, &fb
, sizeof(fb
));
365 struct bifrost_framebuffer fb
= panfrost_emit_mfbd(ctx
);
371 /* By default, Gallium seems to need a BGR framebuffer */
372 unsigned char bgra
[4] = {
373 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_Y
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_W
376 struct bifrost_render_target rt
= {
380 .nr_channels
= MALI_POSITIVE(4),
382 .swizzle
= panfrost_translate_swizzle_4(bgra
),
385 .framebuffer
= framebuffer
,
386 .framebuffer_stride
= (stride
/ 16) & 0xfffffff,
389 memcpy(&ctx
->fragment_rts
[0], &rt
, sizeof(rt
));
391 memset(&ctx
->fragment_extra
, 0, sizeof(ctx
->fragment_extra
));
392 memcpy(&ctx
->fragment_mfbd
, &fb
, sizeof(fb
));
396 /* Maps float 0.0-1.0 to int 0x00-0xFF */
398 normalised_float_to_u8(float f
)
400 return (uint8_t) (int) (f
* 255.0f
);
404 panfrost_clear_sfbd(struct panfrost_job
*job
)
406 struct panfrost_context
*ctx
= job
->ctx
;
407 struct mali_single_framebuffer
*sfbd
= &ctx
->fragment_sfbd
;
409 if (job
->clear
& PIPE_CLEAR_COLOR
) {
410 sfbd
->clear_color_1
= job
->clear_color
;
411 sfbd
->clear_color_2
= job
->clear_color
;
412 sfbd
->clear_color_3
= job
->clear_color
;
413 sfbd
->clear_color_4
= job
->clear_color
;
416 if (job
->clear
& PIPE_CLEAR_DEPTH
) {
417 sfbd
->clear_depth_1
= job
->clear_depth
;
418 sfbd
->clear_depth_2
= job
->clear_depth
;
419 sfbd
->clear_depth_3
= job
->clear_depth
;
420 sfbd
->clear_depth_4
= job
->clear_depth
;
422 sfbd
->depth_buffer
= ctx
->depth_stencil_buffer
.gpu
;
423 sfbd
->depth_buffer_enable
= MALI_DEPTH_STENCIL_ENABLE
;
426 if (job
->clear
& PIPE_CLEAR_STENCIL
) {
427 sfbd
->clear_stencil
= job
->clear_stencil
;
429 sfbd
->stencil_buffer
= ctx
->depth_stencil_buffer
.gpu
;
430 sfbd
->stencil_buffer_enable
= MALI_DEPTH_STENCIL_ENABLE
;
433 /* Set flags based on what has been cleared, for the SFBD case */
434 /* XXX: What do these flags mean? */
435 int clear_flags
= 0x101100;
437 if (!(job
->clear
& ~(PIPE_CLEAR_COLOR
| PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
))) {
438 /* On a tiler like this, it's fastest to clear all three buffers at once */
440 clear_flags
|= MALI_CLEAR_FAST
;
442 clear_flags
|= MALI_CLEAR_SLOW
;
444 if (job
->clear
& PIPE_CLEAR_STENCIL
)
445 clear_flags
|= MALI_CLEAR_SLOW_STENCIL
;
448 sfbd
->clear_flags
= clear_flags
;
452 panfrost_clear_mfbd(struct panfrost_job
*job
)
454 struct panfrost_context
*ctx
= job
->ctx
;
455 struct bifrost_render_target
*buffer_color
= &ctx
->fragment_rts
[0];
456 struct bifrost_framebuffer
*buffer_ds
= &ctx
->fragment_mfbd
;
458 if (job
->clear
& PIPE_CLEAR_COLOR
) {
459 buffer_color
->clear_color_1
= job
->clear_color
;
460 buffer_color
->clear_color_2
= job
->clear_color
;
461 buffer_color
->clear_color_3
= job
->clear_color
;
462 buffer_color
->clear_color_4
= job
->clear_color
;
465 if (job
->clear
& PIPE_CLEAR_DEPTH
) {
466 buffer_ds
->clear_depth
= job
->clear_depth
;
469 if (job
->clear
& PIPE_CLEAR_STENCIL
) {
470 buffer_ds
->clear_stencil
= job
->clear_stencil
;
473 if (job
->clear
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
474 /* Setup combined 24/8 depth/stencil */
475 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
476 ctx
->fragment_extra
.unk
= 0x405;
477 ctx
->fragment_extra
.ds_linear
.depth
= ctx
->depth_stencil_buffer
.gpu
;
478 ctx
->fragment_extra
.ds_linear
.depth_stride
= ctx
->pipe_framebuffer
.width
* 4;
484 struct pipe_context
*pipe
,
486 const union pipe_color_union
*color
,
487 double depth
, unsigned stencil
)
489 struct panfrost_context
*ctx
= pan_context(pipe
);
490 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
492 if (buffers
& PIPE_CLEAR_COLOR
) {
493 /* Alpha clear only meaningful without alpha channel, TODO less ad hoc */
494 bool has_alpha
= util_format_has_alpha(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
495 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
497 uint32_t packed_color
=
498 (normalised_float_to_u8(clear_alpha
) << 24) |
499 (normalised_float_to_u8(color
->f
[2]) << 16) |
500 (normalised_float_to_u8(color
->f
[1]) << 8) |
501 (normalised_float_to_u8(color
->f
[0]) << 0);
503 job
->clear_color
= packed_color
;
507 if (buffers
& PIPE_CLEAR_DEPTH
) {
508 job
->clear_depth
= depth
;
511 if (buffers
& PIPE_CLEAR_STENCIL
) {
512 job
->clear_stencil
= stencil
;
515 job
->clear
|= buffers
;
519 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
521 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
522 struct bifrost_render_target rts_list
[] = {
527 .framebuffer
= ctx
->misc_0
.gpu
,
532 /* Allocate memory for the three components */
533 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
534 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
536 /* Opaque 1024-block */
537 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
539 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
540 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
542 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
546 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
548 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
552 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
554 mali_ptr framebuffer
= ctx
->require_sfbd
?
555 panfrost_attach_vt_sfbd(ctx
) :
556 panfrost_attach_vt_mfbd(ctx
);
558 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
559 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
563 panfrost_viewport(struct panfrost_context
*ctx
,
564 float depth_clip_near
,
565 float depth_clip_far
,
566 int viewport_x0
, int viewport_y0
,
567 int viewport_x1
, int viewport_y1
)
569 /* Clip bounds are encoded as floats. The viewport itself is encoded as
570 * (somewhat) asymmetric ints. */
572 struct mali_viewport ret
= {
573 /* By default, do no viewport clipping, i.e. clip to (-inf,
574 * inf) in each direction. Clipping to the viewport in theory
575 * should work, but in practice causes issues when we're not
576 * explicitly trying to scissor */
583 /* We always perform depth clipping (TODO: Can this be disabled?) */
585 .clip_minz
= depth_clip_near
,
586 .clip_maxz
= depth_clip_far
,
588 .viewport0
= { viewport_x0
, viewport_y0
},
589 .viewport1
= { MALI_POSITIVE(viewport_x1
), MALI_POSITIVE(viewport_y1
) },
592 memcpy(ctx
->viewport
, &ret
, sizeof(ret
));
595 /* Reset per-frame context, called on context initialisation as well as after
596 * flushing a frame */
599 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
601 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
602 DBG("Uploaded transient %d bytes\n", transient_count
);
604 /* Rotate cmdstream */
605 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
606 ctx
->cmdstream_i
= 0;
608 if (ctx
->require_sfbd
)
609 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
611 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
613 panfrost_new_frag_framebuffer(ctx
);
615 /* Reset varyings allocated */
616 ctx
->varying_height
= 0;
618 /* The transient cmdstream is dirty every frame; the only bits worth preserving
619 * (textures, shaders, etc) are in other buffers anyways */
621 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
622 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
624 /* Regenerate payloads */
625 panfrost_attach_vt_framebuffer(ctx
);
628 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
631 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
634 /* In practice, every field of these payloads should be configurable
635 * arbitrarily, which means these functions are basically catch-all's for
636 * as-of-yet unwavering unknowns */
639 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
641 struct midgard_payload_vertex_tiler payload
= {
643 .workgroups_z_shift
= 32,
644 .workgroups_x_shift_2
= 0x2,
645 .workgroups_x_shift_3
= 0x5,
647 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
650 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
654 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
656 struct midgard_payload_vertex_tiler payload
= {
658 .workgroups_z_shift
= 32,
659 .workgroups_x_shift_2
= 0x2,
660 .workgroups_x_shift_3
= 0x6,
662 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
666 /* Reserve the viewport */
667 struct panfrost_transfer t
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_viewport
), HEAP_DESCRIPTOR
);
668 ctx
->viewport
= (struct mali_viewport
*) t
.cpu
;
669 payload
.postfix
.viewport
= t
.gpu
;
671 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
675 translate_tex_wrap(enum pipe_tex_wrap w
)
678 case PIPE_TEX_WRAP_REPEAT
:
679 return MALI_WRAP_REPEAT
;
681 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
682 return MALI_WRAP_CLAMP_TO_EDGE
;
684 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
685 return MALI_WRAP_CLAMP_TO_BORDER
;
687 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
688 return MALI_WRAP_MIRRORED_REPEAT
;
697 translate_tex_filter(enum pipe_tex_filter f
)
700 case PIPE_TEX_FILTER_NEAREST
:
703 case PIPE_TEX_FILTER_LINEAR
:
713 translate_mip_filter(enum pipe_tex_mipfilter f
)
715 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
719 panfrost_translate_compare_func(enum pipe_compare_func in
)
722 case PIPE_FUNC_NEVER
:
723 return MALI_FUNC_NEVER
;
726 return MALI_FUNC_LESS
;
728 case PIPE_FUNC_EQUAL
:
729 return MALI_FUNC_EQUAL
;
731 case PIPE_FUNC_LEQUAL
:
732 return MALI_FUNC_LEQUAL
;
734 case PIPE_FUNC_GREATER
:
735 return MALI_FUNC_GREATER
;
737 case PIPE_FUNC_NOTEQUAL
:
738 return MALI_FUNC_NOTEQUAL
;
740 case PIPE_FUNC_GEQUAL
:
741 return MALI_FUNC_GEQUAL
;
743 case PIPE_FUNC_ALWAYS
:
744 return MALI_FUNC_ALWAYS
;
748 return 0; /* Unreachable */
752 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
755 case PIPE_FUNC_NEVER
:
756 return MALI_ALT_FUNC_NEVER
;
759 return MALI_ALT_FUNC_LESS
;
761 case PIPE_FUNC_EQUAL
:
762 return MALI_ALT_FUNC_EQUAL
;
764 case PIPE_FUNC_LEQUAL
:
765 return MALI_ALT_FUNC_LEQUAL
;
767 case PIPE_FUNC_GREATER
:
768 return MALI_ALT_FUNC_GREATER
;
770 case PIPE_FUNC_NOTEQUAL
:
771 return MALI_ALT_FUNC_NOTEQUAL
;
773 case PIPE_FUNC_GEQUAL
:
774 return MALI_ALT_FUNC_GEQUAL
;
776 case PIPE_FUNC_ALWAYS
:
777 return MALI_ALT_FUNC_ALWAYS
;
781 return 0; /* Unreachable */
785 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
788 case PIPE_STENCIL_OP_KEEP
:
789 return MALI_STENCIL_KEEP
;
791 case PIPE_STENCIL_OP_ZERO
:
792 return MALI_STENCIL_ZERO
;
794 case PIPE_STENCIL_OP_REPLACE
:
795 return MALI_STENCIL_REPLACE
;
797 case PIPE_STENCIL_OP_INCR
:
798 return MALI_STENCIL_INCR
;
800 case PIPE_STENCIL_OP_DECR
:
801 return MALI_STENCIL_DECR
;
803 case PIPE_STENCIL_OP_INCR_WRAP
:
804 return MALI_STENCIL_INCR_WRAP
;
806 case PIPE_STENCIL_OP_DECR_WRAP
:
807 return MALI_STENCIL_DECR_WRAP
;
809 case PIPE_STENCIL_OP_INVERT
:
810 return MALI_STENCIL_INVERT
;
814 return 0; /* Unreachable */
818 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
820 out
->ref
= 0; /* Gallium gets it from elsewhere */
822 out
->mask
= in
->valuemask
;
823 out
->func
= panfrost_translate_compare_func(in
->func
);
824 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
825 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
826 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
830 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
832 struct mali_shader_meta shader
= {
833 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
835 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
836 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
840 shader
.unknown2_4
|= 0x10;
843 struct pipe_stencil_state default_stencil
= {
845 .func
= PIPE_FUNC_ALWAYS
,
846 .fail_op
= MALI_STENCIL_KEEP
,
847 .zfail_op
= MALI_STENCIL_KEEP
,
848 .zpass_op
= MALI_STENCIL_KEEP
,
853 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
854 shader
.stencil_mask_front
= default_stencil
.writemask
;
856 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
857 shader
.stencil_mask_back
= default_stencil
.writemask
;
859 if (default_stencil
.enabled
)
860 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
862 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
865 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
866 * graphics command stream. It should be called once per draw, accordding to
867 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
868 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
871 struct panfrost_transfer
872 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
874 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
875 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
877 struct mali_job_descriptor_header job
= {
878 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
879 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
881 .job_descriptor_size
= 1,
885 /* Only non-elided tiler jobs have dependencies which are known at this point */
887 if (is_tiler
&& !is_elided_tiler
) {
888 /* Tiler jobs depend on vertex jobs */
890 job
.job_dependency_index_1
= draw_job_index
;
892 /* Tiler jobs also depend on the previous tiler job */
895 job
.job_dependency_index_2
= draw_job_index
- 1;
898 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
900 /* There's some padding hacks on 32-bit */
907 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
908 memcpy(transfer
.cpu
, &job
, sizeof(job
));
909 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
913 /* Generates a set value job. It's unclear what exactly this does, why it's
914 * necessary, and when to call it. */
917 panfrost_set_value_job(struct panfrost_context
*ctx
)
919 struct mali_job_descriptor_header job
= {
920 .job_type
= JOB_TYPE_SET_VALUE
,
921 .job_descriptor_size
= 1,
922 .job_index
= 1 + (2 * ctx
->draw_count
),
925 struct mali_payload_set_value payload
= {
926 .out
= ctx
->misc_0
.gpu
,
930 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
931 memcpy(transfer
.cpu
, &job
, sizeof(job
));
932 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
934 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
935 ctx
->set_value_job
= transfer
.gpu
;
938 /* Generate a fragment job. This should be called once per frame. (According to
939 * presentations, this is supposed to correspond to eglSwapBuffers) */
942 panfrost_fragment_job(struct panfrost_context
*ctx
)
944 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
946 /* Actualize the clear late; TODO: Fix order dependency between clear
949 if (ctx
->require_sfbd
) {
950 panfrost_clear_sfbd(job
);
952 panfrost_clear_mfbd(job
);
955 panfrost_set_fragment_afbc(ctx
);
957 if (ctx
->pipe_framebuffer
.nr_cbufs
== 1) {
958 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[0]->texture
;
960 if (rsrc
->bo
->has_checksum
) {
961 if (ctx
->require_sfbd
) {
962 DBG("Checksumming not supported on SFBD\n");
966 int stride
= util_format_get_stride(rsrc
->base
.format
, rsrc
->base
.width0
);
968 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
969 ctx
->fragment_extra
.unk
|= 0x420;
970 ctx
->fragment_extra
.checksum_stride
= rsrc
->bo
->checksum_stride
;
971 ctx
->fragment_extra
.checksum
= rsrc
->bo
->gpu
[0] + stride
* rsrc
->base
.height0
;
975 /* The frame is complete and therefore the framebuffer descriptor is
976 * ready for linkage and upload */
978 size_t sz
= ctx
->require_sfbd
? sizeof(struct mali_single_framebuffer
) : (sizeof(struct bifrost_framebuffer
) + sizeof(struct bifrost_fb_extra
) + sizeof(struct bifrost_render_target
) * 1);
979 struct panfrost_transfer fbd_t
= panfrost_allocate_transient(ctx
, sz
);
982 if (ctx
->require_sfbd
) {
983 /* Upload just the SFBD all at once */
984 memcpy(fbd_t
.cpu
, &ctx
->fragment_sfbd
, sizeof(ctx
->fragment_sfbd
));
985 offset
+= sizeof(ctx
->fragment_sfbd
);
987 /* Upload the MFBD header */
988 memcpy(fbd_t
.cpu
, &ctx
->fragment_mfbd
, sizeof(ctx
->fragment_mfbd
));
989 offset
+= sizeof(ctx
->fragment_mfbd
);
991 /* Upload extra framebuffer info if necessary */
992 if (ctx
->fragment_mfbd
.unk3
& MALI_MFBD_EXTRA
) {
993 memcpy(fbd_t
.cpu
+ offset
, &ctx
->fragment_extra
, sizeof(struct bifrost_fb_extra
));
994 offset
+= sizeof(struct bifrost_fb_extra
);
997 /* Upload (single) render target */
998 memcpy(fbd_t
.cpu
+ offset
, &ctx
->fragment_rts
[0], sizeof(struct bifrost_render_target
) * 1);
1001 /* Generate the fragment (frame) job */
1003 struct mali_job_descriptor_header header
= {
1004 .job_type
= JOB_TYPE_FRAGMENT
,
1007 .job_descriptor_size
= 1
1011 struct mali_payload_fragment payload
= {
1012 .min_tile_coord
= MALI_COORDINATE_TO_TILE_MIN(0, 0),
1013 .max_tile_coord
= MALI_COORDINATE_TO_TILE_MAX(ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
),
1014 .framebuffer
= fbd_t
.gpu
| (ctx
->require_sfbd
? MALI_SFBD
: MALI_MFBD
),
1017 if (!ctx
->require_sfbd
&& ctx
->fragment_mfbd
.unk3
& MALI_MFBD_EXTRA
) {
1018 /* Signal that there is an extra portion of the framebuffer
1021 payload
.framebuffer
|= 2;
1024 /* Normally, there should be no padding. However, fragment jobs are
1025 * shared with 64-bit Bifrost systems, and accordingly there is 4-bytes
1026 * of zero padding in between. */
1028 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(header
) + sizeof(payload
));
1029 memcpy(transfer
.cpu
, &header
, sizeof(header
));
1030 memcpy(transfer
.cpu
+ sizeof(header
), &payload
, sizeof(payload
));
1031 return transfer
.gpu
;
1034 /* Emits attributes and varying descriptors, which should be called every draw,
1035 * excepting some obscure circumstances */
1038 panfrost_emit_vertex_data(struct panfrost_context
*ctx
)
1040 /* TODO: Only update the dirtied buffers */
1041 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
1042 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
1044 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
1046 for (int i
= 0; i
< ctx
->vertex_buffer_count
; ++i
) {
1047 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
1048 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
1050 /* Let's figure out the layout of the attributes in memory so
1051 * we can be smart about size computation. The idea is to
1052 * figure out the maximum src_offset, which tells us the latest
1053 * spot a vertex could start. Meanwhile, we figure out the size
1054 * of the attribute memory (assuming interleaved
1055 * representation) and tack on the max src_offset for a
1056 * reasonably good upper bound on the size.
1058 * Proving correctness is left as an exercise to the reader.
1061 unsigned max_src_offset
= 0;
1063 for (unsigned j
= 0; j
< ctx
->vertex
->num_elements
; ++j
) {
1064 if (ctx
->vertex
->pipe
[j
].vertex_buffer_index
!= i
) continue;
1065 max_src_offset
= MAX2(max_src_offset
, ctx
->vertex
->pipe
[j
].src_offset
);
1068 /* Offset vertex count by draw_start to make sure we upload enough */
1069 attrs
[i
].stride
= buf
->stride
;
1070 attrs
[i
].size
= buf
->stride
* (ctx
->payload_vertex
.draw_start
+ invocation_count
) + max_src_offset
;
1072 /* Vertex elements are -already- GPU-visible, at
1073 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
1074 * it is not, for now we have to duplicate the buffer. */
1076 mali_ptr effective_address
= (rsrc
->bo
->gpu
[0] + buf
->buffer_offset
);
1078 if (effective_address
& 0x3F) {
1079 attrs
[i
].elements
= panfrost_upload_transient(ctx
, rsrc
->bo
->cpu
[0] + buf
->buffer_offset
, attrs
[i
].size
) | 1;
1081 attrs
[i
].elements
= effective_address
| 1;
1085 struct panfrost_varyings
*vars
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
1087 for (int i
= 0; i
< vars
->varying_buffer_count
; ++i
) {
1088 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
1090 varyings
[i
].elements
= varying_address
| 1;
1091 varyings
[i
].stride
= vars
->varyings_stride
[i
];
1092 varyings
[i
].size
= vars
->varyings_stride
[i
] * invocation_count
;
1094 /* If this varying has to be linked somewhere, do it now. See
1095 * pan_assemble.c for the indices. TODO: Use a more generic
1096 * linking interface */
1100 ctx
->payload_tiler
.postfix
.position_varying
= varying_address
;
1101 } else if (i
== 2) {
1103 ctx
->payload_tiler
.primitive_size
.pointer
= varying_address
;
1106 /* Varyings appear to need 64-byte alignment */
1107 ctx
->varying_height
+= ALIGN(varyings
[i
].size
, 64);
1109 /* Ensure that we fit */
1110 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
1113 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, ctx
->vertex_buffer_count
* sizeof(union mali_attr
));
1115 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, vars
->varying_buffer_count
* sizeof(union mali_attr
));
1116 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
1117 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
1120 /* Go through dirty flags and actualise them in the cmdstream. */
1123 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1125 if (with_vertex_data
) {
1126 panfrost_emit_vertex_data(ctx
);
1129 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1130 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1131 panfrost_set_framebuffer_msaa(ctx
, ctx
->rasterizer
->base
.multisample
);
1134 if (ctx
->occlusion_query
) {
1135 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1136 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1139 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1142 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1144 /* Late shader descriptor assignments */
1145 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1146 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1149 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1151 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1153 /* Varying descriptor is tied to the vertex shader. Also the
1154 * fragment shader, I suppose, but it's generated with the
1155 * vertex shader so */
1157 struct panfrost_varyings
*varyings
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
1159 ctx
->payload_vertex
.postfix
.varying_meta
= varyings
->varyings_descriptor
;
1160 ctx
->payload_tiler
.postfix
.varying_meta
= varyings
->varyings_descriptor_fragment
;
1163 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1164 /* Check if we need to link the gl_PointSize varying */
1166 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1168 bool needs_gl_point_size
= vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
1170 if (!needs_gl_point_size
) {
1171 /* If the size is constant, write it out. Otherwise,
1172 * don't touch primitive_size (since we would clobber
1173 * the pointer there) */
1175 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1178 /* Set the flag for varying (pointer) point size if the shader needs that */
1179 SET_BIT(ctx
->payload_tiler
.prefix
.unknown_draw
, MALI_DRAW_VARYING_SIZE
, needs_gl_point_size
);
1182 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1184 ctx
->dirty
|= PAN_DIRTY_FS
;
1186 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1188 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1190 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1193 COPY(attribute_count
);
1194 COPY(varying_count
);
1195 COPY(midgard1
.uniform_count
);
1196 COPY(midgard1
.work_count
);
1197 COPY(midgard1
.unknown2
);
1200 /* If there is a blend shader, work registers are shared */
1202 if (ctx
->blend
->has_blend_shader
)
1203 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1205 /* Set late due to depending on render state */
1206 /* The one at the end seems to mean "1 UBO" */
1207 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1209 /* Assign texture/sample count right before upload */
1210 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1211 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1213 /* Assign the stencil refs late */
1214 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1215 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1217 /* CAN_DISCARD should be set if the fragment shader possibly
1218 * contains a 'discard' instruction. It is likely this is
1219 * related to optimizations related to forward-pixel kill, as
1220 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1221 * thing?" by Peter Harris
1224 if (variant
->can_discard
) {
1225 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1226 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1227 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1228 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1231 /* Check if we're using the default blend descriptor (fast path) */
1234 !ctx
->blend
->has_blend_shader
&&
1235 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1236 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1237 (ctx
->blend
->equation
.color_mask
== 0xf);
1239 if (ctx
->require_sfbd
) {
1240 /* When only a single render target platform is used, the blend
1241 * information is inside the shader meta itself. We
1242 * additionally need to signal CAN_DISCARD for nontrivial blend
1243 * modes (so we're able to read back the destination buffer) */
1245 if (ctx
->blend
->has_blend_shader
) {
1246 ctx
->fragment_shader_core
.blend_shader
= ctx
->blend
->blend_shader
;
1248 memcpy(&ctx
->fragment_shader_core
.blend_equation
, &ctx
->blend
->equation
, sizeof(ctx
->blend
->equation
));
1252 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1256 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct mali_blend_meta
);
1257 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1258 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1260 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1262 if (!ctx
->require_sfbd
) {
1263 /* Additional blend descriptor tacked on for jobs using MFBD */
1265 unsigned blend_count
= 0;
1267 if (ctx
->blend
->has_blend_shader
) {
1268 /* For a blend shader, the bottom nibble corresponds to
1269 * the number of work registers used, which signals the
1270 * -existence- of a blend shader */
1272 assert(ctx
->blend
->blend_work_count
>= 2);
1273 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1275 /* Otherwise, the bottom bit simply specifies if
1276 * blending (anything other than REPLACE) is enabled */
1283 /* Second blend equation is always a simple replace */
1285 uint64_t replace_magic
= 0xf0122122;
1286 struct mali_blend_equation replace_mode
;
1287 memcpy(&replace_mode
, &replace_magic
, sizeof(replace_mode
));
1289 struct mali_blend_meta blend_meta
[] = {
1291 .unk1
= 0x200 | blend_count
,
1292 .blend_equation_1
= ctx
->blend
->equation
,
1293 .blend_equation_2
= replace_mode
1297 if (ctx
->blend
->has_blend_shader
)
1298 memcpy(&blend_meta
[0].blend_equation_1
, &ctx
->blend
->blend_shader
, sizeof(ctx
->blend
->blend_shader
));
1300 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), blend_meta
, sizeof(blend_meta
));
1304 if (ctx
->dirty
& PAN_DIRTY_VERTEX
) {
1305 ctx
->payload_vertex
.postfix
.attribute_meta
= ctx
->vertex
->descriptor_ptr
;
1308 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
1309 /* Upload samplers back to back, no padding */
1311 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1312 if (!ctx
->sampler_count
[t
]) continue;
1314 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
1315 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
1317 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
1318 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
1321 if (t
== PIPE_SHADER_FRAGMENT
)
1322 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
1323 else if (t
== PIPE_SHADER_VERTEX
)
1324 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1330 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1331 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1333 if (!ctx
->sampler_view_count
[t
]) continue;
1335 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1337 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1338 if (!ctx
->sampler_views
[t
][i
])
1341 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1342 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1344 /* Inject the address in. */
1345 for (int l
= 0; l
< (tex_rsrc
->last_level
+ 1); ++l
)
1346 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[l
] = rsrc
->bo
->gpu
[l
];
1348 /* Workaround maybe-errata (?) with non-mipmaps */
1349 int s
= ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
;
1351 if (!rsrc
->bo
->is_mipmap
) {
1353 /* HW ERRATA, not needed after t6XX */
1354 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[1] = rsrc
->bo
->gpu
[0];
1356 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 1;
1359 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= 0;
1362 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1365 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= s
;
1368 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 0;
1372 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1374 if (t
== PIPE_SHADER_FRAGMENT
)
1375 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1376 else if (t
== PIPE_SHADER_VERTEX
)
1377 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1383 /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1384 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1386 float viewport_vec4
[] = {
1388 fabsf(vp
->scale
[1]),
1391 /* -1.0 * vp->translate[1] */ fabs(1.0 * vp
->scale
[1]) /* XXX */
1394 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1395 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1397 if (i
== PIPE_SHADER_VERTEX
|| i
== PIPE_SHADER_FRAGMENT
) {
1398 /* It doesn't matter if we don't use all the memory;
1399 * we'd need a dummy UBO anyway. Compute the max */
1401 size_t size
= sizeof(viewport_vec4
) + buf
->size
;
1402 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1404 /* Keep track how much we've uploaded */
1407 if (i
== PIPE_SHADER_VERTEX
) {
1408 /* Upload viewport */
1409 memcpy(transfer
.cpu
+ offset
, viewport_vec4
, sizeof(viewport_vec4
));
1410 offset
+= sizeof(viewport_vec4
);
1413 /* Upload uniforms */
1414 memcpy(transfer
.cpu
+ offset
, buf
->buffer
, buf
->size
);
1416 int uniform_count
= 0;
1418 struct mali_vertex_tiler_postfix
*postfix
;
1421 case PIPE_SHADER_VERTEX
:
1422 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1423 postfix
= &ctx
->payload_vertex
.postfix
;
1426 case PIPE_SHADER_FRAGMENT
:
1427 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1428 postfix
= &ctx
->payload_tiler
.postfix
;
1432 DBG("Unknown shader stage %d in uniform upload\n", i
);
1436 /* Also attach the same buffer as a UBO for extended access */
1438 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1440 .size
= MALI_POSITIVE((2 + uniform_count
)),
1441 .ptr
= transfer
.gpu
>> 2,
1445 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1446 postfix
->uniforms
= transfer
.gpu
;
1447 postfix
->uniform_buffers
= ubufs
;
1456 /* Corresponds to exactly one draw, but does not submit anything */
1459 panfrost_queue_draw(struct panfrost_context
*ctx
)
1461 /* TODO: Expand the array? */
1462 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1463 DBG("Job buffer overflow, ignoring draw\n");
1467 /* Handle dirty flags now */
1468 panfrost_emit_for_draw(ctx
, true);
1470 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1471 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1473 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1474 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1476 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1477 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1482 /* At the end of the frame, the vertex and tiler jobs are linked together and
1483 * then the fragment job is plonked at the end. Set value job is first for
1484 * unknown reasons. */
1487 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1489 if (first
->job_descriptor_size
)
1490 first
->next_job_64
= (u64
) (uintptr_t) next
;
1492 first
->next_job_32
= (u32
) (uintptr_t) next
;
1496 panfrost_link_jobs(struct panfrost_context
*ctx
)
1498 if (ctx
->draw_count
) {
1499 /* Generate the set_value_job */
1500 panfrost_set_value_job(ctx
);
1502 /* Have the first vertex job depend on the set value job */
1503 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1506 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1509 /* V -> V/T ; T -> T/null */
1510 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1511 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1513 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1517 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1518 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1519 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1523 /* The entire frame is in memory -- send it off to the kernel! */
1526 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1527 struct pipe_fence_handle
**fence
)
1529 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1530 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1532 /* Edge case if screen is cleared and nothing else */
1533 bool has_draws
= ctx
->draw_count
> 0;
1535 /* Workaround a bizarre lockup (a hardware errata?) */
1537 flush_immediate
= true;
1539 /* A number of jobs are batched -- this must be linked and cleared */
1540 panfrost_link_jobs(ctx
);
1542 ctx
->draw_count
= 0;
1543 ctx
->vertex_job_count
= 0;
1544 ctx
->tiler_job_count
= 0;
1548 bool is_scanout
= panfrost_is_scanout(ctx
);
1549 int fragment_id
= screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1551 /* If visual, we can stall a frame */
1553 if (!flush_immediate
)
1554 screen
->driver
->force_flush_fragment(ctx
, fence
);
1556 screen
->last_fragment_id
= fragment_id
;
1557 screen
->last_fragment_flushed
= false;
1559 /* If readback, flush now (hurts the pipelined performance) */
1560 if (flush_immediate
)
1561 screen
->driver
->force_flush_fragment(ctx
, fence
);
1563 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1564 screen
->driver
->dump_counters(screen
);
1567 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1568 FILE *fp
= fopen(filename
, "wb");
1569 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1578 struct pipe_context
*pipe
,
1579 struct pipe_fence_handle
**fence
,
1582 struct panfrost_context
*ctx
= pan_context(pipe
);
1583 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1585 /* Nothing to do! */
1586 if (!ctx
->draw_count
&& !job
->clear
) return;
1588 /* Whether to stall the pipeline for immediately correct results */
1589 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1591 /* Submit the frame itself */
1592 panfrost_submit_frame(ctx
, flush_immediate
, fence
);
1594 /* Prepare for the next frame */
1595 panfrost_invalidate_frame(ctx
);
1598 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1601 g2m_draw_mode(enum pipe_prim_type mode
)
1604 DEFINE_CASE(POINTS
);
1606 DEFINE_CASE(LINE_LOOP
);
1607 DEFINE_CASE(LINE_STRIP
);
1608 DEFINE_CASE(TRIANGLES
);
1609 DEFINE_CASE(TRIANGLE_STRIP
);
1610 DEFINE_CASE(TRIANGLE_FAN
);
1612 DEFINE_CASE(QUAD_STRIP
);
1613 DEFINE_CASE(POLYGON
);
1616 DBG("Illegal draw mode %d\n", mode
);
1618 return MALI_LINE_LOOP
;
1625 panfrost_translate_index_size(unsigned size
)
1629 return MALI_DRAW_INDEXED_UINT8
;
1632 return MALI_DRAW_INDEXED_UINT16
;
1635 return MALI_DRAW_INDEXED_UINT32
;
1638 DBG("Unknown index size %d\n", size
);
1644 static const uint8_t *
1645 panfrost_get_index_buffer_raw(const struct pipe_draw_info
*info
)
1647 if (info
->has_user_indices
) {
1648 return (const uint8_t *) info
->index
.user
;
1650 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1651 return (const uint8_t *) rsrc
->bo
->cpu
[0];
1655 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1656 * good for the duration of the draw (transient), could last longer */
1659 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1661 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1663 off_t offset
= info
->start
* info
->index_size
;
1665 if (!info
->has_user_indices
) {
1666 /* Only resources can be directly mapped */
1667 return rsrc
->bo
->gpu
[0] + offset
;
1669 /* Otherwise, we need to upload to transient memory */
1670 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1671 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1675 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1676 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1677 T idx = buffer[_idx]; \
1678 if (idx > max_index) max_index = idx; \
1679 if (idx < min_index) min_index = idx; \
1684 struct pipe_context
*pipe
,
1685 const struct pipe_draw_info
*info
)
1687 struct panfrost_context
*ctx
= pan_context(pipe
);
1689 ctx
->payload_vertex
.draw_start
= info
->start
;
1690 ctx
->payload_tiler
.draw_start
= info
->start
;
1692 int mode
= info
->mode
;
1694 /* Fallback for unsupported modes */
1696 if (!(ctx
->draw_modes
& mode
)) {
1697 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1698 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1700 if (info
->count
< 4) {
1701 /* Degenerate case? */
1705 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1706 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1711 /* Now that we have a guaranteed terminating path, find the job.
1712 * Assignment commented out to prevent unused warning */
1714 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1716 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1718 ctx
->vertex_count
= info
->count
;
1720 /* For non-indexed draws, they're the same */
1721 unsigned invocation_count
= ctx
->vertex_count
;
1723 /* For higher amounts of vertices (greater than what fits in a 16-bit
1724 * short), the other value is needed, otherwise there will be bizarre
1725 * rendering artefacts. It's not clear what these values mean yet. */
1727 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~(0x3000 | 0x18000);
1728 ctx
->payload_tiler
.prefix
.unknown_draw
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1730 if (info
->index_size
) {
1731 /* Calculate the min/max index used so we can figure out how
1732 * many times to invoke the vertex shader */
1734 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1736 int min_index
= INT_MAX
;
1739 if (info
->index_size
== 1) {
1740 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8
, info
->start
, info
->count
);
1741 } else if (info
->index_size
== 2) {
1742 const uint16_t *ibuf16
= (const uint16_t *) ibuf8
;
1743 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16
, info
->start
, info
->count
);
1744 } else if (info
->index_size
== 4) {
1745 const uint32_t *ibuf32
= (const uint32_t *) ibuf8
;
1746 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32
, info
->start
, info
->count
);
1751 /* Make sure we didn't go crazy */
1752 assert(min_index
< INT_MAX
);
1753 assert(max_index
> 0);
1754 assert(max_index
> min_index
);
1756 /* Use the corresponding values */
1757 invocation_count
= max_index
- min_index
+ 1;
1758 ctx
->payload_vertex
.draw_start
= min_index
;
1759 ctx
->payload_tiler
.draw_start
= min_index
;
1761 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1762 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1764 //assert(!info->restart_index); /* TODO: Research */
1765 assert(!info
->index_bias
);
1766 //assert(!info->min_index); /* TODO: Use value */
1768 ctx
->payload_tiler
.prefix
.unknown_draw
|= panfrost_translate_index_size(info
->index_size
);
1769 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1771 /* Index count == vertex count, if no indexing is applied, as
1772 * if it is internally indexed in the expected order */
1774 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1775 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1777 /* Reverse index state */
1778 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~MALI_DRAW_INDEXED_UINT32
;
1779 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1782 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1783 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1785 /* Fire off the draw itself */
1786 panfrost_queue_draw(ctx
);
1792 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1798 panfrost_set_scissor(struct panfrost_context
*ctx
)
1800 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1802 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
&& 0) {
1803 ctx
->viewport
->viewport0
[0] = ss
->minx
;
1804 ctx
->viewport
->viewport0
[1] = ss
->miny
;
1805 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1806 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ss
->maxy
);
1808 ctx
->viewport
->viewport0
[0] = 0;
1809 ctx
->viewport
->viewport0
[1] = 0;
1810 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ctx
->pipe_framebuffer
.width
);
1811 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ctx
->pipe_framebuffer
.height
);
1816 panfrost_create_rasterizer_state(
1817 struct pipe_context
*pctx
,
1818 const struct pipe_rasterizer_state
*cso
)
1820 struct panfrost_context
*ctx
= pan_context(pctx
);
1821 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1825 /* Bitmask, unknown meaning of the start value */
1826 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1828 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1829 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1831 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1832 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1834 if (cso
->cull_face
& PIPE_FACE_BACK
)
1835 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1841 panfrost_bind_rasterizer_state(
1842 struct pipe_context
*pctx
,
1845 struct panfrost_context
*ctx
= pan_context(pctx
);
1846 struct pipe_rasterizer_state
*cso
= hwcso
;
1848 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1852 /* If scissor test has changed, we'll need to update that now */
1853 bool update_scissor
= !ctx
->rasterizer
|| ctx
->rasterizer
->base
.scissor
!= cso
->scissor
;
1855 ctx
->rasterizer
= hwcso
;
1857 /* Actualise late changes */
1859 panfrost_set_scissor(ctx
);
1861 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1865 panfrost_create_vertex_elements_state(
1866 struct pipe_context
*pctx
,
1867 unsigned num_elements
,
1868 const struct pipe_vertex_element
*elements
)
1870 struct panfrost_context
*ctx
= pan_context(pctx
);
1871 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1873 so
->num_elements
= num_elements
;
1874 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1876 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_attr_meta
) * num_elements
, HEAP_DESCRIPTOR
);
1877 so
->hw
= (struct mali_attr_meta
*) transfer
.cpu
;
1878 so
->descriptor_ptr
= transfer
.gpu
;
1880 /* Allocate memory for the descriptor state */
1882 for (int i
= 0; i
< num_elements
; ++i
) {
1883 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1885 enum pipe_format fmt
= elements
[i
].src_format
;
1886 const struct util_format_description
*desc
= util_format_description(fmt
);
1887 so
->hw
[i
].unknown1
= 0x2;
1888 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1890 so
->hw
[i
].format
= panfrost_find_format(desc
);
1892 /* The field itself should probably be shifted over */
1893 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1900 panfrost_bind_vertex_elements_state(
1901 struct pipe_context
*pctx
,
1904 struct panfrost_context
*ctx
= pan_context(pctx
);
1906 ctx
->vertex
= hwcso
;
1907 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1911 panfrost_delete_vertex_elements_state(struct pipe_context
*pctx
, void *hwcso
)
1913 struct panfrost_vertex_state
*so
= (struct panfrost_vertex_state
*) hwcso
;
1914 unsigned bytes
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
1915 DBG("Vertex elements delete leaks descriptor (%d bytes)\n", bytes
);
1920 panfrost_create_shader_state(
1921 struct pipe_context
*pctx
,
1922 const struct pipe_shader_state
*cso
)
1924 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1927 /* Token deep copy to prevent memory corruption */
1929 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1930 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1936 panfrost_delete_shader_state(
1937 struct pipe_context
*pctx
,
1940 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1942 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1943 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1946 unsigned leak
= cso
->variant_count
* sizeof(struct mali_shader_meta
);
1947 DBG("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak
);
1953 panfrost_create_sampler_state(
1954 struct pipe_context
*pctx
,
1955 const struct pipe_sampler_state
*cso
)
1957 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1960 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1962 struct mali_sampler_descriptor sampler_descriptor
= {
1963 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1964 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1965 | translate_mip_filter(cso
->min_mip_filter
)
1968 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1969 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1970 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1971 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1973 cso
->border_color
.f
[0],
1974 cso
->border_color
.f
[1],
1975 cso
->border_color
.f
[2],
1976 cso
->border_color
.f
[3]
1978 .min_lod
= FIXED_16(0.0),
1979 .max_lod
= FIXED_16(31.0),
1983 so
->hw
= sampler_descriptor
;
1989 panfrost_bind_sampler_states(
1990 struct pipe_context
*pctx
,
1991 enum pipe_shader_type shader
,
1992 unsigned start_slot
, unsigned num_sampler
,
1995 assert(start_slot
== 0);
1997 struct panfrost_context
*ctx
= pan_context(pctx
);
1999 /* XXX: Should upload, not just copy? */
2000 ctx
->sampler_count
[shader
] = num_sampler
;
2001 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
2003 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
2007 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
2009 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
2011 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
2012 /* Make sure enable state is at least the same */
2013 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
2017 /* Check that the contents of the test are the same */
2018 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
2019 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
2021 if (!(same_func
&& same_ref
)) {
2025 /* Otherwise, we're good to go */
2030 panfrost_bind_fs_state(
2031 struct pipe_context
*pctx
,
2034 struct panfrost_context
*ctx
= pan_context(pctx
);
2039 /* Match the appropriate variant */
2041 signed variant
= -1;
2043 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2045 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2046 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
2052 if (variant
== -1) {
2053 /* No variant matched, so create a new one */
2054 variant
= variants
->variant_count
++;
2055 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2057 variants
->variants
[variant
].base
= hwcso
;
2058 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
2060 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
2061 struct panfrost_context
*ctx
= pan_context(pctx
);
2062 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2064 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2065 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
2069 /* Select this variant */
2070 variants
->active_variant
= variant
;
2072 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2073 assert(panfrost_variant_matches(ctx
, shader_state
));
2075 /* Now we have a variant selected, so compile and go */
2077 if (!shader_state
->compiled
) {
2078 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
2079 shader_state
->compiled
= true;
2083 ctx
->dirty
|= PAN_DIRTY_FS
;
2087 panfrost_bind_vs_state(
2088 struct pipe_context
*pctx
,
2091 struct panfrost_context
*ctx
= pan_context(pctx
);
2096 if (!ctx
->vs
->variants
[0].compiled
) {
2097 ctx
->vs
->variants
[0].base
= hwcso
;
2099 /* TODO DRY from above */
2100 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2101 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2102 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
2104 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
2105 ctx
->vs
->variants
[0].compiled
= true;
2109 ctx
->dirty
|= PAN_DIRTY_VS
;
2113 panfrost_set_vertex_buffers(
2114 struct pipe_context
*pctx
,
2115 unsigned start_slot
,
2116 unsigned num_buffers
,
2117 const struct pipe_vertex_buffer
*buffers
)
2119 struct panfrost_context
*ctx
= pan_context(pctx
);
2120 assert(num_buffers
<= PIPE_MAX_ATTRIBS
);
2122 /* XXX: Dirty tracking? etc */
2124 size_t sz
= sizeof(buffers
[0]) * num_buffers
;
2125 ctx
->vertex_buffers
= malloc(sz
);
2126 ctx
->vertex_buffer_count
= num_buffers
;
2127 memcpy(ctx
->vertex_buffers
, buffers
, sz
);
2129 if (ctx
->vertex_buffers
) {
2130 free(ctx
->vertex_buffers
);
2131 ctx
->vertex_buffers
= NULL
;
2134 ctx
->vertex_buffer_count
= 0;
2139 panfrost_set_constant_buffer(
2140 struct pipe_context
*pctx
,
2141 enum pipe_shader_type shader
, uint index
,
2142 const struct pipe_constant_buffer
*buf
)
2144 struct panfrost_context
*ctx
= pan_context(pctx
);
2145 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2147 size_t sz
= buf
? buf
->buffer_size
: 0;
2149 /* Free previous buffer */
2156 pbuf
->buffer
= NULL
;
2159 /* If unbinding, we're done */
2164 /* Multiple constant buffers not yet supported */
2169 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
2172 cpu
= rsrc
->bo
->cpu
[0];
2173 } else if (buf
->user_buffer
) {
2174 cpu
= buf
->user_buffer
;
2176 DBG("No constant buffer?\n");
2180 /* Copy the constant buffer into the driver context for later upload */
2182 pbuf
->buffer
= malloc(sz
);
2183 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
2187 panfrost_set_stencil_ref(
2188 struct pipe_context
*pctx
,
2189 const struct pipe_stencil_ref
*ref
)
2191 struct panfrost_context
*ctx
= pan_context(pctx
);
2192 ctx
->stencil_ref
= *ref
;
2194 /* Shader core dirty */
2195 ctx
->dirty
|= PAN_DIRTY_FS
;
2198 static struct pipe_sampler_view
*
2199 panfrost_create_sampler_view(
2200 struct pipe_context
*pctx
,
2201 struct pipe_resource
*texture
,
2202 const struct pipe_sampler_view
*template)
2204 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
2205 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2207 pipe_reference(NULL
, &texture
->reference
);
2209 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2211 so
->base
= *template;
2212 so
->base
.texture
= texture
;
2213 so
->base
.reference
.count
= 1;
2214 so
->base
.context
= pctx
;
2216 /* sampler_views correspond to texture descriptors, minus the texture
2217 * (data) itself. So, we serialise the descriptor here and cache it for
2220 /* TODO: Other types of textures */
2221 assert(template->target
== PIPE_TEXTURE_2D
);
2223 /* Make sure it's something with which we're familiar */
2224 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2226 /* TODO: Detect from format better */
2227 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2229 unsigned char user_swizzle
[4] = {
2230 template->swizzle_r
,
2231 template->swizzle_g
,
2232 template->swizzle_b
,
2236 enum mali_format format
= panfrost_find_format(desc
);
2238 struct mali_texture_descriptor texture_descriptor
= {
2239 .width
= MALI_POSITIVE(texture
->width0
),
2240 .height
= MALI_POSITIVE(texture
->height0
),
2241 .depth
= MALI_POSITIVE(texture
->depth0
),
2245 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2249 .is_not_cubemap
= 1,
2251 /* 0x11 - regular texture 2d, uncompressed tiled */
2252 /* 0x12 - regular texture 2d, uncompressed linear */
2253 /* 0x1c - AFBC compressed (internally tiled, probably) texture 2D */
2255 .usage2
= prsrc
->bo
->has_afbc
? 0x1c : (prsrc
->bo
->tiled
? 0x11 : 0x12),
2258 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2261 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2262 assert (template->u
.tex
.first_level
== 0);
2264 texture_descriptor
.nr_mipmap_levels
= template->u
.tex
.last_level
- template->u
.tex
.first_level
;
2266 so
->hw
= texture_descriptor
;
2268 return (struct pipe_sampler_view
*) so
;
2272 panfrost_set_sampler_views(
2273 struct pipe_context
*pctx
,
2274 enum pipe_shader_type shader
,
2275 unsigned start_slot
, unsigned num_views
,
2276 struct pipe_sampler_view
**views
)
2278 struct panfrost_context
*ctx
= pan_context(pctx
);
2280 assert(start_slot
== 0);
2282 ctx
->sampler_view_count
[shader
] = num_views
;
2283 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2285 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2289 panfrost_sampler_view_destroy(
2290 struct pipe_context
*pctx
,
2291 struct pipe_sampler_view
*views
)
2293 //struct panfrost_context *ctx = pan_context(pctx);
2301 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2302 const struct pipe_framebuffer_state
*fb
)
2304 struct panfrost_context
*ctx
= pan_context(pctx
);
2306 /* Flush when switching away from an FBO */
2308 if (!panfrost_is_scanout(ctx
)) {
2309 panfrost_flush(pctx
, NULL
, 0);
2312 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2313 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2314 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2315 ctx
->pipe_framebuffer
.width
= fb
->width
;
2316 ctx
->pipe_framebuffer
.height
= fb
->height
;
2318 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2319 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2321 /* check if changing cbuf */
2322 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2324 if (cb
&& (i
!= 0)) {
2325 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2330 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2335 if (ctx
->require_sfbd
)
2336 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2338 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2340 panfrost_attach_vt_framebuffer(ctx
);
2341 panfrost_new_frag_framebuffer(ctx
);
2342 panfrost_set_scissor(ctx
);
2344 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2345 bool is_scanout
= panfrost_is_scanout(ctx
);
2347 if (!is_scanout
&& !tex
->bo
->has_afbc
) {
2348 /* The blob is aggressive about enabling AFBC. As such,
2349 * it's pretty much necessary to use it here, since we
2350 * have no traces of non-compressed FBO. */
2352 panfrost_enable_afbc(ctx
, tex
, false);
2355 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2356 /* Enable transaction elimination if we can */
2357 panfrost_enable_checksum(ctx
, tex
);
2362 struct pipe_surface
*zb
= fb
->zsbuf
;
2364 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2365 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2370 if (ctx
->require_sfbd
)
2371 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2373 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2375 panfrost_attach_vt_framebuffer(ctx
);
2376 panfrost_new_frag_framebuffer(ctx
);
2377 panfrost_set_scissor(ctx
);
2379 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
);
2381 if (!tex
->bo
->has_afbc
&& !panfrost_is_scanout(ctx
))
2382 panfrost_enable_afbc(ctx
, tex
, true);
2389 panfrost_create_blend_state(struct pipe_context
*pipe
,
2390 const struct pipe_blend_state
*blend
)
2392 struct panfrost_context
*ctx
= pan_context(pipe
);
2393 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2396 /* TODO: The following features are not yet implemented */
2397 assert(!blend
->logicop_enable
);
2398 assert(!blend
->alpha_to_coverage
);
2399 assert(!blend
->alpha_to_one
);
2401 /* Compile the blend state, first as fixed-function if we can */
2403 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], &so
->equation
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2406 /* If we can't, compile a blend shader instead */
2408 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2414 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2417 struct panfrost_context
*ctx
= pan_context(pipe
);
2418 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2419 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2420 ctx
->blend
= pblend
;
2425 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2427 /* TODO: Attach color */
2429 /* Shader itself is not dirty, but the shader core is */
2430 ctx
->dirty
|= PAN_DIRTY_FS
;
2434 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2437 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2439 if (so
->has_blend_shader
) {
2440 DBG("Deleting blend state leak blend shaders bytecode\n");
2447 panfrost_set_blend_color(struct pipe_context
*pipe
,
2448 const struct pipe_blend_color
*blend_color
)
2450 struct panfrost_context
*ctx
= pan_context(pipe
);
2452 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2455 ctx
->blend_color
= *blend_color
;
2457 /* The blend mode depends on the blend constant color, due to the
2458 * fixed/programmable split. So, we're forced to regenerate the blend
2461 /* TODO: Attach color */
2466 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2467 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2469 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2473 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2476 struct panfrost_context
*ctx
= pan_context(pipe
);
2477 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2478 ctx
->depth_stencil
= depth_stencil
;
2483 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2484 * emulated in the fragment shader */
2486 if (depth_stencil
->alpha
.enabled
) {
2487 /* We need to trigger a new shader (maybe) */
2488 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2492 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2494 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2495 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2497 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2498 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2500 /* Depth state (TODO: Refactor) */
2501 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2503 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2505 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2506 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2508 /* Bounds test not implemented */
2509 assert(!depth_stencil
->depth
.bounds_test
);
2511 ctx
->dirty
|= PAN_DIRTY_FS
;
2515 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2521 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2522 unsigned sample_mask
)
2527 panfrost_set_clip_state(struct pipe_context
*pipe
,
2528 const struct pipe_clip_state
*clip
)
2530 //struct panfrost_context *panfrost = pan_context(pipe);
2534 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2535 unsigned start_slot
,
2536 unsigned num_viewports
,
2537 const struct pipe_viewport_state
*viewports
)
2539 struct panfrost_context
*ctx
= pan_context(pipe
);
2541 assert(start_slot
== 0);
2542 assert(num_viewports
== 1);
2544 ctx
->pipe_viewport
= *viewports
;
2547 /* TODO: What if not centered? */
2548 float w
= abs(viewports
->scale
[0]) * 2.0;
2549 float h
= abs(viewports
->scale
[1]) * 2.0;
2551 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2552 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2557 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2558 unsigned start_slot
,
2559 unsigned num_scissors
,
2560 const struct pipe_scissor_state
*scissors
)
2562 struct panfrost_context
*ctx
= pan_context(pipe
);
2564 assert(start_slot
== 0);
2565 assert(num_scissors
== 1);
2567 ctx
->scissor
= *scissors
;
2569 panfrost_set_scissor(ctx
);
2573 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2574 const struct pipe_poly_stipple
*stipple
)
2576 //struct panfrost_context *panfrost = pan_context(pipe);
2580 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2583 //struct panfrost_context *panfrost = pan_context(pipe);
2587 panfrost_destroy(struct pipe_context
*pipe
)
2589 struct panfrost_context
*panfrost
= pan_context(pipe
);
2590 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2592 if (panfrost
->blitter
)
2593 util_blitter_destroy(panfrost
->blitter
);
2595 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2596 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2597 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2598 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2599 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2602 static struct pipe_query
*
2603 panfrost_create_query(struct pipe_context
*pipe
,
2607 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2612 return (struct pipe_query
*) q
;
2616 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2622 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2624 struct panfrost_context
*ctx
= pan_context(pipe
);
2625 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2627 switch (query
->type
) {
2628 case PIPE_QUERY_OCCLUSION_COUNTER
:
2629 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2630 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2632 /* Allocate a word for the query results to be stored */
2633 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2635 ctx
->occlusion_query
= query
;
2641 DBG("Skipping query %d\n", query
->type
);
2649 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2651 struct panfrost_context
*ctx
= pan_context(pipe
);
2652 ctx
->occlusion_query
= NULL
;
2657 panfrost_get_query_result(struct pipe_context
*pipe
,
2658 struct pipe_query
*q
,
2660 union pipe_query_result
*vresult
)
2663 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2665 /* We need to flush out the jobs to actually run the counter, TODO
2666 * check wait, TODO wallpaper after if needed */
2668 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2670 switch (query
->type
) {
2671 case PIPE_QUERY_OCCLUSION_COUNTER
:
2672 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2673 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2674 /* Read back the query results */
2675 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2676 unsigned passed
= *result
;
2678 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2679 vresult
->u64
= passed
;
2681 vresult
->b
= !!passed
;
2687 DBG("Skipped query get %d\n", query
->type
);
2695 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2697 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2698 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2700 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2701 /* Allocate the beginning of the transient pool */
2702 int entry_size
= (1 << 22); /* 4MB */
2704 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2705 ctx
->transient_pools
[i
].entry_count
= 1;
2707 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2710 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2711 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2712 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2713 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2714 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2718 /* New context creation, which also does hardware initialisation since I don't
2719 * know the better way to structure this :smirk: */
2721 struct pipe_context
*
2722 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2724 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2725 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2726 memset(ctx
, 0, sizeof(*ctx
));
2727 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2730 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2731 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means t76x or less */
2732 ctx
->require_sfbd
= gpu_id
< 0x0750; /* t76x is the first to support MFD */
2734 gallium
->screen
= screen
;
2736 gallium
->destroy
= panfrost_destroy
;
2738 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2740 gallium
->flush
= panfrost_flush
;
2741 gallium
->clear
= panfrost_clear
;
2742 gallium
->draw_vbo
= panfrost_draw_vbo
;
2744 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2745 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2747 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2749 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2750 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2751 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2753 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2754 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2755 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2757 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2758 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2759 gallium
->delete_vertex_elements_state
= panfrost_delete_vertex_elements_state
;
2761 gallium
->create_fs_state
= panfrost_create_shader_state
;
2762 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2763 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2765 gallium
->create_vs_state
= panfrost_create_shader_state
;
2766 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2767 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2769 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2770 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2771 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2773 gallium
->create_blend_state
= panfrost_create_blend_state
;
2774 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2775 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2777 gallium
->set_blend_color
= panfrost_set_blend_color
;
2779 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2780 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2781 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2783 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2785 gallium
->set_clip_state
= panfrost_set_clip_state
;
2786 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2787 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2788 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2789 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2791 gallium
->create_query
= panfrost_create_query
;
2792 gallium
->destroy_query
= panfrost_destroy_query
;
2793 gallium
->begin_query
= panfrost_begin_query
;
2794 gallium
->end_query
= panfrost_end_query
;
2795 gallium
->get_query_result
= panfrost_get_query_result
;
2797 panfrost_resource_context_init(gallium
);
2799 pscreen
->driver
->init_context(ctx
);
2801 panfrost_setup_hardware(ctx
);
2804 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2805 gallium
->const_uploader
= gallium
->stream_uploader
;
2806 assert(gallium
->stream_uploader
);
2808 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2809 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2811 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2813 ctx
->blitter
= util_blitter_create(gallium
);
2814 assert(ctx
->blitter
);
2816 /* Prepare for render! */
2818 panfrost_job_init(ctx
);
2819 panfrost_emit_vertex_payload(ctx
);
2820 panfrost_emit_tiler_payload(ctx
);
2821 panfrost_invalidate_frame(ctx
);
2822 panfrost_viewport(ctx
, 0.0, 1.0, 0, 0, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
2823 panfrost_default_shader_backend(ctx
);
2824 panfrost_generate_space_filler_indices();