2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
44 #include "pan_wallpaper.h"
46 #ifdef DUMP_PERFORMANCE_COUNTERS
47 static int performance_counter_number
= 0;
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 #define SET_BIT(lval, bit, cond) \
59 /* TODO: Sample size, etc */
61 /* True for t6XX, false for t8xx. TODO: Run-time settable for automatic
62 * hardware configuration. */
64 static bool is_t6xx
= false;
66 /* If set, we'll require the use of single render-target framebuffer
67 * descriptors (SFBD), for older hardware -- specifically, <T760 hardware, If
68 * false, we'll use the MFBD no matter what. New hardware -does- retain support
69 * for SFBD, and in theory we could flip between them on a per-RT basis, but
70 * there's no real advantage to doing so */
72 static bool require_sfbd
= false;
75 panfrost_set_framebuffer_msaa(struct panfrost_context
*ctx
, bool enabled
)
77 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, enabled
);
78 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !enabled
);
81 SET_BIT(ctx
->fragment_sfbd
.format
, MALI_FRAMEBUFFER_MSAA_A
| MALI_FRAMEBUFFER_MSAA_B
, enabled
);
83 SET_BIT(ctx
->fragment_rts
[0].format
, MALI_MFBD_FORMAT_MSAA
, enabled
);
85 SET_BIT(ctx
->fragment_mfbd
.unk1
, (1 << 4) | (1 << 1), enabled
);
88 ctx
->fragment_mfbd
.rt_count_2
= enabled
? 4 : 1;
92 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
93 * indepdent between color buffers and depth/stencil). To enable, we allocate
94 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
95 * edit the fragment job here. This routine should be called ONCE per
96 * AFBC-compressed buffer, rather than on every frame. */
99 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
102 printf("AFBC not supported yet on SFBD\n");
106 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
107 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
108 /* AFBC metadata is 16 bytes per tile */
109 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
110 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
111 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
112 int stride
= bytes_per_pixel
* rsrc
->base
.width0
; /* TODO: Alignment? */
114 stride
*= 2; /* TODO: Should this be carried over? */
115 int main_size
= stride
* rsrc
->base
.height0
;
116 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
118 /* Allocate the AFBC slab itself, large enough to hold the above */
119 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
120 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
123 rsrc
->bo
->has_afbc
= true;
125 /* Compressed textured reads use a tagged pointer to the metadata */
127 rsrc
->bo
->gpu
[0] = rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
128 rsrc
->bo
->cpu
[0] = rsrc
->bo
->afbc_slab
.cpu
;
132 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
134 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
135 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
136 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
137 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
139 /* 8 byte checksum per tile */
140 rsrc
->bo
->checksum_stride
= tile_w
* 8;
141 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
142 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
144 rsrc
->bo
->has_checksum
= true;
147 /* ..by contrast, this routine runs for every FRAGMENT job, but does no
148 * allocation. AFBC is enabled on a per-surface basis */
151 panfrost_set_fragment_afbc(struct panfrost_context
*ctx
)
153 for (int cb
= 0; cb
< ctx
->pipe_framebuffer
.nr_cbufs
; ++cb
) {
154 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[cb
]->texture
;
156 /* Non-AFBC is the default */
157 if (!rsrc
->bo
->has_afbc
)
161 fprintf(stderr
, "Color AFBC not supported on SFBD\n");
165 /* Enable AFBC for the render target */
166 ctx
->fragment_rts
[0].afbc
.metadata
= rsrc
->bo
->afbc_slab
.gpu
;
167 ctx
->fragment_rts
[0].afbc
.stride
= 0;
168 ctx
->fragment_rts
[0].afbc
.unk
= 0x30009;
170 ctx
->fragment_rts
[0].format
|= MALI_MFBD_FORMAT_AFBC
;
172 /* Point rendering to our special framebuffer */
173 ctx
->fragment_rts
[0].framebuffer
= rsrc
->bo
->afbc_slab
.gpu
+ rsrc
->bo
->afbc_metadata_size
;
175 /* WAT? Stride is diff from the scanout case */
176 ctx
->fragment_rts
[0].framebuffer_stride
= ctx
->pipe_framebuffer
.width
* 2 * 4;
179 /* Enable depth/stencil AFBC for the framebuffer (not the render target) */
180 if (ctx
->pipe_framebuffer
.zsbuf
) {
181 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
;
183 if (rsrc
->bo
->has_afbc
) {
185 fprintf(stderr
, "Depth AFBC not supported on SFBD\n");
189 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
191 ctx
->fragment_extra
.ds_afbc
.depth_stencil_afbc_metadata
= rsrc
->bo
->afbc_slab
.gpu
;
192 ctx
->fragment_extra
.ds_afbc
.depth_stencil_afbc_stride
= 0;
194 ctx
->fragment_extra
.ds_afbc
.depth_stencil
= rsrc
->bo
->afbc_slab
.gpu
+ rsrc
->bo
->afbc_metadata_size
;
196 ctx
->fragment_extra
.ds_afbc
.zero1
= 0x10009;
197 ctx
->fragment_extra
.ds_afbc
.padding
= 0x1000;
199 ctx
->fragment_extra
.unk
= 0x435; /* General 0x400 in all unks. 0x5 for depth/stencil. 0x10 for AFBC encoded depth stencil. Unclear where the 0x20 is from */
201 ctx
->fragment_mfbd
.unk3
|= 0x400;
205 /* For the special case of a depth-only FBO, we need to attach a dummy render target */
207 if (ctx
->pipe_framebuffer
.nr_cbufs
== 0) {
209 fprintf(stderr
, "Depth-only FBO not supported on SFBD\n");
213 ctx
->fragment_rts
[0].format
= 0x80008000;
214 ctx
->fragment_rts
[0].framebuffer
= 0;
215 ctx
->fragment_rts
[0].framebuffer_stride
= 0;
219 /* Framebuffer descriptor */
222 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
224 fb
->width
= MALI_POSITIVE(w
);
225 fb
->height
= MALI_POSITIVE(h
);
227 /* No idea why this is needed, but it's how resolution_check is
228 * calculated. It's not clear to us yet why the hardware wants this.
229 * The formula itself was discovered mostly by manual bruteforce and
230 * aggressive algebraic simplification. */
232 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
235 static struct mali_single_framebuffer
236 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
238 struct mali_single_framebuffer framebuffer
= {
240 .format
= 0x30000000,
241 .clear_flags
= 0x1000,
242 .unknown_address_0
= ctx
->scratchpad
.gpu
,
243 .unknown_address_1
= ctx
->misc_0
.gpu
,
244 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
246 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
247 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
250 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
255 static struct bifrost_framebuffer
256 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
258 struct bifrost_framebuffer framebuffer
= {
259 .tiler_meta
= 0xf00000c600,
261 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
262 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
263 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
264 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
269 .rt_count_1
= MALI_POSITIVE(1),
274 /* Presumably corresponds to unknown_address_X of SFBD */
275 .scratchpad
= ctx
->scratchpad
.gpu
,
276 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
277 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ /*ctx->misc_0.size*/40960, /* Size depends on the size of the framebuffer and the number of vertices */
279 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
280 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
286 /* Are we currently rendering to the screen (rather than an FBO)? */
289 panfrost_is_scanout(struct panfrost_context
*ctx
)
291 /* If there is no color buffer, it's an FBO */
292 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
295 /* If we're too early that no framebuffer was sent, it's scanout */
296 if (!ctx
->pipe_framebuffer
.cbufs
[0])
299 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
300 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
301 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
304 /* The above function is for generalised fbd emission, used in both fragment as
305 * well as vertex/tiler payloads. This payload is specific to fragment
309 panfrost_new_frag_framebuffer(struct panfrost_context
*ctx
)
311 mali_ptr framebuffer
;
314 if (ctx
->pipe_framebuffer
.nr_cbufs
> 0) {
315 framebuffer
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[0]->texture
)->bo
->gpu
[0];
316 stride
= util_format_get_stride(ctx
->pipe_framebuffer
.cbufs
[0]->format
, ctx
->pipe_framebuffer
.width
);
318 /* Depth-only framebuffer -> dummy RT */
323 /* The default is upside down from OpenGL's perspective. */
324 if (panfrost_is_scanout(ctx
)) {
325 framebuffer
+= stride
* (ctx
->pipe_framebuffer
.height
- 1);
330 struct mali_single_framebuffer fb
= panfrost_emit_sfbd(ctx
);
332 fb
.framebuffer
= framebuffer
;
335 fb
.format
= 0xb84e0281; /* RGB32, no MSAA */
336 memcpy(&ctx
->fragment_sfbd
, &fb
, sizeof(fb
));
338 struct bifrost_framebuffer fb
= panfrost_emit_mfbd(ctx
);
344 struct bifrost_render_target rt
= {
346 .format
= 0x860a8899, /* RGBA32, no MSAA */
347 .framebuffer
= framebuffer
,
348 .framebuffer_stride
= (stride
/ 16) & 0xfffffff,
351 memcpy(&ctx
->fragment_rts
[0], &rt
, sizeof(rt
));
353 memset(&ctx
->fragment_extra
, 0, sizeof(ctx
->fragment_extra
));
354 memcpy(&ctx
->fragment_mfbd
, &fb
, sizeof(fb
));
358 /* Maps float 0.0-1.0 to int 0x00-0xFF */
360 normalised_float_to_u8(float f
)
362 return (uint8_t) (int) (f
* 255.0f
);
366 panfrost_clear_sfbd(struct panfrost_context
*ctx
,
370 uint32_t packed_color
,
371 double depth
, unsigned stencil
374 struct mali_single_framebuffer
*sfbd
= &ctx
->fragment_sfbd
;
377 sfbd
->clear_color_1
= packed_color
;
378 sfbd
->clear_color_2
= packed_color
;
379 sfbd
->clear_color_3
= packed_color
;
380 sfbd
->clear_color_4
= packed_color
;
384 sfbd
->clear_depth_1
= depth
;
385 sfbd
->clear_depth_2
= depth
;
386 sfbd
->clear_depth_3
= depth
;
387 sfbd
->clear_depth_4
= depth
;
391 sfbd
->clear_stencil
= stencil
;
397 sfbd
->depth_buffer
= ctx
->depth_stencil_buffer
.gpu
;
398 sfbd
->depth_buffer_enable
= MALI_DEPTH_STENCIL_ENABLE
;
402 sfbd
->stencil_buffer
= ctx
->depth_stencil_buffer
.gpu
;
403 sfbd
->stencil_buffer_enable
= MALI_DEPTH_STENCIL_ENABLE
;
406 /* Set flags based on what has been cleared, for the SFBD case */
407 /* XXX: What do these flags mean? */
408 int clear_flags
= 0x101100;
410 if (clear_color
&& clear_depth
&& clear_stencil
) {
411 /* On a tiler like this, it's fastest to clear all three buffers at once */
413 clear_flags
|= MALI_CLEAR_FAST
;
415 clear_flags
|= MALI_CLEAR_SLOW
;
418 clear_flags
|= MALI_CLEAR_SLOW_STENCIL
;
421 sfbd
->clear_flags
= clear_flags
;
425 panfrost_clear_mfbd(struct panfrost_context
*ctx
,
429 uint32_t packed_color
,
430 double depth
, unsigned stencil
433 struct bifrost_render_target
*buffer_color
= &ctx
->fragment_rts
[0];
434 struct bifrost_framebuffer
*buffer_ds
= &ctx
->fragment_mfbd
;
437 buffer_color
->clear_color_1
= packed_color
;
438 buffer_color
->clear_color_2
= packed_color
;
439 buffer_color
->clear_color_3
= packed_color
;
440 buffer_color
->clear_color_4
= packed_color
;
444 buffer_ds
->clear_depth
= depth
;
448 buffer_ds
->clear_stencil
= stencil
;
451 if (clear_depth
|| clear_stencil
) {
452 /* Setup combined 24/8 depth/stencil */
453 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
454 //ctx->fragment_extra.unk = /*0x405*/0x404;
455 ctx
->fragment_extra
.unk
= 0x405;
456 ctx
->fragment_extra
.ds_linear
.depth
= ctx
->depth_stencil_buffer
.gpu
;
457 ctx
->fragment_extra
.ds_linear
.depth_stride
= ctx
->pipe_framebuffer
.width
* 4;
463 struct pipe_context
*pipe
,
465 const union pipe_color_union
*color
,
466 double depth
, unsigned stencil
)
468 struct panfrost_context
*ctx
= pan_context(pipe
);
471 printf("Warning: clear color null?\n");
475 /* Save settings for FBO switch */
476 ctx
->last_clear
.buffers
= buffers
;
477 ctx
->last_clear
.color
= color
;
478 ctx
->last_clear
.depth
= depth
;
479 ctx
->last_clear
.depth
= depth
;
481 bool clear_color
= buffers
& PIPE_CLEAR_COLOR
;
482 bool clear_depth
= buffers
& PIPE_CLEAR_DEPTH
;
483 bool clear_stencil
= buffers
& PIPE_CLEAR_STENCIL
;
485 /* Remember that we've done something */
486 ctx
->frame_cleared
= true;
488 /* Alpha clear only meaningful without alpha channel */
489 bool has_alpha
= ctx
->pipe_framebuffer
.nr_cbufs
&& util_format_has_alpha(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
490 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
492 uint32_t packed_color
=
493 (normalised_float_to_u8(clear_alpha
) << 24) |
494 (normalised_float_to_u8(color
->f
[2]) << 16) |
495 (normalised_float_to_u8(color
->f
[1]) << 8) |
496 (normalised_float_to_u8(color
->f
[0]) << 0);
499 panfrost_clear_sfbd(ctx
, clear_color
, clear_depth
, clear_stencil
, packed_color
, depth
, stencil
);
501 panfrost_clear_mfbd(ctx
, clear_color
, clear_depth
, clear_stencil
, packed_color
, depth
, stencil
);
506 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
508 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
509 struct bifrost_render_target rts_list
[] = {
514 .framebuffer
= ctx
->misc_0
.gpu
,
519 /* Allocate memory for the three components */
520 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
521 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
523 /* Opaque 1024-block */
524 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
526 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
527 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
529 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
533 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
535 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
539 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
541 mali_ptr framebuffer
= require_sfbd
?
542 panfrost_attach_vt_sfbd(ctx
) :
543 panfrost_attach_vt_mfbd(ctx
);
545 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
546 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
550 panfrost_viewport(struct panfrost_context
*ctx
,
553 int viewport_x0
, int viewport_y0
,
554 int viewport_x1
, int viewport_y1
)
556 /* Viewport encoding is asymmetric. Purpose of the floats is unknown? */
558 struct mali_viewport ret
= {
568 .depth_range_n
= depth_range_n
,
569 .depth_range_f
= depth_range_f
,
571 .viewport0
= { viewport_x0
, viewport_y0
},
572 .viewport1
= { MALI_POSITIVE(viewport_x1
), MALI_POSITIVE(viewport_y1
) },
575 memcpy(ctx
->viewport
, &ret
, sizeof(ret
));
578 /* Reset per-frame context, called on context initialisation as well as after
579 * flushing a frame */
582 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
584 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
585 printf("Uploaded transient %d bytes\n", transient_count
);
587 /* Rotate cmdstream */
588 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
589 ctx
->cmdstream_i
= 0;
592 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
594 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
596 panfrost_new_frag_framebuffer(ctx
);
598 /* Reset varyings allocated */
599 ctx
->varying_height
= 0;
601 /* The transient cmdstream is dirty every frame; the only bits worth preserving
602 * (textures, shaders, etc) are in other buffers anyways */
604 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
605 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
607 /* Regenerate payloads */
608 panfrost_attach_vt_framebuffer(ctx
);
611 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
614 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
617 /* In practice, every field of these payloads should be configurable
618 * arbitrarily, which means these functions are basically catch-all's for
619 * as-of-yet unwavering unknowns */
622 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
624 struct midgard_payload_vertex_tiler payload
= {
626 .workgroups_z_shift
= 32,
627 .workgroups_x_shift_2
= 0x2,
628 .workgroups_x_shift_3
= 0x5,
630 .gl_enables
= 0x4 | (is_t6xx
? 0 : 0x2),
633 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
637 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
639 struct midgard_payload_vertex_tiler payload
= {
641 .workgroups_z_shift
= 32,
642 .workgroups_x_shift_2
= 0x2,
643 .workgroups_x_shift_3
= 0x6,
645 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
649 /* Reserve the viewport */
650 struct panfrost_transfer t
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_viewport
), HEAP_DESCRIPTOR
);
651 ctx
->viewport
= (struct mali_viewport
*) t
.cpu
;
652 payload
.postfix
.viewport
= t
.gpu
;
654 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
658 translate_tex_wrap(enum pipe_tex_wrap w
)
661 case PIPE_TEX_WRAP_REPEAT
:
662 return MALI_WRAP_REPEAT
;
664 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
665 return MALI_WRAP_CLAMP_TO_EDGE
;
667 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
668 return MALI_WRAP_CLAMP_TO_BORDER
;
670 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
671 return MALI_WRAP_MIRRORED_REPEAT
;
680 translate_tex_filter(enum pipe_tex_filter f
)
683 case PIPE_TEX_FILTER_NEAREST
:
686 case PIPE_TEX_FILTER_LINEAR
:
696 translate_mip_filter(enum pipe_tex_mipfilter f
)
698 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
702 panfrost_translate_compare_func(enum pipe_compare_func in
)
705 case PIPE_FUNC_NEVER
:
706 return MALI_FUNC_NEVER
;
709 return MALI_FUNC_LESS
;
711 case PIPE_FUNC_EQUAL
:
712 return MALI_FUNC_EQUAL
;
714 case PIPE_FUNC_LEQUAL
:
715 return MALI_FUNC_LEQUAL
;
717 case PIPE_FUNC_GREATER
:
718 return MALI_FUNC_GREATER
;
720 case PIPE_FUNC_NOTEQUAL
:
721 return MALI_FUNC_NOTEQUAL
;
723 case PIPE_FUNC_GEQUAL
:
724 return MALI_FUNC_GEQUAL
;
726 case PIPE_FUNC_ALWAYS
:
727 return MALI_FUNC_ALWAYS
;
731 return 0; /* Unreachable */
735 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
738 case PIPE_FUNC_NEVER
:
739 return MALI_ALT_FUNC_NEVER
;
742 return MALI_ALT_FUNC_LESS
;
744 case PIPE_FUNC_EQUAL
:
745 return MALI_ALT_FUNC_EQUAL
;
747 case PIPE_FUNC_LEQUAL
:
748 return MALI_ALT_FUNC_LEQUAL
;
750 case PIPE_FUNC_GREATER
:
751 return MALI_ALT_FUNC_GREATER
;
753 case PIPE_FUNC_NOTEQUAL
:
754 return MALI_ALT_FUNC_NOTEQUAL
;
756 case PIPE_FUNC_GEQUAL
:
757 return MALI_ALT_FUNC_GEQUAL
;
759 case PIPE_FUNC_ALWAYS
:
760 return MALI_ALT_FUNC_ALWAYS
;
764 return 0; /* Unreachable */
768 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
771 case PIPE_STENCIL_OP_KEEP
:
772 return MALI_STENCIL_KEEP
;
774 case PIPE_STENCIL_OP_ZERO
:
775 return MALI_STENCIL_ZERO
;
777 case PIPE_STENCIL_OP_REPLACE
:
778 return MALI_STENCIL_REPLACE
;
780 case PIPE_STENCIL_OP_INCR
:
781 return MALI_STENCIL_INCR
;
783 case PIPE_STENCIL_OP_DECR
:
784 return MALI_STENCIL_DECR
;
786 case PIPE_STENCIL_OP_INCR_WRAP
:
787 return MALI_STENCIL_INCR_WRAP
;
789 case PIPE_STENCIL_OP_DECR_WRAP
:
790 return MALI_STENCIL_DECR_WRAP
;
792 case PIPE_STENCIL_OP_INVERT
:
793 return MALI_STENCIL_INVERT
;
797 return 0; /* Unreachable */
801 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
803 out
->ref
= 0; /* Gallium gets it from elsewhere */
805 out
->mask
= in
->valuemask
;
806 out
->func
= panfrost_translate_compare_func(in
->func
);
807 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
808 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
809 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
813 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
815 struct mali_shader_meta shader
= {
816 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
818 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
819 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
823 shader
.unknown2_4
|= 0x10;
826 struct pipe_stencil_state default_stencil
= {
828 .func
= PIPE_FUNC_ALWAYS
,
829 .fail_op
= MALI_STENCIL_KEEP
,
830 .zfail_op
= MALI_STENCIL_KEEP
,
831 .zpass_op
= MALI_STENCIL_KEEP
,
836 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
837 shader
.stencil_mask_front
= default_stencil
.writemask
;
839 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
840 shader
.stencil_mask_back
= default_stencil
.writemask
;
842 if (default_stencil
.enabled
)
843 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
845 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
848 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
849 * graphics command stream. It should be called once per draw, accordding to
850 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
851 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
854 struct panfrost_transfer
855 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
857 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
858 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
860 struct mali_job_descriptor_header job
= {
861 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
862 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
864 .job_descriptor_size
= 1,
868 /* Only non-elided tiler jobs have dependencies which are known at this point */
870 if (is_tiler
&& !is_elided_tiler
) {
871 /* Tiler jobs depend on vertex jobs */
873 job
.job_dependency_index_1
= draw_job_index
;
875 /* Tiler jobs also depend on the previous tiler job */
878 job
.job_dependency_index_2
= draw_job_index
- 1;
881 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
883 /* There's some padding hacks on 32-bit */
890 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
891 memcpy(transfer
.cpu
, &job
, sizeof(job
));
892 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
896 /* Generates a set value job. It's unclear what exactly this does, why it's
897 * necessary, and when to call it. */
900 panfrost_set_value_job(struct panfrost_context
*ctx
)
902 struct mali_job_descriptor_header job
= {
903 .job_type
= JOB_TYPE_SET_VALUE
,
904 .job_descriptor_size
= 1,
905 .job_index
= 1 + (2 * ctx
->draw_count
),
908 struct mali_payload_set_value payload
= {
909 .out
= ctx
->misc_0
.gpu
,
913 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
914 memcpy(transfer
.cpu
, &job
, sizeof(job
));
915 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
917 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
918 ctx
->set_value_job
= transfer
.gpu
;
921 /* Generate a fragment job. This should be called once per frame. (According to
922 * presentations, this is supposed to correspond to eglSwapBuffers) */
925 panfrost_fragment_job(struct panfrost_context
*ctx
)
927 /* Update fragment FBD */
928 panfrost_set_fragment_afbc(ctx
);
930 if (ctx
->pipe_framebuffer
.nr_cbufs
== 1) {
931 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[0]->texture
;
933 if (rsrc
->bo
->has_checksum
) {
935 fprintf(stderr
, "Checksumming not supported on SFBD\n");
939 int stride
= util_format_get_stride(rsrc
->base
.format
, rsrc
->base
.width0
);
941 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
942 ctx
->fragment_extra
.unk
|= 0x420;
943 ctx
->fragment_extra
.checksum_stride
= rsrc
->bo
->checksum_stride
;
944 ctx
->fragment_extra
.checksum
= rsrc
->bo
->gpu
[0] + stride
* rsrc
->base
.height0
;
948 /* The frame is complete and therefore the framebuffer descriptor is
949 * ready for linkage and upload */
951 size_t sz
= require_sfbd
? sizeof(struct mali_single_framebuffer
) : (sizeof(struct bifrost_framebuffer
) + sizeof(struct bifrost_fb_extra
) + sizeof(struct bifrost_render_target
) * 1);
952 struct panfrost_transfer fbd_t
= panfrost_allocate_transient(ctx
, sz
);
956 /* Upload just the SFBD all at once */
957 memcpy(fbd_t
.cpu
, &ctx
->fragment_sfbd
, sizeof(ctx
->fragment_sfbd
));
958 offset
+= sizeof(ctx
->fragment_sfbd
);
960 /* Upload the MFBD header */
961 memcpy(fbd_t
.cpu
, &ctx
->fragment_mfbd
, sizeof(ctx
->fragment_mfbd
));
962 offset
+= sizeof(ctx
->fragment_mfbd
);
964 /* Upload extra framebuffer info if necessary */
965 if (ctx
->fragment_mfbd
.unk3
& MALI_MFBD_EXTRA
) {
966 memcpy(fbd_t
.cpu
+ offset
, &ctx
->fragment_extra
, sizeof(struct bifrost_fb_extra
));
967 offset
+= sizeof(struct bifrost_fb_extra
);
970 /* Upload (single) render target */
971 memcpy(fbd_t
.cpu
+ offset
, &ctx
->fragment_rts
[0], sizeof(struct bifrost_render_target
) * 1);
974 /* Generate the fragment (frame) job */
976 struct mali_job_descriptor_header header
= {
977 .job_type
= JOB_TYPE_FRAGMENT
,
980 .job_descriptor_size
= 1
984 struct mali_payload_fragment payload
= {
985 .min_tile_coord
= MALI_COORDINATE_TO_TILE_MIN(0, 0),
986 .max_tile_coord
= MALI_COORDINATE_TO_TILE_MAX(ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
),
987 .framebuffer
= fbd_t
.gpu
| (require_sfbd
? MALI_SFBD
: MALI_MFBD
),
990 if (!require_sfbd
&& ctx
->fragment_mfbd
.unk3
& MALI_MFBD_EXTRA
) {
991 /* Signal that there is an extra portion of the framebuffer
994 payload
.framebuffer
|= 2;
997 /* Normally, there should be no padding. However, fragment jobs are
998 * shared with 64-bit Bifrost systems, and accordingly there is 4-bytes
999 * of zero padding in between. */
1001 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(header
) + sizeof(payload
));
1002 memcpy(transfer
.cpu
, &header
, sizeof(header
));
1003 memcpy(transfer
.cpu
+ sizeof(header
), &payload
, sizeof(payload
));
1004 return transfer
.gpu
;
1007 /* Emits attributes and varying descriptors, which should be called every draw,
1008 * excepting some obscure circumstances */
1011 panfrost_emit_vertex_data(struct panfrost_context
*ctx
)
1013 /* TODO: Only update the dirtied buffers */
1014 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
1015 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
1017 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
1019 for (int i
= 0; i
< ctx
->vertex_buffer_count
; ++i
) {
1020 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
1021 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
1023 /* Let's figure out the layout of the attributes in memory so
1024 * we can be smart about size computation. The idea is to
1025 * figure out the maximum src_offset, which tells us the latest
1026 * spot a vertex could start. Meanwhile, we figure out the size
1027 * of the attribute memory (assuming interleaved
1028 * representation) and tack on the max src_offset for a
1029 * reasonably good upper bound on the size.
1031 * Proving correctness is left as an exercise to the reader.
1034 unsigned max_src_offset
= 0;
1036 for (unsigned j
= 0; j
< ctx
->vertex
->num_elements
; ++j
) {
1037 if (ctx
->vertex
->pipe
[j
].vertex_buffer_index
!= i
) continue;
1038 max_src_offset
= MAX2(max_src_offset
, ctx
->vertex
->pipe
[j
].src_offset
);
1041 /* Offset vertex count by draw_start to make sure we upload enough */
1042 attrs
[i
].stride
= buf
->stride
;
1043 attrs
[i
].size
= buf
->stride
* (ctx
->payload_vertex
.draw_start
+ invocation_count
) + max_src_offset
;
1045 /* Vertex elements are -already- GPU-visible, at
1046 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
1047 * it is not, for now we have to duplicate the buffer. */
1049 mali_ptr effective_address
= (rsrc
->bo
->gpu
[0] + buf
->buffer_offset
);
1051 if (effective_address
& 0x3F) {
1052 attrs
[i
].elements
= panfrost_upload_transient(ctx
, rsrc
->bo
->cpu
[0] + buf
->buffer_offset
, attrs
[i
].size
) | 1;
1054 attrs
[i
].elements
= effective_address
| 1;
1058 struct panfrost_varyings
*vars
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
1060 for (int i
= 0; i
< vars
->varying_buffer_count
; ++i
) {
1061 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
1063 varyings
[i
].elements
= varying_address
| 1;
1064 varyings
[i
].stride
= vars
->varyings_stride
[i
];
1065 varyings
[i
].size
= vars
->varyings_stride
[i
] * invocation_count
;
1067 /* If this varying has to be linked somewhere, do it now. See
1068 * pan_assemble.c for the indices. TODO: Use a more generic
1069 * linking interface */
1073 ctx
->payload_tiler
.postfix
.position_varying
= varying_address
;
1074 } else if (i
== 2) {
1076 ctx
->payload_tiler
.primitive_size
.pointer
= varying_address
;
1079 /* Varyings appear to need 64-byte alignment */
1080 ctx
->varying_height
+= ALIGN(varyings
[i
].size
, 64);
1082 /* Ensure that we fit */
1083 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
1086 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, ctx
->vertex_buffer_count
* sizeof(union mali_attr
));
1088 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, vars
->varying_buffer_count
* sizeof(union mali_attr
));
1089 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
1090 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
1093 /* Go through dirty flags and actualise them in the cmdstream. */
1096 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1098 if (with_vertex_data
) {
1099 panfrost_emit_vertex_data(ctx
);
1102 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1103 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1104 panfrost_set_framebuffer_msaa(ctx
, ctx
->rasterizer
->base
.multisample
);
1107 if (ctx
->occlusion_query
) {
1108 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1109 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1112 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1115 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1117 /* Late shader descriptor assignments */
1118 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1119 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1122 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1124 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1126 /* Varying descriptor is tied to the vertex shader. Also the
1127 * fragment shader, I suppose, but it's generated with the
1128 * vertex shader so */
1130 struct panfrost_varyings
*varyings
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
1132 ctx
->payload_vertex
.postfix
.varying_meta
= varyings
->varyings_descriptor
;
1133 ctx
->payload_tiler
.postfix
.varying_meta
= varyings
->varyings_descriptor_fragment
;
1136 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1137 /* Check if we need to link the gl_PointSize varying */
1139 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1141 bool needs_gl_point_size
= vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
1143 if (!needs_gl_point_size
) {
1144 /* If the size is constant, write it out. Otherwise,
1145 * don't touch primitive_size (since we would clobber
1146 * the pointer there) */
1148 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1151 /* Set the flag for varying (pointer) point size if the shader needs that */
1152 SET_BIT(ctx
->payload_tiler
.prefix
.unknown_draw
, MALI_DRAW_VARYING_SIZE
, needs_gl_point_size
);
1155 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1157 ctx
->dirty
|= PAN_DIRTY_FS
;
1159 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1161 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1163 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1166 COPY(attribute_count
);
1167 COPY(varying_count
);
1168 COPY(midgard1
.uniform_count
);
1169 COPY(midgard1
.work_count
);
1170 COPY(midgard1
.unknown2
);
1173 /* If there is a blend shader, work registers are shared */
1175 if (ctx
->blend
->has_blend_shader
)
1176 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1178 /* Set late due to depending on render state */
1179 /* The one at the end seems to mean "1 UBO" */
1180 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1182 /* Assign texture/sample count right before upload */
1183 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1184 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1186 /* Assign the stencil refs late */
1187 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1188 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1190 /* CAN_DISCARD should be set if the fragment shader possibly
1191 * contains a 'discard' instruction. It is likely this is
1192 * related to optimizations related to forward-pixel kill, as
1193 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1194 * thing?" by Peter Harris
1197 if (variant
->can_discard
) {
1198 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1199 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1200 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1201 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1204 /* Check if we're using the default blend descriptor (fast path) */
1207 !ctx
->blend
->has_blend_shader
&&
1208 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1209 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1210 (ctx
->blend
->equation
.color_mask
== 0xf);
1213 /* When only a single render target platform is used, the blend
1214 * information is inside the shader meta itself. We
1215 * additionally need to signal CAN_DISCARD for nontrivial blend
1216 * modes (so we're able to read back the destination buffer) */
1218 if (ctx
->blend
->has_blend_shader
) {
1219 ctx
->fragment_shader_core
.blend_shader
= ctx
->blend
->blend_shader
;
1221 memcpy(&ctx
->fragment_shader_core
.blend_equation
, &ctx
->blend
->equation
, sizeof(ctx
->blend
->equation
));
1225 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1229 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct mali_blend_meta
);
1230 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1231 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1233 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1235 if (!require_sfbd
) {
1236 /* Additional blend descriptor tacked on for jobs using MFBD */
1238 unsigned blend_count
= 0;
1240 if (ctx
->blend
->has_blend_shader
) {
1241 /* For a blend shader, the bottom nibble corresponds to
1242 * the number of work registers used, which signals the
1243 * -existence- of a blend shader */
1245 assert(ctx
->blend
->blend_work_count
>= 2);
1246 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1248 /* Otherwise, the bottom bit simply specifies if
1249 * blending (anything other than REPLACE) is enabled */
1256 /* Second blend equation is always a simple replace */
1258 uint64_t replace_magic
= 0xf0122122;
1259 struct mali_blend_equation replace_mode
;
1260 memcpy(&replace_mode
, &replace_magic
, sizeof(replace_mode
));
1262 struct mali_blend_meta blend_meta
[] = {
1264 .unk1
= 0x200 | blend_count
,
1265 .blend_equation_1
= ctx
->blend
->equation
,
1266 .blend_equation_2
= replace_mode
1270 if (ctx
->blend
->has_blend_shader
)
1271 memcpy(&blend_meta
[0].blend_equation_1
, &ctx
->blend
->blend_shader
, sizeof(ctx
->blend
->blend_shader
));
1273 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), blend_meta
, sizeof(blend_meta
));
1277 if (ctx
->dirty
& PAN_DIRTY_VERTEX
) {
1278 ctx
->payload_vertex
.postfix
.attribute_meta
= ctx
->vertex
->descriptor_ptr
;
1281 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
1282 /* Upload samplers back to back, no padding */
1284 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1285 if (!ctx
->sampler_count
[t
]) continue;
1287 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
1288 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
1290 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
1291 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
1294 if (t
== PIPE_SHADER_FRAGMENT
)
1295 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
1296 else if (t
== PIPE_SHADER_VERTEX
)
1297 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1303 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1304 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1306 if (!ctx
->sampler_view_count
[t
]) continue;
1308 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1310 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1311 if (!ctx
->sampler_views
[t
][i
])
1314 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1315 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1317 /* Inject the address in. */
1318 for (int l
= 0; l
< (tex_rsrc
->last_level
+ 1); ++l
)
1319 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[l
] = rsrc
->bo
->gpu
[l
];
1321 /* Workaround maybe-errata (?) with non-mipmaps */
1322 int s
= ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
;
1324 if (!rsrc
->bo
->is_mipmap
) {
1326 /* HW ERRATA, not needed after t6XX */
1327 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[1] = rsrc
->bo
->gpu
[0];
1329 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 1;
1332 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= 0;
1335 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1338 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= s
;
1341 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 0;
1345 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1347 if (t
== PIPE_SHADER_FRAGMENT
)
1348 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1349 else if (t
== PIPE_SHADER_VERTEX
)
1350 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1356 /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1357 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1359 float viewport_vec4
[] = {
1361 fabsf(vp
->scale
[1]),
1364 /* -1.0 * vp->translate[1] */ fabs(1.0 * vp
->scale
[1]) /* XXX */
1367 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1368 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1370 if (i
== PIPE_SHADER_VERTEX
|| i
== PIPE_SHADER_FRAGMENT
) {
1371 /* It doesn't matter if we don't use all the memory;
1372 * we'd need a dummy UBO anyway. Compute the max */
1374 size_t size
= sizeof(viewport_vec4
) + buf
->size
;
1375 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1377 /* Keep track how much we've uploaded */
1380 if (i
== PIPE_SHADER_VERTEX
) {
1381 /* Upload viewport */
1382 memcpy(transfer
.cpu
+ offset
, viewport_vec4
, sizeof(viewport_vec4
));
1383 offset
+= sizeof(viewport_vec4
);
1386 /* Upload uniforms */
1387 memcpy(transfer
.cpu
+ offset
, buf
->buffer
, buf
->size
);
1389 int uniform_count
= 0;
1391 struct mali_vertex_tiler_postfix
*postfix
;
1394 case PIPE_SHADER_VERTEX
:
1395 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1396 postfix
= &ctx
->payload_vertex
.postfix
;
1399 case PIPE_SHADER_FRAGMENT
:
1400 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1401 postfix
= &ctx
->payload_tiler
.postfix
;
1405 printf("Unknown shader stage %d in uniform upload\n", i
);
1409 /* Also attach the same buffer as a UBO for extended access */
1411 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1413 .size
= MALI_POSITIVE((2 + uniform_count
)),
1414 .ptr
= transfer
.gpu
>> 2,
1418 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1419 postfix
->uniforms
= transfer
.gpu
;
1420 postfix
->uniform_buffers
= ubufs
;
1429 /* Corresponds to exactly one draw, but does not submit anything */
1432 panfrost_queue_draw(struct panfrost_context
*ctx
)
1434 /* TODO: Expand the array? */
1435 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1436 printf("Job buffer overflow, ignoring draw\n");
1440 /* Handle dirty flags now */
1441 panfrost_emit_for_draw(ctx
, true);
1443 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1444 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1446 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1447 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1449 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1450 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1455 /* At the end of the frame, the vertex and tiler jobs are linked together and
1456 * then the fragment job is plonked at the end. Set value job is first for
1457 * unknown reasons. */
1460 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1462 if (first
->job_descriptor_size
)
1463 first
->next_job_64
= (u64
) (uintptr_t) next
;
1465 first
->next_job_32
= (u32
) (uintptr_t) next
;
1469 panfrost_link_jobs(struct panfrost_context
*ctx
)
1471 if (ctx
->draw_count
) {
1472 /* Generate the set_value_job */
1473 panfrost_set_value_job(ctx
);
1475 /* Have the first vertex job depend on the set value job */
1476 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1479 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1482 /* V -> V/T ; T -> T/null */
1483 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1484 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1486 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1490 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1491 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1492 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1496 /* The entire frame is in memory -- send it off to the kernel! */
1499 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
)
1501 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1502 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1504 /* Edge case if screen is cleared and nothing else */
1505 bool has_draws
= ctx
->draw_count
> 0;
1507 /* Workaround a bizarre lockup (a hardware errata?) */
1509 flush_immediate
= true;
1511 /* A number of jobs are batched -- this must be linked and cleared */
1512 panfrost_link_jobs(ctx
);
1514 ctx
->draw_count
= 0;
1515 ctx
->vertex_job_count
= 0;
1516 ctx
->tiler_job_count
= 0;
1520 bool is_scanout
= panfrost_is_scanout(ctx
);
1521 int fragment_id
= screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1523 /* If visual, we can stall a frame */
1525 if (panfrost_is_scanout(ctx
) && !flush_immediate
)
1526 screen
->driver
->force_flush_fragment(ctx
);
1528 screen
->last_fragment_id
= fragment_id
;
1529 screen
->last_fragment_flushed
= false;
1531 /* If readback, flush now (hurts the pipelined performance) */
1532 if (panfrost_is_scanout(ctx
) && flush_immediate
)
1533 screen
->driver
->force_flush_fragment(ctx
);
1535 #ifdef DUMP_PERFORMANCE_COUNTERS
1537 snprintf(filename
, sizeof(filename
), "/dev/shm/frame%d.mdgprf", ++performance_counter_number
);
1538 FILE *fp
= fopen(filename
, "wb");
1539 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1546 bool dont_scanout
= false;
1550 struct pipe_context
*pipe
,
1551 struct pipe_fence_handle
**fence
,
1554 struct panfrost_context
*ctx
= pan_context(pipe
);
1556 /* If there is nothing drawn, skip the frame */
1557 if (!ctx
->draw_count
&& !ctx
->frame_cleared
) return;
1559 if (!ctx
->frame_cleared
) {
1560 /* While there are draws, there was no clear. This is a partial
1561 * update, which needs to be handled via the "wallpaper"
1562 * method. We also need to fake a clear, just to get the
1563 * FRAGMENT job correct. */
1565 panfrost_clear(&ctx
->base
, ctx
->last_clear
.buffers
, ctx
->last_clear
.color
, ctx
->last_clear
.depth
, ctx
->last_clear
.stencil
);
1567 panfrost_draw_wallpaper(pipe
);
1570 /* Frame clear handled, reset */
1571 ctx
->frame_cleared
= false;
1573 /* Whether to stall the pipeline for immediately correct results */
1574 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1576 /* Submit the frame itself */
1577 panfrost_submit_frame(ctx
, flush_immediate
);
1579 /* Prepare for the next frame */
1580 panfrost_invalidate_frame(ctx
);
1583 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1586 g2m_draw_mode(enum pipe_prim_type mode
)
1589 DEFINE_CASE(POINTS
);
1591 DEFINE_CASE(LINE_LOOP
);
1592 DEFINE_CASE(LINE_STRIP
);
1593 DEFINE_CASE(TRIANGLES
);
1594 DEFINE_CASE(TRIANGLE_STRIP
);
1595 DEFINE_CASE(TRIANGLE_FAN
);
1597 DEFINE_CASE(QUAD_STRIP
);
1598 DEFINE_CASE(POLYGON
);
1601 printf("Illegal draw mode %d\n", mode
);
1603 return MALI_LINE_LOOP
;
1610 panfrost_translate_index_size(unsigned size
)
1614 return MALI_DRAW_INDEXED_UINT8
;
1617 return MALI_DRAW_INDEXED_UINT16
;
1620 return MALI_DRAW_INDEXED_UINT32
;
1623 printf("Unknown index size %d\n", size
);
1629 static const uint8_t *
1630 panfrost_get_index_buffer_raw(const struct pipe_draw_info
*info
)
1632 if (info
->has_user_indices
) {
1633 return (const uint8_t *) info
->index
.user
;
1635 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1636 return (const uint8_t *) rsrc
->bo
->cpu
[0];
1640 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1641 * good for the duration of the draw (transient), could last longer */
1644 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1646 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1648 off_t offset
= info
->start
* info
->index_size
;
1650 if (!info
->has_user_indices
) {
1651 /* Only resources can be directly mapped */
1652 return rsrc
->bo
->gpu
[0] + offset
;
1654 /* Otherwise, we need to upload to transient memory */
1655 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1656 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1662 struct pipe_context
*pipe
,
1663 const struct pipe_draw_info
*info
);
1665 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1666 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1667 T idx = buffer[_idx]; \
1668 if (idx > max_index) max_index = idx; \
1669 if (idx < min_index) min_index = idx; \
1674 struct pipe_context
*pipe
,
1675 const struct pipe_draw_info
*info
)
1677 struct panfrost_context
*ctx
= pan_context(pipe
);
1679 ctx
->payload_vertex
.draw_start
= info
->start
;
1680 ctx
->payload_tiler
.draw_start
= info
->start
;
1682 int mode
= info
->mode
;
1684 /* Fallback for unsupported modes */
1686 if (!(ctx
->draw_modes
& mode
)) {
1687 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1688 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1690 if (info
->count
< 4) {
1691 /* Degenerate case? */
1695 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1696 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1701 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1703 ctx
->vertex_count
= info
->count
;
1705 /* For non-indexed draws, they're the same */
1706 unsigned invocation_count
= ctx
->vertex_count
;
1708 /* For higher amounts of vertices (greater than what fits in a 16-bit
1709 * short), the other value is needed, otherwise there will be bizarre
1710 * rendering artefacts. It's not clear what these values mean yet. */
1712 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~(0x3000 | 0x18000);
1713 ctx
->payload_tiler
.prefix
.unknown_draw
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1715 if (info
->index_size
) {
1716 /* Calculate the min/max index used so we can figure out how
1717 * many times to invoke the vertex shader */
1719 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1721 int min_index
= INT_MAX
;
1724 if (info
->index_size
== 1) {
1725 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8
, info
->start
, info
->count
);
1726 } else if (info
->index_size
== 2) {
1727 const uint16_t *ibuf16
= (const uint16_t *) ibuf8
;
1728 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16
, info
->start
, info
->count
);
1729 } else if (info
->index_size
== 4) {
1730 const uint32_t *ibuf32
= (const uint32_t *) ibuf8
;
1731 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32
, info
->start
, info
->count
);
1736 /* Make sure we didn't go crazy */
1737 assert(min_index
< INT_MAX
);
1738 assert(max_index
> 0);
1739 assert(max_index
> min_index
);
1741 /* Use the corresponding values */
1742 invocation_count
= max_index
- min_index
+ 1;
1743 ctx
->payload_vertex
.draw_start
= min_index
;
1744 ctx
->payload_tiler
.draw_start
= min_index
;
1746 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1747 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1749 //assert(!info->restart_index); /* TODO: Research */
1750 assert(!info
->index_bias
);
1751 //assert(!info->min_index); /* TODO: Use value */
1753 ctx
->payload_tiler
.prefix
.unknown_draw
|= panfrost_translate_index_size(info
->index_size
);
1754 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1756 /* Index count == vertex count, if no indexing is applied, as
1757 * if it is internally indexed in the expected order */
1759 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1760 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1762 /* Reverse index state */
1763 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~MALI_DRAW_INDEXED_UINT32
;
1764 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1767 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1768 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1770 /* Fire off the draw itself */
1771 panfrost_queue_draw(ctx
);
1777 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1783 panfrost_set_scissor(struct panfrost_context
*ctx
)
1785 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1787 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
&& 0) {
1788 ctx
->viewport
->viewport0
[0] = ss
->minx
;
1789 ctx
->viewport
->viewport0
[1] = ss
->miny
;
1790 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1791 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ss
->maxy
);
1793 ctx
->viewport
->viewport0
[0] = 0;
1794 ctx
->viewport
->viewport0
[1] = 0;
1795 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ctx
->pipe_framebuffer
.width
);
1796 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ctx
->pipe_framebuffer
.height
);
1801 panfrost_create_rasterizer_state(
1802 struct pipe_context
*pctx
,
1803 const struct pipe_rasterizer_state
*cso
)
1805 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1809 /* Bitmask, unknown meaning of the start value */
1810 so
->tiler_gl_enables
= is_t6xx
? 0x105 : 0x7;
1812 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1813 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1815 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1816 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1818 if (cso
->cull_face
& PIPE_FACE_BACK
)
1819 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1825 panfrost_bind_rasterizer_state(
1826 struct pipe_context
*pctx
,
1829 struct panfrost_context
*ctx
= pan_context(pctx
);
1830 struct pipe_rasterizer_state
*cso
= hwcso
;
1832 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1836 /* If scissor test has changed, we'll need to update that now */
1837 bool update_scissor
= !ctx
->rasterizer
|| ctx
->rasterizer
->base
.scissor
!= cso
->scissor
;
1839 ctx
->rasterizer
= hwcso
;
1841 /* Actualise late changes */
1843 panfrost_set_scissor(ctx
);
1845 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1849 panfrost_create_vertex_elements_state(
1850 struct pipe_context
*pctx
,
1851 unsigned num_elements
,
1852 const struct pipe_vertex_element
*elements
)
1854 struct panfrost_context
*ctx
= pan_context(pctx
);
1855 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1857 so
->num_elements
= num_elements
;
1858 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1860 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_attr_meta
) * num_elements
, HEAP_DESCRIPTOR
);
1861 so
->hw
= (struct mali_attr_meta
*) transfer
.cpu
;
1862 so
->descriptor_ptr
= transfer
.gpu
;
1864 /* Allocate memory for the descriptor state */
1866 for (int i
= 0; i
< num_elements
; ++i
) {
1867 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1869 enum pipe_format fmt
= elements
[i
].src_format
;
1870 const struct util_format_description
*desc
= util_format_description(fmt
);
1871 so
->hw
[i
].unknown1
= 0x2;
1872 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1874 so
->hw
[i
].format
= panfrost_find_format(desc
);
1876 /* The field itself should probably be shifted over */
1877 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1884 panfrost_bind_vertex_elements_state(
1885 struct pipe_context
*pctx
,
1888 struct panfrost_context
*ctx
= pan_context(pctx
);
1890 ctx
->vertex
= hwcso
;
1891 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1895 panfrost_delete_vertex_elements_state(struct pipe_context
*pctx
, void *hwcso
)
1897 printf("Vertex elements delete leaks descriptor\n");
1902 panfrost_create_shader_state(
1903 struct pipe_context
*pctx
,
1904 const struct pipe_shader_state
*cso
)
1906 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1909 /* Token deep copy to prevent memory corruption */
1911 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1912 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1918 panfrost_delete_shader_state(
1919 struct pipe_context
*pctx
,
1922 printf("Deleting shader state maybe leaks tokens, per-variant compiled shaders, per-variant descriptors\n");
1927 panfrost_create_sampler_state(
1928 struct pipe_context
*pctx
,
1929 const struct pipe_sampler_state
*cso
)
1931 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1934 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1936 struct mali_sampler_descriptor sampler_descriptor
= {
1937 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1938 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1939 | translate_mip_filter(cso
->min_mip_filter
)
1942 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1943 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1944 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1945 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1947 cso
->border_color
.f
[0],
1948 cso
->border_color
.f
[1],
1949 cso
->border_color
.f
[2],
1950 cso
->border_color
.f
[3]
1952 .min_lod
= FIXED_16(0.0),
1953 .max_lod
= FIXED_16(31.0),
1957 so
->hw
= sampler_descriptor
;
1963 panfrost_bind_sampler_states(
1964 struct pipe_context
*pctx
,
1965 enum pipe_shader_type shader
,
1966 unsigned start_slot
, unsigned num_sampler
,
1969 assert(start_slot
== 0);
1971 struct panfrost_context
*ctx
= pan_context(pctx
);
1973 /* XXX: Should upload, not just copy? */
1974 ctx
->sampler_count
[shader
] = num_sampler
;
1975 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1977 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1981 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1983 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1985 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1986 /* Make sure enable state is at least the same */
1987 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1991 /* Check that the contents of the test are the same */
1992 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1993 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1995 if (!(same_func
&& same_ref
)) {
1999 /* Otherwise, we're good to go */
2004 panfrost_bind_fs_state(
2005 struct pipe_context
*pctx
,
2008 struct panfrost_context
*ctx
= pan_context(pctx
);
2013 /* Match the appropriate variant */
2015 signed variant
= -1;
2017 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2019 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2020 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
2026 if (variant
== -1) {
2027 /* No variant matched, so create a new one */
2028 variant
= variants
->variant_count
++;
2029 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2031 variants
->variants
[variant
].base
= hwcso
;
2032 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
2034 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
2035 struct panfrost_context
*ctx
= pan_context(pctx
);
2036 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2038 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2039 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
2043 /* Select this variant */
2044 variants
->active_variant
= variant
;
2046 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2047 assert(panfrost_variant_matches(ctx
, shader_state
));
2049 /* Now we have a variant selected, so compile and go */
2051 if (!shader_state
->compiled
) {
2052 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
2053 shader_state
->compiled
= true;
2057 ctx
->dirty
|= PAN_DIRTY_FS
;
2061 panfrost_bind_vs_state(
2062 struct pipe_context
*pctx
,
2065 struct panfrost_context
*ctx
= pan_context(pctx
);
2070 if (!ctx
->vs
->variants
[0].compiled
) {
2071 ctx
->vs
->variants
[0].base
= hwcso
;
2073 /* TODO DRY from above */
2074 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2075 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2076 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
2078 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
2079 ctx
->vs
->variants
[0].compiled
= true;
2083 ctx
->dirty
|= PAN_DIRTY_VS
;
2087 panfrost_set_vertex_buffers(
2088 struct pipe_context
*pctx
,
2089 unsigned start_slot
,
2090 unsigned num_buffers
,
2091 const struct pipe_vertex_buffer
*buffers
)
2093 struct panfrost_context
*ctx
= pan_context(pctx
);
2094 assert(num_buffers
<= PIPE_MAX_ATTRIBS
);
2096 /* XXX: Dirty tracking? etc */
2098 size_t sz
= sizeof(buffers
[0]) * num_buffers
;
2099 ctx
->vertex_buffers
= malloc(sz
);
2100 ctx
->vertex_buffer_count
= num_buffers
;
2101 memcpy(ctx
->vertex_buffers
, buffers
, sz
);
2103 if (ctx
->vertex_buffers
) {
2104 free(ctx
->vertex_buffers
);
2105 ctx
->vertex_buffers
= NULL
;
2108 ctx
->vertex_buffer_count
= 0;
2113 panfrost_set_constant_buffer(
2114 struct pipe_context
*pctx
,
2115 enum pipe_shader_type shader
, uint index
,
2116 const struct pipe_constant_buffer
*buf
)
2118 struct panfrost_context
*ctx
= pan_context(pctx
);
2119 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2121 size_t sz
= buf
? buf
->buffer_size
: 0;
2123 /* Free previous buffer */
2130 pbuf
->buffer
= NULL
;
2133 /* If unbinding, we're done */
2138 /* Multiple constant buffers not yet supported */
2143 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
2146 cpu
= rsrc
->bo
->cpu
[0];
2147 } else if (buf
->user_buffer
) {
2148 cpu
= buf
->user_buffer
;
2150 printf("No constant buffer?\n");
2154 /* Copy the constant buffer into the driver context for later upload */
2156 pbuf
->buffer
= malloc(sz
);
2157 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
2161 panfrost_set_stencil_ref(
2162 struct pipe_context
*pctx
,
2163 const struct pipe_stencil_ref
*ref
)
2165 struct panfrost_context
*ctx
= pan_context(pctx
);
2166 ctx
->stencil_ref
= *ref
;
2168 /* Shader core dirty */
2169 ctx
->dirty
|= PAN_DIRTY_FS
;
2172 static struct pipe_sampler_view
*
2173 panfrost_create_sampler_view(
2174 struct pipe_context
*pctx
,
2175 struct pipe_resource
*texture
,
2176 const struct pipe_sampler_view
*template)
2178 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
2179 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2181 pipe_reference(NULL
, &texture
->reference
);
2183 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2185 so
->base
= *template;
2186 so
->base
.texture
= texture
;
2187 so
->base
.reference
.count
= 1;
2188 so
->base
.context
= pctx
;
2190 /* sampler_views correspond to texture descriptors, minus the texture
2191 * (data) itself. So, we serialise the descriptor here and cache it for
2194 /* TODO: Other types of textures */
2195 assert(template->target
== PIPE_TEXTURE_2D
);
2197 /* Make sure it's something with which we're familiar */
2198 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2200 /* TODO: Detect from format better */
2201 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2203 unsigned char user_swizzle
[4] = {
2204 template->swizzle_r
,
2205 template->swizzle_g
,
2206 template->swizzle_b
,
2210 enum mali_format format
= panfrost_find_format(desc
);
2212 struct mali_texture_descriptor texture_descriptor
= {
2213 .width
= MALI_POSITIVE(texture
->width0
),
2214 .height
= MALI_POSITIVE(texture
->height0
),
2215 .depth
= MALI_POSITIVE(texture
->depth0
),
2219 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2223 .is_not_cubemap
= 1,
2225 /* 0x11 - regular texture 2d, uncompressed tiled */
2226 /* 0x12 - regular texture 2d, uncompressed linear */
2227 /* 0x1c - AFBC compressed (internally tiled, probably) texture 2D */
2229 .usage2
= prsrc
->bo
->has_afbc
? 0x1c : (prsrc
->bo
->tiled
? 0x11 : 0x12),
2232 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2235 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2236 assert (template->u
.tex
.first_level
== 0);
2238 texture_descriptor
.nr_mipmap_levels
= template->u
.tex
.last_level
- template->u
.tex
.first_level
;
2240 so
->hw
= texture_descriptor
;
2242 return (struct pipe_sampler_view
*) so
;
2246 panfrost_set_sampler_views(
2247 struct pipe_context
*pctx
,
2248 enum pipe_shader_type shader
,
2249 unsigned start_slot
, unsigned num_views
,
2250 struct pipe_sampler_view
**views
)
2252 struct panfrost_context
*ctx
= pan_context(pctx
);
2254 assert(start_slot
== 0);
2256 ctx
->sampler_view_count
[shader
] = num_views
;
2257 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2259 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2263 panfrost_sampler_view_destroy(
2264 struct pipe_context
*pctx
,
2265 struct pipe_sampler_view
*views
)
2267 //struct panfrost_context *ctx = pan_context(pctx);
2275 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2276 const struct pipe_framebuffer_state
*fb
)
2278 struct panfrost_context
*ctx
= pan_context(pctx
);
2280 /* Flush when switching away from an FBO */
2282 if (!panfrost_is_scanout(ctx
)) {
2283 panfrost_flush(pctx
, NULL
, 0);
2286 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2287 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2288 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2289 ctx
->pipe_framebuffer
.width
= fb
->width
;
2290 ctx
->pipe_framebuffer
.height
= fb
->height
;
2292 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2293 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2295 /* check if changing cbuf */
2296 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2298 if (cb
&& (i
!= 0)) {
2299 printf("XXX: Multiple render targets not supported before t7xx!\n");
2304 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2310 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2312 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2314 panfrost_attach_vt_framebuffer(ctx
);
2315 panfrost_new_frag_framebuffer(ctx
);
2316 panfrost_set_scissor(ctx
);
2318 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2319 bool is_scanout
= panfrost_is_scanout(ctx
);
2321 if (!is_scanout
&& !tex
->bo
->has_afbc
) {
2322 /* The blob is aggressive about enabling AFBC. As such,
2323 * it's pretty much necessary to use it here, since we
2324 * have no traces of non-compressed FBO. */
2326 panfrost_enable_afbc(ctx
, tex
, false);
2329 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2330 /* Enable transaction elimination if we can */
2331 panfrost_enable_checksum(ctx
, tex
);
2336 struct pipe_surface
*zb
= fb
->zsbuf
;
2338 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2339 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2345 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2347 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2349 panfrost_attach_vt_framebuffer(ctx
);
2350 panfrost_new_frag_framebuffer(ctx
);
2351 panfrost_set_scissor(ctx
);
2353 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
);
2355 if (!tex
->bo
->has_afbc
&& !panfrost_is_scanout(ctx
))
2356 panfrost_enable_afbc(ctx
, tex
, true);
2361 /* Force a clear XXX wrong? */
2362 if (ctx
->last_clear
.color
)
2363 panfrost_clear(&ctx
->base
, ctx
->last_clear
.buffers
, ctx
->last_clear
.color
, ctx
->last_clear
.depth
, ctx
->last_clear
.stencil
);
2367 panfrost_create_blend_state(struct pipe_context
*pipe
,
2368 const struct pipe_blend_state
*blend
)
2370 struct panfrost_context
*ctx
= pan_context(pipe
);
2371 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2374 /* TODO: The following features are not yet implemented */
2375 assert(!blend
->logicop_enable
);
2376 assert(!blend
->alpha_to_coverage
);
2377 assert(!blend
->alpha_to_one
);
2379 /* Compile the blend state, first as fixed-function if we can */
2381 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], &so
->equation
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2384 /* If we can't, compile a blend shader instead */
2386 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2392 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2395 struct panfrost_context
*ctx
= pan_context(pipe
);
2396 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2397 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2398 ctx
->blend
= pblend
;
2403 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2405 /* TODO: Attach color */
2407 /* Shader itself is not dirty, but the shader core is */
2408 ctx
->dirty
|= PAN_DIRTY_FS
;
2412 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2415 printf("Deleting blend state may leak blend shader\n");
2420 panfrost_set_blend_color(struct pipe_context
*pipe
,
2421 const struct pipe_blend_color
*blend_color
)
2423 struct panfrost_context
*ctx
= pan_context(pipe
);
2425 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2428 ctx
->blend_color
= *blend_color
;
2430 /* The blend mode depends on the blend constant color, due to the
2431 * fixed/programmable split. So, we're forced to regenerate the blend
2434 /* TODO: Attach color */
2439 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2440 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2442 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2446 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2449 struct panfrost_context
*ctx
= pan_context(pipe
);
2450 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2451 ctx
->depth_stencil
= depth_stencil
;
2456 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2457 * emulated in the fragment shader */
2459 if (depth_stencil
->alpha
.enabled
) {
2460 /* We need to trigger a new shader (maybe) */
2461 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2465 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2467 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2468 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2470 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2471 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2473 /* Depth state (TODO: Refactor) */
2474 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2476 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2478 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2479 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2481 /* Bounds test not implemented */
2482 assert(!depth_stencil
->depth
.bounds_test
);
2484 ctx
->dirty
|= PAN_DIRTY_FS
;
2488 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2494 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2495 unsigned sample_mask
)
2500 panfrost_set_clip_state(struct pipe_context
*pipe
,
2501 const struct pipe_clip_state
*clip
)
2503 //struct panfrost_context *panfrost = pan_context(pipe);
2507 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2508 unsigned start_slot
,
2509 unsigned num_viewports
,
2510 const struct pipe_viewport_state
*viewports
)
2512 struct panfrost_context
*ctx
= pan_context(pipe
);
2514 assert(start_slot
== 0);
2515 assert(num_viewports
== 1);
2517 ctx
->pipe_viewport
= *viewports
;
2520 /* TODO: What if not centered? */
2521 float w
= abs(viewports
->scale
[0]) * 2.0;
2522 float h
= abs(viewports
->scale
[1]) * 2.0;
2524 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2525 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2530 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2531 unsigned start_slot
,
2532 unsigned num_scissors
,
2533 const struct pipe_scissor_state
*scissors
)
2535 struct panfrost_context
*ctx
= pan_context(pipe
);
2537 assert(start_slot
== 0);
2538 assert(num_scissors
== 1);
2540 ctx
->scissor
= *scissors
;
2542 panfrost_set_scissor(ctx
);
2546 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2547 const struct pipe_poly_stipple
*stipple
)
2549 //struct panfrost_context *panfrost = pan_context(pipe);
2553 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2556 //struct panfrost_context *panfrost = pan_context(pipe);
2560 panfrost_destroy(struct pipe_context
*pipe
)
2562 struct panfrost_context
*panfrost
= pan_context(pipe
);
2564 if (panfrost
->blitter
)
2565 util_blitter_destroy(panfrost
->blitter
);
2568 static struct pipe_query
*
2569 panfrost_create_query(struct pipe_context
*pipe
,
2573 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2578 return (struct pipe_query
*) q
;
2582 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2588 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2590 struct panfrost_context
*ctx
= pan_context(pipe
);
2591 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2593 switch (query
->type
) {
2594 case PIPE_QUERY_OCCLUSION_COUNTER
:
2595 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2596 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2598 /* Allocate a word for the query results to be stored */
2599 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2601 ctx
->occlusion_query
= query
;
2607 fprintf(stderr
, "Skipping query %d\n", query
->type
);
2615 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2617 struct panfrost_context
*ctx
= pan_context(pipe
);
2618 ctx
->occlusion_query
= NULL
;
2623 panfrost_get_query_result(struct pipe_context
*pipe
,
2624 struct pipe_query
*q
,
2626 union pipe_query_result
*vresult
)
2629 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2631 /* We need to flush out the jobs to actually run the counter, TODO
2632 * check wait, TODO wallpaper after if needed */
2634 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2636 switch (query
->type
) {
2637 case PIPE_QUERY_OCCLUSION_COUNTER
:
2638 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2639 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2640 /* Read back the query results */
2641 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2642 unsigned passed
= *result
;
2644 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2645 vresult
->u64
= passed
;
2647 vresult
->b
= !!passed
;
2653 fprintf(stderr
, "Skipped query get %d\n", query
->type
);
2661 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2663 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2664 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2666 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2667 /* Allocate the beginning of the transient pool */
2668 int entry_size
= (1 << 22); /* 4MB */
2670 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2671 ctx
->transient_pools
[i
].entry_count
= 1;
2673 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2676 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2677 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, 0, 0, 0);
2678 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2679 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_GROWABLE
, 1, 128);
2680 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128, false, PAN_ALLOCATE_GROWABLE
, 1, 128);
2684 /* New context creation, which also does hardware initialisation since I don't
2685 * know the better way to structure this :smirk: */
2687 struct pipe_context
*
2688 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2690 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2691 memset(ctx
, 0, sizeof(*ctx
));
2692 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2694 gallium
->screen
= screen
;
2696 gallium
->destroy
= panfrost_destroy
;
2698 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2700 gallium
->flush
= panfrost_flush
;
2701 gallium
->clear
= panfrost_clear
;
2702 gallium
->draw_vbo
= panfrost_draw_vbo
;
2704 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2705 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2707 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2709 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2710 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2711 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2713 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2714 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2715 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2717 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2718 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2719 gallium
->delete_vertex_elements_state
= panfrost_delete_vertex_elements_state
;
2721 gallium
->create_fs_state
= panfrost_create_shader_state
;
2722 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2723 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2725 gallium
->create_vs_state
= panfrost_create_shader_state
;
2726 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2727 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2729 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2730 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2731 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2733 gallium
->create_blend_state
= panfrost_create_blend_state
;
2734 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2735 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2737 gallium
->set_blend_color
= panfrost_set_blend_color
;
2739 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2740 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2741 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2743 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2745 gallium
->set_clip_state
= panfrost_set_clip_state
;
2746 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2747 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2748 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2749 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2751 gallium
->create_query
= panfrost_create_query
;
2752 gallium
->destroy_query
= panfrost_destroy_query
;
2753 gallium
->begin_query
= panfrost_begin_query
;
2754 gallium
->end_query
= panfrost_end_query
;
2755 gallium
->get_query_result
= panfrost_get_query_result
;
2757 panfrost_resource_context_init(gallium
);
2759 panfrost_setup_hardware(ctx
);
2762 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2763 gallium
->const_uploader
= gallium
->stream_uploader
;
2764 assert(gallium
->stream_uploader
);
2766 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2767 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2769 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2771 ctx
->blitter
= util_blitter_create(gallium
);
2772 assert(ctx
->blitter
);
2774 /* Prepare for render! */
2776 panfrost_emit_vertex_payload(ctx
);
2777 panfrost_emit_tiler_payload(ctx
);
2778 panfrost_invalidate_frame(ctx
);
2779 panfrost_viewport(ctx
, 0.0, 1.0, 0, 0, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
2780 panfrost_default_shader_backend(ctx
);
2781 panfrost_generate_space_filler_indices();