2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
49 #include "pan_tiler.h"
51 static int performance_counter_number
= 0;
52 extern const char *pan_counters_base
;
54 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
57 static enum mali_job_type
58 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
61 case PIPE_SHADER_VERTEX
:
62 return JOB_TYPE_VERTEX
;
64 case PIPE_SHADER_FRAGMENT
:
65 /* Note: JOB_TYPE_FRAGMENT is different.
66 * JOB_TYPE_FRAGMENT actually executes the
67 * fragment shader, but JOB_TYPE_TILER is how you
69 return JOB_TYPE_TILER
;
71 case PIPE_SHADER_GEOMETRY
:
72 return JOB_TYPE_GEOMETRY
;
74 case PIPE_SHADER_COMPUTE
:
75 return JOB_TYPE_COMPUTE
;
78 unreachable("Unsupported shader stage");
83 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
85 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
86 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
87 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
88 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
90 /* 8 byte checksum per tile */
91 rsrc
->bo
->checksum_stride
= tile_w
* 8;
92 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
93 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
95 rsrc
->bo
->has_checksum
= true;
98 /* Framebuffer descriptor */
101 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
103 fb
->width
= MALI_POSITIVE(w
);
104 fb
->height
= MALI_POSITIVE(h
);
106 /* No idea why this is needed, but it's how resolution_check is
107 * calculated. It's not clear to us yet why the hardware wants this.
108 * The formula itself was discovered mostly by manual bruteforce and
109 * aggressive algebraic simplification. */
111 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
114 struct mali_single_framebuffer
115 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
117 struct mali_single_framebuffer framebuffer
= {
119 .format
= 0x30000000,
120 .clear_flags
= 0x1000,
121 .unknown_address_0
= ctx
->scratchpad
.gpu
,
122 .tiler_polygon_list
= ctx
->misc_0
.gpu
,
123 .tiler_polygon_list_body
= ctx
->misc_0
.gpu
+ 40960,
124 .tiler_hierarchy_mask
= 0xF0,
126 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
127 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
130 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
135 struct bifrost_framebuffer
136 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
138 unsigned width
= ctx
->pipe_framebuffer
.width
;
139 unsigned height
= ctx
->pipe_framebuffer
.height
;
141 struct bifrost_framebuffer framebuffer
= {
142 /* The lower 0x1ff controls the hierarchy mask. Set more bits
143 * on for more tile granularity (which can be a performance win
144 * on some scenes, at memory bandwidth costs). For now, be lazy
145 * and enable everything. This might be a terrible idea. */
147 .tiler_hierarchy_mask
= 0xff,
150 /* The hardware deals with suballocation; we don't care */
151 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
152 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
154 /* See pan_tiler.c */
155 .tiler_polygon_list
= ctx
->misc_0
.gpu
,
157 .width1
= MALI_POSITIVE(width
),
158 .height1
= MALI_POSITIVE(height
),
159 .width2
= MALI_POSITIVE(width
),
160 .height2
= MALI_POSITIVE(height
),
165 .rt_count_1
= MALI_POSITIVE(1),
170 .scratchpad
= ctx
->scratchpad
.gpu
,
173 /* Compute the polygon header size and use that to offset the body */
175 unsigned header_size
= panfrost_tiler_header_size(
176 width
, height
, framebuffer
.tiler_hierarchy_mask
);
178 unsigned body_size
= panfrost_tiler_body_size(
179 width
, height
, framebuffer
.tiler_hierarchy_mask
);
181 framebuffer
.tiler_polygon_list_body
=
182 framebuffer
.tiler_polygon_list
+ header_size
;
184 framebuffer
.tiler_polygon_list_size
=
185 header_size
+ body_size
;
190 /* Are we currently rendering to the screen (rather than an FBO)? */
193 panfrost_is_scanout(struct panfrost_context
*ctx
)
195 /* If there is no color buffer, it's an FBO */
196 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
199 /* If we're too early that no framebuffer was sent, it's scanout */
200 if (!ctx
->pipe_framebuffer
.cbufs
[0])
203 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
204 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
205 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
209 pan_pack_color(const union pipe_color_union
*color
, enum pipe_format format
)
211 /* Alpha magicked to 1.0 if there is no alpha */
213 bool has_alpha
= util_format_has_alpha(format
);
214 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
216 /* Packed color depends on the framebuffer format */
218 const struct util_format_description
*desc
=
219 util_format_description(format
);
221 if (util_format_is_rgba8_variant(desc
)) {
222 return (float_to_ubyte(clear_alpha
) << 24) |
223 (float_to_ubyte(color
->f
[2]) << 16) |
224 (float_to_ubyte(color
->f
[1]) << 8) |
225 (float_to_ubyte(color
->f
[0]) << 0);
226 } else if (format
== PIPE_FORMAT_B5G6R5_UNORM
) {
227 /* First, we convert the components to R5, G6, B5 separately */
228 unsigned r5
= CLAMP(color
->f
[0], 0.0, 1.0) * 31.0;
229 unsigned g6
= CLAMP(color
->f
[1], 0.0, 1.0) * 63.0;
230 unsigned b5
= CLAMP(color
->f
[2], 0.0, 1.0) * 31.0;
232 /* Then we pack into a sparse u32. TODO: Why these shifts? */
233 return (b5
<< 25) | (g6
<< 14) | (r5
<< 5);
244 struct pipe_context
*pipe
,
246 const union pipe_color_union
*color
,
247 double depth
, unsigned stencil
)
249 struct panfrost_context
*ctx
= pan_context(pipe
);
250 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
252 if (buffers
& PIPE_CLEAR_COLOR
) {
253 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[0]->format
;
254 job
->clear_color
= pan_pack_color(color
, format
);
257 if (buffers
& PIPE_CLEAR_DEPTH
) {
258 job
->clear_depth
= depth
;
261 if (buffers
& PIPE_CLEAR_STENCIL
) {
262 job
->clear_stencil
= stencil
;
265 job
->clear
|= buffers
;
269 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
271 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
275 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
277 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
281 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
283 mali_ptr framebuffer
= ctx
->require_sfbd
?
284 panfrost_attach_vt_sfbd(ctx
) :
285 panfrost_attach_vt_mfbd(ctx
);
287 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
288 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
291 /* Reset per-frame context, called on context initialisation as well as after
292 * flushing a frame */
295 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
297 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
298 DBG("Uploaded transient %d bytes\n", transient_count
);
300 /* Rotate cmdstream */
301 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
302 ctx
->cmdstream_i
= 0;
304 if (ctx
->require_sfbd
)
305 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
307 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
309 /* Reset varyings allocated */
310 ctx
->varying_height
= 0;
312 /* The transient cmdstream is dirty every frame; the only bits worth preserving
313 * (textures, shaders, etc) are in other buffers anyways */
315 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
316 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
318 /* Regenerate payloads */
319 panfrost_attach_vt_framebuffer(ctx
);
322 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
325 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
327 /* Reset job counters */
329 ctx
->vertex_job_count
= 0;
330 ctx
->tiler_job_count
= 0;
333 /* In practice, every field of these payloads should be configurable
334 * arbitrarily, which means these functions are basically catch-all's for
335 * as-of-yet unwavering unknowns */
338 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
340 struct midgard_payload_vertex_tiler payload
= {
342 .workgroups_z_shift
= 32,
343 .workgroups_x_shift_2
= 0x2,
344 .workgroups_x_shift_3
= 0x5,
346 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
349 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
353 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
355 struct midgard_payload_vertex_tiler payload
= {
357 .workgroups_z_shift
= 32,
358 .workgroups_x_shift_2
= 0x2,
359 .workgroups_x_shift_3
= 0x6,
361 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
365 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
369 translate_tex_wrap(enum pipe_tex_wrap w
)
372 case PIPE_TEX_WRAP_REPEAT
:
373 return MALI_WRAP_REPEAT
;
375 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
376 return MALI_WRAP_CLAMP_TO_EDGE
;
378 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
379 return MALI_WRAP_CLAMP_TO_BORDER
;
381 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
382 return MALI_WRAP_MIRRORED_REPEAT
;
385 unreachable("Invalid wrap");
390 translate_tex_filter(enum pipe_tex_filter f
)
393 case PIPE_TEX_FILTER_NEAREST
:
396 case PIPE_TEX_FILTER_LINEAR
:
400 unreachable("Invalid filter");
405 translate_mip_filter(enum pipe_tex_mipfilter f
)
407 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
411 panfrost_translate_compare_func(enum pipe_compare_func in
)
414 case PIPE_FUNC_NEVER
:
415 return MALI_FUNC_NEVER
;
418 return MALI_FUNC_LESS
;
420 case PIPE_FUNC_EQUAL
:
421 return MALI_FUNC_EQUAL
;
423 case PIPE_FUNC_LEQUAL
:
424 return MALI_FUNC_LEQUAL
;
426 case PIPE_FUNC_GREATER
:
427 return MALI_FUNC_GREATER
;
429 case PIPE_FUNC_NOTEQUAL
:
430 return MALI_FUNC_NOTEQUAL
;
432 case PIPE_FUNC_GEQUAL
:
433 return MALI_FUNC_GEQUAL
;
435 case PIPE_FUNC_ALWAYS
:
436 return MALI_FUNC_ALWAYS
;
439 unreachable("Invalid func");
444 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
447 case PIPE_FUNC_NEVER
:
448 return MALI_ALT_FUNC_NEVER
;
451 return MALI_ALT_FUNC_LESS
;
453 case PIPE_FUNC_EQUAL
:
454 return MALI_ALT_FUNC_EQUAL
;
456 case PIPE_FUNC_LEQUAL
:
457 return MALI_ALT_FUNC_LEQUAL
;
459 case PIPE_FUNC_GREATER
:
460 return MALI_ALT_FUNC_GREATER
;
462 case PIPE_FUNC_NOTEQUAL
:
463 return MALI_ALT_FUNC_NOTEQUAL
;
465 case PIPE_FUNC_GEQUAL
:
466 return MALI_ALT_FUNC_GEQUAL
;
468 case PIPE_FUNC_ALWAYS
:
469 return MALI_ALT_FUNC_ALWAYS
;
472 unreachable("Invalid alt func");
477 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
480 case PIPE_STENCIL_OP_KEEP
:
481 return MALI_STENCIL_KEEP
;
483 case PIPE_STENCIL_OP_ZERO
:
484 return MALI_STENCIL_ZERO
;
486 case PIPE_STENCIL_OP_REPLACE
:
487 return MALI_STENCIL_REPLACE
;
489 case PIPE_STENCIL_OP_INCR
:
490 return MALI_STENCIL_INCR
;
492 case PIPE_STENCIL_OP_DECR
:
493 return MALI_STENCIL_DECR
;
495 case PIPE_STENCIL_OP_INCR_WRAP
:
496 return MALI_STENCIL_INCR_WRAP
;
498 case PIPE_STENCIL_OP_DECR_WRAP
:
499 return MALI_STENCIL_DECR_WRAP
;
501 case PIPE_STENCIL_OP_INVERT
:
502 return MALI_STENCIL_INVERT
;
505 unreachable("Invalid stencil op");
510 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
512 out
->ref
= 0; /* Gallium gets it from elsewhere */
514 out
->mask
= in
->valuemask
;
515 out
->func
= panfrost_translate_compare_func(in
->func
);
516 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
517 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
518 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
522 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
524 struct mali_shader_meta shader
= {
525 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
527 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
528 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
532 shader
.unknown2_4
|= 0x10;
535 struct pipe_stencil_state default_stencil
= {
537 .func
= PIPE_FUNC_ALWAYS
,
538 .fail_op
= MALI_STENCIL_KEEP
,
539 .zfail_op
= MALI_STENCIL_KEEP
,
540 .zpass_op
= MALI_STENCIL_KEEP
,
545 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
546 shader
.stencil_mask_front
= default_stencil
.writemask
;
548 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
549 shader
.stencil_mask_back
= default_stencil
.writemask
;
551 if (default_stencil
.enabled
)
552 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
554 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
558 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
560 if (first
->job_descriptor_size
)
561 first
->next_job_64
= (u64
) (uintptr_t) next
;
563 first
->next_job_32
= (u32
) (uintptr_t) next
;
566 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
567 * graphics command stream. It should be called once per draw, accordding to
568 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
569 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
572 struct panfrost_transfer
573 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
575 /* Each draw call corresponds to two jobs, and the set-value job is first */
576 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
578 struct mali_job_descriptor_header job
= {
579 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
580 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
582 .job_descriptor_size
= 1,
586 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
588 /* There's some padding hacks on 32-bit */
595 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
598 /* Tiler jobs depend on vertex jobs */
600 job
.job_dependency_index_1
= draw_job_index
;
602 /* Tiler jobs also depend on the previous tiler job */
604 if (ctx
->draw_count
) {
605 job
.job_dependency_index_2
= draw_job_index
- 1;
606 /* Previous tiler job points to this tiler job */
607 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
609 /* The only vertex job so far points to first tiler job */
610 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
613 if (ctx
->draw_count
) {
614 /* Previous vertex job points to this vertex job */
615 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
617 /* Last vertex job points to first tiler job */
618 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
620 /* Have the first vertex job depend on the set value job */
621 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
622 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
626 memcpy(transfer
.cpu
, &job
, sizeof(job
));
627 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
631 /* Generates a set value job. It's unclear what exactly this does, why it's
632 * necessary, and when to call it. */
635 panfrost_set_value_job(struct panfrost_context
*ctx
)
637 struct mali_job_descriptor_header job
= {
638 .job_type
= JOB_TYPE_SET_VALUE
,
639 .job_descriptor_size
= 1,
643 struct mali_payload_set_value payload
= {
644 .out
= ctx
->misc_0
.gpu
,
648 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
649 memcpy(transfer
.cpu
, &job
, sizeof(job
));
650 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
652 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
653 ctx
->set_value_job
= transfer
.gpu
;
657 panfrost_emit_varyings(
658 struct panfrost_context
*ctx
,
659 union mali_attr
*slot
,
663 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
665 /* Fill out the descriptor */
666 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
667 slot
->stride
= stride
;
668 slot
->size
= stride
* count
;
670 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
671 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
673 return varying_address
;
677 panfrost_emit_point_coord(union mali_attr
*slot
)
679 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
680 slot
->stride
= slot
->size
= 0;
684 panfrost_emit_varying_descriptor(
685 struct panfrost_context
*ctx
,
686 unsigned invocation_count
)
688 /* Load the shaders */
690 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
691 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
692 unsigned int num_gen_varyings
= 0;
694 /* Allocate the varying descriptor */
696 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
697 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
699 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
703 * Assign ->src_offset now that we know about all the general purpose
704 * varyings that will be used by the fragment and vertex shaders.
706 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
708 * General purpose varyings have ->index set to 0, skip other
711 if (vs
->varyings
[i
].index
)
714 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
717 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
720 if (fs
->varyings
[i
].index
)
724 * Re-use the VS general purpose varying pos if it exists,
725 * create a new one otherwise.
727 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
728 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
732 if (j
< vs
->tripipe
->varying_count
)
733 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
735 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
738 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
739 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
741 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
742 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
744 /* Buffer indices must be in this order per our convention */
745 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
748 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
751 /* fp32 vec4 gl_Position */
752 ctx
->payload_tiler
.postfix
.position_varying
=
753 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
754 sizeof(float) * 4, invocation_count
);
757 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
758 /* fp16 vec1 gl_PointSize */
759 ctx
->payload_tiler
.primitive_size
.pointer
=
760 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
761 2, invocation_count
);
764 if (fs
->reads_point_coord
) {
765 /* Special descriptor */
766 panfrost_emit_point_coord(&varyings
[idx
++]);
769 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
770 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
771 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
775 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
777 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
778 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
780 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
783 /* Emits attributes and varying descriptors, which should be called every draw,
784 * excepting some obscure circumstances */
787 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
789 /* Staged mali_attr, and index into them. i =/= k, depending on the
790 * vertex buffer mask */
791 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
794 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
796 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
797 if (!(ctx
->vb_mask
& (1 << i
))) continue;
799 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
800 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
804 /* Align to 64 bytes by masking off the lower bits. This
805 * will be adjusted back when we fixup the src_offset in
808 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
810 /* Offset vertex count by draw_start to make sure we upload enough */
811 attrs
[k
].stride
= buf
->stride
;
812 attrs
[k
].size
= rsrc
->base
.width0
;
814 panfrost_job_add_bo(job
, rsrc
->bo
);
815 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
820 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
822 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
826 panfrost_writes_point_size(struct panfrost_context
*ctx
)
829 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
831 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
834 /* Stage the attribute descriptors so we can adjust src_offset
835 * to let BOs align nicely */
838 panfrost_stage_attributes(struct panfrost_context
*ctx
)
840 struct panfrost_vertex_state
*so
= ctx
->vertex
;
842 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
843 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
844 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
846 /* Copy as-is for the first pass */
847 memcpy(target
, so
->hw
, sz
);
849 /* Fixup offsets for the second pass. Recall that the hardware
850 * calculates attribute addresses as:
852 * addr = base + (stride * vtx) + src_offset;
854 * However, on Mali, base must be aligned to 64-bytes, so we
857 * base' = base & ~63 = base - (base & 63)
859 * To compensate when using base' (see emit_vertex_data), we have
860 * to adjust src_offset by the masked off piece:
862 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
863 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
864 * = base + (stride * vtx) + src_offset
870 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
871 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
872 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
874 /* Adjust by the masked off bits of the offset */
875 target
[i
].src_offset
+= (addr
& 63);
878 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
882 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
884 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
886 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
887 if (!ctx
->sampler_count
[t
]) continue;
889 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
891 struct panfrost_transfer transfer
=
892 panfrost_allocate_transient(ctx
, transfer_size
);
894 struct mali_sampler_descriptor
*desc
=
895 (struct mali_sampler_descriptor
*) transfer
.cpu
;
897 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
898 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
900 if (t
== PIPE_SHADER_FRAGMENT
)
901 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
902 else if (t
== PIPE_SHADER_VERTEX
)
903 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
909 /* Computes the address to a texture at a particular slice */
912 panfrost_get_texture_address(
913 struct panfrost_resource
*rsrc
,
914 unsigned level
, unsigned face
)
916 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
917 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
919 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
925 struct panfrost_context
*ctx
,
926 struct panfrost_sampler_view
*view
)
929 return (mali_ptr
) NULL
;
931 struct pipe_resource
*tex_rsrc
= view
->base
.texture
;
932 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
934 /* Do we interleave an explicit stride with every element? */
936 bool has_manual_stride
=
937 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
939 /* Inject the addresses in, interleaving mip levels, cube faces, and
940 * strides in that order */
944 for (unsigned l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
945 for (unsigned f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
946 view
->hw
.payload
[idx
++] =
947 panfrost_get_texture_address(rsrc
, l
, f
);
949 if (has_manual_stride
) {
950 view
->hw
.payload
[idx
++] =
951 rsrc
->bo
->slices
[l
].stride
;
956 return panfrost_upload_transient(ctx
, &view
->hw
,
957 sizeof(struct mali_texture_descriptor
));
961 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
963 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
965 if (!ctx
->sampler_view_count
[t
]) continue;
967 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
969 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
971 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
973 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
975 if (t
== PIPE_SHADER_FRAGMENT
)
976 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
977 else if (t
== PIPE_SHADER_VERTEX
)
978 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
984 /* Go through dirty flags and actualise them in the cmdstream. */
987 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
989 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
991 if (with_vertex_data
) {
992 panfrost_emit_vertex_data(ctx
, job
);
995 bool msaa
= ctx
->rasterizer
->base
.multisample
;
997 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
998 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1000 /* TODO: Sample size */
1001 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1002 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1005 /* Enable job requirements at draw-time */
1008 job
->requirements
|= PAN_REQ_MSAA
;
1010 if (ctx
->depth_stencil
->depth
.writemask
)
1011 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
1013 if (ctx
->occlusion_query
) {
1014 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1015 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1018 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1021 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1023 /* Late shader descriptor assignments */
1025 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1026 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1029 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1031 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1034 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1035 /* Check if we need to link the gl_PointSize varying */
1036 if (!panfrost_writes_point_size(ctx
)) {
1037 /* If the size is constant, write it out. Otherwise,
1038 * don't touch primitive_size (since we would clobber
1039 * the pointer there) */
1041 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1045 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1047 ctx
->dirty
|= PAN_DIRTY_FS
;
1049 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1051 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1053 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1056 COPY(attribute_count
);
1057 COPY(varying_count
);
1058 COPY(midgard1
.uniform_count
);
1059 COPY(midgard1
.work_count
);
1060 COPY(midgard1
.unknown2
);
1063 /* If there is a blend shader, work registers are shared */
1065 if (ctx
->blend
->has_blend_shader
)
1066 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1068 /* Set late due to depending on render state */
1069 /* The one at the end seems to mean "1 UBO" */
1070 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1072 /* Assign texture/sample count right before upload */
1073 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1074 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1076 /* Assign the stencil refs late */
1077 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1078 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1080 /* CAN_DISCARD should be set if the fragment shader possibly
1081 * contains a 'discard' instruction. It is likely this is
1082 * related to optimizations related to forward-pixel kill, as
1083 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1084 * thing?" by Peter Harris
1087 if (variant
->can_discard
) {
1088 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1089 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1090 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1091 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1094 /* Check if we're using the default blend descriptor (fast path) */
1097 !ctx
->blend
->has_blend_shader
&&
1098 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1099 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1100 (ctx
->blend
->equation
.color_mask
== 0xf);
1102 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1103 * *also* copied to the blend_meta appended (by convention),
1104 * but this is the field actually read by the hardware. (Or
1105 * maybe both are read...?) */
1107 if (ctx
->blend
->has_blend_shader
) {
1108 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1111 if (ctx
->require_sfbd
) {
1112 /* When only a single render target platform is used, the blend
1113 * information is inside the shader meta itself. We
1114 * additionally need to signal CAN_DISCARD for nontrivial blend
1115 * modes (so we're able to read back the destination buffer) */
1117 if (!ctx
->blend
->has_blend_shader
) {
1118 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1119 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1123 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1127 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1128 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1129 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1131 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1133 if (!ctx
->require_sfbd
) {
1134 /* Additional blend descriptor tacked on for jobs using MFBD */
1136 unsigned blend_count
= 0x200;
1138 if (ctx
->blend
->has_blend_shader
) {
1139 /* For a blend shader, the bottom nibble corresponds to
1140 * the number of work registers used, which signals the
1141 * -existence- of a blend shader */
1143 assert(ctx
->blend
->blend_work_count
>= 2);
1144 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1146 /* Otherwise, the bottom bit simply specifies if
1147 * blending (anything other than REPLACE) is enabled */
1154 struct midgard_blend_rt rts
[4];
1158 for (unsigned i
= 0; i
< 1; ++i
) {
1159 rts
[i
].flags
= blend_count
;
1161 if (ctx
->blend
->has_blend_shader
) {
1162 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1164 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1165 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1169 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1173 /* We stage to transient, so always dirty.. */
1174 panfrost_stage_attributes(ctx
);
1176 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1177 panfrost_upload_sampler_descriptors(ctx
);
1179 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1180 panfrost_upload_texture_descriptors(ctx
);
1182 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1184 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1185 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1187 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1188 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1189 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1191 /* Allocate room for the sysval and the uniforms */
1192 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1193 size_t size
= sys_size
+ buf
->size
;
1194 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1196 /* Upload sysvals requested by the shader */
1197 float *uniforms
= (float *) transfer
.cpu
;
1198 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1199 int sysval
= ss
->sysval
[i
];
1201 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1202 uniforms
[4*i
+ 0] = vp
->scale
[0];
1203 uniforms
[4*i
+ 1] = vp
->scale
[1];
1204 uniforms
[4*i
+ 2] = vp
->scale
[2];
1205 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1206 uniforms
[4*i
+ 0] = vp
->translate
[0];
1207 uniforms
[4*i
+ 1] = vp
->translate
[1];
1208 uniforms
[4*i
+ 2] = vp
->translate
[2];
1214 /* Upload uniforms */
1215 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1217 int uniform_count
= 0;
1219 struct mali_vertex_tiler_postfix
*postfix
;
1222 case PIPE_SHADER_VERTEX
:
1223 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1224 postfix
= &ctx
->payload_vertex
.postfix
;
1227 case PIPE_SHADER_FRAGMENT
:
1228 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1229 postfix
= &ctx
->payload_tiler
.postfix
;
1233 unreachable("Invalid shader stage\n");
1236 /* Also attach the same buffer as a UBO for extended access */
1238 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1240 .size
= MALI_POSITIVE((2 + uniform_count
)),
1241 .ptr
= transfer
.gpu
>> 2,
1245 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1246 postfix
->uniforms
= transfer
.gpu
;
1247 postfix
->uniform_buffers
= ubufs
;
1252 /* TODO: Upload the viewport somewhere more appropriate */
1254 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1255 * (somewhat) asymmetric ints. */
1256 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1258 struct mali_viewport view
= {
1259 /* By default, do no viewport clipping, i.e. clip to (-inf,
1260 * inf) in each direction. Clipping to the viewport in theory
1261 * should work, but in practice causes issues when we're not
1262 * explicitly trying to scissor */
1273 /* Always scissor to the viewport by default. */
1274 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1275 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1277 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1278 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1280 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1281 view
.viewport0
[0] = ss
->minx
;
1282 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1288 /* Hardware needs the min/max to be strictly ordered, so flip if we
1296 view
.viewport0
[1] = miny
;
1297 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1299 ctx
->payload_tiler
.postfix
.viewport
=
1300 panfrost_upload_transient(ctx
,
1302 sizeof(struct mali_viewport
));
1307 /* Corresponds to exactly one draw, but does not submit anything */
1310 panfrost_queue_draw(struct panfrost_context
*ctx
)
1312 /* TODO: Expand the array? */
1313 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1314 DBG("Job buffer overflow, ignoring draw\n");
1318 /* Handle dirty flags now */
1319 panfrost_emit_for_draw(ctx
, true);
1321 /* We need a set_value job before any other draw jobs */
1322 if (ctx
->draw_count
== 0)
1323 panfrost_set_value_job(ctx
);
1325 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1326 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1327 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1329 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1330 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1331 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1336 /* The entire frame is in memory -- send it off to the kernel! */
1339 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1340 struct pipe_fence_handle
**fence
,
1341 struct panfrost_job
*job
)
1343 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1344 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1346 /* Edge case if screen is cleared and nothing else */
1347 bool has_draws
= ctx
->draw_count
> 0;
1349 /* Workaround a bizarre lockup (a hardware errata?) */
1351 flush_immediate
= true;
1355 bool is_scanout
= panfrost_is_scanout(ctx
);
1356 screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1358 /* If visual, we can stall a frame */
1360 if (!flush_immediate
)
1361 screen
->driver
->force_flush_fragment(ctx
, fence
);
1363 screen
->last_fragment_flushed
= false;
1364 screen
->last_job
= job
;
1366 /* If readback, flush now (hurts the pipelined performance) */
1367 if (flush_immediate
)
1368 screen
->driver
->force_flush_fragment(ctx
, fence
);
1370 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1371 screen
->driver
->dump_counters(screen
);
1374 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1375 FILE *fp
= fopen(filename
, "wb");
1376 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1384 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1386 struct panfrost_context
*ctx
= pan_context(pipe
);
1388 /* Nothing to reload? */
1389 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1392 /* Blit the wallpaper in */
1393 panfrost_blit_wallpaper(ctx
);
1395 /* We are flushing all queued draws and we know that no more jobs will
1396 * be added until the next frame.
1397 * We also know that the last jobs are the wallpaper jobs, and they
1398 * need to be linked so they execute right after the set_value job.
1401 /* set_value job to wallpaper vertex job */
1402 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1403 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1405 /* wallpaper vertex job to first vertex job */
1406 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1407 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1409 /* last vertex job to wallpaper tiler job */
1410 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1411 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1412 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1414 /* wallpaper tiler job to first tiler job */
1415 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1416 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1417 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1419 /* last tiler job to NULL */
1420 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1425 struct pipe_context
*pipe
,
1426 struct pipe_fence_handle
**fence
,
1429 struct panfrost_context
*ctx
= pan_context(pipe
);
1430 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1432 /* Nothing to do! */
1433 if (!ctx
->draw_count
&& !job
->clear
) return;
1436 panfrost_draw_wallpaper(&ctx
->base
);
1438 /* Whether to stall the pipeline for immediately correct results */
1439 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1441 /* Submit the frame itself */
1442 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1444 /* Prepare for the next frame */
1445 panfrost_invalidate_frame(ctx
);
1448 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1451 g2m_draw_mode(enum pipe_prim_type mode
)
1454 DEFINE_CASE(POINTS
);
1456 DEFINE_CASE(LINE_LOOP
);
1457 DEFINE_CASE(LINE_STRIP
);
1458 DEFINE_CASE(TRIANGLES
);
1459 DEFINE_CASE(TRIANGLE_STRIP
);
1460 DEFINE_CASE(TRIANGLE_FAN
);
1462 DEFINE_CASE(QUAD_STRIP
);
1463 DEFINE_CASE(POLYGON
);
1466 unreachable("Invalid draw mode");
1473 panfrost_translate_index_size(unsigned size
)
1477 return MALI_DRAW_INDEXED_UINT8
;
1480 return MALI_DRAW_INDEXED_UINT16
;
1483 return MALI_DRAW_INDEXED_UINT32
;
1486 unreachable("Invalid index size");
1490 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1491 * good for the duration of the draw (transient), could last longer */
1494 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1496 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1498 off_t offset
= info
->start
* info
->index_size
;
1500 if (!info
->has_user_indices
) {
1501 /* Only resources can be directly mapped */
1502 return rsrc
->bo
->gpu
+ offset
;
1504 /* Otherwise, we need to upload to transient memory */
1505 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1506 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1512 struct pipe_context
*pipe
,
1513 const struct pipe_draw_info
*info
)
1515 struct panfrost_context
*ctx
= pan_context(pipe
);
1517 ctx
->payload_vertex
.draw_start
= info
->start
;
1518 ctx
->payload_tiler
.draw_start
= info
->start
;
1520 int mode
= info
->mode
;
1522 /* Fallback for unsupported modes */
1524 if (!(ctx
->draw_modes
& (1 << mode
))) {
1525 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1526 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1528 if (info
->count
< 4) {
1529 /* Degenerate case? */
1533 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1534 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1539 /* Now that we have a guaranteed terminating path, find the job.
1540 * Assignment commented out to prevent unused warning */
1542 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1544 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1546 ctx
->vertex_count
= info
->count
;
1548 /* For non-indexed draws, they're the same */
1549 unsigned invocation_count
= ctx
->vertex_count
;
1551 unsigned draw_flags
= 0;
1553 /* The draw flags interpret how primitive size is interpreted */
1555 if (panfrost_writes_point_size(ctx
))
1556 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1558 /* For higher amounts of vertices (greater than what fits in a 16-bit
1559 * short), the other value is needed, otherwise there will be bizarre
1560 * rendering artefacts. It's not clear what these values mean yet. */
1562 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1564 if (info
->index_size
) {
1565 /* Calculate the min/max index used so we can figure out how
1566 * many times to invoke the vertex shader */
1568 /* Fetch / calculate index bounds */
1569 unsigned min_index
= 0, max_index
= 0;
1571 if (info
->max_index
== ~0u) {
1572 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1574 min_index
= info
->min_index
;
1575 max_index
= info
->max_index
;
1578 /* Use the corresponding values */
1579 invocation_count
= max_index
- min_index
+ 1;
1580 ctx
->payload_vertex
.draw_start
= min_index
;
1581 ctx
->payload_tiler
.draw_start
= min_index
;
1583 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1584 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1586 //assert(!info->restart_index); /* TODO: Research */
1587 assert(!info
->index_bias
);
1589 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1590 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1592 /* Index count == vertex count, if no indexing is applied, as
1593 * if it is internally indexed in the expected order */
1595 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1596 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1598 /* Reverse index state */
1599 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1602 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1603 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1604 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1606 /* Fire off the draw itself */
1607 panfrost_queue_draw(ctx
);
1613 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1619 panfrost_create_rasterizer_state(
1620 struct pipe_context
*pctx
,
1621 const struct pipe_rasterizer_state
*cso
)
1623 struct panfrost_context
*ctx
= pan_context(pctx
);
1624 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1628 /* Bitmask, unknown meaning of the start value */
1629 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1632 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1634 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1635 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1637 if (cso
->cull_face
& PIPE_FACE_BACK
)
1638 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1644 panfrost_bind_rasterizer_state(
1645 struct pipe_context
*pctx
,
1648 struct panfrost_context
*ctx
= pan_context(pctx
);
1650 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1654 ctx
->rasterizer
= hwcso
;
1655 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1659 panfrost_create_vertex_elements_state(
1660 struct pipe_context
*pctx
,
1661 unsigned num_elements
,
1662 const struct pipe_vertex_element
*elements
)
1664 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1666 so
->num_elements
= num_elements
;
1667 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1669 /* XXX: What the cornball? This is totally, 100%, unapologetically
1670 * nonsense. And yet it somehow fixes a regression in -bshadow
1671 * (previously, we allocated the descriptor here... a newer commit
1672 * removed that allocation, and then memory corruption led to
1673 * shader_meta getting overwritten in bad ways and then the whole test
1674 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1676 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1678 for (int i
= 0; i
< num_elements
; ++i
) {
1679 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1681 enum pipe_format fmt
= elements
[i
].src_format
;
1682 const struct util_format_description
*desc
= util_format_description(fmt
);
1683 so
->hw
[i
].unknown1
= 0x2;
1684 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1686 so
->hw
[i
].format
= panfrost_find_format(desc
);
1688 /* The field itself should probably be shifted over */
1689 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1696 panfrost_bind_vertex_elements_state(
1697 struct pipe_context
*pctx
,
1700 struct panfrost_context
*ctx
= pan_context(pctx
);
1702 ctx
->vertex
= hwcso
;
1703 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1707 panfrost_create_shader_state(
1708 struct pipe_context
*pctx
,
1709 const struct pipe_shader_state
*cso
)
1711 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1714 /* Token deep copy to prevent memory corruption */
1716 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1717 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1723 panfrost_delete_shader_state(
1724 struct pipe_context
*pctx
,
1727 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1729 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1730 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1737 panfrost_create_sampler_state(
1738 struct pipe_context
*pctx
,
1739 const struct pipe_sampler_state
*cso
)
1741 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1744 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1746 struct mali_sampler_descriptor sampler_descriptor
= {
1747 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1748 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1749 | translate_mip_filter(cso
->min_mip_filter
)
1752 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1753 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1754 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1755 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1757 cso
->border_color
.f
[0],
1758 cso
->border_color
.f
[1],
1759 cso
->border_color
.f
[2],
1760 cso
->border_color
.f
[3]
1762 .min_lod
= FIXED_16(cso
->min_lod
),
1763 .max_lod
= FIXED_16(cso
->max_lod
),
1767 so
->hw
= sampler_descriptor
;
1773 panfrost_bind_sampler_states(
1774 struct pipe_context
*pctx
,
1775 enum pipe_shader_type shader
,
1776 unsigned start_slot
, unsigned num_sampler
,
1779 assert(start_slot
== 0);
1781 struct panfrost_context
*ctx
= pan_context(pctx
);
1783 /* XXX: Should upload, not just copy? */
1784 ctx
->sampler_count
[shader
] = num_sampler
;
1785 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1787 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1791 panfrost_variant_matches(
1792 struct panfrost_context
*ctx
,
1793 struct panfrost_shader_state
*variant
,
1794 enum pipe_shader_type type
)
1796 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1798 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1800 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1801 /* Make sure enable state is at least the same */
1802 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1806 /* Check that the contents of the test are the same */
1807 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1808 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1810 if (!(same_func
&& same_ref
)) {
1814 /* Otherwise, we're good to go */
1819 panfrost_bind_shader_state(
1820 struct pipe_context
*pctx
,
1822 enum pipe_shader_type type
)
1824 struct panfrost_context
*ctx
= pan_context(pctx
);
1826 if (type
== PIPE_SHADER_FRAGMENT
) {
1828 ctx
->dirty
|= PAN_DIRTY_FS
;
1830 assert(type
== PIPE_SHADER_VERTEX
);
1832 ctx
->dirty
|= PAN_DIRTY_VS
;
1837 /* Match the appropriate variant */
1839 signed variant
= -1;
1840 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1842 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1843 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1849 if (variant
== -1) {
1850 /* No variant matched, so create a new one */
1851 variant
= variants
->variant_count
++;
1852 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1854 variants
->variants
[variant
].base
= hwcso
;
1856 if (type
== PIPE_SHADER_FRAGMENT
)
1857 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1859 /* Allocate the mapped descriptor ahead-of-time. */
1860 struct panfrost_context
*ctx
= pan_context(pctx
);
1861 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1863 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1864 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1868 /* Select this variant */
1869 variants
->active_variant
= variant
;
1871 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1872 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1874 /* We finally have a variant, so compile it */
1876 if (!shader_state
->compiled
) {
1877 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
1878 panfrost_job_type_for_pipe(type
), shader_state
);
1880 shader_state
->compiled
= true;
1885 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1887 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1891 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1893 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1897 panfrost_set_vertex_buffers(
1898 struct pipe_context
*pctx
,
1899 unsigned start_slot
,
1900 unsigned num_buffers
,
1901 const struct pipe_vertex_buffer
*buffers
)
1903 struct panfrost_context
*ctx
= pan_context(pctx
);
1905 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1909 panfrost_set_constant_buffer(
1910 struct pipe_context
*pctx
,
1911 enum pipe_shader_type shader
, uint index
,
1912 const struct pipe_constant_buffer
*buf
)
1914 struct panfrost_context
*ctx
= pan_context(pctx
);
1915 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1917 size_t sz
= buf
? buf
->buffer_size
: 0;
1919 /* Free previous buffer */
1926 pbuf
->buffer
= NULL
;
1929 /* If unbinding, we're done */
1934 /* Multiple constant buffers not yet supported */
1939 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1942 cpu
= rsrc
->bo
->cpu
;
1943 } else if (buf
->user_buffer
) {
1944 cpu
= buf
->user_buffer
;
1946 DBG("No constant buffer?\n");
1950 /* Copy the constant buffer into the driver context for later upload */
1952 pbuf
->buffer
= malloc(sz
);
1953 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1957 panfrost_set_stencil_ref(
1958 struct pipe_context
*pctx
,
1959 const struct pipe_stencil_ref
*ref
)
1961 struct panfrost_context
*ctx
= pan_context(pctx
);
1962 ctx
->stencil_ref
= *ref
;
1964 /* Shader core dirty */
1965 ctx
->dirty
|= PAN_DIRTY_FS
;
1968 static struct pipe_sampler_view
*
1969 panfrost_create_sampler_view(
1970 struct pipe_context
*pctx
,
1971 struct pipe_resource
*texture
,
1972 const struct pipe_sampler_view
*template)
1974 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1975 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1977 pipe_reference(NULL
, &texture
->reference
);
1979 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1982 so
->base
= *template;
1983 so
->base
.texture
= texture
;
1984 so
->base
.reference
.count
= 1;
1985 so
->base
.context
= pctx
;
1987 /* sampler_views correspond to texture descriptors, minus the texture
1988 * (data) itself. So, we serialise the descriptor here and cache it for
1991 /* Make sure it's something with which we're familiar */
1992 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1994 /* TODO: Detect from format better */
1995 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1997 unsigned char user_swizzle
[4] = {
1998 template->swizzle_r
,
1999 template->swizzle_g
,
2000 template->swizzle_b
,
2004 enum mali_format format
= panfrost_find_format(desc
);
2006 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2008 unsigned usage2_layout
= 0x10;
2010 switch (prsrc
->bo
->layout
) {
2012 usage2_layout
|= 0x8 | 0x4;
2015 usage2_layout
|= 0x1;
2018 usage2_layout
|= is_depth
? 0x1 : 0x2;
2025 /* Check if we need to set a custom stride by computing the "expected"
2026 * stride and comparing it to what the BO actually wants. Only applies
2027 * to linear textures, since tiled/compressed textures have strict
2028 * alignment requirements for their strides as it is */
2030 unsigned first_level
= template->u
.tex
.first_level
;
2031 unsigned last_level
= template->u
.tex
.last_level
;
2033 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2034 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2035 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2036 unsigned width
= u_minify(texture
->width0
, l
);
2037 unsigned comp_stride
= width
* bytes_per_pixel
;
2039 if (comp_stride
!= actual_stride
) {
2040 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2046 struct mali_texture_descriptor texture_descriptor
= {
2047 .width
= MALI_POSITIVE(texture
->width0
),
2048 .height
= MALI_POSITIVE(texture
->height0
),
2049 .depth
= MALI_POSITIVE(texture
->depth0
),
2053 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2057 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
2059 .usage2
= usage2_layout
2062 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2065 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2066 assert (template->u
.tex
.first_level
== 0);
2068 /* Disable mipmapping for now to avoid regressions while automipmapping
2069 * is being implemented. TODO: Remove me once automipmaps work */
2071 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2072 texture_descriptor
.nr_mipmap_levels
= 0;
2074 so
->hw
= texture_descriptor
;
2076 return (struct pipe_sampler_view
*) so
;
2080 panfrost_set_sampler_views(
2081 struct pipe_context
*pctx
,
2082 enum pipe_shader_type shader
,
2083 unsigned start_slot
, unsigned num_views
,
2084 struct pipe_sampler_view
**views
)
2086 struct panfrost_context
*ctx
= pan_context(pctx
);
2088 assert(start_slot
== 0);
2090 ctx
->sampler_view_count
[shader
] = num_views
;
2091 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2093 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2097 panfrost_sampler_view_destroy(
2098 struct pipe_context
*pctx
,
2099 struct pipe_sampler_view
*view
)
2101 pipe_resource_reference(&view
->texture
, NULL
);
2106 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2107 const struct pipe_framebuffer_state
*fb
)
2109 struct panfrost_context
*ctx
= pan_context(pctx
);
2111 /* Flush when switching away from an FBO, but not if the framebuffer
2112 * state is being restored by u_blitter
2115 if (!panfrost_is_scanout(ctx
) && !ctx
->blitter
->running
) {
2116 panfrost_flush(pctx
, NULL
, 0);
2119 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2120 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2121 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2122 ctx
->pipe_framebuffer
.width
= fb
->width
;
2123 ctx
->pipe_framebuffer
.height
= fb
->height
;
2125 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2126 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2128 /* check if changing cbuf */
2129 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2131 if (cb
&& (i
!= 0)) {
2132 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2137 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2142 if (ctx
->require_sfbd
)
2143 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2145 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2147 panfrost_attach_vt_framebuffer(ctx
);
2149 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2150 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2152 bool can_afbc
= panfrost_format_supports_afbc(format
);
2153 bool is_scanout
= panfrost_is_scanout(ctx
);
2155 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2156 panfrost_enable_afbc(ctx
, tex
, false);
2158 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2159 panfrost_enable_checksum(ctx
, tex
);
2163 struct pipe_surface
*zb
= fb
->zsbuf
;
2165 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2166 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2169 if (ctx
->require_sfbd
)
2170 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2172 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2174 panfrost_attach_vt_framebuffer(ctx
);
2176 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2177 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2178 bool is_scanout
= panfrost_is_scanout(ctx
);
2180 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2181 panfrost_enable_afbc(ctx
, tex
, true);
2188 panfrost_create_blend_state(struct pipe_context
*pipe
,
2189 const struct pipe_blend_state
*blend
)
2191 struct panfrost_context
*ctx
= pan_context(pipe
);
2192 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2195 /* TODO: The following features are not yet implemented */
2196 assert(!blend
->logicop_enable
);
2197 assert(!blend
->alpha_to_coverage
);
2198 assert(!blend
->alpha_to_one
);
2200 /* Compile the blend state, first as fixed-function if we can */
2202 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2205 /* If we can't, compile a blend shader instead */
2207 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2213 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2216 struct panfrost_context
*ctx
= pan_context(pipe
);
2217 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2218 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2219 ctx
->blend
= pblend
;
2224 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2226 /* TODO: Attach color */
2228 /* Shader itself is not dirty, but the shader core is */
2229 ctx
->dirty
|= PAN_DIRTY_FS
;
2233 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2236 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2238 if (so
->has_blend_shader
) {
2239 DBG("Deleting blend state leak blend shaders bytecode\n");
2246 panfrost_set_blend_color(struct pipe_context
*pipe
,
2247 const struct pipe_blend_color
*blend_color
)
2249 struct panfrost_context
*ctx
= pan_context(pipe
);
2251 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2254 ctx
->blend_color
= *blend_color
;
2256 /* The blend mode depends on the blend constant color, due to the
2257 * fixed/programmable split. So, we're forced to regenerate the blend
2260 /* TODO: Attach color */
2265 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2266 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2268 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2272 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2275 struct panfrost_context
*ctx
= pan_context(pipe
);
2276 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2277 ctx
->depth_stencil
= depth_stencil
;
2282 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2283 * emulated in the fragment shader */
2285 if (depth_stencil
->alpha
.enabled
) {
2286 /* We need to trigger a new shader (maybe) */
2287 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2291 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2293 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2294 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2296 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2297 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2299 /* Depth state (TODO: Refactor) */
2300 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2302 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2304 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2305 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2307 /* Bounds test not implemented */
2308 assert(!depth_stencil
->depth
.bounds_test
);
2310 ctx
->dirty
|= PAN_DIRTY_FS
;
2314 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2320 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2321 unsigned sample_mask
)
2326 panfrost_set_clip_state(struct pipe_context
*pipe
,
2327 const struct pipe_clip_state
*clip
)
2329 //struct panfrost_context *panfrost = pan_context(pipe);
2333 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2334 unsigned start_slot
,
2335 unsigned num_viewports
,
2336 const struct pipe_viewport_state
*viewports
)
2338 struct panfrost_context
*ctx
= pan_context(pipe
);
2340 assert(start_slot
== 0);
2341 assert(num_viewports
== 1);
2343 ctx
->pipe_viewport
= *viewports
;
2347 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2348 unsigned start_slot
,
2349 unsigned num_scissors
,
2350 const struct pipe_scissor_state
*scissors
)
2352 struct panfrost_context
*ctx
= pan_context(pipe
);
2354 assert(start_slot
== 0);
2355 assert(num_scissors
== 1);
2357 ctx
->scissor
= *scissors
;
2361 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2362 const struct pipe_poly_stipple
*stipple
)
2364 //struct panfrost_context *panfrost = pan_context(pipe);
2368 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2371 //struct panfrost_context *panfrost = pan_context(pipe);
2375 panfrost_destroy(struct pipe_context
*pipe
)
2377 struct panfrost_context
*panfrost
= pan_context(pipe
);
2378 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2380 if (panfrost
->blitter
)
2381 util_blitter_destroy(panfrost
->blitter
);
2383 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2384 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2385 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2386 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2387 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2390 static struct pipe_query
*
2391 panfrost_create_query(struct pipe_context
*pipe
,
2395 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2400 return (struct pipe_query
*) q
;
2404 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2410 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2412 struct panfrost_context
*ctx
= pan_context(pipe
);
2413 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2415 switch (query
->type
) {
2416 case PIPE_QUERY_OCCLUSION_COUNTER
:
2417 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2418 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2420 /* Allocate a word for the query results to be stored */
2421 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2423 ctx
->occlusion_query
= query
;
2429 DBG("Skipping query %d\n", query
->type
);
2437 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2439 struct panfrost_context
*ctx
= pan_context(pipe
);
2440 ctx
->occlusion_query
= NULL
;
2445 panfrost_get_query_result(struct pipe_context
*pipe
,
2446 struct pipe_query
*q
,
2448 union pipe_query_result
*vresult
)
2451 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2453 /* We need to flush out the jobs to actually run the counter, TODO
2454 * check wait, TODO wallpaper after if needed */
2456 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2458 switch (query
->type
) {
2459 case PIPE_QUERY_OCCLUSION_COUNTER
:
2460 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2461 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2462 /* Read back the query results */
2463 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2464 unsigned passed
= *result
;
2466 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2467 vresult
->u64
= passed
;
2469 vresult
->b
= !!passed
;
2475 DBG("Skipped query get %d\n", query
->type
);
2482 static struct pipe_stream_output_target
*
2483 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2484 struct pipe_resource
*prsc
,
2485 unsigned buffer_offset
,
2486 unsigned buffer_size
)
2488 struct pipe_stream_output_target
*target
;
2490 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2495 pipe_reference_init(&target
->reference
, 1);
2496 pipe_resource_reference(&target
->buffer
, prsc
);
2498 target
->context
= pctx
;
2499 target
->buffer_offset
= buffer_offset
;
2500 target
->buffer_size
= buffer_size
;
2506 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2507 struct pipe_stream_output_target
*target
)
2509 pipe_resource_reference(&target
->buffer
, NULL
);
2514 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2515 unsigned num_targets
,
2516 struct pipe_stream_output_target
**targets
,
2517 const unsigned *offsets
)
2523 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2525 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2526 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2528 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2529 /* Allocate the beginning of the transient pool */
2530 int entry_size
= (1 << 22); /* 4MB */
2532 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2533 ctx
->transient_pools
[i
].entry_count
= 1;
2535 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2538 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2539 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2540 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2541 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2542 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2546 /* New context creation, which also does hardware initialisation since I don't
2547 * know the better way to structure this :smirk: */
2549 struct pipe_context
*
2550 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2552 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2553 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2554 memset(ctx
, 0, sizeof(*ctx
));
2555 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2558 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2560 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2561 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2563 gallium
->screen
= screen
;
2565 gallium
->destroy
= panfrost_destroy
;
2567 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2569 gallium
->flush
= panfrost_flush
;
2570 gallium
->clear
= panfrost_clear
;
2571 gallium
->draw_vbo
= panfrost_draw_vbo
;
2573 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2574 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2576 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2578 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2579 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2580 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2582 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2583 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2584 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2586 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2587 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2588 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2590 gallium
->create_fs_state
= panfrost_create_shader_state
;
2591 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2592 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2594 gallium
->create_vs_state
= panfrost_create_shader_state
;
2595 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2596 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2598 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2599 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2600 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2602 gallium
->create_blend_state
= panfrost_create_blend_state
;
2603 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2604 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2606 gallium
->set_blend_color
= panfrost_set_blend_color
;
2608 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2609 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2610 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2612 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2614 gallium
->set_clip_state
= panfrost_set_clip_state
;
2615 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2616 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2617 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2618 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2620 gallium
->create_query
= panfrost_create_query
;
2621 gallium
->destroy_query
= panfrost_destroy_query
;
2622 gallium
->begin_query
= panfrost_begin_query
;
2623 gallium
->end_query
= panfrost_end_query
;
2624 gallium
->get_query_result
= panfrost_get_query_result
;
2626 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2627 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2628 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2630 panfrost_resource_context_init(gallium
);
2632 pscreen
->driver
->init_context(ctx
);
2634 panfrost_setup_hardware(ctx
);
2637 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2638 gallium
->const_uploader
= gallium
->stream_uploader
;
2639 assert(gallium
->stream_uploader
);
2641 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2642 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2644 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2646 ctx
->blitter
= util_blitter_create(gallium
);
2647 assert(ctx
->blitter
);
2649 /* Prepare for render! */
2651 panfrost_job_init(ctx
);
2652 panfrost_emit_vertex_payload(ctx
);
2653 panfrost_emit_tiler_payload(ctx
);
2654 panfrost_invalidate_frame(ctx
);
2655 panfrost_default_shader_backend(ctx
);
2656 panfrost_generate_space_filler_indices();