2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_format.h"
31 #include "util/macros.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_memory.h"
36 #include "util/u_vbuf.h"
37 #include "util/half_float.h"
38 #include "util/u_helpers.h"
39 #include "util/u_format.h"
40 #include "indices/u_primconvert.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "util/u_math.h"
44 #include "pan_screen.h"
45 #include "pan_blending.h"
46 #include "pan_blend_shaders.h"
48 #include "pan_tiler.h"
50 static int performance_counter_number
= 0;
51 extern const char *pan_counters_base
;
53 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
56 static enum mali_job_type
57 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
60 case PIPE_SHADER_VERTEX
:
61 return JOB_TYPE_VERTEX
;
63 case PIPE_SHADER_FRAGMENT
:
64 /* Note: JOB_TYPE_FRAGMENT is different.
65 * JOB_TYPE_FRAGMENT actually executes the
66 * fragment shader, but JOB_TYPE_TILER is how you
68 return JOB_TYPE_TILER
;
70 case PIPE_SHADER_GEOMETRY
:
71 return JOB_TYPE_GEOMETRY
;
73 case PIPE_SHADER_COMPUTE
:
74 return JOB_TYPE_COMPUTE
;
77 unreachable("Unsupported shader stage");
82 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
84 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
85 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
86 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
87 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
89 /* 8 byte checksum per tile */
90 rsrc
->bo
->checksum_stride
= tile_w
* 8;
91 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
92 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
94 rsrc
->bo
->has_checksum
= true;
97 /* Framebuffer descriptor */
100 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
102 fb
->width
= MALI_POSITIVE(w
);
103 fb
->height
= MALI_POSITIVE(h
);
105 /* No idea why this is needed, but it's how resolution_check is
106 * calculated. It's not clear to us yet why the hardware wants this.
107 * The formula itself was discovered mostly by manual bruteforce and
108 * aggressive algebraic simplification. */
110 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
113 struct mali_single_framebuffer
114 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
116 struct mali_single_framebuffer framebuffer
= {
118 .format
= 0x30000000,
119 .clear_flags
= 0x1000,
120 .unknown_address_0
= ctx
->scratchpad
.gpu
,
121 .tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
,
122 .tiler_polygon_list_body
= ctx
->tiler_polygon_list
.gpu
+ 40960,
123 .tiler_hierarchy_mask
= 0xF0,
125 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
126 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
129 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
134 struct bifrost_framebuffer
135 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
137 unsigned width
= ctx
->pipe_framebuffer
.width
;
138 unsigned height
= ctx
->pipe_framebuffer
.height
;
140 struct bifrost_framebuffer framebuffer
= {
141 .width1
= MALI_POSITIVE(width
),
142 .height1
= MALI_POSITIVE(height
),
143 .width2
= MALI_POSITIVE(width
),
144 .height2
= MALI_POSITIVE(height
),
149 .rt_count_1
= MALI_POSITIVE(1),
154 .scratchpad
= ctx
->scratchpad
.gpu
,
157 framebuffer
.tiler_hierarchy_mask
=
158 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
160 /* Compute the polygon header size and use that to offset the body */
162 unsigned header_size
= panfrost_tiler_header_size(
163 width
, height
, framebuffer
.tiler_hierarchy_mask
);
165 unsigned body_size
= panfrost_tiler_body_size(
166 width
, height
, framebuffer
.tiler_hierarchy_mask
);
170 unsigned total_size
= header_size
+ body_size
;
172 if (framebuffer
.tiler_hierarchy_mask
) {
173 assert(ctx
->tiler_polygon_list
.size
>= total_size
);
175 /* Specify allocated tiler structures */
176 framebuffer
.tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
;
178 /* Allow the entire tiler heap */
179 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
180 framebuffer
.tiler_heap_end
=
181 ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
;
183 /* The tiler is disabled, so don't allow the tiler heap */
184 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
185 framebuffer
.tiler_heap_end
= framebuffer
.tiler_heap_start
;
187 /* Use a dummy polygon list */
188 framebuffer
.tiler_polygon_list
= ctx
->tiler_dummy
.gpu
;
190 /* Also, set a "tiler disabled?" flag? */
191 framebuffer
.tiler_hierarchy_mask
|= 0x1000;
194 framebuffer
.tiler_polygon_list_body
=
195 framebuffer
.tiler_polygon_list
+ header_size
;
197 framebuffer
.tiler_polygon_list_size
=
198 header_size
+ body_size
;
205 /* Are we currently rendering to the screen (rather than an FBO)? */
208 panfrost_is_scanout(struct panfrost_context
*ctx
)
210 /* If there is no color buffer, it's an FBO */
211 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
214 /* If we're too early that no framebuffer was sent, it's scanout */
215 if (!ctx
->pipe_framebuffer
.cbufs
[0])
218 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
219 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
220 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
225 struct pipe_context
*pipe
,
227 const union pipe_color_union
*color
,
228 double depth
, unsigned stencil
)
230 struct panfrost_context
*ctx
= pan_context(pipe
);
231 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
233 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
237 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
239 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
243 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
245 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
249 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
251 mali_ptr framebuffer
= ctx
->require_sfbd
?
252 panfrost_attach_vt_sfbd(ctx
) :
253 panfrost_attach_vt_mfbd(ctx
);
255 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
256 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
259 /* Reset per-frame context, called on context initialisation as well as after
260 * flushing a frame */
263 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
265 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
266 DBG("Uploaded transient %d bytes\n", transient_count
);
268 /* Rotate cmdstream */
269 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
270 ctx
->cmdstream_i
= 0;
272 if (ctx
->require_sfbd
)
273 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
275 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
277 /* Reset varyings allocated */
278 ctx
->varying_height
= 0;
280 /* The transient cmdstream is dirty every frame; the only bits worth preserving
281 * (textures, shaders, etc) are in other buffers anyways */
283 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
284 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
286 /* Regenerate payloads */
287 panfrost_attach_vt_framebuffer(ctx
);
290 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
293 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
296 /* In practice, every field of these payloads should be configurable
297 * arbitrarily, which means these functions are basically catch-all's for
298 * as-of-yet unwavering unknowns */
301 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
303 struct midgard_payload_vertex_tiler payload
= {
305 .workgroups_z_shift
= 32,
306 .workgroups_x_shift_2
= 0x2,
307 .workgroups_x_shift_3
= 0x5,
309 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
312 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
316 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
318 struct midgard_payload_vertex_tiler payload
= {
320 .workgroups_z_shift
= 32,
321 .workgroups_x_shift_2
= 0x2,
322 .workgroups_x_shift_3
= 0x6,
324 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
328 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
332 translate_tex_wrap(enum pipe_tex_wrap w
)
335 case PIPE_TEX_WRAP_REPEAT
:
336 return MALI_WRAP_REPEAT
;
338 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
339 return MALI_WRAP_CLAMP_TO_EDGE
;
341 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
342 return MALI_WRAP_CLAMP_TO_BORDER
;
344 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
345 return MALI_WRAP_MIRRORED_REPEAT
;
348 unreachable("Invalid wrap");
353 translate_tex_filter(enum pipe_tex_filter f
)
356 case PIPE_TEX_FILTER_NEAREST
:
359 case PIPE_TEX_FILTER_LINEAR
:
363 unreachable("Invalid filter");
368 translate_mip_filter(enum pipe_tex_mipfilter f
)
370 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
374 panfrost_translate_compare_func(enum pipe_compare_func in
)
377 case PIPE_FUNC_NEVER
:
378 return MALI_FUNC_NEVER
;
381 return MALI_FUNC_LESS
;
383 case PIPE_FUNC_EQUAL
:
384 return MALI_FUNC_EQUAL
;
386 case PIPE_FUNC_LEQUAL
:
387 return MALI_FUNC_LEQUAL
;
389 case PIPE_FUNC_GREATER
:
390 return MALI_FUNC_GREATER
;
392 case PIPE_FUNC_NOTEQUAL
:
393 return MALI_FUNC_NOTEQUAL
;
395 case PIPE_FUNC_GEQUAL
:
396 return MALI_FUNC_GEQUAL
;
398 case PIPE_FUNC_ALWAYS
:
399 return MALI_FUNC_ALWAYS
;
402 unreachable("Invalid func");
407 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
410 case PIPE_FUNC_NEVER
:
411 return MALI_ALT_FUNC_NEVER
;
414 return MALI_ALT_FUNC_LESS
;
416 case PIPE_FUNC_EQUAL
:
417 return MALI_ALT_FUNC_EQUAL
;
419 case PIPE_FUNC_LEQUAL
:
420 return MALI_ALT_FUNC_LEQUAL
;
422 case PIPE_FUNC_GREATER
:
423 return MALI_ALT_FUNC_GREATER
;
425 case PIPE_FUNC_NOTEQUAL
:
426 return MALI_ALT_FUNC_NOTEQUAL
;
428 case PIPE_FUNC_GEQUAL
:
429 return MALI_ALT_FUNC_GEQUAL
;
431 case PIPE_FUNC_ALWAYS
:
432 return MALI_ALT_FUNC_ALWAYS
;
435 unreachable("Invalid alt func");
440 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
443 case PIPE_STENCIL_OP_KEEP
:
444 return MALI_STENCIL_KEEP
;
446 case PIPE_STENCIL_OP_ZERO
:
447 return MALI_STENCIL_ZERO
;
449 case PIPE_STENCIL_OP_REPLACE
:
450 return MALI_STENCIL_REPLACE
;
452 case PIPE_STENCIL_OP_INCR
:
453 return MALI_STENCIL_INCR
;
455 case PIPE_STENCIL_OP_DECR
:
456 return MALI_STENCIL_DECR
;
458 case PIPE_STENCIL_OP_INCR_WRAP
:
459 return MALI_STENCIL_INCR_WRAP
;
461 case PIPE_STENCIL_OP_DECR_WRAP
:
462 return MALI_STENCIL_DECR_WRAP
;
464 case PIPE_STENCIL_OP_INVERT
:
465 return MALI_STENCIL_INVERT
;
468 unreachable("Invalid stencil op");
473 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
475 out
->ref
= 0; /* Gallium gets it from elsewhere */
477 out
->mask
= in
->valuemask
;
478 out
->func
= panfrost_translate_compare_func(in
->func
);
479 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
480 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
481 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
485 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
487 struct mali_shader_meta shader
= {
488 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
490 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
491 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
495 shader
.unknown2_4
|= 0x10;
498 struct pipe_stencil_state default_stencil
= {
500 .func
= PIPE_FUNC_ALWAYS
,
501 .fail_op
= MALI_STENCIL_KEEP
,
502 .zfail_op
= MALI_STENCIL_KEEP
,
503 .zpass_op
= MALI_STENCIL_KEEP
,
508 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
509 shader
.stencil_mask_front
= default_stencil
.writemask
;
511 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
512 shader
.stencil_mask_back
= default_stencil
.writemask
;
514 if (default_stencil
.enabled
)
515 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
517 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
521 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
523 if (first
->job_descriptor_size
)
524 first
->next_job_64
= (u64
) (uintptr_t) next
;
526 first
->next_job_32
= (u32
) (uintptr_t) next
;
529 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
530 * graphics command stream. It should be called once per draw, accordding to
531 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
532 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
535 struct panfrost_transfer
536 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
538 /* Each draw call corresponds to two jobs, and the set-value job is first */
539 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
541 struct mali_job_descriptor_header job
= {
542 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
543 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
545 .job_descriptor_size
= 1,
549 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
551 /* There's some padding hacks on 32-bit */
558 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
561 /* Tiler jobs depend on vertex jobs */
563 job
.job_dependency_index_1
= draw_job_index
;
565 /* Tiler jobs also depend on the previous tiler job */
567 if (ctx
->draw_count
) {
568 job
.job_dependency_index_2
= draw_job_index
- 1;
569 /* Previous tiler job points to this tiler job */
570 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
572 /* The only vertex job so far points to first tiler job */
573 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
576 if (ctx
->draw_count
) {
577 /* Previous vertex job points to this vertex job */
578 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
580 /* Last vertex job points to first tiler job */
581 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
583 /* Have the first vertex job depend on the set value job */
584 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
585 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
589 memcpy(transfer
.cpu
, &job
, sizeof(job
));
590 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
594 /* Generates a set value job. It's unclear what exactly this does, why it's
595 * necessary, and when to call it. */
598 panfrost_set_value_job(struct panfrost_context
*ctx
)
600 struct mali_job_descriptor_header job
= {
601 .job_type
= JOB_TYPE_SET_VALUE
,
602 .job_descriptor_size
= 1,
606 struct mali_payload_set_value payload
= {
607 .out
= ctx
->tiler_polygon_list
.gpu
,
611 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
612 memcpy(transfer
.cpu
, &job
, sizeof(job
));
613 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
615 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
616 ctx
->set_value_job
= transfer
.gpu
;
620 panfrost_emit_varyings(
621 struct panfrost_context
*ctx
,
622 union mali_attr
*slot
,
626 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
628 /* Fill out the descriptor */
629 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
630 slot
->stride
= stride
;
631 slot
->size
= stride
* count
;
633 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
634 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
636 return varying_address
;
640 panfrost_emit_point_coord(union mali_attr
*slot
)
642 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
643 slot
->stride
= slot
->size
= 0;
647 panfrost_emit_varying_descriptor(
648 struct panfrost_context
*ctx
,
649 unsigned invocation_count
)
651 /* Load the shaders */
653 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
654 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
655 unsigned int num_gen_varyings
= 0;
657 /* Allocate the varying descriptor */
659 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
660 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
662 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
666 * Assign ->src_offset now that we know about all the general purpose
667 * varyings that will be used by the fragment and vertex shaders.
669 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
671 * General purpose varyings have ->index set to 0, skip other
674 if (vs
->varyings
[i
].index
)
677 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
680 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
683 if (fs
->varyings
[i
].index
)
687 * Re-use the VS general purpose varying pos if it exists,
688 * create a new one otherwise.
690 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
691 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
695 if (j
< vs
->tripipe
->varying_count
)
696 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
698 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
701 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
702 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
704 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
705 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
707 /* Buffer indices must be in this order per our convention */
708 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
711 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
714 /* fp32 vec4 gl_Position */
715 ctx
->payload_tiler
.postfix
.position_varying
=
716 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
717 sizeof(float) * 4, invocation_count
);
720 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
721 /* fp16 vec1 gl_PointSize */
722 ctx
->payload_tiler
.primitive_size
.pointer
=
723 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
724 2, invocation_count
);
727 if (fs
->reads_point_coord
) {
728 /* Special descriptor */
729 panfrost_emit_point_coord(&varyings
[idx
++]);
732 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
733 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
734 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
738 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
740 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
741 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
743 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
746 /* Emits attributes and varying descriptors, which should be called every draw,
747 * excepting some obscure circumstances */
750 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
752 /* Staged mali_attr, and index into them. i =/= k, depending on the
753 * vertex buffer mask */
754 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
757 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
759 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
760 if (!(ctx
->vb_mask
& (1 << i
))) continue;
762 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
763 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
767 /* Align to 64 bytes by masking off the lower bits. This
768 * will be adjusted back when we fixup the src_offset in
771 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
773 /* Offset vertex count by draw_start to make sure we upload enough */
774 attrs
[k
].stride
= buf
->stride
;
775 attrs
[k
].size
= rsrc
->base
.width0
;
777 panfrost_job_add_bo(job
, rsrc
->bo
);
778 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
783 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
785 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
789 panfrost_writes_point_size(struct panfrost_context
*ctx
)
792 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
794 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
797 /* Stage the attribute descriptors so we can adjust src_offset
798 * to let BOs align nicely */
801 panfrost_stage_attributes(struct panfrost_context
*ctx
)
803 struct panfrost_vertex_state
*so
= ctx
->vertex
;
805 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
806 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
807 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
809 /* Copy as-is for the first pass */
810 memcpy(target
, so
->hw
, sz
);
812 /* Fixup offsets for the second pass. Recall that the hardware
813 * calculates attribute addresses as:
815 * addr = base + (stride * vtx) + src_offset;
817 * However, on Mali, base must be aligned to 64-bytes, so we
820 * base' = base & ~63 = base - (base & 63)
822 * To compensate when using base' (see emit_vertex_data), we have
823 * to adjust src_offset by the masked off piece:
825 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
826 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
827 * = base + (stride * vtx) + src_offset
833 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
834 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
835 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
837 /* Adjust by the masked off bits of the offset */
838 target
[i
].src_offset
+= (addr
& 63);
841 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
845 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
847 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
849 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
852 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
853 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
855 struct panfrost_transfer transfer
=
856 panfrost_allocate_transient(ctx
, transfer_size
);
858 struct mali_sampler_descriptor
*desc
=
859 (struct mali_sampler_descriptor
*) transfer
.cpu
;
861 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
862 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
864 upload
= transfer
.gpu
;
867 if (t
== PIPE_SHADER_FRAGMENT
)
868 ctx
->payload_tiler
.postfix
.sampler_descriptor
= upload
;
869 else if (t
== PIPE_SHADER_VERTEX
)
870 ctx
->payload_vertex
.postfix
.sampler_descriptor
= upload
;
876 /* Computes the address to a texture at a particular slice */
879 panfrost_get_texture_address(
880 struct panfrost_resource
*rsrc
,
881 unsigned level
, unsigned face
)
883 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
884 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
886 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
892 struct panfrost_context
*ctx
,
893 struct panfrost_sampler_view
*view
)
896 return (mali_ptr
) NULL
;
898 struct pipe_sampler_view
*pview
= &view
->base
;
899 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
901 /* Do we interleave an explicit stride with every element? */
903 bool has_manual_stride
=
904 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
906 /* For easy access */
908 assert(pview
->target
!= PIPE_BUFFER
);
909 unsigned first_level
= pview
->u
.tex
.first_level
;
910 unsigned last_level
= pview
->u
.tex
.last_level
;
912 /* Inject the addresses in, interleaving mip levels, cube faces, and
913 * strides in that order */
917 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
918 for (unsigned f
= 0; f
< pview
->texture
->array_size
; ++f
) {
919 view
->hw
.payload
[idx
++] =
920 panfrost_get_texture_address(rsrc
, l
, f
);
922 if (has_manual_stride
) {
923 view
->hw
.payload
[idx
++] =
924 rsrc
->bo
->slices
[l
].stride
;
929 return panfrost_upload_transient(ctx
, &view
->hw
,
930 sizeof(struct mali_texture_descriptor
));
934 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
936 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
937 mali_ptr trampoline
= 0;
939 if (ctx
->sampler_view_count
[t
]) {
940 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
942 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
944 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
946 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
949 if (t
== PIPE_SHADER_FRAGMENT
)
950 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
951 else if (t
== PIPE_SHADER_VERTEX
)
952 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
958 struct sysval_uniform
{
966 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
967 struct sysval_uniform
*uniform
)
969 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
971 uniform
->f
[0] = vp
->scale
[0];
972 uniform
->f
[1] = vp
->scale
[1];
973 uniform
->f
[2] = vp
->scale
[2];
976 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
977 struct sysval_uniform
*uniform
)
979 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
981 uniform
->f
[0] = vp
->translate
[0];
982 uniform
->f
[1] = vp
->translate
[1];
983 uniform
->f
[2] = vp
->translate
[2];
986 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
987 enum pipe_shader_type st
,
988 unsigned int sysvalid
,
989 struct sysval_uniform
*uniform
)
991 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
992 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
993 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
994 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
997 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
1000 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
1001 tex
->u
.tex
.first_level
);
1004 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
1005 tex
->u
.tex
.first_level
);
1008 uniform
->i
[dim
] = tex
->texture
->array_size
;
1011 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
1012 struct panfrost_shader_state
*ss
,
1013 enum pipe_shader_type st
)
1015 struct sysval_uniform
*uniforms
= (void *)buf
;
1017 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1018 int sysval
= ss
->sysval
[i
];
1020 switch (PAN_SYSVAL_TYPE(sysval
)) {
1021 case PAN_SYSVAL_VIEWPORT_SCALE
:
1022 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
1024 case PAN_SYSVAL_VIEWPORT_OFFSET
:
1025 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
1027 case PAN_SYSVAL_TEXTURE_SIZE
:
1028 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
1037 /* Go through dirty flags and actualise them in the cmdstream. */
1040 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1042 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1044 if (with_vertex_data
) {
1045 panfrost_emit_vertex_data(ctx
, job
);
1048 bool msaa
= ctx
->rasterizer
->base
.multisample
;
1050 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1051 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1053 /* TODO: Sample size */
1054 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1055 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1058 panfrost_job_set_requirements(ctx
, job
);
1060 if (ctx
->occlusion_query
) {
1061 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1062 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1065 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1068 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1070 /* Late shader descriptor assignments */
1072 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1073 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1076 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1078 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1081 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1082 /* Check if we need to link the gl_PointSize varying */
1083 if (!panfrost_writes_point_size(ctx
)) {
1084 /* If the size is constant, write it out. Otherwise,
1085 * don't touch primitive_size (since we would clobber
1086 * the pointer there) */
1088 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1092 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1094 ctx
->dirty
|= PAN_DIRTY_FS
;
1096 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1098 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1100 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1103 COPY(attribute_count
);
1104 COPY(varying_count
);
1105 COPY(midgard1
.uniform_count
);
1106 COPY(midgard1
.work_count
);
1107 COPY(midgard1
.unknown2
);
1110 /* If there is a blend shader, work registers are shared */
1112 if (ctx
->blend
->has_blend_shader
)
1113 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1115 /* Set late due to depending on render state */
1116 /* The one at the end seems to mean "1 UBO" */
1117 unsigned flags
= MALI_EARLY_Z
| 0x200 | 0x2000 | 0x1;
1119 /* Any time texturing is used, derivatives are implicitly
1120 * calculated, so we need to enable helper invocations */
1122 if (ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
])
1123 flags
|= MALI_HELPER_INVOCATIONS
;
1125 ctx
->fragment_shader_core
.midgard1
.unknown1
= flags
;
1127 /* Assign texture/sample count right before upload */
1128 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1129 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1131 /* Assign the stencil refs late */
1132 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1133 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1135 /* CAN_DISCARD should be set if the fragment shader possibly
1136 * contains a 'discard' instruction. It is likely this is
1137 * related to optimizations related to forward-pixel kill, as
1138 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1139 * thing?" by Peter Harris
1142 if (variant
->can_discard
) {
1143 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1144 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_EARLY_Z
;
1145 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1146 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1149 /* Check if we're using the default blend descriptor (fast path) */
1152 !ctx
->blend
->has_blend_shader
&&
1153 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1154 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1155 (ctx
->blend
->equation
.color_mask
== 0xf);
1157 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1158 * *also* copied to the blend_meta appended (by convention),
1159 * but this is the field actually read by the hardware. (Or
1160 * maybe both are read...?) */
1162 if (ctx
->blend
->has_blend_shader
) {
1163 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1165 ctx
->fragment_shader_core
.blend
.shader
= 0;
1168 if (ctx
->require_sfbd
) {
1169 /* When only a single render target platform is used, the blend
1170 * information is inside the shader meta itself. We
1171 * additionally need to signal CAN_DISCARD for nontrivial blend
1172 * modes (so we're able to read back the destination buffer) */
1174 if (!ctx
->blend
->has_blend_shader
) {
1175 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1176 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1180 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1184 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1185 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1186 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1188 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1190 if (!ctx
->require_sfbd
) {
1191 /* Additional blend descriptor tacked on for jobs using MFBD */
1193 unsigned blend_count
= 0x200;
1195 if (ctx
->blend
->has_blend_shader
) {
1196 /* For a blend shader, the bottom nibble corresponds to
1197 * the number of work registers used, which signals the
1198 * -existence- of a blend shader */
1200 assert(ctx
->blend
->blend_work_count
>= 2);
1201 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1203 /* Otherwise, the bottom bit simply specifies if
1204 * blending (anything other than REPLACE) is enabled */
1211 struct midgard_blend_rt rts
[4];
1215 for (unsigned i
= 0; i
< 1; ++i
) {
1217 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1219 rts
[i
].flags
= blend_count
;
1222 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1224 /* TODO: sRGB in blend shaders is currently
1225 * unimplemented. Contact me (Alyssa) if you're
1226 * interested in working on this. We have
1227 * native Midgard ops for helping here, but
1228 * they're not well-understood yet. */
1230 assert(!(is_srgb
&& ctx
->blend
->has_blend_shader
));
1232 if (ctx
->blend
->has_blend_shader
) {
1233 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1235 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1236 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1240 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1244 /* We stage to transient, so always dirty.. */
1245 panfrost_stage_attributes(ctx
);
1247 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1248 panfrost_upload_sampler_descriptors(ctx
);
1250 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1251 panfrost_upload_texture_descriptors(ctx
);
1253 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1255 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1256 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1258 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1259 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1260 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1262 /* Allocate room for the sysval and the uniforms */
1263 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1264 size_t size
= sys_size
+ buf
->size
;
1265 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1267 /* Upload sysvals requested by the shader */
1268 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1270 /* Upload uniforms */
1271 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1273 int uniform_count
= 0;
1275 struct mali_vertex_tiler_postfix
*postfix
;
1278 case PIPE_SHADER_VERTEX
:
1279 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1280 postfix
= &ctx
->payload_vertex
.postfix
;
1283 case PIPE_SHADER_FRAGMENT
:
1284 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1285 postfix
= &ctx
->payload_tiler
.postfix
;
1289 unreachable("Invalid shader stage\n");
1292 /* Also attach the same buffer as a UBO for extended access */
1294 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1296 .size
= MALI_POSITIVE((2 + uniform_count
)),
1297 .ptr
= transfer
.gpu
>> 2,
1301 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1302 postfix
->uniforms
= transfer
.gpu
;
1303 postfix
->uniform_buffers
= ubufs
;
1308 /* TODO: Upload the viewport somewhere more appropriate */
1310 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1311 * (somewhat) asymmetric ints. */
1312 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1314 struct mali_viewport view
= {
1315 /* By default, do no viewport clipping, i.e. clip to (-inf,
1316 * inf) in each direction. Clipping to the viewport in theory
1317 * should work, but in practice causes issues when we're not
1318 * explicitly trying to scissor */
1329 /* Always scissor to the viewport by default. */
1330 int minx
= (int) (vp
->translate
[0] - vp
->scale
[0]);
1331 int maxx
= (int) (vp
->translate
[0] + vp
->scale
[0]);
1333 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1334 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1336 /* Apply the scissor test */
1338 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1345 /* Hardware needs the min/max to be strictly ordered, so flip if we
1346 * need to. The viewport transformation in the vertex shader will
1347 * handle the negatives if we don't */
1361 /* Clamp everything positive, just in case */
1363 maxx
= MAX2(0, maxx
);
1364 maxy
= MAX2(0, maxy
);
1365 minx
= MAX2(0, minx
);
1366 miny
= MAX2(0, miny
);
1368 /* Clamp to the framebuffer size as a last check */
1370 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1371 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1373 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1374 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1376 /* Update the job, unless we're doing wallpapering (whose lack of
1377 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1378 * just... be faster :) */
1380 if (!ctx
->in_wallpaper
)
1381 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1385 view
.viewport0
[0] = minx
;
1386 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1388 view
.viewport0
[1] = miny
;
1389 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1391 ctx
->payload_tiler
.postfix
.viewport
=
1392 panfrost_upload_transient(ctx
,
1394 sizeof(struct mali_viewport
));
1399 /* Corresponds to exactly one draw, but does not submit anything */
1402 panfrost_queue_draw(struct panfrost_context
*ctx
)
1404 /* TODO: Expand the array? */
1405 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1406 DBG("Job buffer overflow, ignoring draw\n");
1410 /* Handle dirty flags now */
1411 panfrost_emit_for_draw(ctx
, true);
1413 /* We need a set_value job before any other draw jobs */
1414 if (ctx
->draw_count
== 0)
1415 panfrost_set_value_job(ctx
);
1417 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1418 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1419 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1421 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1422 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1423 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1428 /* The entire frame is in memory -- send it off to the kernel! */
1431 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1432 struct pipe_fence_handle
**fence
,
1433 struct panfrost_job
*job
)
1435 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1436 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1440 panfrost_job_submit(ctx
, job
);
1442 /* If visual, we can stall a frame */
1444 if (!flush_immediate
)
1445 screen
->driver
->force_flush_fragment(ctx
, fence
);
1447 screen
->last_fragment_flushed
= false;
1448 screen
->last_job
= job
;
1450 /* If readback, flush now (hurts the pipelined performance) */
1451 if (flush_immediate
)
1452 screen
->driver
->force_flush_fragment(ctx
, fence
);
1454 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1455 screen
->driver
->dump_counters(screen
);
1458 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1459 FILE *fp
= fopen(filename
, "wb");
1460 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1468 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1470 struct panfrost_context
*ctx
= pan_context(pipe
);
1472 /* Nothing to reload? */
1473 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1476 /* Blit the wallpaper in */
1477 ctx
->in_wallpaper
= true;
1478 panfrost_blit_wallpaper(ctx
);
1479 ctx
->in_wallpaper
= false;
1481 /* We are flushing all queued draws and we know that no more jobs will
1482 * be added until the next frame.
1483 * We also know that the last jobs are the wallpaper jobs, and they
1484 * need to be linked so they execute right after the set_value job.
1487 /* set_value job to wallpaper vertex job */
1488 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1489 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1491 /* wallpaper vertex job to first vertex job */
1492 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1493 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1495 /* last vertex job to wallpaper tiler job */
1496 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1497 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1498 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1500 /* wallpaper tiler job to first tiler job */
1501 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1502 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1503 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1505 /* last tiler job to NULL */
1506 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1511 struct pipe_context
*pipe
,
1512 struct pipe_fence_handle
**fence
,
1515 struct panfrost_context
*ctx
= pan_context(pipe
);
1516 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1518 /* Nothing to do! */
1519 if (!ctx
->draw_count
&& !job
->clear
) return;
1522 panfrost_draw_wallpaper(&ctx
->base
);
1524 /* Whether to stall the pipeline for immediately correct results. Since
1525 * pipelined rendering is quite broken right now (to be fixed by the
1526 * panfrost_job refactor, just take the perf hit for correctness) */
1527 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1529 /* Submit the frame itself */
1530 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1532 /* Prepare for the next frame */
1533 panfrost_invalidate_frame(ctx
);
1536 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1539 g2m_draw_mode(enum pipe_prim_type mode
)
1542 DEFINE_CASE(POINTS
);
1544 DEFINE_CASE(LINE_LOOP
);
1545 DEFINE_CASE(LINE_STRIP
);
1546 DEFINE_CASE(TRIANGLES
);
1547 DEFINE_CASE(TRIANGLE_STRIP
);
1548 DEFINE_CASE(TRIANGLE_FAN
);
1550 DEFINE_CASE(QUAD_STRIP
);
1551 DEFINE_CASE(POLYGON
);
1554 unreachable("Invalid draw mode");
1561 panfrost_translate_index_size(unsigned size
)
1565 return MALI_DRAW_INDEXED_UINT8
;
1568 return MALI_DRAW_INDEXED_UINT16
;
1571 return MALI_DRAW_INDEXED_UINT32
;
1574 unreachable("Invalid index size");
1578 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1579 * good for the duration of the draw (transient), could last longer */
1582 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1584 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1586 off_t offset
= info
->start
* info
->index_size
;
1588 if (!info
->has_user_indices
) {
1589 /* Only resources can be directly mapped */
1590 return rsrc
->bo
->gpu
+ offset
;
1592 /* Otherwise, we need to upload to transient memory */
1593 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1594 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1599 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1601 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1603 /* Check if we're scissoring at all */
1605 if (!(ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1608 return (ss
->minx
== ss
->maxx
) && (ss
->miny
== ss
->maxy
);
1613 struct pipe_context
*pipe
,
1614 const struct pipe_draw_info
*info
)
1616 struct panfrost_context
*ctx
= pan_context(pipe
);
1618 /* First of all, check the scissor to see if anything is drawn at all.
1619 * If it's not, we drop the draw (mostly a conformance issue;
1620 * well-behaved apps shouldn't hit this) */
1622 if (panfrost_scissor_culls_everything(ctx
))
1625 ctx
->payload_vertex
.draw_start
= info
->start
;
1626 ctx
->payload_tiler
.draw_start
= info
->start
;
1628 int mode
= info
->mode
;
1630 /* Fallback for unsupported modes */
1632 if (!(ctx
->draw_modes
& (1 << mode
))) {
1633 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1634 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1636 if (info
->count
< 4) {
1637 /* Degenerate case? */
1641 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1642 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1647 /* Now that we have a guaranteed terminating path, find the job.
1648 * Assignment commented out to prevent unused warning */
1650 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1652 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1654 ctx
->vertex_count
= info
->count
;
1656 /* For non-indexed draws, they're the same */
1657 unsigned invocation_count
= ctx
->vertex_count
;
1659 unsigned draw_flags
= 0;
1661 /* The draw flags interpret how primitive size is interpreted */
1663 if (panfrost_writes_point_size(ctx
))
1664 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1666 /* For higher amounts of vertices (greater than what fits in a 16-bit
1667 * short), the other value is needed, otherwise there will be bizarre
1668 * rendering artefacts. It's not clear what these values mean yet. */
1670 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1672 if (info
->index_size
) {
1673 /* Calculate the min/max index used so we can figure out how
1674 * many times to invoke the vertex shader */
1676 /* Fetch / calculate index bounds */
1677 unsigned min_index
= 0, max_index
= 0;
1679 if (info
->max_index
== ~0u) {
1680 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1682 min_index
= info
->min_index
;
1683 max_index
= info
->max_index
;
1686 /* Use the corresponding values */
1687 invocation_count
= max_index
- min_index
+ 1;
1688 ctx
->payload_vertex
.draw_start
= min_index
;
1689 ctx
->payload_tiler
.draw_start
= min_index
;
1691 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1692 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1694 //assert(!info->restart_index); /* TODO: Research */
1695 assert(!info
->index_bias
);
1697 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1698 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1700 /* Index count == vertex count, if no indexing is applied, as
1701 * if it is internally indexed in the expected order */
1703 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1704 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1706 /* Reverse index state */
1707 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1710 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1711 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1712 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1714 /* Fire off the draw itself */
1715 panfrost_queue_draw(ctx
);
1721 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1727 panfrost_create_rasterizer_state(
1728 struct pipe_context
*pctx
,
1729 const struct pipe_rasterizer_state
*cso
)
1731 struct panfrost_context
*ctx
= pan_context(pctx
);
1732 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1736 /* Bitmask, unknown meaning of the start value */
1737 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1740 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1742 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1743 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1745 if (cso
->cull_face
& PIPE_FACE_BACK
)
1746 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1752 panfrost_bind_rasterizer_state(
1753 struct pipe_context
*pctx
,
1756 struct panfrost_context
*ctx
= pan_context(pctx
);
1758 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1762 ctx
->rasterizer
= hwcso
;
1763 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1767 panfrost_create_vertex_elements_state(
1768 struct pipe_context
*pctx
,
1769 unsigned num_elements
,
1770 const struct pipe_vertex_element
*elements
)
1772 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1774 so
->num_elements
= num_elements
;
1775 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1777 /* XXX: What the cornball? This is totally, 100%, unapologetically
1778 * nonsense. And yet it somehow fixes a regression in -bshadow
1779 * (previously, we allocated the descriptor here... a newer commit
1780 * removed that allocation, and then memory corruption led to
1781 * shader_meta getting overwritten in bad ways and then the whole test
1782 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1784 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1786 for (int i
= 0; i
< num_elements
; ++i
) {
1787 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1789 enum pipe_format fmt
= elements
[i
].src_format
;
1790 const struct util_format_description
*desc
= util_format_description(fmt
);
1791 so
->hw
[i
].unknown1
= 0x2;
1792 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1794 so
->hw
[i
].format
= panfrost_find_format(desc
);
1796 /* The field itself should probably be shifted over */
1797 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1804 panfrost_bind_vertex_elements_state(
1805 struct pipe_context
*pctx
,
1808 struct panfrost_context
*ctx
= pan_context(pctx
);
1810 ctx
->vertex
= hwcso
;
1811 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1815 panfrost_create_shader_state(
1816 struct pipe_context
*pctx
,
1817 const struct pipe_shader_state
*cso
)
1819 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1822 /* Token deep copy to prevent memory corruption */
1824 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1825 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1831 panfrost_delete_shader_state(
1832 struct pipe_context
*pctx
,
1835 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1837 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1838 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1845 panfrost_create_sampler_state(
1846 struct pipe_context
*pctx
,
1847 const struct pipe_sampler_state
*cso
)
1849 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1852 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1854 struct mali_sampler_descriptor sampler_descriptor
= {
1855 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1856 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1857 | translate_mip_filter(cso
->min_mip_filter
)
1860 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1861 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1862 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1863 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1865 cso
->border_color
.f
[0],
1866 cso
->border_color
.f
[1],
1867 cso
->border_color
.f
[2],
1868 cso
->border_color
.f
[3]
1870 .min_lod
= FIXED_16(cso
->min_lod
),
1871 .max_lod
= FIXED_16(cso
->max_lod
),
1875 so
->hw
= sampler_descriptor
;
1881 panfrost_bind_sampler_states(
1882 struct pipe_context
*pctx
,
1883 enum pipe_shader_type shader
,
1884 unsigned start_slot
, unsigned num_sampler
,
1887 assert(start_slot
== 0);
1889 struct panfrost_context
*ctx
= pan_context(pctx
);
1891 /* XXX: Should upload, not just copy? */
1892 ctx
->sampler_count
[shader
] = num_sampler
;
1893 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1895 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1899 panfrost_variant_matches(
1900 struct panfrost_context
*ctx
,
1901 struct panfrost_shader_state
*variant
,
1902 enum pipe_shader_type type
)
1904 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1906 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1908 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1909 /* Make sure enable state is at least the same */
1910 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1914 /* Check that the contents of the test are the same */
1915 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1916 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1918 if (!(same_func
&& same_ref
)) {
1922 /* Otherwise, we're good to go */
1927 panfrost_bind_shader_state(
1928 struct pipe_context
*pctx
,
1930 enum pipe_shader_type type
)
1932 struct panfrost_context
*ctx
= pan_context(pctx
);
1934 if (type
== PIPE_SHADER_FRAGMENT
) {
1936 ctx
->dirty
|= PAN_DIRTY_FS
;
1938 assert(type
== PIPE_SHADER_VERTEX
);
1940 ctx
->dirty
|= PAN_DIRTY_VS
;
1945 /* Match the appropriate variant */
1947 signed variant
= -1;
1948 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1950 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1951 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1957 if (variant
== -1) {
1958 /* No variant matched, so create a new one */
1959 variant
= variants
->variant_count
++;
1960 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1962 variants
->variants
[variant
].base
= hwcso
;
1964 if (type
== PIPE_SHADER_FRAGMENT
)
1965 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1967 /* Allocate the mapped descriptor ahead-of-time. */
1968 struct panfrost_context
*ctx
= pan_context(pctx
);
1969 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1971 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1972 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1976 /* Select this variant */
1977 variants
->active_variant
= variant
;
1979 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1980 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1982 /* We finally have a variant, so compile it */
1984 if (!shader_state
->compiled
) {
1985 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
1986 panfrost_job_type_for_pipe(type
), shader_state
);
1988 shader_state
->compiled
= true;
1993 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1995 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1999 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2001 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2005 panfrost_set_vertex_buffers(
2006 struct pipe_context
*pctx
,
2007 unsigned start_slot
,
2008 unsigned num_buffers
,
2009 const struct pipe_vertex_buffer
*buffers
)
2011 struct panfrost_context
*ctx
= pan_context(pctx
);
2013 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2017 panfrost_set_constant_buffer(
2018 struct pipe_context
*pctx
,
2019 enum pipe_shader_type shader
, uint index
,
2020 const struct pipe_constant_buffer
*buf
)
2022 struct panfrost_context
*ctx
= pan_context(pctx
);
2023 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2025 size_t sz
= buf
? buf
->buffer_size
: 0;
2027 /* Free previous buffer */
2033 ralloc_free(pbuf
->buffer
);
2034 pbuf
->buffer
= NULL
;
2037 /* If unbinding, we're done */
2042 /* Multiple constant buffers not yet supported */
2047 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
2050 cpu
= rsrc
->bo
->cpu
;
2051 } else if (buf
->user_buffer
) {
2052 cpu
= buf
->user_buffer
;
2054 DBG("No constant buffer?\n");
2058 /* Copy the constant buffer into the driver context for later upload */
2060 pbuf
->buffer
= rzalloc_size(ctx
, sz
);
2061 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
2065 panfrost_set_stencil_ref(
2066 struct pipe_context
*pctx
,
2067 const struct pipe_stencil_ref
*ref
)
2069 struct panfrost_context
*ctx
= pan_context(pctx
);
2070 ctx
->stencil_ref
= *ref
;
2072 /* Shader core dirty */
2073 ctx
->dirty
|= PAN_DIRTY_FS
;
2076 static enum mali_texture_type
2077 panfrost_translate_texture_type(enum pipe_texture_target t
)
2081 case PIPE_TEXTURE_1D
:
2082 case PIPE_TEXTURE_1D_ARRAY
:
2085 case PIPE_TEXTURE_2D
:
2086 case PIPE_TEXTURE_2D_ARRAY
:
2087 case PIPE_TEXTURE_RECT
:
2090 case PIPE_TEXTURE_3D
:
2093 case PIPE_TEXTURE_CUBE
:
2094 case PIPE_TEXTURE_CUBE_ARRAY
:
2095 return MALI_TEX_CUBE
;
2098 unreachable("Unknown target");
2102 static struct pipe_sampler_view
*
2103 panfrost_create_sampler_view(
2104 struct pipe_context
*pctx
,
2105 struct pipe_resource
*texture
,
2106 const struct pipe_sampler_view
*template)
2108 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2109 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2111 pipe_reference(NULL
, &texture
->reference
);
2113 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2116 so
->base
= *template;
2117 so
->base
.texture
= texture
;
2118 so
->base
.reference
.count
= 1;
2119 so
->base
.context
= pctx
;
2121 /* sampler_views correspond to texture descriptors, minus the texture
2122 * (data) itself. So, we serialise the descriptor here and cache it for
2125 /* Make sure it's something with which we're familiar */
2126 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2128 /* TODO: Detect from format better */
2129 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2131 unsigned char user_swizzle
[4] = {
2132 template->swizzle_r
,
2133 template->swizzle_g
,
2134 template->swizzle_b
,
2138 enum mali_format format
= panfrost_find_format(desc
);
2140 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2142 unsigned usage2_layout
= 0x10;
2144 switch (prsrc
->bo
->layout
) {
2146 usage2_layout
|= 0x8 | 0x4;
2149 usage2_layout
|= 0x1;
2152 usage2_layout
|= is_depth
? 0x1 : 0x2;
2159 /* Check if we need to set a custom stride by computing the "expected"
2160 * stride and comparing it to what the BO actually wants. Only applies
2161 * to linear textures, since tiled/compressed textures have strict
2162 * alignment requirements for their strides as it is */
2164 unsigned first_level
= template->u
.tex
.first_level
;
2165 unsigned last_level
= template->u
.tex
.last_level
;
2167 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2168 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2169 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2170 unsigned width
= u_minify(texture
->width0
, l
);
2171 unsigned comp_stride
= width
* bytes_per_pixel
;
2173 if (comp_stride
!= actual_stride
) {
2174 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2180 /* In the hardware, array_size refers specifically to array textures,
2181 * whereas in Gallium, it also covers cubemaps */
2183 unsigned array_size
= texture
->array_size
;
2185 if (texture
->target
== PIPE_TEXTURE_CUBE
) {
2186 /* TODO: Cubemap arrays */
2187 assert(array_size
== 6);
2190 struct mali_texture_descriptor texture_descriptor
= {
2191 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2192 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2193 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2194 .array_size
= MALI_POSITIVE(array_size
),
2198 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2201 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2202 .type
= panfrost_translate_texture_type(texture
->target
),
2204 .usage2
= usage2_layout
2207 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2210 //texture_descriptor.nr_mipmap_levels = last_level - first_level;
2212 so
->hw
= texture_descriptor
;
2214 return (struct pipe_sampler_view
*) so
;
2218 panfrost_set_sampler_views(
2219 struct pipe_context
*pctx
,
2220 enum pipe_shader_type shader
,
2221 unsigned start_slot
, unsigned num_views
,
2222 struct pipe_sampler_view
**views
)
2224 struct panfrost_context
*ctx
= pan_context(pctx
);
2226 assert(start_slot
== 0);
2228 unsigned new_nr
= 0;
2229 for (unsigned i
= 0; i
< num_views
; ++i
) {
2234 ctx
->sampler_view_count
[shader
] = new_nr
;
2235 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2237 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2241 panfrost_sampler_view_destroy(
2242 struct pipe_context
*pctx
,
2243 struct pipe_sampler_view
*view
)
2245 pipe_resource_reference(&view
->texture
, NULL
);
2250 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2251 const struct pipe_framebuffer_state
*fb
)
2253 struct panfrost_context
*ctx
= pan_context(pctx
);
2255 /* Flush when switching framebuffers, but not if the framebuffer
2256 * state is being restored by u_blitter
2259 bool is_scanout
= panfrost_is_scanout(ctx
);
2260 bool has_draws
= ctx
->draw_count
> 0;
2262 if (!ctx
->blitter
->running
&& (!is_scanout
|| has_draws
)) {
2263 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2266 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2267 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2268 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2269 ctx
->pipe_framebuffer
.width
= fb
->width
;
2270 ctx
->pipe_framebuffer
.height
= fb
->height
;
2272 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2273 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2275 /* check if changing cbuf */
2276 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2278 if (cb
&& (i
!= 0)) {
2279 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2284 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2289 if (ctx
->require_sfbd
)
2290 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2292 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2294 panfrost_attach_vt_framebuffer(ctx
);
2296 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2297 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2299 bool can_afbc
= panfrost_format_supports_afbc(format
);
2300 bool is_scanout
= panfrost_is_scanout(ctx
);
2302 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2303 panfrost_enable_afbc(ctx
, tex
, false);
2305 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2306 panfrost_enable_checksum(ctx
, tex
);
2310 struct pipe_surface
*zb
= fb
->zsbuf
;
2312 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2313 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2316 if (ctx
->require_sfbd
)
2317 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2319 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2321 panfrost_attach_vt_framebuffer(ctx
);
2323 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2324 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2325 bool is_scanout
= panfrost_is_scanout(ctx
);
2327 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2328 panfrost_enable_afbc(ctx
, tex
, true);
2335 panfrost_create_blend_state(struct pipe_context
*pipe
,
2336 const struct pipe_blend_state
*blend
)
2338 struct panfrost_context
*ctx
= pan_context(pipe
);
2339 struct panfrost_blend_state
*so
= rzalloc(ctx
, struct panfrost_blend_state
);
2342 /* TODO: The following features are not yet implemented */
2343 assert(!blend
->logicop_enable
);
2344 assert(!blend
->alpha_to_coverage
);
2345 assert(!blend
->alpha_to_one
);
2347 /* Compile the blend state, first as fixed-function if we can */
2349 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2352 /* If we can't, compile a blend shader instead */
2354 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2360 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2363 struct panfrost_context
*ctx
= pan_context(pipe
);
2364 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2365 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2366 ctx
->blend
= pblend
;
2371 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2373 /* TODO: Attach color */
2375 /* Shader itself is not dirty, but the shader core is */
2376 ctx
->dirty
|= PAN_DIRTY_FS
;
2380 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2383 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2385 if (so
->has_blend_shader
) {
2386 DBG("Deleting blend state leak blend shaders bytecode\n");
2393 panfrost_set_blend_color(struct pipe_context
*pipe
,
2394 const struct pipe_blend_color
*blend_color
)
2396 struct panfrost_context
*ctx
= pan_context(pipe
);
2398 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2401 ctx
->blend_color
= *blend_color
;
2403 /* The blend mode depends on the blend constant color, due to the
2404 * fixed/programmable split. So, we're forced to regenerate the blend
2407 /* TODO: Attach color */
2412 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2413 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2415 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2419 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2422 struct panfrost_context
*ctx
= pan_context(pipe
);
2423 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2424 ctx
->depth_stencil
= depth_stencil
;
2429 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2430 * emulated in the fragment shader */
2432 if (depth_stencil
->alpha
.enabled
) {
2433 /* We need to trigger a new shader (maybe) */
2434 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2438 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2440 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2441 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2443 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2444 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2446 /* Depth state (TODO: Refactor) */
2447 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2449 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2451 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2452 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2454 /* Bounds test not implemented */
2455 assert(!depth_stencil
->depth
.bounds_test
);
2457 ctx
->dirty
|= PAN_DIRTY_FS
;
2461 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2467 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2468 unsigned sample_mask
)
2473 panfrost_set_clip_state(struct pipe_context
*pipe
,
2474 const struct pipe_clip_state
*clip
)
2476 //struct panfrost_context *panfrost = pan_context(pipe);
2480 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2481 unsigned start_slot
,
2482 unsigned num_viewports
,
2483 const struct pipe_viewport_state
*viewports
)
2485 struct panfrost_context
*ctx
= pan_context(pipe
);
2487 assert(start_slot
== 0);
2488 assert(num_viewports
== 1);
2490 ctx
->pipe_viewport
= *viewports
;
2494 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2495 unsigned start_slot
,
2496 unsigned num_scissors
,
2497 const struct pipe_scissor_state
*scissors
)
2499 struct panfrost_context
*ctx
= pan_context(pipe
);
2501 assert(start_slot
== 0);
2502 assert(num_scissors
== 1);
2504 ctx
->scissor
= *scissors
;
2508 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2509 const struct pipe_poly_stipple
*stipple
)
2511 //struct panfrost_context *panfrost = pan_context(pipe);
2515 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2518 //struct panfrost_context *panfrost = pan_context(pipe);
2522 panfrost_destroy(struct pipe_context
*pipe
)
2524 struct panfrost_context
*panfrost
= pan_context(pipe
);
2525 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2527 if (panfrost
->blitter
)
2528 util_blitter_destroy(panfrost
->blitter
);
2530 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2531 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2532 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2533 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2534 screen
->driver
->free_slab(screen
, &panfrost
->tiler_polygon_list
);
2535 screen
->driver
->free_slab(screen
, &panfrost
->tiler_dummy
);
2537 for (int i
= 0; i
< ARRAY_SIZE(panfrost
->transient_pools
); ++i
) {
2538 struct panfrost_memory_entry
*entry
;
2539 entry
= panfrost
->transient_pools
[i
].entries
[0];
2540 pb_slab_free(&screen
->slabs
, (struct pb_slab_entry
*)entry
);
2546 static struct pipe_query
*
2547 panfrost_create_query(struct pipe_context
*pipe
,
2551 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2556 return (struct pipe_query
*) q
;
2560 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2566 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2568 struct panfrost_context
*ctx
= pan_context(pipe
);
2569 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2571 switch (query
->type
) {
2572 case PIPE_QUERY_OCCLUSION_COUNTER
:
2573 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2574 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2576 /* Allocate a word for the query results to be stored */
2577 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2579 ctx
->occlusion_query
= query
;
2585 DBG("Skipping query %d\n", query
->type
);
2593 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2595 struct panfrost_context
*ctx
= pan_context(pipe
);
2596 ctx
->occlusion_query
= NULL
;
2601 panfrost_get_query_result(struct pipe_context
*pipe
,
2602 struct pipe_query
*q
,
2604 union pipe_query_result
*vresult
)
2607 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2609 /* We need to flush out the jobs to actually run the counter, TODO
2610 * check wait, TODO wallpaper after if needed */
2612 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2614 switch (query
->type
) {
2615 case PIPE_QUERY_OCCLUSION_COUNTER
:
2616 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2617 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2618 /* Read back the query results */
2619 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2620 unsigned passed
= *result
;
2622 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2623 vresult
->u64
= passed
;
2625 vresult
->b
= !!passed
;
2631 DBG("Skipped query get %d\n", query
->type
);
2638 static struct pipe_stream_output_target
*
2639 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2640 struct pipe_resource
*prsc
,
2641 unsigned buffer_offset
,
2642 unsigned buffer_size
)
2644 struct pipe_stream_output_target
*target
;
2646 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2651 pipe_reference_init(&target
->reference
, 1);
2652 pipe_resource_reference(&target
->buffer
, prsc
);
2654 target
->context
= pctx
;
2655 target
->buffer_offset
= buffer_offset
;
2656 target
->buffer_size
= buffer_size
;
2662 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2663 struct pipe_stream_output_target
*target
)
2665 pipe_resource_reference(&target
->buffer
, NULL
);
2666 ralloc_free(target
);
2670 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2671 unsigned num_targets
,
2672 struct pipe_stream_output_target
**targets
,
2673 const unsigned *offsets
)
2679 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2681 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2682 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2684 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2685 /* Allocate the beginning of the transient pool */
2686 int entry_size
= (1 << 22); /* 4MB */
2688 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2689 ctx
->transient_pools
[i
].entry_count
= 1;
2691 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2694 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2695 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2696 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2697 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2698 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2699 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2702 /* New context creation, which also does hardware initialisation since I don't
2703 * know the better way to structure this :smirk: */
2705 struct pipe_context
*
2706 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2708 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2709 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2710 memset(ctx
, 0, sizeof(*ctx
));
2711 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2714 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2716 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2717 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2719 gallium
->screen
= screen
;
2721 gallium
->destroy
= panfrost_destroy
;
2723 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2725 gallium
->flush
= panfrost_flush
;
2726 gallium
->clear
= panfrost_clear
;
2727 gallium
->draw_vbo
= panfrost_draw_vbo
;
2729 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2730 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2732 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2734 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2735 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2736 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2738 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2739 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2740 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2742 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2743 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2744 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2746 gallium
->create_fs_state
= panfrost_create_shader_state
;
2747 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2748 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2750 gallium
->create_vs_state
= panfrost_create_shader_state
;
2751 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2752 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2754 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2755 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2756 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2758 gallium
->create_blend_state
= panfrost_create_blend_state
;
2759 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2760 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2762 gallium
->set_blend_color
= panfrost_set_blend_color
;
2764 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2765 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2766 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2768 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2770 gallium
->set_clip_state
= panfrost_set_clip_state
;
2771 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2772 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2773 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2774 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2776 gallium
->create_query
= panfrost_create_query
;
2777 gallium
->destroy_query
= panfrost_destroy_query
;
2778 gallium
->begin_query
= panfrost_begin_query
;
2779 gallium
->end_query
= panfrost_end_query
;
2780 gallium
->get_query_result
= panfrost_get_query_result
;
2782 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2783 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2784 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2786 panfrost_resource_context_init(gallium
);
2788 pscreen
->driver
->init_context(ctx
);
2790 panfrost_setup_hardware(ctx
);
2793 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2794 gallium
->const_uploader
= gallium
->stream_uploader
;
2795 assert(gallium
->stream_uploader
);
2797 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2798 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2800 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2802 ctx
->blitter
= util_blitter_create(gallium
);
2803 assert(ctx
->blitter
);
2805 /* Prepare for render! */
2807 panfrost_job_init(ctx
);
2808 panfrost_emit_vertex_payload(ctx
);
2809 panfrost_emit_tiler_payload(ctx
);
2810 panfrost_invalidate_frame(ctx
);
2811 panfrost_default_shader_backend(ctx
);