2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
49 #include "pan_tiler.h"
51 static int performance_counter_number
= 0;
52 extern const char *pan_counters_base
;
54 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
57 static enum mali_job_type
58 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
61 case PIPE_SHADER_VERTEX
:
62 return JOB_TYPE_VERTEX
;
64 case PIPE_SHADER_FRAGMENT
:
65 /* Note: JOB_TYPE_FRAGMENT is different.
66 * JOB_TYPE_FRAGMENT actually executes the
67 * fragment shader, but JOB_TYPE_TILER is how you
69 return JOB_TYPE_TILER
;
71 case PIPE_SHADER_GEOMETRY
:
72 return JOB_TYPE_GEOMETRY
;
74 case PIPE_SHADER_COMPUTE
:
75 return JOB_TYPE_COMPUTE
;
78 unreachable("Unsupported shader stage");
83 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
85 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
86 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
87 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
88 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
90 /* 8 byte checksum per tile */
91 rsrc
->bo
->checksum_stride
= tile_w
* 8;
92 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
93 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
95 rsrc
->bo
->has_checksum
= true;
98 /* Framebuffer descriptor */
101 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
103 fb
->width
= MALI_POSITIVE(w
);
104 fb
->height
= MALI_POSITIVE(h
);
106 /* No idea why this is needed, but it's how resolution_check is
107 * calculated. It's not clear to us yet why the hardware wants this.
108 * The formula itself was discovered mostly by manual bruteforce and
109 * aggressive algebraic simplification. */
111 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
114 struct mali_single_framebuffer
115 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
117 struct mali_single_framebuffer framebuffer
= {
119 .format
= 0x30000000,
120 .clear_flags
= 0x1000,
121 .unknown_address_0
= ctx
->scratchpad
.gpu
,
122 .tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
,
123 .tiler_polygon_list_body
= ctx
->tiler_polygon_list
.gpu
+ 40960,
124 .tiler_hierarchy_mask
= 0xF0,
126 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
127 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
130 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
135 struct bifrost_framebuffer
136 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
138 unsigned width
= ctx
->pipe_framebuffer
.width
;
139 unsigned height
= ctx
->pipe_framebuffer
.height
;
141 struct bifrost_framebuffer framebuffer
= {
142 .width1
= MALI_POSITIVE(width
),
143 .height1
= MALI_POSITIVE(height
),
144 .width2
= MALI_POSITIVE(width
),
145 .height2
= MALI_POSITIVE(height
),
150 .rt_count_1
= MALI_POSITIVE(1),
155 .scratchpad
= ctx
->scratchpad
.gpu
,
158 framebuffer
.tiler_hierarchy_mask
=
159 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
161 /* Compute the polygon header size and use that to offset the body */
163 unsigned header_size
= panfrost_tiler_header_size(
164 width
, height
, framebuffer
.tiler_hierarchy_mask
);
166 unsigned body_size
= panfrost_tiler_body_size(
167 width
, height
, framebuffer
.tiler_hierarchy_mask
);
171 unsigned total_size
= header_size
+ body_size
;
173 if (framebuffer
.tiler_hierarchy_mask
) {
174 assert(ctx
->tiler_polygon_list
.size
>= total_size
);
176 /* Specify allocated tiler structures */
177 framebuffer
.tiler_polygon_list
= ctx
->tiler_polygon_list
.gpu
;
179 /* Allow the entire tiler heap */
180 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
181 framebuffer
.tiler_heap_end
=
182 ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
;
184 /* The tiler is disabled, so don't allow the tiler heap */
185 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.gpu
;
186 framebuffer
.tiler_heap_end
= framebuffer
.tiler_heap_start
;
188 /* Use a dummy polygon list */
189 framebuffer
.tiler_polygon_list
= ctx
->tiler_dummy
.gpu
;
191 /* Also, set a "tiler disabled?" flag? */
192 framebuffer
.tiler_hierarchy_mask
|= 0x1000;
195 framebuffer
.tiler_polygon_list_body
=
196 framebuffer
.tiler_polygon_list
+ header_size
;
198 framebuffer
.tiler_polygon_list_size
=
199 header_size
+ body_size
;
206 /* Are we currently rendering to the screen (rather than an FBO)? */
209 panfrost_is_scanout(struct panfrost_context
*ctx
)
211 /* If there is no color buffer, it's an FBO */
212 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
215 /* If we're too early that no framebuffer was sent, it's scanout */
216 if (!ctx
->pipe_framebuffer
.cbufs
[0])
219 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
220 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
221 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
226 struct pipe_context
*pipe
,
228 const union pipe_color_union
*color
,
229 double depth
, unsigned stencil
)
231 struct panfrost_context
*ctx
= pan_context(pipe
);
232 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
234 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
238 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
240 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
244 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
246 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
250 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
252 mali_ptr framebuffer
= ctx
->require_sfbd
?
253 panfrost_attach_vt_sfbd(ctx
) :
254 panfrost_attach_vt_mfbd(ctx
);
256 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
257 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
260 /* Reset per-frame context, called on context initialisation as well as after
261 * flushing a frame */
264 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
266 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
267 DBG("Uploaded transient %d bytes\n", transient_count
);
269 /* Rotate cmdstream */
270 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
271 ctx
->cmdstream_i
= 0;
273 if (ctx
->require_sfbd
)
274 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
276 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
278 /* Reset varyings allocated */
279 ctx
->varying_height
= 0;
281 /* The transient cmdstream is dirty every frame; the only bits worth preserving
282 * (textures, shaders, etc) are in other buffers anyways */
284 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
285 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
287 /* Regenerate payloads */
288 panfrost_attach_vt_framebuffer(ctx
);
291 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
294 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
297 /* In practice, every field of these payloads should be configurable
298 * arbitrarily, which means these functions are basically catch-all's for
299 * as-of-yet unwavering unknowns */
302 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
304 struct midgard_payload_vertex_tiler payload
= {
306 .workgroups_z_shift
= 32,
307 .workgroups_x_shift_2
= 0x2,
308 .workgroups_x_shift_3
= 0x5,
310 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
313 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
317 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
319 struct midgard_payload_vertex_tiler payload
= {
321 .workgroups_z_shift
= 32,
322 .workgroups_x_shift_2
= 0x2,
323 .workgroups_x_shift_3
= 0x6,
325 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
329 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
333 translate_tex_wrap(enum pipe_tex_wrap w
)
336 case PIPE_TEX_WRAP_REPEAT
:
337 return MALI_WRAP_REPEAT
;
339 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
340 return MALI_WRAP_CLAMP_TO_EDGE
;
342 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
343 return MALI_WRAP_CLAMP_TO_BORDER
;
345 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
346 return MALI_WRAP_MIRRORED_REPEAT
;
349 unreachable("Invalid wrap");
354 translate_tex_filter(enum pipe_tex_filter f
)
357 case PIPE_TEX_FILTER_NEAREST
:
360 case PIPE_TEX_FILTER_LINEAR
:
364 unreachable("Invalid filter");
369 translate_mip_filter(enum pipe_tex_mipfilter f
)
371 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
375 panfrost_translate_compare_func(enum pipe_compare_func in
)
378 case PIPE_FUNC_NEVER
:
379 return MALI_FUNC_NEVER
;
382 return MALI_FUNC_LESS
;
384 case PIPE_FUNC_EQUAL
:
385 return MALI_FUNC_EQUAL
;
387 case PIPE_FUNC_LEQUAL
:
388 return MALI_FUNC_LEQUAL
;
390 case PIPE_FUNC_GREATER
:
391 return MALI_FUNC_GREATER
;
393 case PIPE_FUNC_NOTEQUAL
:
394 return MALI_FUNC_NOTEQUAL
;
396 case PIPE_FUNC_GEQUAL
:
397 return MALI_FUNC_GEQUAL
;
399 case PIPE_FUNC_ALWAYS
:
400 return MALI_FUNC_ALWAYS
;
403 unreachable("Invalid func");
408 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
411 case PIPE_FUNC_NEVER
:
412 return MALI_ALT_FUNC_NEVER
;
415 return MALI_ALT_FUNC_LESS
;
417 case PIPE_FUNC_EQUAL
:
418 return MALI_ALT_FUNC_EQUAL
;
420 case PIPE_FUNC_LEQUAL
:
421 return MALI_ALT_FUNC_LEQUAL
;
423 case PIPE_FUNC_GREATER
:
424 return MALI_ALT_FUNC_GREATER
;
426 case PIPE_FUNC_NOTEQUAL
:
427 return MALI_ALT_FUNC_NOTEQUAL
;
429 case PIPE_FUNC_GEQUAL
:
430 return MALI_ALT_FUNC_GEQUAL
;
432 case PIPE_FUNC_ALWAYS
:
433 return MALI_ALT_FUNC_ALWAYS
;
436 unreachable("Invalid alt func");
441 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
444 case PIPE_STENCIL_OP_KEEP
:
445 return MALI_STENCIL_KEEP
;
447 case PIPE_STENCIL_OP_ZERO
:
448 return MALI_STENCIL_ZERO
;
450 case PIPE_STENCIL_OP_REPLACE
:
451 return MALI_STENCIL_REPLACE
;
453 case PIPE_STENCIL_OP_INCR
:
454 return MALI_STENCIL_INCR
;
456 case PIPE_STENCIL_OP_DECR
:
457 return MALI_STENCIL_DECR
;
459 case PIPE_STENCIL_OP_INCR_WRAP
:
460 return MALI_STENCIL_INCR_WRAP
;
462 case PIPE_STENCIL_OP_DECR_WRAP
:
463 return MALI_STENCIL_DECR_WRAP
;
465 case PIPE_STENCIL_OP_INVERT
:
466 return MALI_STENCIL_INVERT
;
469 unreachable("Invalid stencil op");
474 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
476 out
->ref
= 0; /* Gallium gets it from elsewhere */
478 out
->mask
= in
->valuemask
;
479 out
->func
= panfrost_translate_compare_func(in
->func
);
480 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
481 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
482 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
486 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
488 struct mali_shader_meta shader
= {
489 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
491 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
492 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
496 shader
.unknown2_4
|= 0x10;
499 struct pipe_stencil_state default_stencil
= {
501 .func
= PIPE_FUNC_ALWAYS
,
502 .fail_op
= MALI_STENCIL_KEEP
,
503 .zfail_op
= MALI_STENCIL_KEEP
,
504 .zpass_op
= MALI_STENCIL_KEEP
,
509 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
510 shader
.stencil_mask_front
= default_stencil
.writemask
;
512 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
513 shader
.stencil_mask_back
= default_stencil
.writemask
;
515 if (default_stencil
.enabled
)
516 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
518 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
522 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
524 if (first
->job_descriptor_size
)
525 first
->next_job_64
= (u64
) (uintptr_t) next
;
527 first
->next_job_32
= (u32
) (uintptr_t) next
;
530 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
531 * graphics command stream. It should be called once per draw, accordding to
532 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
533 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
536 struct panfrost_transfer
537 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
539 /* Each draw call corresponds to two jobs, and the set-value job is first */
540 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
542 struct mali_job_descriptor_header job
= {
543 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
544 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
546 .job_descriptor_size
= 1,
550 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
552 /* There's some padding hacks on 32-bit */
559 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
562 /* Tiler jobs depend on vertex jobs */
564 job
.job_dependency_index_1
= draw_job_index
;
566 /* Tiler jobs also depend on the previous tiler job */
568 if (ctx
->draw_count
) {
569 job
.job_dependency_index_2
= draw_job_index
- 1;
570 /* Previous tiler job points to this tiler job */
571 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
573 /* The only vertex job so far points to first tiler job */
574 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
577 if (ctx
->draw_count
) {
578 /* Previous vertex job points to this vertex job */
579 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
581 /* Last vertex job points to first tiler job */
582 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
584 /* Have the first vertex job depend on the set value job */
585 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
586 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
590 memcpy(transfer
.cpu
, &job
, sizeof(job
));
591 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
595 /* Generates a set value job. It's unclear what exactly this does, why it's
596 * necessary, and when to call it. */
599 panfrost_set_value_job(struct panfrost_context
*ctx
)
601 struct mali_job_descriptor_header job
= {
602 .job_type
= JOB_TYPE_SET_VALUE
,
603 .job_descriptor_size
= 1,
607 struct mali_payload_set_value payload
= {
608 .out
= ctx
->tiler_polygon_list
.gpu
,
612 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
613 memcpy(transfer
.cpu
, &job
, sizeof(job
));
614 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
616 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
617 ctx
->set_value_job
= transfer
.gpu
;
621 panfrost_emit_varyings(
622 struct panfrost_context
*ctx
,
623 union mali_attr
*slot
,
627 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
629 /* Fill out the descriptor */
630 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
631 slot
->stride
= stride
;
632 slot
->size
= stride
* count
;
634 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
635 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
637 return varying_address
;
641 panfrost_emit_point_coord(union mali_attr
*slot
)
643 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
644 slot
->stride
= slot
->size
= 0;
648 panfrost_emit_varying_descriptor(
649 struct panfrost_context
*ctx
,
650 unsigned invocation_count
)
652 /* Load the shaders */
654 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
655 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
656 unsigned int num_gen_varyings
= 0;
658 /* Allocate the varying descriptor */
660 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
661 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
663 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
667 * Assign ->src_offset now that we know about all the general purpose
668 * varyings that will be used by the fragment and vertex shaders.
670 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
672 * General purpose varyings have ->index set to 0, skip other
675 if (vs
->varyings
[i
].index
)
678 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
681 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
684 if (fs
->varyings
[i
].index
)
688 * Re-use the VS general purpose varying pos if it exists,
689 * create a new one otherwise.
691 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
692 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
696 if (j
< vs
->tripipe
->varying_count
)
697 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
699 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
702 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
703 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
705 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
706 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
708 /* Buffer indices must be in this order per our convention */
709 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
712 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
715 /* fp32 vec4 gl_Position */
716 ctx
->payload_tiler
.postfix
.position_varying
=
717 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
718 sizeof(float) * 4, invocation_count
);
721 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
722 /* fp16 vec1 gl_PointSize */
723 ctx
->payload_tiler
.primitive_size
.pointer
=
724 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
725 2, invocation_count
);
728 if (fs
->reads_point_coord
) {
729 /* Special descriptor */
730 panfrost_emit_point_coord(&varyings
[idx
++]);
733 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
734 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
735 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
739 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
741 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
742 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
744 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
747 /* Emits attributes and varying descriptors, which should be called every draw,
748 * excepting some obscure circumstances */
751 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
753 /* Staged mali_attr, and index into them. i =/= k, depending on the
754 * vertex buffer mask */
755 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
758 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
760 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
761 if (!(ctx
->vb_mask
& (1 << i
))) continue;
763 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
764 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
768 /* Align to 64 bytes by masking off the lower bits. This
769 * will be adjusted back when we fixup the src_offset in
772 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
774 /* Offset vertex count by draw_start to make sure we upload enough */
775 attrs
[k
].stride
= buf
->stride
;
776 attrs
[k
].size
= rsrc
->base
.width0
;
778 panfrost_job_add_bo(job
, rsrc
->bo
);
779 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
784 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
786 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
790 panfrost_writes_point_size(struct panfrost_context
*ctx
)
793 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
795 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
798 /* Stage the attribute descriptors so we can adjust src_offset
799 * to let BOs align nicely */
802 panfrost_stage_attributes(struct panfrost_context
*ctx
)
804 struct panfrost_vertex_state
*so
= ctx
->vertex
;
806 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
807 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
808 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
810 /* Copy as-is for the first pass */
811 memcpy(target
, so
->hw
, sz
);
813 /* Fixup offsets for the second pass. Recall that the hardware
814 * calculates attribute addresses as:
816 * addr = base + (stride * vtx) + src_offset;
818 * However, on Mali, base must be aligned to 64-bytes, so we
821 * base' = base & ~63 = base - (base & 63)
823 * To compensate when using base' (see emit_vertex_data), we have
824 * to adjust src_offset by the masked off piece:
826 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
827 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
828 * = base + (stride * vtx) + src_offset
834 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
835 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
836 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
838 /* Adjust by the masked off bits of the offset */
839 target
[i
].src_offset
+= (addr
& 63);
842 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
846 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
848 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
850 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
853 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
854 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
856 struct panfrost_transfer transfer
=
857 panfrost_allocate_transient(ctx
, transfer_size
);
859 struct mali_sampler_descriptor
*desc
=
860 (struct mali_sampler_descriptor
*) transfer
.cpu
;
862 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
863 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
865 upload
= transfer
.gpu
;
868 if (t
== PIPE_SHADER_FRAGMENT
)
869 ctx
->payload_tiler
.postfix
.sampler_descriptor
= upload
;
870 else if (t
== PIPE_SHADER_VERTEX
)
871 ctx
->payload_vertex
.postfix
.sampler_descriptor
= upload
;
877 /* Computes the address to a texture at a particular slice */
880 panfrost_get_texture_address(
881 struct panfrost_resource
*rsrc
,
882 unsigned level
, unsigned face
)
884 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
885 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
887 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
893 struct panfrost_context
*ctx
,
894 struct panfrost_sampler_view
*view
)
897 return (mali_ptr
) NULL
;
899 struct pipe_sampler_view
*pview
= &view
->base
;
900 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
902 /* Do we interleave an explicit stride with every element? */
904 bool has_manual_stride
=
905 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
907 /* For easy access */
909 assert(pview
->target
!= PIPE_BUFFER
);
910 unsigned first_level
= pview
->u
.tex
.first_level
;
911 unsigned last_level
= pview
->u
.tex
.last_level
;
913 /* Inject the addresses in, interleaving mip levels, cube faces, and
914 * strides in that order */
918 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
919 for (unsigned f
= 0; f
< pview
->texture
->array_size
; ++f
) {
920 view
->hw
.payload
[idx
++] =
921 panfrost_get_texture_address(rsrc
, l
, f
);
923 if (has_manual_stride
) {
924 view
->hw
.payload
[idx
++] =
925 rsrc
->bo
->slices
[l
].stride
;
930 return panfrost_upload_transient(ctx
, &view
->hw
,
931 sizeof(struct mali_texture_descriptor
));
935 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
937 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
938 mali_ptr trampoline
= 0;
940 if (ctx
->sampler_view_count
[t
]) {
941 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
943 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
945 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
947 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
950 if (t
== PIPE_SHADER_FRAGMENT
)
951 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
952 else if (t
== PIPE_SHADER_VERTEX
)
953 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
959 struct sysval_uniform
{
967 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
968 struct sysval_uniform
*uniform
)
970 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
972 uniform
->f
[0] = vp
->scale
[0];
973 uniform
->f
[1] = vp
->scale
[1];
974 uniform
->f
[2] = vp
->scale
[2];
977 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
978 struct sysval_uniform
*uniform
)
980 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
982 uniform
->f
[0] = vp
->translate
[0];
983 uniform
->f
[1] = vp
->translate
[1];
984 uniform
->f
[2] = vp
->translate
[2];
987 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
988 enum pipe_shader_type st
,
989 unsigned int sysvalid
,
990 struct sysval_uniform
*uniform
)
992 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
993 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
994 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
995 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
998 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
1001 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
1002 tex
->u
.tex
.first_level
);
1005 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
1006 tex
->u
.tex
.first_level
);
1009 uniform
->i
[dim
] = tex
->texture
->array_size
;
1012 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
1013 struct panfrost_shader_state
*ss
,
1014 enum pipe_shader_type st
)
1016 struct sysval_uniform
*uniforms
= (void *)buf
;
1018 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1019 int sysval
= ss
->sysval
[i
];
1021 switch (PAN_SYSVAL_TYPE(sysval
)) {
1022 case PAN_SYSVAL_VIEWPORT_SCALE
:
1023 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
1025 case PAN_SYSVAL_VIEWPORT_OFFSET
:
1026 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
1028 case PAN_SYSVAL_TEXTURE_SIZE
:
1029 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
1038 /* Go through dirty flags and actualise them in the cmdstream. */
1041 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1043 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1045 if (with_vertex_data
) {
1046 panfrost_emit_vertex_data(ctx
, job
);
1049 bool msaa
= ctx
->rasterizer
->base
.multisample
;
1051 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1052 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1054 /* TODO: Sample size */
1055 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1056 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1059 if (ctx
->occlusion_query
) {
1060 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1061 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1064 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1067 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1069 /* Late shader descriptor assignments */
1071 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1072 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1075 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1077 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1080 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1081 /* Check if we need to link the gl_PointSize varying */
1082 if (!panfrost_writes_point_size(ctx
)) {
1083 /* If the size is constant, write it out. Otherwise,
1084 * don't touch primitive_size (since we would clobber
1085 * the pointer there) */
1087 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1091 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1093 ctx
->dirty
|= PAN_DIRTY_FS
;
1095 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1097 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1099 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1102 COPY(attribute_count
);
1103 COPY(varying_count
);
1104 COPY(midgard1
.uniform_count
);
1105 COPY(midgard1
.work_count
);
1106 COPY(midgard1
.unknown2
);
1109 /* If there is a blend shader, work registers are shared */
1111 if (ctx
->blend
->has_blend_shader
)
1112 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1114 /* Set late due to depending on render state */
1115 /* The one at the end seems to mean "1 UBO" */
1116 unsigned flags
= MALI_EARLY_Z
| 0x200 | 0x2000 | 0x1;
1118 /* Any time texturing is used, derivatives are implicitly
1119 * calculated, so we need to enable helper invocations */
1121 if (ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
])
1122 flags
|= MALI_HELPER_INVOCATIONS
;
1124 ctx
->fragment_shader_core
.midgard1
.unknown1
= flags
;
1126 /* Assign texture/sample count right before upload */
1127 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1128 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1130 /* Assign the stencil refs late */
1131 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1132 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1134 /* CAN_DISCARD should be set if the fragment shader possibly
1135 * contains a 'discard' instruction. It is likely this is
1136 * related to optimizations related to forward-pixel kill, as
1137 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1138 * thing?" by Peter Harris
1141 if (variant
->can_discard
) {
1142 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1143 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_EARLY_Z
;
1144 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1145 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1148 /* Check if we're using the default blend descriptor (fast path) */
1151 !ctx
->blend
->has_blend_shader
&&
1152 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1153 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1154 (ctx
->blend
->equation
.color_mask
== 0xf);
1156 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1157 * *also* copied to the blend_meta appended (by convention),
1158 * but this is the field actually read by the hardware. (Or
1159 * maybe both are read...?) */
1161 if (ctx
->blend
->has_blend_shader
) {
1162 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1164 ctx
->fragment_shader_core
.blend
.shader
= 0;
1167 if (ctx
->require_sfbd
) {
1168 /* When only a single render target platform is used, the blend
1169 * information is inside the shader meta itself. We
1170 * additionally need to signal CAN_DISCARD for nontrivial blend
1171 * modes (so we're able to read back the destination buffer) */
1173 if (!ctx
->blend
->has_blend_shader
) {
1174 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1175 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1179 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1183 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1184 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1185 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1187 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1189 if (!ctx
->require_sfbd
) {
1190 /* Additional blend descriptor tacked on for jobs using MFBD */
1192 unsigned blend_count
= 0x200;
1194 if (ctx
->blend
->has_blend_shader
) {
1195 /* For a blend shader, the bottom nibble corresponds to
1196 * the number of work registers used, which signals the
1197 * -existence- of a blend shader */
1199 assert(ctx
->blend
->blend_work_count
>= 2);
1200 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1202 /* Otherwise, the bottom bit simply specifies if
1203 * blending (anything other than REPLACE) is enabled */
1210 struct midgard_blend_rt rts
[4];
1214 for (unsigned i
= 0; i
< 1; ++i
) {
1216 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1218 rts
[i
].flags
= blend_count
;
1221 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1223 /* TODO: sRGB in blend shaders is currently
1224 * unimplemented. Contact me (Alyssa) if you're
1225 * interested in working on this. We have
1226 * native Midgard ops for helping here, but
1227 * they're not well-understood yet. */
1229 assert(!(is_srgb
&& ctx
->blend
->has_blend_shader
));
1231 if (ctx
->blend
->has_blend_shader
) {
1232 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1234 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1235 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1239 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1243 /* We stage to transient, so always dirty.. */
1244 panfrost_stage_attributes(ctx
);
1246 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1247 panfrost_upload_sampler_descriptors(ctx
);
1249 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1250 panfrost_upload_texture_descriptors(ctx
);
1252 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1254 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1255 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1257 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1258 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1259 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1261 /* Allocate room for the sysval and the uniforms */
1262 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1263 size_t size
= sys_size
+ buf
->size
;
1264 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1266 /* Upload sysvals requested by the shader */
1267 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1269 /* Upload uniforms */
1270 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1272 int uniform_count
= 0;
1274 struct mali_vertex_tiler_postfix
*postfix
;
1277 case PIPE_SHADER_VERTEX
:
1278 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1279 postfix
= &ctx
->payload_vertex
.postfix
;
1282 case PIPE_SHADER_FRAGMENT
:
1283 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1284 postfix
= &ctx
->payload_tiler
.postfix
;
1288 unreachable("Invalid shader stage\n");
1291 /* Also attach the same buffer as a UBO for extended access */
1293 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1295 .size
= MALI_POSITIVE((2 + uniform_count
)),
1296 .ptr
= transfer
.gpu
>> 2,
1300 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1301 postfix
->uniforms
= transfer
.gpu
;
1302 postfix
->uniform_buffers
= ubufs
;
1307 /* TODO: Upload the viewport somewhere more appropriate */
1309 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1310 * (somewhat) asymmetric ints. */
1311 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1313 struct mali_viewport view
= {
1314 /* By default, do no viewport clipping, i.e. clip to (-inf,
1315 * inf) in each direction. Clipping to the viewport in theory
1316 * should work, but in practice causes issues when we're not
1317 * explicitly trying to scissor */
1328 /* Always scissor to the viewport by default. */
1329 int minx
= (int) (vp
->translate
[0] - vp
->scale
[0]);
1330 int maxx
= (int) (vp
->translate
[0] + vp
->scale
[0]);
1332 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1333 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1335 /* Apply the scissor test */
1337 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1344 /* Hardware needs the min/max to be strictly ordered, so flip if we
1345 * need to. The viewport transformation in the vertex shader will
1346 * handle the negatives if we don't */
1360 /* Clamp everything positive, just in case */
1362 maxx
= MAX2(0, maxx
);
1363 maxy
= MAX2(0, maxy
);
1364 minx
= MAX2(0, minx
);
1365 miny
= MAX2(0, miny
);
1367 /* Clamp to the framebuffer size as a last check */
1369 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1370 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1372 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1373 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1377 view
.viewport0
[0] = minx
;
1378 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1380 view
.viewport0
[1] = miny
;
1381 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1383 ctx
->payload_tiler
.postfix
.viewport
=
1384 panfrost_upload_transient(ctx
,
1386 sizeof(struct mali_viewport
));
1391 /* Corresponds to exactly one draw, but does not submit anything */
1394 panfrost_queue_draw(struct panfrost_context
*ctx
)
1396 /* TODO: Expand the array? */
1397 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1398 DBG("Job buffer overflow, ignoring draw\n");
1402 /* Handle dirty flags now */
1403 panfrost_emit_for_draw(ctx
, true);
1405 /* We need a set_value job before any other draw jobs */
1406 if (ctx
->draw_count
== 0)
1407 panfrost_set_value_job(ctx
);
1409 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1410 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1411 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1413 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1414 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1415 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1420 /* The entire frame is in memory -- send it off to the kernel! */
1423 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1424 struct pipe_fence_handle
**fence
,
1425 struct panfrost_job
*job
)
1427 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1428 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1432 panfrost_job_submit(ctx
, job
);
1434 /* If visual, we can stall a frame */
1436 if (!flush_immediate
)
1437 screen
->driver
->force_flush_fragment(ctx
, fence
);
1439 screen
->last_fragment_flushed
= false;
1440 screen
->last_job
= job
;
1442 /* If readback, flush now (hurts the pipelined performance) */
1443 if (flush_immediate
)
1444 screen
->driver
->force_flush_fragment(ctx
, fence
);
1446 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1447 screen
->driver
->dump_counters(screen
);
1450 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1451 FILE *fp
= fopen(filename
, "wb");
1452 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1460 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1462 struct panfrost_context
*ctx
= pan_context(pipe
);
1464 /* Nothing to reload? */
1465 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1468 /* Blit the wallpaper in */
1469 panfrost_blit_wallpaper(ctx
);
1471 /* We are flushing all queued draws and we know that no more jobs will
1472 * be added until the next frame.
1473 * We also know that the last jobs are the wallpaper jobs, and they
1474 * need to be linked so they execute right after the set_value job.
1477 /* set_value job to wallpaper vertex job */
1478 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1479 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1481 /* wallpaper vertex job to first vertex job */
1482 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1483 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1485 /* last vertex job to wallpaper tiler job */
1486 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1487 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1488 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1490 /* wallpaper tiler job to first tiler job */
1491 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1492 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1493 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1495 /* last tiler job to NULL */
1496 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1501 struct pipe_context
*pipe
,
1502 struct pipe_fence_handle
**fence
,
1505 struct panfrost_context
*ctx
= pan_context(pipe
);
1506 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1508 /* Nothing to do! */
1509 if (!ctx
->draw_count
&& !job
->clear
) return;
1512 panfrost_draw_wallpaper(&ctx
->base
);
1514 /* Whether to stall the pipeline for immediately correct results. Since
1515 * pipelined rendering is quite broken right now (to be fixed by the
1516 * panfrost_job refactor, just take the perf hit for correctness) */
1517 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1519 /* Submit the frame itself */
1520 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1522 /* Prepare for the next frame */
1523 panfrost_invalidate_frame(ctx
);
1526 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1529 g2m_draw_mode(enum pipe_prim_type mode
)
1532 DEFINE_CASE(POINTS
);
1534 DEFINE_CASE(LINE_LOOP
);
1535 DEFINE_CASE(LINE_STRIP
);
1536 DEFINE_CASE(TRIANGLES
);
1537 DEFINE_CASE(TRIANGLE_STRIP
);
1538 DEFINE_CASE(TRIANGLE_FAN
);
1540 DEFINE_CASE(QUAD_STRIP
);
1541 DEFINE_CASE(POLYGON
);
1544 unreachable("Invalid draw mode");
1551 panfrost_translate_index_size(unsigned size
)
1555 return MALI_DRAW_INDEXED_UINT8
;
1558 return MALI_DRAW_INDEXED_UINT16
;
1561 return MALI_DRAW_INDEXED_UINT32
;
1564 unreachable("Invalid index size");
1568 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1569 * good for the duration of the draw (transient), could last longer */
1572 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1574 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1576 off_t offset
= info
->start
* info
->index_size
;
1578 if (!info
->has_user_indices
) {
1579 /* Only resources can be directly mapped */
1580 return rsrc
->bo
->gpu
+ offset
;
1582 /* Otherwise, we need to upload to transient memory */
1583 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1584 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1589 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1591 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1593 /* Check if we're scissoring at all */
1595 if (!(ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1598 return (ss
->minx
== ss
->maxx
) && (ss
->miny
== ss
->maxy
);
1603 struct pipe_context
*pipe
,
1604 const struct pipe_draw_info
*info
)
1606 struct panfrost_context
*ctx
= pan_context(pipe
);
1608 /* First of all, check the scissor to see if anything is drawn at all.
1609 * If it's not, we drop the draw (mostly a conformance issue;
1610 * well-behaved apps shouldn't hit this) */
1612 if (panfrost_scissor_culls_everything(ctx
))
1615 ctx
->payload_vertex
.draw_start
= info
->start
;
1616 ctx
->payload_tiler
.draw_start
= info
->start
;
1618 int mode
= info
->mode
;
1620 /* Fallback for unsupported modes */
1622 if (!(ctx
->draw_modes
& (1 << mode
))) {
1623 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1624 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1626 if (info
->count
< 4) {
1627 /* Degenerate case? */
1631 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1632 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1637 /* Now that we have a guaranteed terminating path, find the job.
1638 * Assignment commented out to prevent unused warning */
1640 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1642 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1644 ctx
->vertex_count
= info
->count
;
1646 /* For non-indexed draws, they're the same */
1647 unsigned invocation_count
= ctx
->vertex_count
;
1649 unsigned draw_flags
= 0;
1651 /* The draw flags interpret how primitive size is interpreted */
1653 if (panfrost_writes_point_size(ctx
))
1654 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1656 /* For higher amounts of vertices (greater than what fits in a 16-bit
1657 * short), the other value is needed, otherwise there will be bizarre
1658 * rendering artefacts. It's not clear what these values mean yet. */
1660 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1662 if (info
->index_size
) {
1663 /* Calculate the min/max index used so we can figure out how
1664 * many times to invoke the vertex shader */
1666 /* Fetch / calculate index bounds */
1667 unsigned min_index
= 0, max_index
= 0;
1669 if (info
->max_index
== ~0u) {
1670 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1672 min_index
= info
->min_index
;
1673 max_index
= info
->max_index
;
1676 /* Use the corresponding values */
1677 invocation_count
= max_index
- min_index
+ 1;
1678 ctx
->payload_vertex
.draw_start
= min_index
;
1679 ctx
->payload_tiler
.draw_start
= min_index
;
1681 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1682 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1684 //assert(!info->restart_index); /* TODO: Research */
1685 assert(!info
->index_bias
);
1687 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1688 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1690 /* Index count == vertex count, if no indexing is applied, as
1691 * if it is internally indexed in the expected order */
1693 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1694 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1696 /* Reverse index state */
1697 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1700 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1701 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1702 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1704 /* Fire off the draw itself */
1705 panfrost_queue_draw(ctx
);
1711 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1717 panfrost_create_rasterizer_state(
1718 struct pipe_context
*pctx
,
1719 const struct pipe_rasterizer_state
*cso
)
1721 struct panfrost_context
*ctx
= pan_context(pctx
);
1722 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1726 /* Bitmask, unknown meaning of the start value */
1727 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1730 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1732 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1733 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1735 if (cso
->cull_face
& PIPE_FACE_BACK
)
1736 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1742 panfrost_bind_rasterizer_state(
1743 struct pipe_context
*pctx
,
1746 struct panfrost_context
*ctx
= pan_context(pctx
);
1748 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1752 ctx
->rasterizer
= hwcso
;
1753 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1757 panfrost_create_vertex_elements_state(
1758 struct pipe_context
*pctx
,
1759 unsigned num_elements
,
1760 const struct pipe_vertex_element
*elements
)
1762 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1764 so
->num_elements
= num_elements
;
1765 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1767 /* XXX: What the cornball? This is totally, 100%, unapologetically
1768 * nonsense. And yet it somehow fixes a regression in -bshadow
1769 * (previously, we allocated the descriptor here... a newer commit
1770 * removed that allocation, and then memory corruption led to
1771 * shader_meta getting overwritten in bad ways and then the whole test
1772 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1774 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1776 for (int i
= 0; i
< num_elements
; ++i
) {
1777 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1779 enum pipe_format fmt
= elements
[i
].src_format
;
1780 const struct util_format_description
*desc
= util_format_description(fmt
);
1781 so
->hw
[i
].unknown1
= 0x2;
1782 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1784 so
->hw
[i
].format
= panfrost_find_format(desc
);
1786 /* The field itself should probably be shifted over */
1787 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1794 panfrost_bind_vertex_elements_state(
1795 struct pipe_context
*pctx
,
1798 struct panfrost_context
*ctx
= pan_context(pctx
);
1800 ctx
->vertex
= hwcso
;
1801 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1805 panfrost_create_shader_state(
1806 struct pipe_context
*pctx
,
1807 const struct pipe_shader_state
*cso
)
1809 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1812 /* Token deep copy to prevent memory corruption */
1814 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1815 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1821 panfrost_delete_shader_state(
1822 struct pipe_context
*pctx
,
1825 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1827 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1828 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1835 panfrost_create_sampler_state(
1836 struct pipe_context
*pctx
,
1837 const struct pipe_sampler_state
*cso
)
1839 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1842 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1844 struct mali_sampler_descriptor sampler_descriptor
= {
1845 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1846 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1847 | translate_mip_filter(cso
->min_mip_filter
)
1850 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1851 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1852 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1853 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1855 cso
->border_color
.f
[0],
1856 cso
->border_color
.f
[1],
1857 cso
->border_color
.f
[2],
1858 cso
->border_color
.f
[3]
1860 .min_lod
= FIXED_16(cso
->min_lod
),
1861 .max_lod
= FIXED_16(cso
->max_lod
),
1865 so
->hw
= sampler_descriptor
;
1871 panfrost_bind_sampler_states(
1872 struct pipe_context
*pctx
,
1873 enum pipe_shader_type shader
,
1874 unsigned start_slot
, unsigned num_sampler
,
1877 assert(start_slot
== 0);
1879 struct panfrost_context
*ctx
= pan_context(pctx
);
1881 /* XXX: Should upload, not just copy? */
1882 ctx
->sampler_count
[shader
] = num_sampler
;
1883 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1885 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1889 panfrost_variant_matches(
1890 struct panfrost_context
*ctx
,
1891 struct panfrost_shader_state
*variant
,
1892 enum pipe_shader_type type
)
1894 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1896 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1898 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1899 /* Make sure enable state is at least the same */
1900 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1904 /* Check that the contents of the test are the same */
1905 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1906 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1908 if (!(same_func
&& same_ref
)) {
1912 /* Otherwise, we're good to go */
1917 panfrost_bind_shader_state(
1918 struct pipe_context
*pctx
,
1920 enum pipe_shader_type type
)
1922 struct panfrost_context
*ctx
= pan_context(pctx
);
1924 if (type
== PIPE_SHADER_FRAGMENT
) {
1926 ctx
->dirty
|= PAN_DIRTY_FS
;
1928 assert(type
== PIPE_SHADER_VERTEX
);
1930 ctx
->dirty
|= PAN_DIRTY_VS
;
1935 /* Match the appropriate variant */
1937 signed variant
= -1;
1938 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1940 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1941 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
1947 if (variant
== -1) {
1948 /* No variant matched, so create a new one */
1949 variant
= variants
->variant_count
++;
1950 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1952 variants
->variants
[variant
].base
= hwcso
;
1954 if (type
== PIPE_SHADER_FRAGMENT
)
1955 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1957 /* Allocate the mapped descriptor ahead-of-time. */
1958 struct panfrost_context
*ctx
= pan_context(pctx
);
1959 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1961 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1962 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1966 /* Select this variant */
1967 variants
->active_variant
= variant
;
1969 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1970 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
1972 /* We finally have a variant, so compile it */
1974 if (!shader_state
->compiled
) {
1975 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
1976 panfrost_job_type_for_pipe(type
), shader_state
);
1978 shader_state
->compiled
= true;
1983 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1985 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1989 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1991 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1995 panfrost_set_vertex_buffers(
1996 struct pipe_context
*pctx
,
1997 unsigned start_slot
,
1998 unsigned num_buffers
,
1999 const struct pipe_vertex_buffer
*buffers
)
2001 struct panfrost_context
*ctx
= pan_context(pctx
);
2003 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2007 panfrost_set_constant_buffer(
2008 struct pipe_context
*pctx
,
2009 enum pipe_shader_type shader
, uint index
,
2010 const struct pipe_constant_buffer
*buf
)
2012 struct panfrost_context
*ctx
= pan_context(pctx
);
2013 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2015 size_t sz
= buf
? buf
->buffer_size
: 0;
2017 /* Free previous buffer */
2023 ralloc_free(pbuf
->buffer
);
2024 pbuf
->buffer
= NULL
;
2027 /* If unbinding, we're done */
2032 /* Multiple constant buffers not yet supported */
2037 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
2040 cpu
= rsrc
->bo
->cpu
;
2041 } else if (buf
->user_buffer
) {
2042 cpu
= buf
->user_buffer
;
2044 DBG("No constant buffer?\n");
2048 /* Copy the constant buffer into the driver context for later upload */
2050 pbuf
->buffer
= rzalloc_size(ctx
, sz
);
2051 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
2055 panfrost_set_stencil_ref(
2056 struct pipe_context
*pctx
,
2057 const struct pipe_stencil_ref
*ref
)
2059 struct panfrost_context
*ctx
= pan_context(pctx
);
2060 ctx
->stencil_ref
= *ref
;
2062 /* Shader core dirty */
2063 ctx
->dirty
|= PAN_DIRTY_FS
;
2066 static enum mali_texture_type
2067 panfrost_translate_texture_type(enum pipe_texture_target t
)
2071 case PIPE_TEXTURE_1D
:
2072 case PIPE_TEXTURE_1D_ARRAY
:
2075 case PIPE_TEXTURE_2D
:
2076 case PIPE_TEXTURE_2D_ARRAY
:
2077 case PIPE_TEXTURE_RECT
:
2080 case PIPE_TEXTURE_3D
:
2083 case PIPE_TEXTURE_CUBE
:
2084 case PIPE_TEXTURE_CUBE_ARRAY
:
2085 return MALI_TEX_CUBE
;
2088 unreachable("Unknown target");
2092 static struct pipe_sampler_view
*
2093 panfrost_create_sampler_view(
2094 struct pipe_context
*pctx
,
2095 struct pipe_resource
*texture
,
2096 const struct pipe_sampler_view
*template)
2098 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2099 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2101 pipe_reference(NULL
, &texture
->reference
);
2103 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2106 so
->base
= *template;
2107 so
->base
.texture
= texture
;
2108 so
->base
.reference
.count
= 1;
2109 so
->base
.context
= pctx
;
2111 /* sampler_views correspond to texture descriptors, minus the texture
2112 * (data) itself. So, we serialise the descriptor here and cache it for
2115 /* Make sure it's something with which we're familiar */
2116 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2118 /* TODO: Detect from format better */
2119 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2121 unsigned char user_swizzle
[4] = {
2122 template->swizzle_r
,
2123 template->swizzle_g
,
2124 template->swizzle_b
,
2128 enum mali_format format
= panfrost_find_format(desc
);
2130 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2132 unsigned usage2_layout
= 0x10;
2134 switch (prsrc
->bo
->layout
) {
2136 usage2_layout
|= 0x8 | 0x4;
2139 usage2_layout
|= 0x1;
2142 usage2_layout
|= is_depth
? 0x1 : 0x2;
2149 /* Check if we need to set a custom stride by computing the "expected"
2150 * stride and comparing it to what the BO actually wants. Only applies
2151 * to linear textures, since tiled/compressed textures have strict
2152 * alignment requirements for their strides as it is */
2154 unsigned first_level
= template->u
.tex
.first_level
;
2155 unsigned last_level
= template->u
.tex
.last_level
;
2157 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2158 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2159 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2160 unsigned width
= u_minify(texture
->width0
, l
);
2161 unsigned comp_stride
= width
* bytes_per_pixel
;
2163 if (comp_stride
!= actual_stride
) {
2164 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2170 /* In the hardware, array_size refers specifically to array textures,
2171 * whereas in Gallium, it also covers cubemaps */
2173 unsigned array_size
= texture
->array_size
;
2175 if (texture
->target
== PIPE_TEXTURE_CUBE
) {
2176 /* TODO: Cubemap arrays */
2177 assert(array_size
== 6);
2180 struct mali_texture_descriptor texture_descriptor
= {
2181 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2182 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2183 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2184 .array_size
= MALI_POSITIVE(array_size
),
2188 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2191 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2192 .type
= panfrost_translate_texture_type(texture
->target
),
2194 .usage2
= usage2_layout
2197 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2200 //texture_descriptor.nr_mipmap_levels = last_level - first_level;
2202 so
->hw
= texture_descriptor
;
2204 return (struct pipe_sampler_view
*) so
;
2208 panfrost_set_sampler_views(
2209 struct pipe_context
*pctx
,
2210 enum pipe_shader_type shader
,
2211 unsigned start_slot
, unsigned num_views
,
2212 struct pipe_sampler_view
**views
)
2214 struct panfrost_context
*ctx
= pan_context(pctx
);
2216 assert(start_slot
== 0);
2218 unsigned new_nr
= 0;
2219 for (unsigned i
= 0; i
< num_views
; ++i
) {
2224 ctx
->sampler_view_count
[shader
] = new_nr
;
2225 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2227 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2231 panfrost_sampler_view_destroy(
2232 struct pipe_context
*pctx
,
2233 struct pipe_sampler_view
*view
)
2235 pipe_resource_reference(&view
->texture
, NULL
);
2240 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2241 const struct pipe_framebuffer_state
*fb
)
2243 struct panfrost_context
*ctx
= pan_context(pctx
);
2245 /* Flush when switching framebuffers, but not if the framebuffer
2246 * state is being restored by u_blitter
2249 bool is_scanout
= panfrost_is_scanout(ctx
);
2250 bool has_draws
= ctx
->draw_count
> 0;
2252 if (!ctx
->blitter
->running
&& (!is_scanout
|| has_draws
)) {
2253 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2256 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2257 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2258 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2259 ctx
->pipe_framebuffer
.width
= fb
->width
;
2260 ctx
->pipe_framebuffer
.height
= fb
->height
;
2262 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2263 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2265 /* check if changing cbuf */
2266 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2268 if (cb
&& (i
!= 0)) {
2269 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2274 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2279 if (ctx
->require_sfbd
)
2280 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2282 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2284 panfrost_attach_vt_framebuffer(ctx
);
2286 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2287 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2289 bool can_afbc
= panfrost_format_supports_afbc(format
);
2290 bool is_scanout
= panfrost_is_scanout(ctx
);
2292 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2293 panfrost_enable_afbc(ctx
, tex
, false);
2295 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2296 panfrost_enable_checksum(ctx
, tex
);
2300 struct pipe_surface
*zb
= fb
->zsbuf
;
2302 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2303 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2306 if (ctx
->require_sfbd
)
2307 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2309 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2311 panfrost_attach_vt_framebuffer(ctx
);
2313 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2314 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2315 bool is_scanout
= panfrost_is_scanout(ctx
);
2317 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2318 panfrost_enable_afbc(ctx
, tex
, true);
2325 panfrost_create_blend_state(struct pipe_context
*pipe
,
2326 const struct pipe_blend_state
*blend
)
2328 struct panfrost_context
*ctx
= pan_context(pipe
);
2329 struct panfrost_blend_state
*so
= rzalloc(ctx
, struct panfrost_blend_state
);
2332 /* TODO: The following features are not yet implemented */
2333 assert(!blend
->logicop_enable
);
2334 assert(!blend
->alpha_to_coverage
);
2335 assert(!blend
->alpha_to_one
);
2337 /* Compile the blend state, first as fixed-function if we can */
2339 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2342 /* If we can't, compile a blend shader instead */
2344 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2350 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2353 struct panfrost_context
*ctx
= pan_context(pipe
);
2354 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2355 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2356 ctx
->blend
= pblend
;
2361 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2363 /* TODO: Attach color */
2365 /* Shader itself is not dirty, but the shader core is */
2366 ctx
->dirty
|= PAN_DIRTY_FS
;
2370 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2373 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2375 if (so
->has_blend_shader
) {
2376 DBG("Deleting blend state leak blend shaders bytecode\n");
2383 panfrost_set_blend_color(struct pipe_context
*pipe
,
2384 const struct pipe_blend_color
*blend_color
)
2386 struct panfrost_context
*ctx
= pan_context(pipe
);
2388 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2391 ctx
->blend_color
= *blend_color
;
2393 /* The blend mode depends on the blend constant color, due to the
2394 * fixed/programmable split. So, we're forced to regenerate the blend
2397 /* TODO: Attach color */
2402 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2403 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2405 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2409 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2412 struct panfrost_context
*ctx
= pan_context(pipe
);
2413 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2414 ctx
->depth_stencil
= depth_stencil
;
2419 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2420 * emulated in the fragment shader */
2422 if (depth_stencil
->alpha
.enabled
) {
2423 /* We need to trigger a new shader (maybe) */
2424 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2428 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2430 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2431 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2433 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2434 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2436 /* Depth state (TODO: Refactor) */
2437 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2439 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2441 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2442 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2444 /* Bounds test not implemented */
2445 assert(!depth_stencil
->depth
.bounds_test
);
2447 ctx
->dirty
|= PAN_DIRTY_FS
;
2451 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2457 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2458 unsigned sample_mask
)
2463 panfrost_set_clip_state(struct pipe_context
*pipe
,
2464 const struct pipe_clip_state
*clip
)
2466 //struct panfrost_context *panfrost = pan_context(pipe);
2470 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2471 unsigned start_slot
,
2472 unsigned num_viewports
,
2473 const struct pipe_viewport_state
*viewports
)
2475 struct panfrost_context
*ctx
= pan_context(pipe
);
2477 assert(start_slot
== 0);
2478 assert(num_viewports
== 1);
2480 ctx
->pipe_viewport
= *viewports
;
2484 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2485 unsigned start_slot
,
2486 unsigned num_scissors
,
2487 const struct pipe_scissor_state
*scissors
)
2489 struct panfrost_context
*ctx
= pan_context(pipe
);
2491 assert(start_slot
== 0);
2492 assert(num_scissors
== 1);
2494 ctx
->scissor
= *scissors
;
2498 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2499 const struct pipe_poly_stipple
*stipple
)
2501 //struct panfrost_context *panfrost = pan_context(pipe);
2505 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2508 //struct panfrost_context *panfrost = pan_context(pipe);
2512 panfrost_destroy(struct pipe_context
*pipe
)
2514 struct panfrost_context
*panfrost
= pan_context(pipe
);
2515 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2517 if (panfrost
->blitter
)
2518 util_blitter_destroy(panfrost
->blitter
);
2520 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2521 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2522 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2523 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2524 screen
->driver
->free_slab(screen
, &panfrost
->tiler_polygon_list
);
2525 screen
->driver
->free_slab(screen
, &panfrost
->tiler_dummy
);
2527 for (int i
= 0; i
< ARRAY_SIZE(panfrost
->transient_pools
); ++i
) {
2528 struct panfrost_memory_entry
*entry
;
2529 entry
= panfrost
->transient_pools
[i
].entries
[0];
2530 pb_slab_free(&screen
->slabs
, (struct pb_slab_entry
*)entry
);
2536 static struct pipe_query
*
2537 panfrost_create_query(struct pipe_context
*pipe
,
2541 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2546 return (struct pipe_query
*) q
;
2550 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2556 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2558 struct panfrost_context
*ctx
= pan_context(pipe
);
2559 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2561 switch (query
->type
) {
2562 case PIPE_QUERY_OCCLUSION_COUNTER
:
2563 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2564 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2566 /* Allocate a word for the query results to be stored */
2567 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2569 ctx
->occlusion_query
= query
;
2575 DBG("Skipping query %d\n", query
->type
);
2583 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2585 struct panfrost_context
*ctx
= pan_context(pipe
);
2586 ctx
->occlusion_query
= NULL
;
2591 panfrost_get_query_result(struct pipe_context
*pipe
,
2592 struct pipe_query
*q
,
2594 union pipe_query_result
*vresult
)
2597 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2599 /* We need to flush out the jobs to actually run the counter, TODO
2600 * check wait, TODO wallpaper after if needed */
2602 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2604 switch (query
->type
) {
2605 case PIPE_QUERY_OCCLUSION_COUNTER
:
2606 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2607 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2608 /* Read back the query results */
2609 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2610 unsigned passed
= *result
;
2612 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2613 vresult
->u64
= passed
;
2615 vresult
->b
= !!passed
;
2621 DBG("Skipped query get %d\n", query
->type
);
2628 static struct pipe_stream_output_target
*
2629 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2630 struct pipe_resource
*prsc
,
2631 unsigned buffer_offset
,
2632 unsigned buffer_size
)
2634 struct pipe_stream_output_target
*target
;
2636 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2641 pipe_reference_init(&target
->reference
, 1);
2642 pipe_resource_reference(&target
->buffer
, prsc
);
2644 target
->context
= pctx
;
2645 target
->buffer_offset
= buffer_offset
;
2646 target
->buffer_size
= buffer_size
;
2652 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2653 struct pipe_stream_output_target
*target
)
2655 pipe_resource_reference(&target
->buffer
, NULL
);
2656 ralloc_free(target
);
2660 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2661 unsigned num_targets
,
2662 struct pipe_stream_output_target
**targets
,
2663 const unsigned *offsets
)
2669 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2671 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2672 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2674 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2675 /* Allocate the beginning of the transient pool */
2676 int entry_size
= (1 << 22); /* 4MB */
2678 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2679 ctx
->transient_pools
[i
].entry_count
= 1;
2681 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2684 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2685 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2686 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2687 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2688 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2689 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2692 /* New context creation, which also does hardware initialisation since I don't
2693 * know the better way to structure this :smirk: */
2695 struct pipe_context
*
2696 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2698 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2699 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2700 memset(ctx
, 0, sizeof(*ctx
));
2701 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2704 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2706 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2707 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2709 gallium
->screen
= screen
;
2711 gallium
->destroy
= panfrost_destroy
;
2713 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2715 gallium
->flush
= panfrost_flush
;
2716 gallium
->clear
= panfrost_clear
;
2717 gallium
->draw_vbo
= panfrost_draw_vbo
;
2719 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2720 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2722 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2724 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2725 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2726 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2728 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2729 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2730 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2732 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2733 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2734 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2736 gallium
->create_fs_state
= panfrost_create_shader_state
;
2737 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2738 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2740 gallium
->create_vs_state
= panfrost_create_shader_state
;
2741 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2742 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2744 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2745 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2746 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2748 gallium
->create_blend_state
= panfrost_create_blend_state
;
2749 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2750 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2752 gallium
->set_blend_color
= panfrost_set_blend_color
;
2754 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2755 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2756 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2758 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2760 gallium
->set_clip_state
= panfrost_set_clip_state
;
2761 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2762 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2763 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2764 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2766 gallium
->create_query
= panfrost_create_query
;
2767 gallium
->destroy_query
= panfrost_destroy_query
;
2768 gallium
->begin_query
= panfrost_begin_query
;
2769 gallium
->end_query
= panfrost_end_query
;
2770 gallium
->get_query_result
= panfrost_get_query_result
;
2772 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2773 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2774 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2776 panfrost_resource_context_init(gallium
);
2778 pscreen
->driver
->init_context(ctx
);
2780 panfrost_setup_hardware(ctx
);
2783 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2784 gallium
->const_uploader
= gallium
->stream_uploader
;
2785 assert(gallium
->stream_uploader
);
2787 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2788 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2790 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2792 ctx
->blitter
= util_blitter_create(gallium
);
2793 assert(ctx
->blitter
);
2795 /* Prepare for render! */
2797 panfrost_job_init(ctx
);
2798 panfrost_emit_vertex_payload(ctx
);
2799 panfrost_emit_tiler_payload(ctx
);
2800 panfrost_invalidate_frame(ctx
);
2801 panfrost_default_shader_backend(ctx
);
2802 panfrost_generate_space_filler_indices();