2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
45 #include "pan_wallpaper.h"
47 static int performance_counter_number
= 0;
48 extern const char *pan_counters_base
;
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 /* TODO: Sample size, etc */
56 panfrost_set_framebuffer_msaa(struct panfrost_context
*ctx
, bool enabled
)
58 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
62 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, enabled
);
63 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !enabled
);
66 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
67 * indepdent between color buffers and depth/stencil). To enable, we allocate
68 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
69 * edit the fragment job here. This routine should be called ONCE per
70 * AFBC-compressed buffer, rather than on every frame. */
73 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
75 if (ctx
->require_sfbd
) {
76 DBG("AFBC not supported yet on SFBD\n");
80 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
81 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
82 /* AFBC metadata is 16 bytes per tile */
83 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
84 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
85 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
86 int stride
= bytes_per_pixel
* rsrc
->base
.width0
; /* TODO: Alignment? */
88 stride
*= 2; /* TODO: Should this be carried over? */
89 int main_size
= stride
* rsrc
->base
.height0
;
90 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
92 /* Allocate the AFBC slab itself, large enough to hold the above */
93 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
94 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
97 rsrc
->bo
->layout
= PAN_AFBC
;
99 /* Compressed textured reads use a tagged pointer to the metadata */
101 rsrc
->bo
->gpu
[0] = rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
102 rsrc
->bo
->cpu
[0] = rsrc
->bo
->afbc_slab
.cpu
;
106 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
108 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
109 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
110 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
111 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
113 /* 8 byte checksum per tile */
114 rsrc
->bo
->checksum_stride
= tile_w
* 8;
115 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
116 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
118 rsrc
->bo
->has_checksum
= true;
121 /* Framebuffer descriptor */
124 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
126 fb
->width
= MALI_POSITIVE(w
);
127 fb
->height
= MALI_POSITIVE(h
);
129 /* No idea why this is needed, but it's how resolution_check is
130 * calculated. It's not clear to us yet why the hardware wants this.
131 * The formula itself was discovered mostly by manual bruteforce and
132 * aggressive algebraic simplification. */
134 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
137 struct mali_single_framebuffer
138 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
140 struct mali_single_framebuffer framebuffer
= {
142 .format
= 0x30000000,
143 .clear_flags
= 0x1000,
144 .unknown_address_0
= ctx
->scratchpad
.gpu
,
145 .unknown_address_1
= ctx
->misc_0
.gpu
,
146 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
148 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
149 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
152 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
157 struct bifrost_framebuffer
158 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
160 struct bifrost_framebuffer framebuffer
= {
161 /* It is not yet clear what tiler_meta means or how it's
162 * calculated, but we can tell the lower 32-bits are a
163 * (monotonically increasing?) function of tile count and
164 * geometry complexity; I suspect it defines a memory size of
165 * some kind? for the tiler. It's really unclear at the
166 * moment... but to add to the confusion, the hardware is happy
167 * enough to accept a zero in this field, so we don't even have
168 * to worry about it right now.
170 * The byte (just after the 32-bit mark) is much more
171 * interesting. The higher nibble I've only ever seen as 0xF,
172 * but the lower one I've seen as 0x0 or 0xF, and it's not
173 * obvious what the difference is. But what -is- obvious is
174 * that when the lower nibble is zero, performance is severely
175 * degraded compared to when the lower nibble is set.
176 * Evidently, that nibble enables some sort of fast path,
177 * perhaps relating to caching or tile flush? Regardless, at
178 * this point there's no clear reason not to set it, aside from
179 * substantially increased memory requirements (of the misc_0
182 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
184 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
185 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
186 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
187 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
192 .rt_count_1
= MALI_POSITIVE(1),
197 /* Corresponds to unknown_address_X of SFBD */
198 .scratchpad
= ctx
->scratchpad
.gpu
,
199 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
201 /* The constant added here is, like the lower word of
202 * tiler_meta, (loosely) another product of framebuffer size
203 * and geometry complexity. It must be sufficiently large for
204 * the tiler_meta fast path to work; if it's too small, there
205 * will be DATA_INVALID_FAULTs. Conversely, it must be less
206 * than the total size of misc_0, or else there's no room. It's
207 * possible this constant configures a partition between two
208 * parts of misc_0? We haven't investigated the functionality,
209 * as these buffers are internally used by the hardware
210 * (presumably by the tiler) but not seemingly touched by the driver
213 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
215 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
216 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
222 /* Are we currently rendering to the screen (rather than an FBO)? */
225 panfrost_is_scanout(struct panfrost_context
*ctx
)
227 /* If there is no color buffer, it's an FBO */
228 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
231 /* If we're too early that no framebuffer was sent, it's scanout */
232 if (!ctx
->pipe_framebuffer
.cbufs
[0])
235 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
236 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
237 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
240 /* Maps float 0.0-1.0 to int 0x00-0xFF */
242 normalised_float_to_u8(float f
)
244 return (uint8_t) (int) (f
* 255.0f
);
249 struct pipe_context
*pipe
,
251 const union pipe_color_union
*color
,
252 double depth
, unsigned stencil
)
254 struct panfrost_context
*ctx
= pan_context(pipe
);
255 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
257 if (buffers
& PIPE_CLEAR_COLOR
) {
258 /* Alpha clear only meaningful without alpha channel, TODO less ad hoc */
259 bool has_alpha
= util_format_has_alpha(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
260 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
262 uint32_t packed_color
=
263 (normalised_float_to_u8(clear_alpha
) << 24) |
264 (normalised_float_to_u8(color
->f
[2]) << 16) |
265 (normalised_float_to_u8(color
->f
[1]) << 8) |
266 (normalised_float_to_u8(color
->f
[0]) << 0);
268 job
->clear_color
= packed_color
;
272 if (buffers
& PIPE_CLEAR_DEPTH
) {
273 job
->clear_depth
= depth
;
276 if (buffers
& PIPE_CLEAR_STENCIL
) {
277 job
->clear_stencil
= stencil
;
280 job
->clear
|= buffers
;
284 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
286 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
287 struct bifrost_render_target rts_list
[] = {
292 .framebuffer
= ctx
->misc_0
.gpu
,
297 /* Allocate memory for the three components */
298 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
299 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
301 /* Opaque 1024-block */
302 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
304 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
305 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
307 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
311 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
313 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
317 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
319 mali_ptr framebuffer
= ctx
->require_sfbd
?
320 panfrost_attach_vt_sfbd(ctx
) :
321 panfrost_attach_vt_mfbd(ctx
);
323 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
324 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
328 panfrost_viewport(struct panfrost_context
*ctx
,
329 float depth_clip_near
,
330 float depth_clip_far
,
331 int viewport_x0
, int viewport_y0
,
332 int viewport_x1
, int viewport_y1
)
334 /* Clip bounds are encoded as floats. The viewport itself is encoded as
335 * (somewhat) asymmetric ints. */
337 struct mali_viewport ret
= {
338 /* By default, do no viewport clipping, i.e. clip to (-inf,
339 * inf) in each direction. Clipping to the viewport in theory
340 * should work, but in practice causes issues when we're not
341 * explicitly trying to scissor */
348 /* We always perform depth clipping (TODO: Can this be disabled?) */
350 .clip_minz
= depth_clip_near
,
351 .clip_maxz
= depth_clip_far
,
353 .viewport0
= { viewport_x0
, viewport_y0
},
354 .viewport1
= { MALI_POSITIVE(viewport_x1
), MALI_POSITIVE(viewport_y1
) },
357 memcpy(ctx
->viewport
, &ret
, sizeof(ret
));
360 /* Reset per-frame context, called on context initialisation as well as after
361 * flushing a frame */
364 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
366 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
367 DBG("Uploaded transient %d bytes\n", transient_count
);
369 /* Rotate cmdstream */
370 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
371 ctx
->cmdstream_i
= 0;
373 if (ctx
->require_sfbd
)
374 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
376 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
378 /* Reset varyings allocated */
379 ctx
->varying_height
= 0;
381 /* The transient cmdstream is dirty every frame; the only bits worth preserving
382 * (textures, shaders, etc) are in other buffers anyways */
384 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
385 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
387 /* Regenerate payloads */
388 panfrost_attach_vt_framebuffer(ctx
);
391 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
394 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
397 /* In practice, every field of these payloads should be configurable
398 * arbitrarily, which means these functions are basically catch-all's for
399 * as-of-yet unwavering unknowns */
402 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
404 struct midgard_payload_vertex_tiler payload
= {
406 .workgroups_z_shift
= 32,
407 .workgroups_x_shift_2
= 0x2,
408 .workgroups_x_shift_3
= 0x5,
410 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
413 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
417 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
419 struct midgard_payload_vertex_tiler payload
= {
421 .workgroups_z_shift
= 32,
422 .workgroups_x_shift_2
= 0x2,
423 .workgroups_x_shift_3
= 0x6,
425 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
429 /* Reserve the viewport */
430 struct panfrost_transfer t
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_viewport
), HEAP_DESCRIPTOR
);
431 ctx
->viewport
= (struct mali_viewport
*) t
.cpu
;
432 payload
.postfix
.viewport
= t
.gpu
;
434 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
438 translate_tex_wrap(enum pipe_tex_wrap w
)
441 case PIPE_TEX_WRAP_REPEAT
:
442 return MALI_WRAP_REPEAT
;
444 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
445 return MALI_WRAP_CLAMP_TO_EDGE
;
447 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
448 return MALI_WRAP_CLAMP_TO_BORDER
;
450 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
451 return MALI_WRAP_MIRRORED_REPEAT
;
460 translate_tex_filter(enum pipe_tex_filter f
)
463 case PIPE_TEX_FILTER_NEAREST
:
466 case PIPE_TEX_FILTER_LINEAR
:
476 translate_mip_filter(enum pipe_tex_mipfilter f
)
478 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
482 panfrost_translate_compare_func(enum pipe_compare_func in
)
485 case PIPE_FUNC_NEVER
:
486 return MALI_FUNC_NEVER
;
489 return MALI_FUNC_LESS
;
491 case PIPE_FUNC_EQUAL
:
492 return MALI_FUNC_EQUAL
;
494 case PIPE_FUNC_LEQUAL
:
495 return MALI_FUNC_LEQUAL
;
497 case PIPE_FUNC_GREATER
:
498 return MALI_FUNC_GREATER
;
500 case PIPE_FUNC_NOTEQUAL
:
501 return MALI_FUNC_NOTEQUAL
;
503 case PIPE_FUNC_GEQUAL
:
504 return MALI_FUNC_GEQUAL
;
506 case PIPE_FUNC_ALWAYS
:
507 return MALI_FUNC_ALWAYS
;
511 return 0; /* Unreachable */
515 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
518 case PIPE_FUNC_NEVER
:
519 return MALI_ALT_FUNC_NEVER
;
522 return MALI_ALT_FUNC_LESS
;
524 case PIPE_FUNC_EQUAL
:
525 return MALI_ALT_FUNC_EQUAL
;
527 case PIPE_FUNC_LEQUAL
:
528 return MALI_ALT_FUNC_LEQUAL
;
530 case PIPE_FUNC_GREATER
:
531 return MALI_ALT_FUNC_GREATER
;
533 case PIPE_FUNC_NOTEQUAL
:
534 return MALI_ALT_FUNC_NOTEQUAL
;
536 case PIPE_FUNC_GEQUAL
:
537 return MALI_ALT_FUNC_GEQUAL
;
539 case PIPE_FUNC_ALWAYS
:
540 return MALI_ALT_FUNC_ALWAYS
;
544 return 0; /* Unreachable */
548 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
551 case PIPE_STENCIL_OP_KEEP
:
552 return MALI_STENCIL_KEEP
;
554 case PIPE_STENCIL_OP_ZERO
:
555 return MALI_STENCIL_ZERO
;
557 case PIPE_STENCIL_OP_REPLACE
:
558 return MALI_STENCIL_REPLACE
;
560 case PIPE_STENCIL_OP_INCR
:
561 return MALI_STENCIL_INCR
;
563 case PIPE_STENCIL_OP_DECR
:
564 return MALI_STENCIL_DECR
;
566 case PIPE_STENCIL_OP_INCR_WRAP
:
567 return MALI_STENCIL_INCR_WRAP
;
569 case PIPE_STENCIL_OP_DECR_WRAP
:
570 return MALI_STENCIL_DECR_WRAP
;
572 case PIPE_STENCIL_OP_INVERT
:
573 return MALI_STENCIL_INVERT
;
577 return 0; /* Unreachable */
581 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
583 out
->ref
= 0; /* Gallium gets it from elsewhere */
585 out
->mask
= in
->valuemask
;
586 out
->func
= panfrost_translate_compare_func(in
->func
);
587 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
588 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
589 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
593 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
595 struct mali_shader_meta shader
= {
596 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
598 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
599 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
603 shader
.unknown2_4
|= 0x10;
606 struct pipe_stencil_state default_stencil
= {
608 .func
= PIPE_FUNC_ALWAYS
,
609 .fail_op
= MALI_STENCIL_KEEP
,
610 .zfail_op
= MALI_STENCIL_KEEP
,
611 .zpass_op
= MALI_STENCIL_KEEP
,
616 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
617 shader
.stencil_mask_front
= default_stencil
.writemask
;
619 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
620 shader
.stencil_mask_back
= default_stencil
.writemask
;
622 if (default_stencil
.enabled
)
623 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
625 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
628 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
629 * graphics command stream. It should be called once per draw, accordding to
630 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
631 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
634 struct panfrost_transfer
635 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
637 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
638 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
640 struct mali_job_descriptor_header job
= {
641 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
642 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
644 .job_descriptor_size
= 1,
648 /* Only non-elided tiler jobs have dependencies which are known at this point */
650 if (is_tiler
&& !is_elided_tiler
) {
651 /* Tiler jobs depend on vertex jobs */
653 job
.job_dependency_index_1
= draw_job_index
;
655 /* Tiler jobs also depend on the previous tiler job */
658 job
.job_dependency_index_2
= draw_job_index
- 1;
661 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
663 /* There's some padding hacks on 32-bit */
670 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
671 memcpy(transfer
.cpu
, &job
, sizeof(job
));
672 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
676 /* Generates a set value job. It's unclear what exactly this does, why it's
677 * necessary, and when to call it. */
680 panfrost_set_value_job(struct panfrost_context
*ctx
)
682 struct mali_job_descriptor_header job
= {
683 .job_type
= JOB_TYPE_SET_VALUE
,
684 .job_descriptor_size
= 1,
685 .job_index
= 1 + (2 * ctx
->draw_count
),
688 struct mali_payload_set_value payload
= {
689 .out
= ctx
->misc_0
.gpu
,
693 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
694 memcpy(transfer
.cpu
, &job
, sizeof(job
));
695 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
697 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
698 ctx
->set_value_job
= transfer
.gpu
;
701 /* Emits attributes and varying descriptors, which should be called every draw,
702 * excepting some obscure circumstances */
705 panfrost_emit_vertex_data(struct panfrost_context
*ctx
)
707 /* TODO: Only update the dirtied buffers */
708 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
709 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
711 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
713 for (int i
= 0; i
< ctx
->vertex_buffer_count
; ++i
) {
714 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
715 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
717 /* Let's figure out the layout of the attributes in memory so
718 * we can be smart about size computation. The idea is to
719 * figure out the maximum src_offset, which tells us the latest
720 * spot a vertex could start. Meanwhile, we figure out the size
721 * of the attribute memory (assuming interleaved
722 * representation) and tack on the max src_offset for a
723 * reasonably good upper bound on the size.
725 * Proving correctness is left as an exercise to the reader.
728 unsigned max_src_offset
= 0;
730 for (unsigned j
= 0; j
< ctx
->vertex
->num_elements
; ++j
) {
731 if (ctx
->vertex
->pipe
[j
].vertex_buffer_index
!= i
) continue;
732 max_src_offset
= MAX2(max_src_offset
, ctx
->vertex
->pipe
[j
].src_offset
);
735 /* Offset vertex count by draw_start to make sure we upload enough */
736 attrs
[i
].stride
= buf
->stride
;
737 attrs
[i
].size
= buf
->stride
* (ctx
->payload_vertex
.draw_start
+ invocation_count
) + max_src_offset
;
739 /* Vertex elements are -already- GPU-visible, at
740 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
741 * it is not, for now we have to duplicate the buffer. */
743 mali_ptr effective_address
= (rsrc
->bo
->gpu
[0] + buf
->buffer_offset
);
745 if (effective_address
& 0x3F) {
746 attrs
[i
].elements
= panfrost_upload_transient(ctx
, rsrc
->bo
->cpu
[0] + buf
->buffer_offset
, attrs
[i
].size
) | 1;
748 attrs
[i
].elements
= effective_address
| 1;
752 struct panfrost_varyings
*vars
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
754 for (int i
= 0; i
< vars
->varying_buffer_count
; ++i
) {
755 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
757 varyings
[i
].elements
= varying_address
| 1;
758 varyings
[i
].stride
= vars
->varyings_stride
[i
];
759 varyings
[i
].size
= vars
->varyings_stride
[i
] * invocation_count
;
761 /* If this varying has to be linked somewhere, do it now. See
762 * pan_assemble.c for the indices. TODO: Use a more generic
763 * linking interface */
767 ctx
->payload_tiler
.postfix
.position_varying
= varying_address
;
770 ctx
->payload_tiler
.primitive_size
.pointer
= varying_address
;
773 /* Varyings appear to need 64-byte alignment */
774 ctx
->varying_height
+= ALIGN(varyings
[i
].size
, 64);
776 /* Ensure that we fit */
777 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
780 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, ctx
->vertex_buffer_count
* sizeof(union mali_attr
));
782 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, vars
->varying_buffer_count
* sizeof(union mali_attr
));
783 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
784 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
787 /* Go through dirty flags and actualise them in the cmdstream. */
790 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
792 if (with_vertex_data
) {
793 panfrost_emit_vertex_data(ctx
);
796 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
797 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
798 panfrost_set_framebuffer_msaa(ctx
, ctx
->rasterizer
->base
.multisample
);
801 if (ctx
->occlusion_query
) {
802 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
803 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
806 if (ctx
->dirty
& PAN_DIRTY_VS
) {
809 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
811 /* Late shader descriptor assignments */
812 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
813 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
816 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
818 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
820 /* Varying descriptor is tied to the vertex shader. Also the
821 * fragment shader, I suppose, but it's generated with the
822 * vertex shader so */
824 struct panfrost_varyings
*varyings
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
826 ctx
->payload_vertex
.postfix
.varying_meta
= varyings
->varyings_descriptor
;
827 ctx
->payload_tiler
.postfix
.varying_meta
= varyings
->varyings_descriptor_fragment
;
830 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
831 /* Check if we need to link the gl_PointSize varying */
833 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
835 bool needs_gl_point_size
= vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
837 if (!needs_gl_point_size
) {
838 /* If the size is constant, write it out. Otherwise,
839 * don't touch primitive_size (since we would clobber
840 * the pointer there) */
842 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
845 /* Set the flag for varying (pointer) point size if the shader needs that */
846 SET_BIT(ctx
->payload_tiler
.prefix
.unknown_draw
, MALI_DRAW_VARYING_SIZE
, needs_gl_point_size
);
849 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
851 ctx
->dirty
|= PAN_DIRTY_FS
;
853 if (ctx
->dirty
& PAN_DIRTY_FS
) {
855 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
857 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
860 COPY(attribute_count
);
862 COPY(midgard1
.uniform_count
);
863 COPY(midgard1
.work_count
);
864 COPY(midgard1
.unknown2
);
867 /* If there is a blend shader, work registers are shared */
869 if (ctx
->blend
->has_blend_shader
)
870 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
872 /* Set late due to depending on render state */
873 /* The one at the end seems to mean "1 UBO" */
874 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
876 /* Assign texture/sample count right before upload */
877 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
878 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
880 /* Assign the stencil refs late */
881 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
882 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
884 /* CAN_DISCARD should be set if the fragment shader possibly
885 * contains a 'discard' instruction. It is likely this is
886 * related to optimizations related to forward-pixel kill, as
887 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
888 * thing?" by Peter Harris
891 if (variant
->can_discard
) {
892 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
893 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
894 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
895 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
898 /* Check if we're using the default blend descriptor (fast path) */
901 !ctx
->blend
->has_blend_shader
&&
902 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
903 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
904 (ctx
->blend
->equation
.color_mask
== 0xf);
906 if (ctx
->require_sfbd
) {
907 /* When only a single render target platform is used, the blend
908 * information is inside the shader meta itself. We
909 * additionally need to signal CAN_DISCARD for nontrivial blend
910 * modes (so we're able to read back the destination buffer) */
912 if (ctx
->blend
->has_blend_shader
) {
913 ctx
->fragment_shader_core
.blend_shader
= ctx
->blend
->blend_shader
;
915 memcpy(&ctx
->fragment_shader_core
.blend_equation
, &ctx
->blend
->equation
, sizeof(ctx
->blend
->equation
));
919 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
923 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct mali_blend_meta
);
924 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
925 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
927 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
929 if (!ctx
->require_sfbd
) {
930 /* Additional blend descriptor tacked on for jobs using MFBD */
932 unsigned blend_count
= 0;
934 if (ctx
->blend
->has_blend_shader
) {
935 /* For a blend shader, the bottom nibble corresponds to
936 * the number of work registers used, which signals the
937 * -existence- of a blend shader */
939 assert(ctx
->blend
->blend_work_count
>= 2);
940 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
942 /* Otherwise, the bottom bit simply specifies if
943 * blending (anything other than REPLACE) is enabled */
950 /* Second blend equation is always a simple replace */
952 uint64_t replace_magic
= 0xf0122122;
953 struct mali_blend_equation replace_mode
;
954 memcpy(&replace_mode
, &replace_magic
, sizeof(replace_mode
));
956 struct mali_blend_meta blend_meta
[] = {
958 .unk1
= 0x200 | blend_count
,
959 .blend_equation_1
= ctx
->blend
->equation
,
960 .blend_equation_2
= replace_mode
964 if (ctx
->blend
->has_blend_shader
)
965 memcpy(&blend_meta
[0].blend_equation_1
, &ctx
->blend
->blend_shader
, sizeof(ctx
->blend
->blend_shader
));
967 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), blend_meta
, sizeof(blend_meta
));
971 if (ctx
->dirty
& PAN_DIRTY_VERTEX
) {
972 ctx
->payload_vertex
.postfix
.attribute_meta
= ctx
->vertex
->descriptor_ptr
;
975 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
976 /* Upload samplers back to back, no padding */
978 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
979 if (!ctx
->sampler_count
[t
]) continue;
981 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
982 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
984 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
985 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
988 if (t
== PIPE_SHADER_FRAGMENT
)
989 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
990 else if (t
== PIPE_SHADER_VERTEX
)
991 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
997 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
998 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1000 if (!ctx
->sampler_view_count
[t
]) continue;
1002 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1004 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1005 if (!ctx
->sampler_views
[t
][i
])
1008 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1009 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1011 /* Inject the address in. */
1012 for (int l
= 0; l
< (tex_rsrc
->last_level
+ 1); ++l
)
1013 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[l
] = rsrc
->bo
->gpu
[l
];
1015 /* Workaround maybe-errata (?) with non-mipmaps */
1016 int s
= ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
;
1018 if (!rsrc
->bo
->is_mipmap
) {
1020 /* HW ERRATA, not needed after t6XX */
1021 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[1] = rsrc
->bo
->gpu
[0];
1023 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 1;
1026 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= 0;
1029 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1032 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= s
;
1035 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 0;
1039 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1041 if (t
== PIPE_SHADER_FRAGMENT
)
1042 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1043 else if (t
== PIPE_SHADER_VERTEX
)
1044 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1050 /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1051 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1053 float viewport_vec4
[] = {
1055 fabsf(vp
->scale
[1]),
1058 /* -1.0 * vp->translate[1] */ fabs(1.0 * vp
->scale
[1]) /* XXX */
1061 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1062 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1064 if (i
== PIPE_SHADER_VERTEX
|| i
== PIPE_SHADER_FRAGMENT
) {
1065 /* It doesn't matter if we don't use all the memory;
1066 * we'd need a dummy UBO anyway. Compute the max */
1068 size_t size
= sizeof(viewport_vec4
) + buf
->size
;
1069 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1071 /* Keep track how much we've uploaded */
1074 if (i
== PIPE_SHADER_VERTEX
) {
1075 /* Upload viewport */
1076 memcpy(transfer
.cpu
+ offset
, viewport_vec4
, sizeof(viewport_vec4
));
1077 offset
+= sizeof(viewport_vec4
);
1080 /* Upload uniforms */
1081 memcpy(transfer
.cpu
+ offset
, buf
->buffer
, buf
->size
);
1083 int uniform_count
= 0;
1085 struct mali_vertex_tiler_postfix
*postfix
;
1088 case PIPE_SHADER_VERTEX
:
1089 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1090 postfix
= &ctx
->payload_vertex
.postfix
;
1093 case PIPE_SHADER_FRAGMENT
:
1094 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1095 postfix
= &ctx
->payload_tiler
.postfix
;
1099 DBG("Unknown shader stage %d in uniform upload\n", i
);
1103 /* Also attach the same buffer as a UBO for extended access */
1105 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1107 .size
= MALI_POSITIVE((2 + uniform_count
)),
1108 .ptr
= transfer
.gpu
>> 2,
1112 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1113 postfix
->uniforms
= transfer
.gpu
;
1114 postfix
->uniform_buffers
= ubufs
;
1123 /* Corresponds to exactly one draw, but does not submit anything */
1126 panfrost_queue_draw(struct panfrost_context
*ctx
)
1128 /* TODO: Expand the array? */
1129 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1130 DBG("Job buffer overflow, ignoring draw\n");
1134 /* Handle dirty flags now */
1135 panfrost_emit_for_draw(ctx
, true);
1137 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1138 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1140 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1141 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1143 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1144 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1149 /* At the end of the frame, the vertex and tiler jobs are linked together and
1150 * then the fragment job is plonked at the end. Set value job is first for
1151 * unknown reasons. */
1154 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1156 if (first
->job_descriptor_size
)
1157 first
->next_job_64
= (u64
) (uintptr_t) next
;
1159 first
->next_job_32
= (u32
) (uintptr_t) next
;
1163 panfrost_link_jobs(struct panfrost_context
*ctx
)
1165 if (ctx
->draw_count
) {
1166 /* Generate the set_value_job */
1167 panfrost_set_value_job(ctx
);
1169 /* Have the first vertex job depend on the set value job */
1170 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1173 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1176 /* V -> V/T ; T -> T/null */
1177 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1178 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1180 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1184 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1185 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1186 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1190 /* The entire frame is in memory -- send it off to the kernel! */
1193 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1194 struct pipe_fence_handle
**fence
)
1196 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1197 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1199 /* Edge case if screen is cleared and nothing else */
1200 bool has_draws
= ctx
->draw_count
> 0;
1202 /* Workaround a bizarre lockup (a hardware errata?) */
1204 flush_immediate
= true;
1206 /* A number of jobs are batched -- this must be linked and cleared */
1207 panfrost_link_jobs(ctx
);
1209 ctx
->draw_count
= 0;
1210 ctx
->vertex_job_count
= 0;
1211 ctx
->tiler_job_count
= 0;
1215 bool is_scanout
= panfrost_is_scanout(ctx
);
1216 int fragment_id
= screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1218 /* If visual, we can stall a frame */
1220 if (!flush_immediate
)
1221 screen
->driver
->force_flush_fragment(ctx
, fence
);
1223 screen
->last_fragment_id
= fragment_id
;
1224 screen
->last_fragment_flushed
= false;
1226 /* If readback, flush now (hurts the pipelined performance) */
1227 if (flush_immediate
)
1228 screen
->driver
->force_flush_fragment(ctx
, fence
);
1230 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1231 screen
->driver
->dump_counters(screen
);
1234 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1235 FILE *fp
= fopen(filename
, "wb");
1236 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1245 struct pipe_context
*pipe
,
1246 struct pipe_fence_handle
**fence
,
1249 struct panfrost_context
*ctx
= pan_context(pipe
);
1250 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1252 /* Nothing to do! */
1253 if (!ctx
->draw_count
&& !job
->clear
) return;
1255 /* Whether to stall the pipeline for immediately correct results */
1256 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1258 /* Submit the frame itself */
1259 panfrost_submit_frame(ctx
, flush_immediate
, fence
);
1261 /* Prepare for the next frame */
1262 panfrost_invalidate_frame(ctx
);
1265 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1268 g2m_draw_mode(enum pipe_prim_type mode
)
1271 DEFINE_CASE(POINTS
);
1273 DEFINE_CASE(LINE_LOOP
);
1274 DEFINE_CASE(LINE_STRIP
);
1275 DEFINE_CASE(TRIANGLES
);
1276 DEFINE_CASE(TRIANGLE_STRIP
);
1277 DEFINE_CASE(TRIANGLE_FAN
);
1279 DEFINE_CASE(QUAD_STRIP
);
1280 DEFINE_CASE(POLYGON
);
1283 DBG("Illegal draw mode %d\n", mode
);
1285 return MALI_LINE_LOOP
;
1292 panfrost_translate_index_size(unsigned size
)
1296 return MALI_DRAW_INDEXED_UINT8
;
1299 return MALI_DRAW_INDEXED_UINT16
;
1302 return MALI_DRAW_INDEXED_UINT32
;
1305 DBG("Unknown index size %d\n", size
);
1311 static const uint8_t *
1312 panfrost_get_index_buffer_raw(const struct pipe_draw_info
*info
)
1314 if (info
->has_user_indices
) {
1315 return (const uint8_t *) info
->index
.user
;
1317 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1318 return (const uint8_t *) rsrc
->bo
->cpu
[0];
1322 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1323 * good for the duration of the draw (transient), could last longer */
1326 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1328 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1330 off_t offset
= info
->start
* info
->index_size
;
1332 if (!info
->has_user_indices
) {
1333 /* Only resources can be directly mapped */
1334 return rsrc
->bo
->gpu
[0] + offset
;
1336 /* Otherwise, we need to upload to transient memory */
1337 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1338 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1342 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1343 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1344 T idx = buffer[_idx]; \
1345 if (idx > max_index) max_index = idx; \
1346 if (idx < min_index) min_index = idx; \
1351 struct pipe_context
*pipe
,
1352 const struct pipe_draw_info
*info
)
1354 struct panfrost_context
*ctx
= pan_context(pipe
);
1356 ctx
->payload_vertex
.draw_start
= info
->start
;
1357 ctx
->payload_tiler
.draw_start
= info
->start
;
1359 int mode
= info
->mode
;
1361 /* Fallback for unsupported modes */
1363 if (!(ctx
->draw_modes
& mode
)) {
1364 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1365 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1367 if (info
->count
< 4) {
1368 /* Degenerate case? */
1372 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1373 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1378 /* Now that we have a guaranteed terminating path, find the job.
1379 * Assignment commented out to prevent unused warning */
1381 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1383 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1385 ctx
->vertex_count
= info
->count
;
1387 /* For non-indexed draws, they're the same */
1388 unsigned invocation_count
= ctx
->vertex_count
;
1390 /* For higher amounts of vertices (greater than what fits in a 16-bit
1391 * short), the other value is needed, otherwise there will be bizarre
1392 * rendering artefacts. It's not clear what these values mean yet. */
1394 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~(0x3000 | 0x18000);
1395 ctx
->payload_tiler
.prefix
.unknown_draw
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1397 if (info
->index_size
) {
1398 /* Calculate the min/max index used so we can figure out how
1399 * many times to invoke the vertex shader */
1401 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1403 int min_index
= INT_MAX
;
1406 if (info
->index_size
== 1) {
1407 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8
, info
->start
, info
->count
);
1408 } else if (info
->index_size
== 2) {
1409 const uint16_t *ibuf16
= (const uint16_t *) ibuf8
;
1410 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16
, info
->start
, info
->count
);
1411 } else if (info
->index_size
== 4) {
1412 const uint32_t *ibuf32
= (const uint32_t *) ibuf8
;
1413 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32
, info
->start
, info
->count
);
1418 /* Make sure we didn't go crazy */
1419 assert(min_index
< INT_MAX
);
1420 assert(max_index
> 0);
1421 assert(max_index
> min_index
);
1423 /* Use the corresponding values */
1424 invocation_count
= max_index
- min_index
+ 1;
1425 ctx
->payload_vertex
.draw_start
= min_index
;
1426 ctx
->payload_tiler
.draw_start
= min_index
;
1428 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1429 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1431 //assert(!info->restart_index); /* TODO: Research */
1432 assert(!info
->index_bias
);
1433 //assert(!info->min_index); /* TODO: Use value */
1435 ctx
->payload_tiler
.prefix
.unknown_draw
|= panfrost_translate_index_size(info
->index_size
);
1436 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1438 /* Index count == vertex count, if no indexing is applied, as
1439 * if it is internally indexed in the expected order */
1441 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1442 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1444 /* Reverse index state */
1445 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~MALI_DRAW_INDEXED_UINT32
;
1446 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1449 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1450 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1452 /* Fire off the draw itself */
1453 panfrost_queue_draw(ctx
);
1459 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1465 panfrost_set_scissor(struct panfrost_context
*ctx
)
1467 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1469 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
&& 0) {
1470 ctx
->viewport
->viewport0
[0] = ss
->minx
;
1471 ctx
->viewport
->viewport0
[1] = ss
->miny
;
1472 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1473 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ss
->maxy
);
1475 ctx
->viewport
->viewport0
[0] = 0;
1476 ctx
->viewport
->viewport0
[1] = 0;
1477 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ctx
->pipe_framebuffer
.width
);
1478 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ctx
->pipe_framebuffer
.height
);
1483 panfrost_create_rasterizer_state(
1484 struct pipe_context
*pctx
,
1485 const struct pipe_rasterizer_state
*cso
)
1487 struct panfrost_context
*ctx
= pan_context(pctx
);
1488 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1492 /* Bitmask, unknown meaning of the start value */
1493 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1495 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1496 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1498 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1499 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1501 if (cso
->cull_face
& PIPE_FACE_BACK
)
1502 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1508 panfrost_bind_rasterizer_state(
1509 struct pipe_context
*pctx
,
1512 struct panfrost_context
*ctx
= pan_context(pctx
);
1513 struct pipe_rasterizer_state
*cso
= hwcso
;
1515 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1519 /* If scissor test has changed, we'll need to update that now */
1520 bool update_scissor
= !ctx
->rasterizer
|| ctx
->rasterizer
->base
.scissor
!= cso
->scissor
;
1522 ctx
->rasterizer
= hwcso
;
1524 /* Actualise late changes */
1526 panfrost_set_scissor(ctx
);
1528 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1532 panfrost_create_vertex_elements_state(
1533 struct pipe_context
*pctx
,
1534 unsigned num_elements
,
1535 const struct pipe_vertex_element
*elements
)
1537 struct panfrost_context
*ctx
= pan_context(pctx
);
1538 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1540 so
->num_elements
= num_elements
;
1541 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1543 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_attr_meta
) * num_elements
, HEAP_DESCRIPTOR
);
1544 so
->hw
= (struct mali_attr_meta
*) transfer
.cpu
;
1545 so
->descriptor_ptr
= transfer
.gpu
;
1547 /* Allocate memory for the descriptor state */
1549 for (int i
= 0; i
< num_elements
; ++i
) {
1550 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1552 enum pipe_format fmt
= elements
[i
].src_format
;
1553 const struct util_format_description
*desc
= util_format_description(fmt
);
1554 so
->hw
[i
].unknown1
= 0x2;
1555 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1557 so
->hw
[i
].format
= panfrost_find_format(desc
);
1559 /* The field itself should probably be shifted over */
1560 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1567 panfrost_bind_vertex_elements_state(
1568 struct pipe_context
*pctx
,
1571 struct panfrost_context
*ctx
= pan_context(pctx
);
1573 ctx
->vertex
= hwcso
;
1574 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1578 panfrost_delete_vertex_elements_state(struct pipe_context
*pctx
, void *hwcso
)
1580 struct panfrost_vertex_state
*so
= (struct panfrost_vertex_state
*) hwcso
;
1581 unsigned bytes
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
1582 DBG("Vertex elements delete leaks descriptor (%d bytes)\n", bytes
);
1587 panfrost_create_shader_state(
1588 struct pipe_context
*pctx
,
1589 const struct pipe_shader_state
*cso
)
1591 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1594 /* Token deep copy to prevent memory corruption */
1596 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1597 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1603 panfrost_delete_shader_state(
1604 struct pipe_context
*pctx
,
1607 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1609 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1610 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1613 unsigned leak
= cso
->variant_count
* sizeof(struct mali_shader_meta
);
1614 DBG("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak
);
1620 panfrost_create_sampler_state(
1621 struct pipe_context
*pctx
,
1622 const struct pipe_sampler_state
*cso
)
1624 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1627 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1629 struct mali_sampler_descriptor sampler_descriptor
= {
1630 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1631 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1632 | translate_mip_filter(cso
->min_mip_filter
)
1635 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1636 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1637 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1638 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1640 cso
->border_color
.f
[0],
1641 cso
->border_color
.f
[1],
1642 cso
->border_color
.f
[2],
1643 cso
->border_color
.f
[3]
1645 .min_lod
= FIXED_16(0.0),
1646 .max_lod
= FIXED_16(31.0),
1650 so
->hw
= sampler_descriptor
;
1656 panfrost_bind_sampler_states(
1657 struct pipe_context
*pctx
,
1658 enum pipe_shader_type shader
,
1659 unsigned start_slot
, unsigned num_sampler
,
1662 assert(start_slot
== 0);
1664 struct panfrost_context
*ctx
= pan_context(pctx
);
1666 /* XXX: Should upload, not just copy? */
1667 ctx
->sampler_count
[shader
] = num_sampler
;
1668 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1670 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1674 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1676 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1678 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1679 /* Make sure enable state is at least the same */
1680 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1684 /* Check that the contents of the test are the same */
1685 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1686 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1688 if (!(same_func
&& same_ref
)) {
1692 /* Otherwise, we're good to go */
1697 panfrost_bind_fs_state(
1698 struct pipe_context
*pctx
,
1701 struct panfrost_context
*ctx
= pan_context(pctx
);
1706 /* Match the appropriate variant */
1708 signed variant
= -1;
1710 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1712 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1713 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
1719 if (variant
== -1) {
1720 /* No variant matched, so create a new one */
1721 variant
= variants
->variant_count
++;
1722 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1724 variants
->variants
[variant
].base
= hwcso
;
1725 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1727 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
1728 struct panfrost_context
*ctx
= pan_context(pctx
);
1729 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1731 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1732 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1736 /* Select this variant */
1737 variants
->active_variant
= variant
;
1739 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1740 assert(panfrost_variant_matches(ctx
, shader_state
));
1742 /* Now we have a variant selected, so compile and go */
1744 if (!shader_state
->compiled
) {
1745 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
1746 shader_state
->compiled
= true;
1750 ctx
->dirty
|= PAN_DIRTY_FS
;
1754 panfrost_bind_vs_state(
1755 struct pipe_context
*pctx
,
1758 struct panfrost_context
*ctx
= pan_context(pctx
);
1763 if (!ctx
->vs
->variants
[0].compiled
) {
1764 ctx
->vs
->variants
[0].base
= hwcso
;
1766 /* TODO DRY from above */
1767 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1768 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1769 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
1771 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
1772 ctx
->vs
->variants
[0].compiled
= true;
1776 ctx
->dirty
|= PAN_DIRTY_VS
;
1780 panfrost_set_vertex_buffers(
1781 struct pipe_context
*pctx
,
1782 unsigned start_slot
,
1783 unsigned num_buffers
,
1784 const struct pipe_vertex_buffer
*buffers
)
1786 struct panfrost_context
*ctx
= pan_context(pctx
);
1787 assert(num_buffers
<= PIPE_MAX_ATTRIBS
);
1789 /* XXX: Dirty tracking? etc */
1791 size_t sz
= sizeof(buffers
[0]) * num_buffers
;
1792 ctx
->vertex_buffers
= malloc(sz
);
1793 ctx
->vertex_buffer_count
= num_buffers
;
1794 memcpy(ctx
->vertex_buffers
, buffers
, sz
);
1796 if (ctx
->vertex_buffers
) {
1797 free(ctx
->vertex_buffers
);
1798 ctx
->vertex_buffers
= NULL
;
1801 ctx
->vertex_buffer_count
= 0;
1806 panfrost_set_constant_buffer(
1807 struct pipe_context
*pctx
,
1808 enum pipe_shader_type shader
, uint index
,
1809 const struct pipe_constant_buffer
*buf
)
1811 struct panfrost_context
*ctx
= pan_context(pctx
);
1812 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1814 size_t sz
= buf
? buf
->buffer_size
: 0;
1816 /* Free previous buffer */
1823 pbuf
->buffer
= NULL
;
1826 /* If unbinding, we're done */
1831 /* Multiple constant buffers not yet supported */
1836 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1839 cpu
= rsrc
->bo
->cpu
[0];
1840 } else if (buf
->user_buffer
) {
1841 cpu
= buf
->user_buffer
;
1843 DBG("No constant buffer?\n");
1847 /* Copy the constant buffer into the driver context for later upload */
1849 pbuf
->buffer
= malloc(sz
);
1850 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1854 panfrost_set_stencil_ref(
1855 struct pipe_context
*pctx
,
1856 const struct pipe_stencil_ref
*ref
)
1858 struct panfrost_context
*ctx
= pan_context(pctx
);
1859 ctx
->stencil_ref
= *ref
;
1861 /* Shader core dirty */
1862 ctx
->dirty
|= PAN_DIRTY_FS
;
1865 static struct pipe_sampler_view
*
1866 panfrost_create_sampler_view(
1867 struct pipe_context
*pctx
,
1868 struct pipe_resource
*texture
,
1869 const struct pipe_sampler_view
*template)
1871 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1872 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1874 pipe_reference(NULL
, &texture
->reference
);
1876 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1878 so
->base
= *template;
1879 so
->base
.texture
= texture
;
1880 so
->base
.reference
.count
= 1;
1881 so
->base
.context
= pctx
;
1883 /* sampler_views correspond to texture descriptors, minus the texture
1884 * (data) itself. So, we serialise the descriptor here and cache it for
1887 /* TODO: Other types of textures */
1888 assert(template->target
== PIPE_TEXTURE_2D
);
1890 /* Make sure it's something with which we're familiar */
1891 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1893 /* TODO: Detect from format better */
1894 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1896 unsigned char user_swizzle
[4] = {
1897 template->swizzle_r
,
1898 template->swizzle_g
,
1899 template->swizzle_b
,
1903 enum mali_format format
= panfrost_find_format(desc
);
1905 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
1907 unsigned usage2_layout
= 0x10;
1909 switch (prsrc
->bo
->layout
) {
1911 usage2_layout
|= 0x8 | 0x4;
1914 usage2_layout
|= 0x1;
1917 usage2_layout
|= is_depth
? 0x1 : 0x2;
1924 struct mali_texture_descriptor texture_descriptor
= {
1925 .width
= MALI_POSITIVE(texture
->width0
),
1926 .height
= MALI_POSITIVE(texture
->height0
),
1927 .depth
= MALI_POSITIVE(texture
->depth0
),
1931 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
1935 .is_not_cubemap
= 1,
1937 .usage2
= usage2_layout
1940 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
1943 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
1944 assert (template->u
.tex
.first_level
== 0);
1946 texture_descriptor
.nr_mipmap_levels
= template->u
.tex
.last_level
- template->u
.tex
.first_level
;
1948 so
->hw
= texture_descriptor
;
1950 return (struct pipe_sampler_view
*) so
;
1954 panfrost_set_sampler_views(
1955 struct pipe_context
*pctx
,
1956 enum pipe_shader_type shader
,
1957 unsigned start_slot
, unsigned num_views
,
1958 struct pipe_sampler_view
**views
)
1960 struct panfrost_context
*ctx
= pan_context(pctx
);
1962 assert(start_slot
== 0);
1964 ctx
->sampler_view_count
[shader
] = num_views
;
1965 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
1967 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
1971 panfrost_sampler_view_destroy(
1972 struct pipe_context
*pctx
,
1973 struct pipe_sampler_view
*views
)
1975 //struct panfrost_context *ctx = pan_context(pctx);
1983 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
1984 const struct pipe_framebuffer_state
*fb
)
1986 struct panfrost_context
*ctx
= pan_context(pctx
);
1988 /* Flush when switching away from an FBO */
1990 if (!panfrost_is_scanout(ctx
)) {
1991 panfrost_flush(pctx
, NULL
, 0);
1994 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
1995 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
1996 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
1997 ctx
->pipe_framebuffer
.width
= fb
->width
;
1998 ctx
->pipe_framebuffer
.height
= fb
->height
;
2000 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2001 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2003 /* check if changing cbuf */
2004 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2006 if (cb
&& (i
!= 0)) {
2007 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2012 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2017 if (ctx
->require_sfbd
)
2018 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2020 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2022 panfrost_attach_vt_framebuffer(ctx
);
2023 panfrost_set_scissor(ctx
);
2025 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2026 bool is_scanout
= panfrost_is_scanout(ctx
);
2028 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
) {
2029 /* The blob is aggressive about enabling AFBC. As such,
2030 * it's pretty much necessary to use it here, since we
2031 * have no traces of non-compressed FBO. */
2033 panfrost_enable_afbc(ctx
, tex
, false);
2036 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2037 /* Enable transaction elimination if we can */
2038 panfrost_enable_checksum(ctx
, tex
);
2043 struct pipe_surface
*zb
= fb
->zsbuf
;
2045 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2046 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2051 if (ctx
->require_sfbd
)
2052 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2054 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2056 panfrost_attach_vt_framebuffer(ctx
);
2057 panfrost_set_scissor(ctx
);
2059 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
);
2061 if (tex
->bo
->layout
!= PAN_AFBC
&& !panfrost_is_scanout(ctx
))
2062 panfrost_enable_afbc(ctx
, tex
, true);
2069 panfrost_create_blend_state(struct pipe_context
*pipe
,
2070 const struct pipe_blend_state
*blend
)
2072 struct panfrost_context
*ctx
= pan_context(pipe
);
2073 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2076 /* TODO: The following features are not yet implemented */
2077 assert(!blend
->logicop_enable
);
2078 assert(!blend
->alpha_to_coverage
);
2079 assert(!blend
->alpha_to_one
);
2081 /* Compile the blend state, first as fixed-function if we can */
2083 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], &so
->equation
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2086 /* If we can't, compile a blend shader instead */
2088 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2094 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2097 struct panfrost_context
*ctx
= pan_context(pipe
);
2098 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2099 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2100 ctx
->blend
= pblend
;
2105 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2107 /* TODO: Attach color */
2109 /* Shader itself is not dirty, but the shader core is */
2110 ctx
->dirty
|= PAN_DIRTY_FS
;
2114 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2117 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2119 if (so
->has_blend_shader
) {
2120 DBG("Deleting blend state leak blend shaders bytecode\n");
2127 panfrost_set_blend_color(struct pipe_context
*pipe
,
2128 const struct pipe_blend_color
*blend_color
)
2130 struct panfrost_context
*ctx
= pan_context(pipe
);
2132 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2135 ctx
->blend_color
= *blend_color
;
2137 /* The blend mode depends on the blend constant color, due to the
2138 * fixed/programmable split. So, we're forced to regenerate the blend
2141 /* TODO: Attach color */
2146 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2147 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2149 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2153 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2156 struct panfrost_context
*ctx
= pan_context(pipe
);
2157 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2158 ctx
->depth_stencil
= depth_stencil
;
2163 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2164 * emulated in the fragment shader */
2166 if (depth_stencil
->alpha
.enabled
) {
2167 /* We need to trigger a new shader (maybe) */
2168 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2172 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2174 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2175 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2177 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2178 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2180 /* Depth state (TODO: Refactor) */
2181 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2183 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2185 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2186 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2188 /* Bounds test not implemented */
2189 assert(!depth_stencil
->depth
.bounds_test
);
2191 ctx
->dirty
|= PAN_DIRTY_FS
;
2195 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2201 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2202 unsigned sample_mask
)
2207 panfrost_set_clip_state(struct pipe_context
*pipe
,
2208 const struct pipe_clip_state
*clip
)
2210 //struct panfrost_context *panfrost = pan_context(pipe);
2214 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2215 unsigned start_slot
,
2216 unsigned num_viewports
,
2217 const struct pipe_viewport_state
*viewports
)
2219 struct panfrost_context
*ctx
= pan_context(pipe
);
2221 assert(start_slot
== 0);
2222 assert(num_viewports
== 1);
2224 ctx
->pipe_viewport
= *viewports
;
2227 /* TODO: What if not centered? */
2228 float w
= abs(viewports
->scale
[0]) * 2.0;
2229 float h
= abs(viewports
->scale
[1]) * 2.0;
2231 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2232 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2237 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2238 unsigned start_slot
,
2239 unsigned num_scissors
,
2240 const struct pipe_scissor_state
*scissors
)
2242 struct panfrost_context
*ctx
= pan_context(pipe
);
2244 assert(start_slot
== 0);
2245 assert(num_scissors
== 1);
2247 ctx
->scissor
= *scissors
;
2249 panfrost_set_scissor(ctx
);
2253 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2254 const struct pipe_poly_stipple
*stipple
)
2256 //struct panfrost_context *panfrost = pan_context(pipe);
2260 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2263 //struct panfrost_context *panfrost = pan_context(pipe);
2267 panfrost_destroy(struct pipe_context
*pipe
)
2269 struct panfrost_context
*panfrost
= pan_context(pipe
);
2270 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2272 if (panfrost
->blitter
)
2273 util_blitter_destroy(panfrost
->blitter
);
2275 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2276 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2277 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2278 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2279 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2282 static struct pipe_query
*
2283 panfrost_create_query(struct pipe_context
*pipe
,
2287 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2292 return (struct pipe_query
*) q
;
2296 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2302 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2304 struct panfrost_context
*ctx
= pan_context(pipe
);
2305 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2307 switch (query
->type
) {
2308 case PIPE_QUERY_OCCLUSION_COUNTER
:
2309 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2310 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2312 /* Allocate a word for the query results to be stored */
2313 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2315 ctx
->occlusion_query
= query
;
2321 DBG("Skipping query %d\n", query
->type
);
2329 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2331 struct panfrost_context
*ctx
= pan_context(pipe
);
2332 ctx
->occlusion_query
= NULL
;
2337 panfrost_get_query_result(struct pipe_context
*pipe
,
2338 struct pipe_query
*q
,
2340 union pipe_query_result
*vresult
)
2343 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2345 /* We need to flush out the jobs to actually run the counter, TODO
2346 * check wait, TODO wallpaper after if needed */
2348 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2350 switch (query
->type
) {
2351 case PIPE_QUERY_OCCLUSION_COUNTER
:
2352 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2353 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2354 /* Read back the query results */
2355 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2356 unsigned passed
= *result
;
2358 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2359 vresult
->u64
= passed
;
2361 vresult
->b
= !!passed
;
2367 DBG("Skipped query get %d\n", query
->type
);
2375 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2377 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2378 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2380 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2381 /* Allocate the beginning of the transient pool */
2382 int entry_size
= (1 << 22); /* 4MB */
2384 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2385 ctx
->transient_pools
[i
].entry_count
= 1;
2387 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2390 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2391 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2392 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2393 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2394 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2398 /* New context creation, which also does hardware initialisation since I don't
2399 * know the better way to structure this :smirk: */
2401 struct pipe_context
*
2402 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2404 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2405 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2406 memset(ctx
, 0, sizeof(*ctx
));
2407 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2410 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2411 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means t76x or less */
2412 ctx
->require_sfbd
= gpu_id
< 0x0750; /* t76x is the first to support MFD */
2414 gallium
->screen
= screen
;
2416 gallium
->destroy
= panfrost_destroy
;
2418 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2420 gallium
->flush
= panfrost_flush
;
2421 gallium
->clear
= panfrost_clear
;
2422 gallium
->draw_vbo
= panfrost_draw_vbo
;
2424 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2425 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2427 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2429 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2430 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2431 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2433 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2434 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2435 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2437 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2438 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2439 gallium
->delete_vertex_elements_state
= panfrost_delete_vertex_elements_state
;
2441 gallium
->create_fs_state
= panfrost_create_shader_state
;
2442 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2443 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2445 gallium
->create_vs_state
= panfrost_create_shader_state
;
2446 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2447 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2449 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2450 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2451 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2453 gallium
->create_blend_state
= panfrost_create_blend_state
;
2454 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2455 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2457 gallium
->set_blend_color
= panfrost_set_blend_color
;
2459 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2460 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2461 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2463 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2465 gallium
->set_clip_state
= panfrost_set_clip_state
;
2466 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2467 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2468 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2469 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2471 gallium
->create_query
= panfrost_create_query
;
2472 gallium
->destroy_query
= panfrost_destroy_query
;
2473 gallium
->begin_query
= panfrost_begin_query
;
2474 gallium
->end_query
= panfrost_end_query
;
2475 gallium
->get_query_result
= panfrost_get_query_result
;
2477 panfrost_resource_context_init(gallium
);
2479 pscreen
->driver
->init_context(ctx
);
2481 panfrost_setup_hardware(ctx
);
2484 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2485 gallium
->const_uploader
= gallium
->stream_uploader
;
2486 assert(gallium
->stream_uploader
);
2488 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2489 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2491 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2493 ctx
->blitter
= util_blitter_create(gallium
);
2494 assert(ctx
->blitter
);
2496 /* Prepare for render! */
2498 panfrost_job_init(ctx
);
2499 panfrost_emit_vertex_payload(ctx
);
2500 panfrost_emit_tiler_payload(ctx
);
2501 panfrost_invalidate_frame(ctx
);
2502 panfrost_viewport(ctx
, 0.0, 1.0, 0, 0, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
2503 panfrost_default_shader_backend(ctx
);
2504 panfrost_generate_space_filler_indices();