2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
50 static int performance_counter_number
= 0;
51 extern const char *pan_counters_base
;
53 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
56 static enum mali_job_type
57 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
60 case PIPE_SHADER_VERTEX
:
61 return JOB_TYPE_VERTEX
;
63 case PIPE_SHADER_FRAGMENT
:
64 /* Note: JOB_TYPE_FRAGMENT is different.
65 * JOB_TYPE_FRAGMENT actually executes the
66 * fragment shader, but JOB_TYPE_TILER is how you
68 return JOB_TYPE_TILER
;
70 case PIPE_SHADER_GEOMETRY
:
71 return JOB_TYPE_GEOMETRY
;
73 case PIPE_SHADER_COMPUTE
:
74 return JOB_TYPE_COMPUTE
;
77 unreachable("Unsupported shader stage");
82 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
84 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
85 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
86 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
87 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
89 /* 8 byte checksum per tile */
90 rsrc
->bo
->checksum_stride
= tile_w
* 8;
91 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
92 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
94 rsrc
->bo
->has_checksum
= true;
97 /* Framebuffer descriptor */
100 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
102 fb
->width
= MALI_POSITIVE(w
);
103 fb
->height
= MALI_POSITIVE(h
);
105 /* No idea why this is needed, but it's how resolution_check is
106 * calculated. It's not clear to us yet why the hardware wants this.
107 * The formula itself was discovered mostly by manual bruteforce and
108 * aggressive algebraic simplification. */
110 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
113 struct mali_single_framebuffer
114 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
116 struct mali_single_framebuffer framebuffer
= {
118 .format
= 0x30000000,
119 .clear_flags
= 0x1000,
120 .unknown_address_0
= ctx
->scratchpad
.gpu
,
121 .unknown_address_1
= ctx
->misc_0
.gpu
,
122 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
124 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
125 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
128 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
133 struct bifrost_framebuffer
134 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
136 struct bifrost_framebuffer framebuffer
= {
137 /* It is not yet clear what tiler_meta means or how it's
138 * calculated, but we can tell the lower 32-bits are a
139 * (monotonically increasing?) function of tile count and
140 * geometry complexity; I suspect it defines a memory size of
141 * some kind? for the tiler. It's really unclear at the
142 * moment... but to add to the confusion, the hardware is happy
143 * enough to accept a zero in this field, so we don't even have
144 * to worry about it right now.
146 * The byte (just after the 32-bit mark) is much more
147 * interesting. The higher nibble I've only ever seen as 0xF,
148 * but the lower one I've seen as 0x0 or 0xF, and it's not
149 * obvious what the difference is. But what -is- obvious is
150 * that when the lower nibble is zero, performance is severely
151 * degraded compared to when the lower nibble is set.
152 * Evidently, that nibble enables some sort of fast path,
153 * perhaps relating to caching or tile flush? Regardless, at
154 * this point there's no clear reason not to set it, aside from
155 * substantially increased memory requirements (of the misc_0
158 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
160 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
161 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
162 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
163 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
168 .rt_count_1
= MALI_POSITIVE(1),
173 /* Corresponds to unknown_address_X of SFBD */
174 .scratchpad
= ctx
->scratchpad
.gpu
,
175 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
177 /* The constant added here is, like the lower word of
178 * tiler_meta, (loosely) another product of framebuffer size
179 * and geometry complexity. It must be sufficiently large for
180 * the tiler_meta fast path to work; if it's too small, there
181 * will be DATA_INVALID_FAULTs. Conversely, it must be less
182 * than the total size of misc_0, or else there's no room. It's
183 * possible this constant configures a partition between two
184 * parts of misc_0? We haven't investigated the functionality,
185 * as these buffers are internally used by the hardware
186 * (presumably by the tiler) but not seemingly touched by the driver
189 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
191 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
192 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
198 /* Are we currently rendering to the screen (rather than an FBO)? */
201 panfrost_is_scanout(struct panfrost_context
*ctx
)
203 /* If there is no color buffer, it's an FBO */
204 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
207 /* If we're too early that no framebuffer was sent, it's scanout */
208 if (!ctx
->pipe_framebuffer
.cbufs
[0])
211 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
212 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
213 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
217 pan_pack_color(const union pipe_color_union
*color
, enum pipe_format format
)
219 /* Alpha magicked to 1.0 if there is no alpha */
221 bool has_alpha
= util_format_has_alpha(format
);
222 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
224 /* Packed color depends on the framebuffer format */
226 const struct util_format_description
*desc
=
227 util_format_description(format
);
229 if (util_format_is_rgba8_variant(desc
)) {
230 return (float_to_ubyte(clear_alpha
) << 24) |
231 (float_to_ubyte(color
->f
[2]) << 16) |
232 (float_to_ubyte(color
->f
[1]) << 8) |
233 (float_to_ubyte(color
->f
[0]) << 0);
234 } else if (format
== PIPE_FORMAT_B5G6R5_UNORM
) {
235 /* First, we convert the components to R5, G6, B5 separately */
236 unsigned r5
= CLAMP(color
->f
[0], 0.0, 1.0) * 31.0;
237 unsigned g6
= CLAMP(color
->f
[1], 0.0, 1.0) * 63.0;
238 unsigned b5
= CLAMP(color
->f
[2], 0.0, 1.0) * 31.0;
240 /* Then we pack into a sparse u32. TODO: Why these shifts? */
241 return (b5
<< 25) | (g6
<< 14) | (r5
<< 5);
252 struct pipe_context
*pipe
,
254 const union pipe_color_union
*color
,
255 double depth
, unsigned stencil
)
257 struct panfrost_context
*ctx
= pan_context(pipe
);
258 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
260 if (buffers
& PIPE_CLEAR_COLOR
) {
261 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[0]->format
;
262 job
->clear_color
= pan_pack_color(color
, format
);
265 if (buffers
& PIPE_CLEAR_DEPTH
) {
266 job
->clear_depth
= depth
;
269 if (buffers
& PIPE_CLEAR_STENCIL
) {
270 job
->clear_stencil
= stencil
;
273 job
->clear
|= buffers
;
277 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
279 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
283 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
285 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
289 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
291 mali_ptr framebuffer
= ctx
->require_sfbd
?
292 panfrost_attach_vt_sfbd(ctx
) :
293 panfrost_attach_vt_mfbd(ctx
);
295 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
296 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
299 /* Reset per-frame context, called on context initialisation as well as after
300 * flushing a frame */
303 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
305 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
306 DBG("Uploaded transient %d bytes\n", transient_count
);
308 /* Rotate cmdstream */
309 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
310 ctx
->cmdstream_i
= 0;
312 if (ctx
->require_sfbd
)
313 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
315 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
317 /* Reset varyings allocated */
318 ctx
->varying_height
= 0;
320 /* The transient cmdstream is dirty every frame; the only bits worth preserving
321 * (textures, shaders, etc) are in other buffers anyways */
323 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
324 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
326 /* Regenerate payloads */
327 panfrost_attach_vt_framebuffer(ctx
);
330 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
333 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
335 /* Reset job counters */
337 ctx
->vertex_job_count
= 0;
338 ctx
->tiler_job_count
= 0;
341 /* In practice, every field of these payloads should be configurable
342 * arbitrarily, which means these functions are basically catch-all's for
343 * as-of-yet unwavering unknowns */
346 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
348 struct midgard_payload_vertex_tiler payload
= {
350 .workgroups_z_shift
= 32,
351 .workgroups_x_shift_2
= 0x2,
352 .workgroups_x_shift_3
= 0x5,
354 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
357 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
361 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
363 struct midgard_payload_vertex_tiler payload
= {
365 .workgroups_z_shift
= 32,
366 .workgroups_x_shift_2
= 0x2,
367 .workgroups_x_shift_3
= 0x6,
369 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
373 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
377 translate_tex_wrap(enum pipe_tex_wrap w
)
380 case PIPE_TEX_WRAP_REPEAT
:
381 return MALI_WRAP_REPEAT
;
383 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
384 return MALI_WRAP_CLAMP_TO_EDGE
;
386 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
387 return MALI_WRAP_CLAMP_TO_BORDER
;
389 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
390 return MALI_WRAP_MIRRORED_REPEAT
;
393 unreachable("Invalid wrap");
398 translate_tex_filter(enum pipe_tex_filter f
)
401 case PIPE_TEX_FILTER_NEAREST
:
404 case PIPE_TEX_FILTER_LINEAR
:
408 unreachable("Invalid filter");
413 translate_mip_filter(enum pipe_tex_mipfilter f
)
415 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
419 panfrost_translate_compare_func(enum pipe_compare_func in
)
422 case PIPE_FUNC_NEVER
:
423 return MALI_FUNC_NEVER
;
426 return MALI_FUNC_LESS
;
428 case PIPE_FUNC_EQUAL
:
429 return MALI_FUNC_EQUAL
;
431 case PIPE_FUNC_LEQUAL
:
432 return MALI_FUNC_LEQUAL
;
434 case PIPE_FUNC_GREATER
:
435 return MALI_FUNC_GREATER
;
437 case PIPE_FUNC_NOTEQUAL
:
438 return MALI_FUNC_NOTEQUAL
;
440 case PIPE_FUNC_GEQUAL
:
441 return MALI_FUNC_GEQUAL
;
443 case PIPE_FUNC_ALWAYS
:
444 return MALI_FUNC_ALWAYS
;
447 unreachable("Invalid func");
452 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
455 case PIPE_FUNC_NEVER
:
456 return MALI_ALT_FUNC_NEVER
;
459 return MALI_ALT_FUNC_LESS
;
461 case PIPE_FUNC_EQUAL
:
462 return MALI_ALT_FUNC_EQUAL
;
464 case PIPE_FUNC_LEQUAL
:
465 return MALI_ALT_FUNC_LEQUAL
;
467 case PIPE_FUNC_GREATER
:
468 return MALI_ALT_FUNC_GREATER
;
470 case PIPE_FUNC_NOTEQUAL
:
471 return MALI_ALT_FUNC_NOTEQUAL
;
473 case PIPE_FUNC_GEQUAL
:
474 return MALI_ALT_FUNC_GEQUAL
;
476 case PIPE_FUNC_ALWAYS
:
477 return MALI_ALT_FUNC_ALWAYS
;
480 unreachable("Invalid alt func");
485 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
488 case PIPE_STENCIL_OP_KEEP
:
489 return MALI_STENCIL_KEEP
;
491 case PIPE_STENCIL_OP_ZERO
:
492 return MALI_STENCIL_ZERO
;
494 case PIPE_STENCIL_OP_REPLACE
:
495 return MALI_STENCIL_REPLACE
;
497 case PIPE_STENCIL_OP_INCR
:
498 return MALI_STENCIL_INCR
;
500 case PIPE_STENCIL_OP_DECR
:
501 return MALI_STENCIL_DECR
;
503 case PIPE_STENCIL_OP_INCR_WRAP
:
504 return MALI_STENCIL_INCR_WRAP
;
506 case PIPE_STENCIL_OP_DECR_WRAP
:
507 return MALI_STENCIL_DECR_WRAP
;
509 case PIPE_STENCIL_OP_INVERT
:
510 return MALI_STENCIL_INVERT
;
513 unreachable("Invalid stencil op");
518 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
520 out
->ref
= 0; /* Gallium gets it from elsewhere */
522 out
->mask
= in
->valuemask
;
523 out
->func
= panfrost_translate_compare_func(in
->func
);
524 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
525 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
526 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
530 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
532 struct mali_shader_meta shader
= {
533 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
535 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
536 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
540 shader
.unknown2_4
|= 0x10;
543 struct pipe_stencil_state default_stencil
= {
545 .func
= PIPE_FUNC_ALWAYS
,
546 .fail_op
= MALI_STENCIL_KEEP
,
547 .zfail_op
= MALI_STENCIL_KEEP
,
548 .zpass_op
= MALI_STENCIL_KEEP
,
553 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
554 shader
.stencil_mask_front
= default_stencil
.writemask
;
556 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
557 shader
.stencil_mask_back
= default_stencil
.writemask
;
559 if (default_stencil
.enabled
)
560 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
562 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
566 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
568 if (first
->job_descriptor_size
)
569 first
->next_job_64
= (u64
) (uintptr_t) next
;
571 first
->next_job_32
= (u32
) (uintptr_t) next
;
574 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
575 * graphics command stream. It should be called once per draw, accordding to
576 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
577 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
580 struct panfrost_transfer
581 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
583 /* Each draw call corresponds to two jobs, and the set-value job is first */
584 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
586 struct mali_job_descriptor_header job
= {
587 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
588 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
590 .job_descriptor_size
= 1,
594 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
596 /* There's some padding hacks on 32-bit */
603 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
606 /* Tiler jobs depend on vertex jobs */
608 job
.job_dependency_index_1
= draw_job_index
;
610 /* Tiler jobs also depend on the previous tiler job */
612 if (ctx
->draw_count
) {
613 job
.job_dependency_index_2
= draw_job_index
- 1;
614 /* Previous tiler job points to this tiler job */
615 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
617 /* The only vertex job so far points to first tiler job */
618 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
621 if (ctx
->draw_count
) {
622 /* Previous vertex job points to this vertex job */
623 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
625 /* Last vertex job points to first tiler job */
626 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
628 /* Have the first vertex job depend on the set value job */
629 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
630 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
634 memcpy(transfer
.cpu
, &job
, sizeof(job
));
635 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
639 /* Generates a set value job. It's unclear what exactly this does, why it's
640 * necessary, and when to call it. */
643 panfrost_set_value_job(struct panfrost_context
*ctx
)
645 struct mali_job_descriptor_header job
= {
646 .job_type
= JOB_TYPE_SET_VALUE
,
647 .job_descriptor_size
= 1,
651 struct mali_payload_set_value payload
= {
652 .out
= ctx
->misc_0
.gpu
,
656 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
657 memcpy(transfer
.cpu
, &job
, sizeof(job
));
658 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
660 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
661 ctx
->set_value_job
= transfer
.gpu
;
665 panfrost_emit_varyings(
666 struct panfrost_context
*ctx
,
667 union mali_attr
*slot
,
671 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
673 /* Fill out the descriptor */
674 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
675 slot
->stride
= stride
;
676 slot
->size
= stride
* count
;
678 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
679 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
681 return varying_address
;
685 panfrost_emit_point_coord(union mali_attr
*slot
)
687 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
688 slot
->stride
= slot
->size
= 0;
692 panfrost_emit_varying_descriptor(
693 struct panfrost_context
*ctx
,
694 unsigned invocation_count
)
696 /* Load the shaders */
698 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
699 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
701 /* Allocate the varying descriptor */
703 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
704 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
706 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
709 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
710 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
712 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
713 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
715 /* Buffer indices must be in this order per our convention */
716 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
719 /* General varyings -- use the VS's, since those are more likely to be
720 * accurate on desktop */
722 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
723 vs
->general_varying_stride
, invocation_count
);
725 /* fp32 vec4 gl_Position */
726 ctx
->payload_tiler
.postfix
.position_varying
=
727 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
728 sizeof(float) * 4, invocation_count
);
731 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
732 /* fp16 vec1 gl_PointSize */
733 ctx
->payload_tiler
.primitive_size
.pointer
=
734 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
735 2, invocation_count
);
738 if (fs
->reads_point_coord
) {
739 /* Special descriptor */
740 panfrost_emit_point_coord(&varyings
[idx
++]);
743 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
744 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
745 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
749 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
751 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
752 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
754 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
757 /* Emits attributes and varying descriptors, which should be called every draw,
758 * excepting some obscure circumstances */
761 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
763 /* Staged mali_attr, and index into them. i =/= k, depending on the
764 * vertex buffer mask */
765 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
768 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
770 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
771 if (!(ctx
->vb_mask
& (1 << i
))) continue;
773 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
774 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
778 /* Align to 64 bytes by masking off the lower bits. This
779 * will be adjusted back when we fixup the src_offset in
782 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
784 /* Offset vertex count by draw_start to make sure we upload enough */
785 attrs
[k
].stride
= buf
->stride
;
786 attrs
[k
].size
= rsrc
->base
.width0
;
788 panfrost_job_add_bo(job
, rsrc
->bo
);
789 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
794 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
796 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
800 panfrost_writes_point_size(struct panfrost_context
*ctx
)
803 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
805 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
808 /* Stage the attribute descriptors so we can adjust src_offset
809 * to let BOs align nicely */
812 panfrost_stage_attributes(struct panfrost_context
*ctx
)
814 struct panfrost_vertex_state
*so
= ctx
->vertex
;
816 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
817 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
818 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
820 /* Copy as-is for the first pass */
821 memcpy(target
, so
->hw
, sz
);
823 /* Fixup offsets for the second pass. Recall that the hardware
824 * calculates attribute addresses as:
826 * addr = base + (stride * vtx) + src_offset;
828 * However, on Mali, base must be aligned to 64-bytes, so we
831 * base' = base & ~63 = base - (base & 63)
833 * To compensate when using base' (see emit_vertex_data), we have
834 * to adjust src_offset by the masked off piece:
836 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
837 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
838 * = base + (stride * vtx) + src_offset
844 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
845 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
846 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
848 /* Adjust by the masked off bits of the offset */
849 target
[i
].src_offset
+= (addr
& 63);
852 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
856 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
858 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
860 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
861 if (!ctx
->sampler_count
[t
]) continue;
863 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
865 struct panfrost_transfer transfer
=
866 panfrost_allocate_transient(ctx
, transfer_size
);
868 struct mali_sampler_descriptor
*desc
=
869 (struct mali_sampler_descriptor
*) transfer
.cpu
;
871 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
872 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
874 if (t
== PIPE_SHADER_FRAGMENT
)
875 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
876 else if (t
== PIPE_SHADER_VERTEX
)
877 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
883 /* Computes the address to a texture at a particular slice */
886 panfrost_get_texture_address(
887 struct panfrost_resource
*rsrc
,
888 unsigned level
, unsigned face
)
890 unsigned level_offset
= rsrc
->bo
->slices
[level
].offset
;
891 unsigned face_offset
= face
* rsrc
->bo
->cubemap_stride
;
893 return rsrc
->bo
->gpu
+ level_offset
+ face_offset
;
899 struct panfrost_context
*ctx
,
900 struct panfrost_sampler_view
*view
)
903 return (mali_ptr
) NULL
;
905 struct pipe_resource
*tex_rsrc
= view
->base
.texture
;
906 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
908 /* Do we interleave an explicit stride with every element? */
910 bool has_manual_stride
=
911 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
913 /* Inject the addresses in, interleaving mip levels, cube faces, and
914 * strides in that order */
918 for (unsigned l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
919 for (unsigned f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
920 view
->hw
.payload
[idx
++] =
921 panfrost_get_texture_address(rsrc
, l
, f
);
923 if (has_manual_stride
) {
924 view
->hw
.payload
[idx
++] =
925 rsrc
->bo
->slices
[l
].stride
;
930 return panfrost_upload_transient(ctx
, &view
->hw
,
931 sizeof(struct mali_texture_descriptor
));
935 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
937 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
939 if (!ctx
->sampler_view_count
[t
]) continue;
941 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
943 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
945 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
947 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
949 if (t
== PIPE_SHADER_FRAGMENT
)
950 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
951 else if (t
== PIPE_SHADER_VERTEX
)
952 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
958 /* Go through dirty flags and actualise them in the cmdstream. */
961 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
963 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
965 if (with_vertex_data
) {
966 panfrost_emit_vertex_data(ctx
, job
);
969 bool msaa
= ctx
->rasterizer
->base
.multisample
;
971 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
972 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
974 /* TODO: Sample size */
975 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
976 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
979 /* Enable job requirements at draw-time */
982 job
->requirements
|= PAN_REQ_MSAA
;
984 if (ctx
->depth_stencil
->depth
.writemask
)
985 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
987 if (ctx
->occlusion_query
) {
988 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
989 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
992 if (ctx
->dirty
& PAN_DIRTY_VS
) {
995 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
997 /* Late shader descriptor assignments */
999 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1000 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1003 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1005 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1008 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1009 /* Check if we need to link the gl_PointSize varying */
1010 if (!panfrost_writes_point_size(ctx
)) {
1011 /* If the size is constant, write it out. Otherwise,
1012 * don't touch primitive_size (since we would clobber
1013 * the pointer there) */
1015 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1019 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1021 ctx
->dirty
|= PAN_DIRTY_FS
;
1023 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1025 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1027 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1030 COPY(attribute_count
);
1031 COPY(varying_count
);
1032 COPY(midgard1
.uniform_count
);
1033 COPY(midgard1
.work_count
);
1034 COPY(midgard1
.unknown2
);
1037 /* If there is a blend shader, work registers are shared */
1039 if (ctx
->blend
->has_blend_shader
)
1040 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1042 /* Set late due to depending on render state */
1043 /* The one at the end seems to mean "1 UBO" */
1044 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1046 /* Assign texture/sample count right before upload */
1047 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1048 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1050 /* Assign the stencil refs late */
1051 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1052 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1054 /* CAN_DISCARD should be set if the fragment shader possibly
1055 * contains a 'discard' instruction. It is likely this is
1056 * related to optimizations related to forward-pixel kill, as
1057 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1058 * thing?" by Peter Harris
1061 if (variant
->can_discard
) {
1062 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1063 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1064 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1065 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1068 /* Check if we're using the default blend descriptor (fast path) */
1071 !ctx
->blend
->has_blend_shader
&&
1072 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1073 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1074 (ctx
->blend
->equation
.color_mask
== 0xf);
1076 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1077 * *also* copied to the blend_meta appended (by convention),
1078 * but this is the field actually read by the hardware. (Or
1079 * maybe both are read...?) */
1081 if (ctx
->blend
->has_blend_shader
) {
1082 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1085 if (ctx
->require_sfbd
) {
1086 /* When only a single render target platform is used, the blend
1087 * information is inside the shader meta itself. We
1088 * additionally need to signal CAN_DISCARD for nontrivial blend
1089 * modes (so we're able to read back the destination buffer) */
1091 if (!ctx
->blend
->has_blend_shader
) {
1092 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1093 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1097 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1101 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1102 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1103 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1105 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1107 if (!ctx
->require_sfbd
) {
1108 /* Additional blend descriptor tacked on for jobs using MFBD */
1110 unsigned blend_count
= 0x200;
1112 if (ctx
->blend
->has_blend_shader
) {
1113 /* For a blend shader, the bottom nibble corresponds to
1114 * the number of work registers used, which signals the
1115 * -existence- of a blend shader */
1117 assert(ctx
->blend
->blend_work_count
>= 2);
1118 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1120 /* Otherwise, the bottom bit simply specifies if
1121 * blending (anything other than REPLACE) is enabled */
1128 struct midgard_blend_rt rts
[4];
1132 for (unsigned i
= 0; i
< 1; ++i
) {
1133 rts
[i
].flags
= blend_count
;
1135 if (ctx
->blend
->has_blend_shader
) {
1136 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1138 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1139 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1143 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1147 /* We stage to transient, so always dirty.. */
1148 panfrost_stage_attributes(ctx
);
1150 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1151 panfrost_upload_sampler_descriptors(ctx
);
1153 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1154 panfrost_upload_texture_descriptors(ctx
);
1156 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1158 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1159 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1161 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1162 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1163 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1165 /* Allocate room for the sysval and the uniforms */
1166 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1167 size_t size
= sys_size
+ buf
->size
;
1168 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1170 /* Upload sysvals requested by the shader */
1171 float *uniforms
= (float *) transfer
.cpu
;
1172 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1173 int sysval
= ss
->sysval
[i
];
1175 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1176 uniforms
[4*i
+ 0] = vp
->scale
[0];
1177 uniforms
[4*i
+ 1] = vp
->scale
[1];
1178 uniforms
[4*i
+ 2] = vp
->scale
[2];
1179 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1180 uniforms
[4*i
+ 0] = vp
->translate
[0];
1181 uniforms
[4*i
+ 1] = vp
->translate
[1];
1182 uniforms
[4*i
+ 2] = vp
->translate
[2];
1188 /* Upload uniforms */
1189 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1191 int uniform_count
= 0;
1193 struct mali_vertex_tiler_postfix
*postfix
;
1196 case PIPE_SHADER_VERTEX
:
1197 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1198 postfix
= &ctx
->payload_vertex
.postfix
;
1201 case PIPE_SHADER_FRAGMENT
:
1202 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1203 postfix
= &ctx
->payload_tiler
.postfix
;
1207 unreachable("Invalid shader stage\n");
1210 /* Also attach the same buffer as a UBO for extended access */
1212 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1214 .size
= MALI_POSITIVE((2 + uniform_count
)),
1215 .ptr
= transfer
.gpu
>> 2,
1219 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1220 postfix
->uniforms
= transfer
.gpu
;
1221 postfix
->uniform_buffers
= ubufs
;
1226 /* TODO: Upload the viewport somewhere more appropriate */
1228 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1229 * (somewhat) asymmetric ints. */
1230 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1232 struct mali_viewport view
= {
1233 /* By default, do no viewport clipping, i.e. clip to (-inf,
1234 * inf) in each direction. Clipping to the viewport in theory
1235 * should work, but in practice causes issues when we're not
1236 * explicitly trying to scissor */
1247 /* Always scissor to the viewport by default. */
1248 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1249 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1251 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1252 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1254 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1255 view
.viewport0
[0] = ss
->minx
;
1256 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1262 /* Hardware needs the min/max to be strictly ordered, so flip if we
1270 view
.viewport0
[1] = miny
;
1271 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1273 ctx
->payload_tiler
.postfix
.viewport
=
1274 panfrost_upload_transient(ctx
,
1276 sizeof(struct mali_viewport
));
1281 /* Corresponds to exactly one draw, but does not submit anything */
1284 panfrost_queue_draw(struct panfrost_context
*ctx
)
1286 /* TODO: Expand the array? */
1287 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1288 DBG("Job buffer overflow, ignoring draw\n");
1292 /* Handle dirty flags now */
1293 panfrost_emit_for_draw(ctx
, true);
1295 /* We need a set_value job before any other draw jobs */
1296 if (ctx
->draw_count
== 0)
1297 panfrost_set_value_job(ctx
);
1299 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1300 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1301 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1303 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1304 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1305 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1310 /* The entire frame is in memory -- send it off to the kernel! */
1313 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1314 struct pipe_fence_handle
**fence
,
1315 struct panfrost_job
*job
)
1317 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1318 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1320 /* Edge case if screen is cleared and nothing else */
1321 bool has_draws
= ctx
->draw_count
> 0;
1323 /* Workaround a bizarre lockup (a hardware errata?) */
1325 flush_immediate
= true;
1329 bool is_scanout
= panfrost_is_scanout(ctx
);
1330 screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1332 /* If visual, we can stall a frame */
1334 if (!flush_immediate
)
1335 screen
->driver
->force_flush_fragment(ctx
, fence
);
1337 screen
->last_fragment_flushed
= false;
1338 screen
->last_job
= job
;
1340 /* If readback, flush now (hurts the pipelined performance) */
1341 if (flush_immediate
)
1342 screen
->driver
->force_flush_fragment(ctx
, fence
);
1344 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1345 screen
->driver
->dump_counters(screen
);
1348 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1349 FILE *fp
= fopen(filename
, "wb");
1350 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1358 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1360 struct panfrost_context
*ctx
= pan_context(pipe
);
1362 /* Nothing to reload? */
1363 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1366 /* Blit the wallpaper in */
1367 panfrost_blit_wallpaper(ctx
);
1369 /* We are flushing all queued draws and we know that no more jobs will
1370 * be added until the next frame.
1371 * We also know that the last jobs are the wallpaper jobs, and they
1372 * need to be linked so they execute right after the set_value job.
1375 /* set_value job to wallpaper vertex job */
1376 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1377 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1379 /* wallpaper vertex job to first vertex job */
1380 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1381 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1383 /* last vertex job to wallpaper tiler job */
1384 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1385 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1386 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1388 /* wallpaper tiler job to first tiler job */
1389 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1390 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1391 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1393 /* last tiler job to NULL */
1394 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1399 struct pipe_context
*pipe
,
1400 struct pipe_fence_handle
**fence
,
1403 struct panfrost_context
*ctx
= pan_context(pipe
);
1404 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1406 /* Nothing to do! */
1407 if (!ctx
->draw_count
&& !job
->clear
) return;
1410 panfrost_draw_wallpaper(&ctx
->base
);
1412 /* Whether to stall the pipeline for immediately correct results */
1413 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1415 /* Submit the frame itself */
1416 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1418 /* Prepare for the next frame */
1419 panfrost_invalidate_frame(ctx
);
1422 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1425 g2m_draw_mode(enum pipe_prim_type mode
)
1428 DEFINE_CASE(POINTS
);
1430 DEFINE_CASE(LINE_LOOP
);
1431 DEFINE_CASE(LINE_STRIP
);
1432 DEFINE_CASE(TRIANGLES
);
1433 DEFINE_CASE(TRIANGLE_STRIP
);
1434 DEFINE_CASE(TRIANGLE_FAN
);
1436 DEFINE_CASE(QUAD_STRIP
);
1437 DEFINE_CASE(POLYGON
);
1440 unreachable("Invalid draw mode");
1447 panfrost_translate_index_size(unsigned size
)
1451 return MALI_DRAW_INDEXED_UINT8
;
1454 return MALI_DRAW_INDEXED_UINT16
;
1457 return MALI_DRAW_INDEXED_UINT32
;
1460 unreachable("Invalid index size");
1464 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1465 * good for the duration of the draw (transient), could last longer */
1468 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1470 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1472 off_t offset
= info
->start
* info
->index_size
;
1474 if (!info
->has_user_indices
) {
1475 /* Only resources can be directly mapped */
1476 return rsrc
->bo
->gpu
+ offset
;
1478 /* Otherwise, we need to upload to transient memory */
1479 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1480 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1486 struct pipe_context
*pipe
,
1487 const struct pipe_draw_info
*info
)
1489 struct panfrost_context
*ctx
= pan_context(pipe
);
1491 ctx
->payload_vertex
.draw_start
= info
->start
;
1492 ctx
->payload_tiler
.draw_start
= info
->start
;
1494 int mode
= info
->mode
;
1496 /* Fallback for unsupported modes */
1498 if (!(ctx
->draw_modes
& (1 << mode
))) {
1499 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1500 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1502 if (info
->count
< 4) {
1503 /* Degenerate case? */
1507 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1508 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1513 /* Now that we have a guaranteed terminating path, find the job.
1514 * Assignment commented out to prevent unused warning */
1516 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1518 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1520 ctx
->vertex_count
= info
->count
;
1522 /* For non-indexed draws, they're the same */
1523 unsigned invocation_count
= ctx
->vertex_count
;
1525 unsigned draw_flags
= 0;
1527 /* The draw flags interpret how primitive size is interpreted */
1529 if (panfrost_writes_point_size(ctx
))
1530 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1532 /* For higher amounts of vertices (greater than what fits in a 16-bit
1533 * short), the other value is needed, otherwise there will be bizarre
1534 * rendering artefacts. It's not clear what these values mean yet. */
1536 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1538 if (info
->index_size
) {
1539 /* Calculate the min/max index used so we can figure out how
1540 * many times to invoke the vertex shader */
1542 /* Fetch / calculate index bounds */
1543 unsigned min_index
= 0, max_index
= 0;
1545 if (info
->max_index
== ~0u) {
1546 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1548 min_index
= info
->min_index
;
1549 max_index
= info
->max_index
;
1552 /* Use the corresponding values */
1553 invocation_count
= max_index
- min_index
+ 1;
1554 ctx
->payload_vertex
.draw_start
= min_index
;
1555 ctx
->payload_tiler
.draw_start
= min_index
;
1557 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1558 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1560 //assert(!info->restart_index); /* TODO: Research */
1561 assert(!info
->index_bias
);
1563 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1564 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1566 /* Index count == vertex count, if no indexing is applied, as
1567 * if it is internally indexed in the expected order */
1569 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1570 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1572 /* Reverse index state */
1573 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1576 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1577 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1578 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1580 /* Fire off the draw itself */
1581 panfrost_queue_draw(ctx
);
1587 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1593 panfrost_create_rasterizer_state(
1594 struct pipe_context
*pctx
,
1595 const struct pipe_rasterizer_state
*cso
)
1597 struct panfrost_context
*ctx
= pan_context(pctx
);
1598 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1602 /* Bitmask, unknown meaning of the start value */
1603 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1606 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1608 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1609 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1611 if (cso
->cull_face
& PIPE_FACE_BACK
)
1612 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1618 panfrost_bind_rasterizer_state(
1619 struct pipe_context
*pctx
,
1622 struct panfrost_context
*ctx
= pan_context(pctx
);
1624 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1628 ctx
->rasterizer
= hwcso
;
1629 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1633 panfrost_create_vertex_elements_state(
1634 struct pipe_context
*pctx
,
1635 unsigned num_elements
,
1636 const struct pipe_vertex_element
*elements
)
1638 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1640 so
->num_elements
= num_elements
;
1641 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1643 /* XXX: What the cornball? This is totally, 100%, unapologetically
1644 * nonsense. And yet it somehow fixes a regression in -bshadow
1645 * (previously, we allocated the descriptor here... a newer commit
1646 * removed that allocation, and then memory corruption led to
1647 * shader_meta getting overwritten in bad ways and then the whole test
1648 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1650 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1652 for (int i
= 0; i
< num_elements
; ++i
) {
1653 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1655 enum pipe_format fmt
= elements
[i
].src_format
;
1656 const struct util_format_description
*desc
= util_format_description(fmt
);
1657 so
->hw
[i
].unknown1
= 0x2;
1658 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1660 so
->hw
[i
].format
= panfrost_find_format(desc
);
1662 /* The field itself should probably be shifted over */
1663 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1670 panfrost_bind_vertex_elements_state(
1671 struct pipe_context
*pctx
,
1674 struct panfrost_context
*ctx
= pan_context(pctx
);
1676 ctx
->vertex
= hwcso
;
1677 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1681 panfrost_create_shader_state(
1682 struct pipe_context
*pctx
,
1683 const struct pipe_shader_state
*cso
)
1685 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1688 /* Token deep copy to prevent memory corruption */
1690 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1691 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1697 panfrost_delete_shader_state(
1698 struct pipe_context
*pctx
,
1701 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1703 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1704 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1711 panfrost_create_sampler_state(
1712 struct pipe_context
*pctx
,
1713 const struct pipe_sampler_state
*cso
)
1715 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1718 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1720 struct mali_sampler_descriptor sampler_descriptor
= {
1721 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1722 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1723 | translate_mip_filter(cso
->min_mip_filter
)
1726 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1727 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1728 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1729 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1731 cso
->border_color
.f
[0],
1732 cso
->border_color
.f
[1],
1733 cso
->border_color
.f
[2],
1734 cso
->border_color
.f
[3]
1736 .min_lod
= FIXED_16(cso
->min_lod
),
1737 .max_lod
= FIXED_16(cso
->max_lod
),
1741 so
->hw
= sampler_descriptor
;
1747 panfrost_bind_sampler_states(
1748 struct pipe_context
*pctx
,
1749 enum pipe_shader_type shader
,
1750 unsigned start_slot
, unsigned num_sampler
,
1753 assert(start_slot
== 0);
1755 struct panfrost_context
*ctx
= pan_context(pctx
);
1757 /* XXX: Should upload, not just copy? */
1758 ctx
->sampler_count
[shader
] = num_sampler
;
1759 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1761 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1765 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1767 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1769 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1770 /* Make sure enable state is at least the same */
1771 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1775 /* Check that the contents of the test are the same */
1776 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1777 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1779 if (!(same_func
&& same_ref
)) {
1783 /* Otherwise, we're good to go */
1788 panfrost_bind_shader_state(
1789 struct pipe_context
*pctx
,
1791 enum pipe_shader_type type
)
1793 struct panfrost_context
*ctx
= pan_context(pctx
);
1795 if (type
== PIPE_SHADER_FRAGMENT
) {
1797 ctx
->dirty
|= PAN_DIRTY_FS
;
1800 ctx
->dirty
|= PAN_DIRTY_VS
;
1805 /* Match the appropriate variant */
1807 signed variant
= -1;
1808 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1810 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1811 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
1817 if (variant
== -1) {
1818 /* No variant matched, so create a new one */
1819 variant
= variants
->variant_count
++;
1820 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1822 variants
->variants
[variant
].base
= hwcso
;
1824 if (type
== PIPE_SHADER_FRAGMENT
)
1825 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1827 /* Allocate the mapped descriptor ahead-of-time. */
1828 struct panfrost_context
*ctx
= pan_context(pctx
);
1829 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1831 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1832 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1836 /* Select this variant */
1837 variants
->active_variant
= variant
;
1839 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1840 assert(panfrost_variant_matches(ctx
, shader_state
));
1842 /* We finally have a variant, so compile it */
1844 if (!shader_state
->compiled
) {
1845 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
1846 panfrost_job_type_for_pipe(type
), shader_state
);
1848 shader_state
->compiled
= true;
1853 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
1855 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
1859 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
1861 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
1865 panfrost_set_vertex_buffers(
1866 struct pipe_context
*pctx
,
1867 unsigned start_slot
,
1868 unsigned num_buffers
,
1869 const struct pipe_vertex_buffer
*buffers
)
1871 struct panfrost_context
*ctx
= pan_context(pctx
);
1873 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1877 panfrost_set_constant_buffer(
1878 struct pipe_context
*pctx
,
1879 enum pipe_shader_type shader
, uint index
,
1880 const struct pipe_constant_buffer
*buf
)
1882 struct panfrost_context
*ctx
= pan_context(pctx
);
1883 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1885 size_t sz
= buf
? buf
->buffer_size
: 0;
1887 /* Free previous buffer */
1894 pbuf
->buffer
= NULL
;
1897 /* If unbinding, we're done */
1902 /* Multiple constant buffers not yet supported */
1907 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1910 cpu
= rsrc
->bo
->cpu
;
1911 } else if (buf
->user_buffer
) {
1912 cpu
= buf
->user_buffer
;
1914 DBG("No constant buffer?\n");
1918 /* Copy the constant buffer into the driver context for later upload */
1920 pbuf
->buffer
= malloc(sz
);
1921 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1925 panfrost_set_stencil_ref(
1926 struct pipe_context
*pctx
,
1927 const struct pipe_stencil_ref
*ref
)
1929 struct panfrost_context
*ctx
= pan_context(pctx
);
1930 ctx
->stencil_ref
= *ref
;
1932 /* Shader core dirty */
1933 ctx
->dirty
|= PAN_DIRTY_FS
;
1936 static struct pipe_sampler_view
*
1937 panfrost_create_sampler_view(
1938 struct pipe_context
*pctx
,
1939 struct pipe_resource
*texture
,
1940 const struct pipe_sampler_view
*template)
1942 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1943 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1945 pipe_reference(NULL
, &texture
->reference
);
1947 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1950 so
->base
= *template;
1951 so
->base
.texture
= texture
;
1952 so
->base
.reference
.count
= 1;
1953 so
->base
.context
= pctx
;
1955 /* sampler_views correspond to texture descriptors, minus the texture
1956 * (data) itself. So, we serialise the descriptor here and cache it for
1959 /* Make sure it's something with which we're familiar */
1960 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1962 /* TODO: Detect from format better */
1963 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1965 unsigned char user_swizzle
[4] = {
1966 template->swizzle_r
,
1967 template->swizzle_g
,
1968 template->swizzle_b
,
1972 enum mali_format format
= panfrost_find_format(desc
);
1974 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
1976 unsigned usage2_layout
= 0x10;
1978 switch (prsrc
->bo
->layout
) {
1980 usage2_layout
|= 0x8 | 0x4;
1983 usage2_layout
|= 0x1;
1986 usage2_layout
|= is_depth
? 0x1 : 0x2;
1993 /* Check if we need to set a custom stride by computing the "expected"
1994 * stride and comparing it to what the BO actually wants. Only applies
1995 * to linear textures, since tiled/compressed textures have strict
1996 * alignment requirements for their strides as it is */
1998 unsigned first_level
= template->u
.tex
.first_level
;
1999 unsigned last_level
= template->u
.tex
.last_level
;
2001 if (prsrc
->bo
->layout
== PAN_LINEAR
) {
2002 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2003 unsigned actual_stride
= prsrc
->bo
->slices
[l
].stride
;
2004 unsigned width
= u_minify(texture
->width0
, l
);
2005 unsigned comp_stride
= width
* bytes_per_pixel
;
2007 if (comp_stride
!= actual_stride
) {
2008 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2014 struct mali_texture_descriptor texture_descriptor
= {
2015 .width
= MALI_POSITIVE(texture
->width0
),
2016 .height
= MALI_POSITIVE(texture
->height0
),
2017 .depth
= MALI_POSITIVE(texture
->depth0
),
2021 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2025 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
2027 .usage2
= usage2_layout
2030 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2033 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2034 assert (template->u
.tex
.first_level
== 0);
2036 /* Disable mipmapping for now to avoid regressions while automipmapping
2037 * is being implemented. TODO: Remove me once automipmaps work */
2039 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2040 texture_descriptor
.nr_mipmap_levels
= 0;
2042 so
->hw
= texture_descriptor
;
2044 return (struct pipe_sampler_view
*) so
;
2048 panfrost_set_sampler_views(
2049 struct pipe_context
*pctx
,
2050 enum pipe_shader_type shader
,
2051 unsigned start_slot
, unsigned num_views
,
2052 struct pipe_sampler_view
**views
)
2054 struct panfrost_context
*ctx
= pan_context(pctx
);
2056 assert(start_slot
== 0);
2058 ctx
->sampler_view_count
[shader
] = num_views
;
2059 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2061 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2065 panfrost_sampler_view_destroy(
2066 struct pipe_context
*pctx
,
2067 struct pipe_sampler_view
*view
)
2069 pipe_resource_reference(&view
->texture
, NULL
);
2074 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2075 const struct pipe_framebuffer_state
*fb
)
2077 struct panfrost_context
*ctx
= pan_context(pctx
);
2079 /* Flush when switching away from an FBO, but not if the framebuffer
2080 * state is being restored by u_blitter
2083 if (!panfrost_is_scanout(ctx
) && !ctx
->blitter
->running
) {
2084 panfrost_flush(pctx
, NULL
, 0);
2087 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2088 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2089 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2090 ctx
->pipe_framebuffer
.width
= fb
->width
;
2091 ctx
->pipe_framebuffer
.height
= fb
->height
;
2093 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2094 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2096 /* check if changing cbuf */
2097 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2099 if (cb
&& (i
!= 0)) {
2100 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2105 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2110 if (ctx
->require_sfbd
)
2111 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2113 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2115 panfrost_attach_vt_framebuffer(ctx
);
2117 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2118 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2120 bool can_afbc
= panfrost_format_supports_afbc(format
);
2121 bool is_scanout
= panfrost_is_scanout(ctx
);
2123 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2124 panfrost_enable_afbc(ctx
, tex
, false);
2126 if (!is_scanout
&& !tex
->bo
->has_checksum
)
2127 panfrost_enable_checksum(ctx
, tex
);
2131 struct pipe_surface
*zb
= fb
->zsbuf
;
2133 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2134 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2137 if (ctx
->require_sfbd
)
2138 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2140 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2142 panfrost_attach_vt_framebuffer(ctx
);
2144 struct panfrost_resource
*tex
= pan_resource(zb
->texture
);
2145 bool can_afbc
= panfrost_format_supports_afbc(zb
->format
);
2146 bool is_scanout
= panfrost_is_scanout(ctx
);
2148 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& can_afbc
)
2149 panfrost_enable_afbc(ctx
, tex
, true);
2156 panfrost_create_blend_state(struct pipe_context
*pipe
,
2157 const struct pipe_blend_state
*blend
)
2159 struct panfrost_context
*ctx
= pan_context(pipe
);
2160 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2163 /* TODO: The following features are not yet implemented */
2164 assert(!blend
->logicop_enable
);
2165 assert(!blend
->alpha_to_coverage
);
2166 assert(!blend
->alpha_to_one
);
2168 /* Compile the blend state, first as fixed-function if we can */
2170 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2173 /* If we can't, compile a blend shader instead */
2175 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2181 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2184 struct panfrost_context
*ctx
= pan_context(pipe
);
2185 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2186 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2187 ctx
->blend
= pblend
;
2192 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2194 /* TODO: Attach color */
2196 /* Shader itself is not dirty, but the shader core is */
2197 ctx
->dirty
|= PAN_DIRTY_FS
;
2201 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2204 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2206 if (so
->has_blend_shader
) {
2207 DBG("Deleting blend state leak blend shaders bytecode\n");
2214 panfrost_set_blend_color(struct pipe_context
*pipe
,
2215 const struct pipe_blend_color
*blend_color
)
2217 struct panfrost_context
*ctx
= pan_context(pipe
);
2219 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2222 ctx
->blend_color
= *blend_color
;
2224 /* The blend mode depends on the blend constant color, due to the
2225 * fixed/programmable split. So, we're forced to regenerate the blend
2228 /* TODO: Attach color */
2233 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2234 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2236 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2240 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2243 struct panfrost_context
*ctx
= pan_context(pipe
);
2244 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2245 ctx
->depth_stencil
= depth_stencil
;
2250 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2251 * emulated in the fragment shader */
2253 if (depth_stencil
->alpha
.enabled
) {
2254 /* We need to trigger a new shader (maybe) */
2255 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2259 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2261 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2262 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2264 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2265 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2267 /* Depth state (TODO: Refactor) */
2268 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2270 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2272 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2273 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2275 /* Bounds test not implemented */
2276 assert(!depth_stencil
->depth
.bounds_test
);
2278 ctx
->dirty
|= PAN_DIRTY_FS
;
2282 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2288 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2289 unsigned sample_mask
)
2294 panfrost_set_clip_state(struct pipe_context
*pipe
,
2295 const struct pipe_clip_state
*clip
)
2297 //struct panfrost_context *panfrost = pan_context(pipe);
2301 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2302 unsigned start_slot
,
2303 unsigned num_viewports
,
2304 const struct pipe_viewport_state
*viewports
)
2306 struct panfrost_context
*ctx
= pan_context(pipe
);
2308 assert(start_slot
== 0);
2309 assert(num_viewports
== 1);
2311 ctx
->pipe_viewport
= *viewports
;
2315 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2316 unsigned start_slot
,
2317 unsigned num_scissors
,
2318 const struct pipe_scissor_state
*scissors
)
2320 struct panfrost_context
*ctx
= pan_context(pipe
);
2322 assert(start_slot
== 0);
2323 assert(num_scissors
== 1);
2325 ctx
->scissor
= *scissors
;
2329 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2330 const struct pipe_poly_stipple
*stipple
)
2332 //struct panfrost_context *panfrost = pan_context(pipe);
2336 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2339 //struct panfrost_context *panfrost = pan_context(pipe);
2343 panfrost_destroy(struct pipe_context
*pipe
)
2345 struct panfrost_context
*panfrost
= pan_context(pipe
);
2346 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2348 if (panfrost
->blitter
)
2349 util_blitter_destroy(panfrost
->blitter
);
2351 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2352 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2353 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2354 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2355 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2358 static struct pipe_query
*
2359 panfrost_create_query(struct pipe_context
*pipe
,
2363 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2368 return (struct pipe_query
*) q
;
2372 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2378 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2380 struct panfrost_context
*ctx
= pan_context(pipe
);
2381 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2383 switch (query
->type
) {
2384 case PIPE_QUERY_OCCLUSION_COUNTER
:
2385 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2386 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2388 /* Allocate a word for the query results to be stored */
2389 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2391 ctx
->occlusion_query
= query
;
2397 DBG("Skipping query %d\n", query
->type
);
2405 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2407 struct panfrost_context
*ctx
= pan_context(pipe
);
2408 ctx
->occlusion_query
= NULL
;
2413 panfrost_get_query_result(struct pipe_context
*pipe
,
2414 struct pipe_query
*q
,
2416 union pipe_query_result
*vresult
)
2419 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2421 /* We need to flush out the jobs to actually run the counter, TODO
2422 * check wait, TODO wallpaper after if needed */
2424 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2426 switch (query
->type
) {
2427 case PIPE_QUERY_OCCLUSION_COUNTER
:
2428 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2429 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2430 /* Read back the query results */
2431 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2432 unsigned passed
= *result
;
2434 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2435 vresult
->u64
= passed
;
2437 vresult
->b
= !!passed
;
2443 DBG("Skipped query get %d\n", query
->type
);
2450 static struct pipe_stream_output_target
*
2451 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2452 struct pipe_resource
*prsc
,
2453 unsigned buffer_offset
,
2454 unsigned buffer_size
)
2456 struct pipe_stream_output_target
*target
;
2458 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2463 pipe_reference_init(&target
->reference
, 1);
2464 pipe_resource_reference(&target
->buffer
, prsc
);
2466 target
->context
= pctx
;
2467 target
->buffer_offset
= buffer_offset
;
2468 target
->buffer_size
= buffer_size
;
2474 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2475 struct pipe_stream_output_target
*target
)
2477 pipe_resource_reference(&target
->buffer
, NULL
);
2482 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2483 unsigned num_targets
,
2484 struct pipe_stream_output_target
**targets
,
2485 const unsigned *offsets
)
2491 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2493 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2494 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2496 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2497 /* Allocate the beginning of the transient pool */
2498 int entry_size
= (1 << 22); /* 4MB */
2500 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2501 ctx
->transient_pools
[i
].entry_count
= 1;
2503 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2506 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2507 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2508 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2509 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2510 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2514 /* New context creation, which also does hardware initialisation since I don't
2515 * know the better way to structure this :smirk: */
2517 struct pipe_context
*
2518 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2520 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2521 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2522 memset(ctx
, 0, sizeof(*ctx
));
2523 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2526 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2528 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2529 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2531 gallium
->screen
= screen
;
2533 gallium
->destroy
= panfrost_destroy
;
2535 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2537 gallium
->flush
= panfrost_flush
;
2538 gallium
->clear
= panfrost_clear
;
2539 gallium
->draw_vbo
= panfrost_draw_vbo
;
2541 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2542 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2544 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2546 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2547 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2548 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2550 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2551 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2552 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2554 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2555 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2556 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2558 gallium
->create_fs_state
= panfrost_create_shader_state
;
2559 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2560 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2562 gallium
->create_vs_state
= panfrost_create_shader_state
;
2563 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2564 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2566 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2567 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2568 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2570 gallium
->create_blend_state
= panfrost_create_blend_state
;
2571 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2572 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2574 gallium
->set_blend_color
= panfrost_set_blend_color
;
2576 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2577 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2578 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2580 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2582 gallium
->set_clip_state
= panfrost_set_clip_state
;
2583 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2584 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2585 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2586 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2588 gallium
->create_query
= panfrost_create_query
;
2589 gallium
->destroy_query
= panfrost_destroy_query
;
2590 gallium
->begin_query
= panfrost_begin_query
;
2591 gallium
->end_query
= panfrost_end_query
;
2592 gallium
->get_query_result
= panfrost_get_query_result
;
2594 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2595 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2596 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2598 panfrost_resource_context_init(gallium
);
2600 pscreen
->driver
->init_context(ctx
);
2602 panfrost_setup_hardware(ctx
);
2605 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2606 gallium
->const_uploader
= gallium
->stream_uploader
;
2607 assert(gallium
->stream_uploader
);
2609 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2610 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2612 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2614 ctx
->blitter
= util_blitter_create(gallium
);
2615 assert(ctx
->blitter
);
2617 /* Prepare for render! */
2619 panfrost_job_init(ctx
);
2620 panfrost_emit_vertex_payload(ctx
);
2621 panfrost_emit_tiler_payload(ctx
);
2622 panfrost_invalidate_frame(ctx
);
2623 panfrost_default_shader_backend(ctx
);
2624 panfrost_generate_space_filler_indices();