src/gallium/drivers/panfrost/pan_context.c

   1 /*
   2  * © Copyright 2018 Alyssa Rosenzweig
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24
  25 #include <sys/poll.h>
  26 #include <errno.h>
  27
  28 #include "pan_context.h"
  29 #include "pan_swizzle.h"
  30 #include "pan_format.h"
  31
  32 #include "util/macros.h"
  33 #include "util/u_format.h"
  34 #include "util/u_inlines.h"
  35 #include "util/u_upload_mgr.h"
  36 #include "util/u_memory.h"
  37 #include "util/half_float.h"
  38 #include "indices/u_primconvert.h"
  39 #include "tgsi/tgsi_parse.h"
  40
  41 #include "pan_screen.h"
  42 #include "pan_blending.h"
  43 #include "pan_blend_shaders.h"
  44 #include "pan_wallpaper.h"
  45
  46 #ifdef DUMP_PERFORMANCE_COUNTERS
  47 static int performance_counter_number = 0;
  48 #endif
  49
  50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
  51 //#define DRY_RUN
  52
  53 #define SET_BIT(lval, bit, cond) \
  54         if (cond) \
  55                 lval |= (bit); \
  56         else \
  57                 lval &= ~(bit);
  58
  59 /* TODO: Sample size, etc */
  60
  61 static void
  62 panfrost_set_framebuffer_msaa(struct panfrost_context *ctx, bool enabled)
  63 {
  64         SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_HAS_MSAA, enabled);
  65         SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_NO_MSAA, !enabled);
  66
  67 #ifdef SFBD
  68         SET_BIT(ctx->fragment_fbd.format, MALI_FRAMEBUFFER_MSAA_A | MALI_FRAMEBUFFER_MSAA_B, enabled);
  69 #else
  70         SET_BIT(ctx->fragment_rts[0].format, MALI_MFBD_FORMAT_MSAA, enabled);
  71
  72         SET_BIT(ctx->fragment_fbd.unk1, (1 << 4) | (1 << 1), enabled);
  73
  74         /* XXX */
  75         ctx->fragment_fbd.rt_count_2 = enabled ? 4 : 1;
  76 #endif
  77 }
  78
  79 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
  80  * indepdent between color buffers and depth/stencil). To enable, we allocate
  81  * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
  82  * edit the fragment job here. This routine should be called ONCE per
  83  * AFBC-compressed buffer, rather than on every frame. */
  84
  85 static void
  86 panfrost_enable_afbc(struct panfrost_context *ctx, struct panfrost_resource *rsrc, bool ds)
  87 {
  88 #ifdef MFBD
  89         struct pipe_context *gallium = (struct pipe_context *) ctx;
  90         struct panfrost_screen *screen = pan_screen(gallium->screen);
  91        /* AFBC metadata is 16 bytes per tile */
  92         int tile_w = (rsrc->base.width0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
  93         int tile_h = (rsrc->base.height0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
  94         int bytes_per_pixel = util_format_get_blocksize(rsrc->base.format);
  95         int stride = bytes_per_pixel * rsrc->base.width0; /* TODO: Alignment? */
  96
  97         stride *= 2;  /* TODO: Should this be carried over? */
  98         int main_size = stride * rsrc->base.height0;
  99         rsrc->bo->afbc_metadata_size = tile_w * tile_h * 16;
 100
 101         /* Allocate the AFBC slab itself, large enough to hold the above */
 102         screen->driver->allocate_slab(screen, &rsrc->bo->afbc_slab,
 103                                (rsrc->bo->afbc_metadata_size + main_size + 4095) / 4096,
 104                                true, 0, 0, 0);
 105
 106         rsrc->bo->has_afbc = true;
 107
 108         /* Compressed textured reads use a tagged pointer to the metadata */
 109
 110         rsrc->bo->gpu[0] = rsrc->bo->afbc_slab.gpu | (ds ? 0 : 1);
 111         rsrc->bo->cpu[0] = rsrc->bo->afbc_slab.cpu;
 112 #else
 113         printf("AFBC not supported yet on SFBD\n");
 114         assert(0);
 115 #endif
 116 }
 117
 118 static void
 119 panfrost_enable_checksum(struct panfrost_context *ctx, struct panfrost_resource *rsrc)
 120 {
 121         struct pipe_context *gallium = (struct pipe_context *) ctx;
 122         struct panfrost_screen *screen = pan_screen(gallium->screen);
 123         int tile_w = (rsrc->base.width0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
 124         int tile_h = (rsrc->base.height0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
 125
 126         /* 8 byte checksum per tile */
 127         rsrc->bo->checksum_stride = tile_w * 8;
 128         int pages = (((rsrc->bo->checksum_stride * tile_h) + 4095) / 4096);
 129         screen->driver->allocate_slab(screen, &rsrc->bo->checksum_slab, pages, false, 0, 0, 0);
 130
 131         rsrc->bo->has_checksum = true;
 132 }
 133
 134 /* ..by contrast, this routine runs for every FRAGMENT job, but does no
 135  * allocation. AFBC is enabled on a per-surface basis */
 136
 137 static void
 138 panfrost_set_fragment_afbc(struct panfrost_context *ctx)
 139 {
 140         for (int cb = 0; cb < ctx->pipe_framebuffer.nr_cbufs; ++cb) {
 141                 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[cb]->texture;
 142
 143                 /* Non-AFBC is the default */
 144                 if (!rsrc->bo->has_afbc)
 145                         continue;
 146
 147                 /* Enable AFBC for the render target */
 148                 ctx->fragment_rts[0].afbc.metadata = rsrc->bo->afbc_slab.gpu;
 149                 ctx->fragment_rts[0].afbc.stride = 0;
 150                 ctx->fragment_rts[0].afbc.unk = 0x30009;
 151
 152                 ctx->fragment_rts[0].format |= MALI_MFBD_FORMAT_AFBC;
 153
 154                 /* Point rendering to our special framebuffer */
 155                 ctx->fragment_rts[0].framebuffer = rsrc->bo->afbc_slab.gpu + rsrc->bo->afbc_metadata_size;
 156
 157                 /* WAT? Stride is diff from the scanout case */
 158                 ctx->fragment_rts[0].framebuffer_stride = ctx->pipe_framebuffer.width * 2 * 4;
 159         }
 160
 161         /* Enable depth/stencil AFBC for the framebuffer (not the render target) */
 162         if (ctx->pipe_framebuffer.zsbuf) {
 163                 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.zsbuf->texture;
 164
 165                 if (rsrc->bo->has_afbc) {
 166                         ctx->fragment_fbd.unk3 |= MALI_MFBD_EXTRA;
 167
 168                         ctx->fragment_extra.ds_afbc.depth_stencil_afbc_metadata = rsrc->bo->afbc_slab.gpu;
 169                         ctx->fragment_extra.ds_afbc.depth_stencil_afbc_stride = 0;
 170
 171                         ctx->fragment_extra.ds_afbc.depth_stencil = rsrc->bo->afbc_slab.gpu + rsrc->bo->afbc_metadata_size;
 172
 173                         ctx->fragment_extra.ds_afbc.zero1 = 0x10009;
 174                         ctx->fragment_extra.ds_afbc.padding = 0x1000;
 175
 176                         ctx->fragment_extra.unk = 0x435; /* General 0x400 in all unks. 0x5 for depth/stencil. 0x10 for AFBC encoded depth stencil. Unclear where the 0x20 is from */
 177
 178                         ctx->fragment_fbd.unk3 |= 0x400;
 179                 }
 180         }
 181
 182         /* For the special case of a depth-only FBO, we need to attach a dummy render target */
 183
 184         if (ctx->pipe_framebuffer.nr_cbufs == 0) {
 185                 ctx->fragment_rts[0].format = 0x80008000;
 186                 ctx->fragment_rts[0].framebuffer = 0;
 187                 ctx->fragment_rts[0].framebuffer_stride = 0;
 188         }
 189 }
 190
 191 /* Framebuffer descriptor */
 192
 193 #ifdef SFBD
 194 static void
 195 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer *fb, int w, int h)
 196 {
 197         fb->width = MALI_POSITIVE(w);
 198         fb->height = MALI_POSITIVE(h);
 199
 200         /* No idea why this is needed, but it's how resolution_check is
 201          * calculated.  It's not clear to us yet why the hardware wants this.
 202          * The formula itself was discovered mostly by manual bruteforce and
 203          * aggressive algebraic simplification. */
 204
 205         fb->resolution_check = ((w + h) / 3) << 4;
 206 }
 207 #endif
 208
 209 static PANFROST_FRAMEBUFFER
 210 panfrost_emit_fbd(struct panfrost_context *ctx)
 211 {
 212 #ifdef SFBD
 213         struct mali_single_framebuffer framebuffer = {
 214                 .unknown2 = 0x1f,
 215                 .format = 0x30000000,
 216                 .clear_flags = 0x1000,
 217                 .unknown_address_0 = ctx->scratchpad.gpu,
 218                 .unknown_address_1 = ctx->scratchpad.gpu + 0x6000,
 219                 .unknown_address_2 = ctx->scratchpad.gpu + 0x6200,
 220                 .tiler_flags = 0xf0,
 221                 .tiler_heap_free = ctx->tiler_heap.gpu,
 222                 .tiler_heap_end = ctx->tiler_heap.gpu + ctx->tiler_heap.size,
 223         };
 224
 225         panfrost_set_framebuffer_resolution(&framebuffer, ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height);
 226 #else
 227         struct bifrost_framebuffer framebuffer = {
 228                 .tiler_meta = 0xf00000c600,
 229
 230                 .width1 = MALI_POSITIVE(ctx->pipe_framebuffer.width),
 231                 .height1 = MALI_POSITIVE(ctx->pipe_framebuffer.height),
 232                 .width2 = MALI_POSITIVE(ctx->pipe_framebuffer.width),
 233                 .height2 = MALI_POSITIVE(ctx->pipe_framebuffer.height),
 234
 235                 .unk1 = 0x1080,
 236
 237                 /* TODO: MRT */
 238                 .rt_count_1 = MALI_POSITIVE(1),
 239                 .rt_count_2 = 4,
 240
 241                 .unknown2 = 0x1f,
 242
 243                 /* Presumably corresponds to unknown_address_X of SFBD */
 244                 .scratchpad = ctx->scratchpad.gpu,
 245                 .tiler_scratch_start  = ctx->misc_0.gpu,
 246                 .tiler_scratch_middle = ctx->misc_0.gpu + /*ctx->misc_0.size*/40960, /* Size depends on the size of the framebuffer and the number of vertices */
 247
 248                 .tiler_heap_start = ctx->tiler_heap.gpu,
 249                 .tiler_heap_end = ctx->tiler_heap.gpu + ctx->tiler_heap.size,
 250         };
 251
 252 #endif
 253
 254         return framebuffer;
 255 }
 256
 257 /* Are we currently rendering to the screen (rather than an FBO)? */
 258
 259 static bool
 260 panfrost_is_scanout(struct panfrost_context *ctx)
 261 {
 262         /* If there is no color buffer, it's an FBO */
 263         if (!ctx->pipe_framebuffer.nr_cbufs)
 264                 return false;
 265
 266         /* If we're too early that no framebuffer was sent, it's scanout */
 267         if (!ctx->pipe_framebuffer.cbufs[0])
 268                 return true;
 269
 270         return ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_DISPLAY_TARGET ||
 271                ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_SCANOUT ||
 272                ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_SHARED;
 273 }
 274
 275 /* The above function is for generalised fbd emission, used in both fragment as
 276  * well as vertex/tiler payloads. This payload is specific to fragment
 277  * payloads. */
 278
 279 static void
 280 panfrost_new_frag_framebuffer(struct panfrost_context *ctx)
 281 {
 282         mali_ptr framebuffer;
 283         int stride;
 284
 285         if (ctx->pipe_framebuffer.nr_cbufs > 0) {
 286                 framebuffer = ((struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[0]->texture)->bo->gpu[0];
 287                 stride = util_format_get_stride(ctx->pipe_framebuffer.cbufs[0]->format, ctx->pipe_framebuffer.width);
 288         } else {
 289                 /* Depth-only framebuffer -> dummy RT */
 290                 framebuffer = 0;
 291                 stride = 0;
 292         }
 293
 294         /* The default is upside down from OpenGL's perspective. */
 295         if (panfrost_is_scanout(ctx)) {
 296                 framebuffer += stride * (ctx->pipe_framebuffer.height - 1);
 297                 stride = -stride;
 298         }
 299
 300 #ifdef SFBD
 301         struct mali_single_framebuffer fb = panfrost_emit_fbd(ctx);
 302
 303         fb.framebuffer = framebuffer;
 304         fb.stride = stride;
 305
 306         fb.format = 0xb84e0281; /* RGB32, no MSAA */
 307 #else
 308         struct bifrost_framebuffer fb = panfrost_emit_fbd(ctx);
 309
 310         /* XXX: MRT case */
 311         fb.rt_count_2 = 1;
 312         fb.unk3 = 0x100;
 313
 314         struct bifrost_render_target rt = {
 315                 .unk1 = 0x4000000,
 316                 .format = 0x860a8899, /* RGBA32, no MSAA */
 317                 .framebuffer = framebuffer,
 318                 .framebuffer_stride = (stride / 16) & 0xfffffff,
 319         };
 320
 321         memcpy(&ctx->fragment_rts[0], &rt, sizeof(rt));
 322
 323         memset(&ctx->fragment_extra, 0, sizeof(ctx->fragment_extra));
 324 #endif
 325
 326         memcpy(&ctx->fragment_fbd, &fb, sizeof(fb));
 327 }
 328
 329 /* Maps float 0.0-1.0 to int 0x00-0xFF */
 330 static uint8_t
 331 normalised_float_to_u8(float f)
 332 {
 333         return (uint8_t) (int) (f * 255.0f);
 334 }
 335
 336 static void
 337 panfrost_clear(
 338         struct pipe_context *pipe,
 339         unsigned buffers,
 340         const union pipe_color_union *color,
 341         double depth, unsigned stencil)
 342 {
 343         struct panfrost_context *ctx = pan_context(pipe);
 344
 345         if (!color) {
 346                 printf("Warning: clear color null?\n");
 347                 return;
 348         }
 349
 350         /* Save settings for FBO switch */
 351         ctx->last_clear.buffers = buffers;
 352         ctx->last_clear.color = color;
 353         ctx->last_clear.depth = depth;
 354         ctx->last_clear.depth = depth;
 355
 356         bool clear_color = buffers & PIPE_CLEAR_COLOR;
 357         bool clear_depth = buffers & PIPE_CLEAR_DEPTH;
 358         bool clear_stencil = buffers & PIPE_CLEAR_STENCIL;
 359
 360         /* Remember that we've done something */
 361         ctx->frame_cleared = true;
 362
 363         /* Alpha clear only meaningful without alpha channel */
 364         bool has_alpha = ctx->pipe_framebuffer.nr_cbufs && util_format_has_alpha(ctx->pipe_framebuffer.cbufs[0]->format);
 365         float clear_alpha = has_alpha ? color->f[3] : 1.0f;
 366
 367         uint32_t packed_color =
 368                 (normalised_float_to_u8(clear_alpha) << 24) |
 369                 (normalised_float_to_u8(color->f[2]) << 16) |
 370                 (normalised_float_to_u8(color->f[1]) <<  8) |
 371                 (normalised_float_to_u8(color->f[0]) <<  0);
 372
 373 #ifdef MFBD
 374         struct bifrost_render_target *buffer_color = &ctx->fragment_rts[0];
 375 #else
 376         struct mali_single_framebuffer *buffer_color = &ctx->fragment_fbd;
 377 #endif
 378
 379 #ifdef MFBD
 380         struct bifrost_framebuffer *buffer_ds = &ctx->fragment_fbd;
 381 #else
 382         struct mali_single_framebuffer *buffer_ds = buffer_color;
 383 #endif
 384
 385         if (clear_color) {
 386                 /* Fields duplicated 4x for unknown reasons. Same in Utgard,
 387                  * too, which is doubly weird. */
 388
 389                 buffer_color->clear_color_1 = packed_color;
 390                 buffer_color->clear_color_2 = packed_color;
 391                 buffer_color->clear_color_3 = packed_color;
 392                 buffer_color->clear_color_4 = packed_color;
 393         }
 394
 395         if (clear_depth) {
 396 #ifdef SFBD
 397                 buffer_ds->clear_depth_1 = depth;
 398                 buffer_ds->clear_depth_2 = depth;
 399                 buffer_ds->clear_depth_3 = depth;
 400                 buffer_ds->clear_depth_4 = depth;
 401 #else
 402                 buffer_ds->clear_depth = depth;
 403 #endif
 404         }
 405
 406         if (clear_stencil) {
 407                 buffer_ds->clear_stencil = stencil;
 408         }
 409
 410         /* Setup buffers depending on MFBD/SFBD */
 411
 412 #ifdef MFBD
 413
 414         if (clear_depth || clear_stencil) {
 415                 /* Setup combined 24/8 depth/stencil */
 416                 ctx->fragment_fbd.unk3 |= MALI_MFBD_EXTRA;
 417                 //ctx->fragment_extra.unk = /*0x405*/0x404;
 418                 ctx->fragment_extra.unk = 0x405;
 419                 ctx->fragment_extra.ds_linear.depth = ctx->depth_stencil_buffer.gpu;
 420                 ctx->fragment_extra.ds_linear.depth_stride = ctx->pipe_framebuffer.width * 4;
 421         }
 422
 423 #else
 424
 425         if (clear_depth) {
 426                 buffer_ds->depth_buffer = ctx->depth_stencil_buffer.gpu;
 427                 buffer_ds->depth_buffer_enable = MALI_DEPTH_STENCIL_ENABLE;
 428         }
 429
 430         if (clear_stencil) {
 431                 buffer_ds->stencil_buffer = ctx->depth_stencil_buffer.gpu;
 432                 buffer_ds->stencil_buffer_enable = MALI_DEPTH_STENCIL_ENABLE;
 433         }
 434
 435 #endif
 436
 437 #ifdef SFBD
 438         /* Set flags based on what has been cleared, for the SFBD case */
 439         /* XXX: What do these flags mean? */
 440         int clear_flags = 0x101100;
 441
 442         if (clear_color && clear_depth && clear_stencil) {
 443                 /* On a tiler like this, it's fastest to clear all three buffers at once */
 444
 445                 clear_flags |= MALI_CLEAR_FAST;
 446         } else {
 447                 clear_flags |= MALI_CLEAR_SLOW;
 448
 449                 if (clear_stencil)
 450                         clear_flags |= MALI_CLEAR_SLOW_STENCIL;
 451         }
 452
 453         fbd->clear_flags = clear_flags;
 454 #endif
 455 }
 456
 457 static void
 458 panfrost_attach_vt_framebuffer(struct panfrost_context *ctx)
 459 {
 460 #ifdef MFBD
 461         /* MFBD needs a sequential semi-render target upload, but this is, is beyond me for now */
 462         struct bifrost_render_target rts_list[] = {
 463                 {
 464                         .chunknown = {
 465                                 .unk = 0x30005,
 466                         },
 467                         .framebuffer = ctx->misc_0.gpu,
 468                         .zero2 = 0x3,
 469                 },
 470         };
 471
 472         /* Allocate memory for the three components */
 473         int size = 1024 + sizeof(ctx->vt_framebuffer) + sizeof(rts_list);
 474         struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
 475
 476         /* Opaque 1024-block */
 477         rts_list[0].chunknown.pointer = transfer.gpu;
 478
 479         mali_ptr framebuffer = (transfer.gpu + 1024) | PANFROST_DEFAULT_FBD;
 480         memcpy(transfer.cpu + 1024, &ctx->vt_framebuffer, sizeof(ctx->vt_framebuffer));
 481         memcpy(transfer.cpu + 1024 + sizeof(ctx->vt_framebuffer), rts_list, sizeof(rts_list));
 482 #else
 483         mali_ptr framebuffer = panfrost_upload_transient(ctx, &ctx->vt_framebuffer, sizeof(ctx->vt_framebuffer)) | PANFROST_DEFAULT_FBD;
 484 #endif
 485         ctx->payload_vertex.postfix.framebuffer = framebuffer;
 486         ctx->payload_tiler.postfix.framebuffer = framebuffer;
 487 }
 488
 489 static void
 490 panfrost_viewport(struct panfrost_context *ctx,
 491                   float depth_range_n,
 492                   float depth_range_f,
 493                   int viewport_x0, int viewport_y0,
 494                   int viewport_x1, int viewport_y1)
 495 {
 496         /* Viewport encoding is asymmetric. Purpose of the floats is unknown? */
 497
 498         struct mali_viewport ret = {
 499                 .floats = {
 500 #if 0
 501                         -inff, -inff,
 502                         inff, inff,
 503 #endif
 504                         0.0, 0.0,
 505                         2048.0, 1600.0,
 506                 },
 507
 508                 .depth_range_n = depth_range_n,
 509                 .depth_range_f = depth_range_f,
 510
 511                 .viewport0 = { viewport_x0, viewport_y0 },
 512                 .viewport1 = { MALI_POSITIVE(viewport_x1), MALI_POSITIVE(viewport_y1) },
 513         };
 514
 515         memcpy(ctx->viewport, &ret, sizeof(ret));
 516 }
 517
 518 /* Reset per-frame context, called on context initialisation as well as after
 519  * flushing a frame */
 520
 521 static void
 522 panfrost_invalidate_frame(struct panfrost_context *ctx)
 523 {
 524         unsigned transient_count = ctx->transient_pools[ctx->cmdstream_i].entry_index*ctx->transient_pools[0].entry_size + ctx->transient_pools[ctx->cmdstream_i].entry_offset;
 525         printf("Uploaded transient %d bytes\n", transient_count);
 526
 527         /* Rotate cmdstream */
 528         if ((++ctx->cmdstream_i) == (sizeof(ctx->transient_pools) / sizeof(ctx->transient_pools[0])))
 529                 ctx->cmdstream_i = 0;
 530
 531         ctx->vt_framebuffer = panfrost_emit_fbd(ctx);
 532         panfrost_new_frag_framebuffer(ctx);
 533
 534         /* Reset varyings allocated */
 535         ctx->varying_height = 0;
 536
 537         /* The transient cmdstream is dirty every frame; the only bits worth preserving
 538          * (textures, shaders, etc) are in other buffers anyways */
 539
 540         ctx->transient_pools[ctx->cmdstream_i].entry_index = 0;
 541         ctx->transient_pools[ctx->cmdstream_i].entry_offset = 0;
 542
 543         /* Regenerate payloads */
 544         panfrost_attach_vt_framebuffer(ctx);
 545
 546         if (ctx->rasterizer)
 547                 ctx->dirty |= PAN_DIRTY_RASTERIZER;
 548
 549         /* XXX */
 550         ctx->dirty |= PAN_DIRTY_SAMPLERS | PAN_DIRTY_TEXTURES;
 551 }
 552
 553 /* In practice, every field of these payloads should be configurable
 554  * arbitrarily, which means these functions are basically catch-all's for
 555  * as-of-yet unwavering unknowns */
 556
 557 static void
 558 panfrost_emit_vertex_payload(struct panfrost_context *ctx)
 559 {
 560         struct midgard_payload_vertex_tiler payload = {
 561                 .prefix = {
 562                         .workgroups_z_shift = 32,
 563                         .workgroups_x_shift_2 = 0x2,
 564                         .workgroups_x_shift_3 = 0x5,
 565                 },
 566                 .gl_enables = 0x6
 567         };
 568
 569         memcpy(&ctx->payload_vertex, &payload, sizeof(payload));
 570 }
 571
 572 static void
 573 panfrost_emit_tiler_payload(struct panfrost_context *ctx)
 574 {
 575         struct midgard_payload_vertex_tiler payload = {
 576                 .prefix = {
 577                         .workgroups_z_shift = 32,
 578                         .workgroups_x_shift_2 = 0x2,
 579                         .workgroups_x_shift_3 = 0x6,
 580
 581                         .zero1 = 0xffff, /* Why is this only seen on test-quad-textured? */
 582                 },
 583         };
 584
 585         /* Reserve the viewport */
 586         struct panfrost_transfer t = panfrost_allocate_chunk(ctx, sizeof(struct mali_viewport), HEAP_DESCRIPTOR);
 587         ctx->viewport = (struct mali_viewport *) t.cpu;
 588         payload.postfix.viewport = t.gpu;
 589
 590         memcpy(&ctx->payload_tiler, &payload, sizeof(payload));
 591 }
 592
 593 static unsigned
 594 translate_tex_wrap(enum pipe_tex_wrap w)
 595 {
 596         switch (w) {
 597         case PIPE_TEX_WRAP_REPEAT:
 598                 return MALI_WRAP_REPEAT;
 599
 600         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 601                 return MALI_WRAP_CLAMP_TO_EDGE;
 602
 603         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 604                 return MALI_WRAP_CLAMP_TO_BORDER;
 605
 606         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 607                 return MALI_WRAP_MIRRORED_REPEAT;
 608
 609         default:
 610                 assert(0);
 611                 return 0;
 612         }
 613 }
 614
 615 static unsigned
 616 translate_tex_filter(enum pipe_tex_filter f)
 617 {
 618         switch (f) {
 619         case PIPE_TEX_FILTER_NEAREST:
 620                 return MALI_NEAREST;
 621
 622         case PIPE_TEX_FILTER_LINEAR:
 623                 return MALI_LINEAR;
 624
 625         default:
 626                 assert(0);
 627                 return 0;
 628         }
 629 }
 630
 631 static unsigned
 632 translate_mip_filter(enum pipe_tex_mipfilter f)
 633 {
 634         return (f == PIPE_TEX_MIPFILTER_LINEAR) ? MALI_MIP_LINEAR : 0;
 635 }
 636
 637 static unsigned
 638 panfrost_translate_compare_func(enum pipe_compare_func in)
 639 {
 640         switch (in) {
 641         case PIPE_FUNC_NEVER:
 642                 return MALI_FUNC_NEVER;
 643
 644         case PIPE_FUNC_LESS:
 645                 return MALI_FUNC_LESS;
 646
 647         case PIPE_FUNC_EQUAL:
 648                 return MALI_FUNC_EQUAL;
 649
 650         case PIPE_FUNC_LEQUAL:
 651                 return MALI_FUNC_LEQUAL;
 652
 653         case PIPE_FUNC_GREATER:
 654                 return MALI_FUNC_GREATER;
 655
 656         case PIPE_FUNC_NOTEQUAL:
 657                 return MALI_FUNC_NOTEQUAL;
 658
 659         case PIPE_FUNC_GEQUAL:
 660                 return MALI_FUNC_GEQUAL;
 661
 662         case PIPE_FUNC_ALWAYS:
 663                 return MALI_FUNC_ALWAYS;
 664         }
 665
 666         assert (0);
 667         return 0; /* Unreachable */
 668 }
 669
 670 static unsigned
 671 panfrost_translate_alt_compare_func(enum pipe_compare_func in)
 672 {
 673         switch (in) {
 674         case PIPE_FUNC_NEVER:
 675                 return MALI_ALT_FUNC_NEVER;
 676
 677         case PIPE_FUNC_LESS:
 678                 return MALI_ALT_FUNC_LESS;
 679
 680         case PIPE_FUNC_EQUAL:
 681                 return MALI_ALT_FUNC_EQUAL;
 682
 683         case PIPE_FUNC_LEQUAL:
 684                 return MALI_ALT_FUNC_LEQUAL;
 685
 686         case PIPE_FUNC_GREATER:
 687                 return MALI_ALT_FUNC_GREATER;
 688
 689         case PIPE_FUNC_NOTEQUAL:
 690                 return MALI_ALT_FUNC_NOTEQUAL;
 691
 692         case PIPE_FUNC_GEQUAL:
 693                 return MALI_ALT_FUNC_GEQUAL;
 694
 695         case PIPE_FUNC_ALWAYS:
 696                 return MALI_ALT_FUNC_ALWAYS;
 697         }
 698
 699         assert (0);
 700         return 0; /* Unreachable */
 701 }
 702
 703 static unsigned
 704 panfrost_translate_stencil_op(enum pipe_stencil_op in)
 705 {
 706         switch (in) {
 707         case PIPE_STENCIL_OP_KEEP:
 708                 return MALI_STENCIL_KEEP;
 709
 710         case PIPE_STENCIL_OP_ZERO:
 711                 return MALI_STENCIL_ZERO;
 712
 713         case PIPE_STENCIL_OP_REPLACE:
 714                 return MALI_STENCIL_REPLACE;
 715
 716         case PIPE_STENCIL_OP_INCR:
 717                 return MALI_STENCIL_INCR;
 718
 719         case PIPE_STENCIL_OP_DECR:
 720                 return MALI_STENCIL_DECR;
 721
 722         case PIPE_STENCIL_OP_INCR_WRAP:
 723                 return MALI_STENCIL_INCR_WRAP;
 724
 725         case PIPE_STENCIL_OP_DECR_WRAP:
 726                 return MALI_STENCIL_DECR_WRAP;
 727
 728         case PIPE_STENCIL_OP_INVERT:
 729                 return MALI_STENCIL_INVERT;
 730         }
 731
 732         assert (0);
 733         return 0; /* Unreachable */
 734 }
 735
 736 static void
 737 panfrost_make_stencil_state(const struct pipe_stencil_state *in, struct mali_stencil_test *out)
 738 {
 739         out->ref = 0; /* Gallium gets it from elsewhere */
 740
 741         out->mask = in->valuemask;
 742         out->func = panfrost_translate_compare_func(in->func);
 743         out->sfail = panfrost_translate_stencil_op(in->fail_op);
 744         out->dpfail = panfrost_translate_stencil_op(in->zfail_op);
 745         out->dppass = panfrost_translate_stencil_op(in->zpass_op);
 746 }
 747
 748 static void
 749 panfrost_default_shader_backend(struct panfrost_context *ctx)
 750 {
 751         struct mali_shader_meta shader = {
 752                 .alpha_coverage = ~MALI_ALPHA_COVERAGE(0.000000),
 753
 754                 .unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x3010 /*| MALI_CAN_DISCARD*/,
 755 #ifdef T8XX
 756                 .unknown2_4 = MALI_NO_MSAA | 0x4e0,
 757 #else
 758                 .unknown2_4 = MALI_NO_MSAA | 0x4f0,
 759 #endif
 760         };
 761
 762         struct pipe_stencil_state default_stencil = {
 763                 .enabled = 0,
 764                 .func = PIPE_FUNC_ALWAYS,
 765                 .fail_op = MALI_STENCIL_KEEP,
 766                 .zfail_op = MALI_STENCIL_KEEP,
 767                 .zpass_op = MALI_STENCIL_KEEP,
 768                 .writemask = 0xFF,
 769                 .valuemask = 0xFF
 770         };
 771
 772         panfrost_make_stencil_state(&default_stencil, &shader.stencil_front);
 773         shader.stencil_mask_front = default_stencil.writemask;
 774
 775         panfrost_make_stencil_state(&default_stencil, &shader.stencil_back);
 776         shader.stencil_mask_back = default_stencil.writemask;
 777
 778         if (default_stencil.enabled)
 779                 shader.unknown2_4 |= MALI_STENCIL_TEST;
 780
 781         memcpy(&ctx->fragment_shader_core, &shader, sizeof(shader));
 782 }
 783
 784 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
 785  * graphics command stream. It should be called once per draw, accordding to
 786  * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
 787  * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
 788  * vertex jobs. */
 789
 790 struct panfrost_transfer
 791 panfrost_vertex_tiler_job(struct panfrost_context *ctx, bool is_tiler, bool is_elided_tiler)
 792 {
 793         /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
 794         int draw_job_index = 1 + (2 * ctx->draw_count);
 795
 796         struct mali_job_descriptor_header job = {
 797                 .job_type = is_tiler ? JOB_TYPE_TILER : JOB_TYPE_VERTEX,
 798                 .job_index = draw_job_index + (is_tiler ? 1 : 0),
 799 #ifdef __LP64__
 800                 .job_descriptor_size = 1,
 801 #endif
 802         };
 803
 804         /* XXX: What is this? */
 805 #ifdef T6XX
 806
 807         if (is_tiler)
 808                 job.unknown_flags = ctx->draw_count ? 64 : 1;
 809
 810 #endif
 811
 812         /* Only non-elided tiler jobs have dependencies which are known at this point */
 813
 814         if (is_tiler && !is_elided_tiler) {
 815                 /* Tiler jobs depend on vertex jobs */
 816
 817                 job.job_dependency_index_1 = draw_job_index;
 818
 819                 /* Tiler jobs also depend on the previous tiler job */
 820
 821                 if (ctx->draw_count)
 822                         job.job_dependency_index_2 = draw_job_index - 1;
 823         }
 824
 825         struct midgard_payload_vertex_tiler *payload = is_tiler ? &ctx->payload_tiler : &ctx->payload_vertex;
 826
 827         /* There's some padding hacks on 32-bit */
 828
 829 #ifdef __LP64__
 830         int offset = 0;
 831 #else
 832         int offset = 4;
 833 #endif
 834         struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(job) + sizeof(*payload));
 835         memcpy(transfer.cpu, &job, sizeof(job));
 836         memcpy(transfer.cpu + sizeof(job) - offset, payload, sizeof(*payload));
 837         return transfer;
 838 }
 839
 840 /* Generates a set value job. It's unclear what exactly this does, why it's
 841  * necessary, and when to call it. */
 842
 843 static void
 844 panfrost_set_value_job(struct panfrost_context *ctx)
 845 {
 846         struct mali_job_descriptor_header job = {
 847                 .job_type = JOB_TYPE_SET_VALUE,
 848                 .job_descriptor_size = 1,
 849                 .job_index = 1 + (2 * ctx->draw_count),
 850         };
 851
 852         struct mali_payload_set_value payload = {
 853                 .out = ctx->misc_0.gpu,
 854                 .unknown = 0x3,
 855         };
 856
 857         struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(job) + sizeof(payload));
 858         memcpy(transfer.cpu, &job, sizeof(job));
 859         memcpy(transfer.cpu + sizeof(job), &payload, sizeof(payload));
 860
 861         ctx->u_set_value_job = (struct mali_job_descriptor_header *) transfer.cpu;
 862         ctx->set_value_job = transfer.gpu;
 863 }
 864
 865 /* Generate a fragment job. This should be called once per frame. (According to
 866  * presentations, this is supposed to correspond to eglSwapBuffers) */
 867
 868 mali_ptr
 869 panfrost_fragment_job(struct panfrost_context *ctx)
 870 {
 871         /* Update fragment FBD */
 872         panfrost_set_fragment_afbc(ctx);
 873
 874         if (ctx->pipe_framebuffer.nr_cbufs == 1) {
 875                 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[0]->texture;
 876                 int stride = util_format_get_stride(rsrc->base.format, rsrc->base.width0);
 877
 878                 if (rsrc->bo->has_checksum) {
 879                         //ctx->fragment_fbd.unk3 |= 0xa00000;
 880                         //ctx->fragment_fbd.unk3 = 0xa02100;
 881                         ctx->fragment_fbd.unk3 |= MALI_MFBD_EXTRA;
 882                         ctx->fragment_extra.unk |= 0x420;
 883                         ctx->fragment_extra.checksum_stride = rsrc->bo->checksum_stride;
 884                         ctx->fragment_extra.checksum = rsrc->bo->gpu[0] + stride * rsrc->base.height0;
 885                 }
 886         }
 887
 888         /* The frame is complete and therefore the framebuffer descriptor is
 889          * ready for linkage and upload */
 890
 891         size_t sz = sizeof(ctx->fragment_fbd) + sizeof(struct bifrost_fb_extra) + sizeof(struct bifrost_render_target) * 1;
 892         struct panfrost_transfer fbd_t = panfrost_allocate_transient(ctx, sz);
 893         off_t offset = 0;
 894
 895         memcpy(fbd_t.cpu, &ctx->fragment_fbd, sizeof(ctx->fragment_fbd));
 896         offset += sizeof(ctx->fragment_fbd);
 897
 898         /* Upload extra framebuffer info if necessary */
 899         if (ctx->fragment_fbd.unk3 & MALI_MFBD_EXTRA) {
 900                 memcpy(fbd_t.cpu + offset, &ctx->fragment_extra, sizeof(struct bifrost_fb_extra));
 901                 offset += sizeof(struct bifrost_fb_extra);
 902         }
 903
 904         /* Upload (single) render target */
 905         memcpy(fbd_t.cpu + offset, &ctx->fragment_rts[0], sizeof(struct bifrost_render_target) * 1);
 906
 907         /* Generate the fragment (frame) job */
 908
 909         struct mali_job_descriptor_header header = {
 910                 .job_type = JOB_TYPE_FRAGMENT,
 911                 .job_index = 1,
 912 #ifdef __LP64__
 913                 .job_descriptor_size = 1
 914 #endif
 915         };
 916
 917         struct mali_payload_fragment payload = {
 918                 .min_tile_coord = MALI_COORDINATE_TO_TILE_MIN(0, 0),
 919                 .max_tile_coord = MALI_COORDINATE_TO_TILE_MAX(ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height),
 920                 .framebuffer = fbd_t.gpu | PANFROST_DEFAULT_FBD | (ctx->fragment_fbd.unk3 & MALI_MFBD_EXTRA ? 2 : 0),
 921         };
 922
 923         /* Normally, there should be no padding. However, fragment jobs are
 924          * shared with 64-bit Bifrost systems, and accordingly there is 4-bytes
 925          * of zero padding in between. */
 926
 927         struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(header) + sizeof(payload));
 928         memcpy(transfer.cpu, &header, sizeof(header));
 929         memcpy(transfer.cpu + sizeof(header), &payload, sizeof(payload));
 930         return transfer.gpu;
 931 }
 932
 933 /* Emits attributes and varying descriptors, which should be called every draw,
 934  * excepting some obscure circumstances */
 935
 936 static void
 937 panfrost_emit_vertex_data(struct panfrost_context *ctx)
 938 {
 939         /* TODO: Only update the dirtied buffers */
 940         union mali_attr attrs[PIPE_MAX_ATTRIBS];
 941         union mali_attr varyings[PIPE_MAX_ATTRIBS];
 942
 943         unsigned invocation_count = MALI_NEGATIVE(ctx->payload_tiler.prefix.invocation_count);
 944
 945         for (int i = 0; i < ctx->vertex_buffer_count; ++i) {
 946                 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[i];
 947                 struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer.resource);
 948
 949                 /* Let's figure out the layout of the attributes in memory so
 950                  * we can be smart about size computation. The idea is to
 951                  * figure out the maximum src_offset, which tells us the latest
 952                  * spot a vertex could start. Meanwhile, we figure out the size
 953                  * of the attribute memory (assuming interleaved
 954                  * representation) and tack on the max src_offset for a
 955                  * reasonably good upper bound on the size.
 956                  *
 957                  * Proving correctness is left as an exercise to the reader.
 958                  */
 959
 960                 unsigned max_src_offset = 0;
 961
 962                 for (unsigned j = 0; j < ctx->vertex->num_elements; ++j) {
 963                         if (ctx->vertex->pipe[j].vertex_buffer_index != i) continue;
 964                         max_src_offset = MAX2(max_src_offset, ctx->vertex->pipe[j].src_offset);
 965                 }
 966
 967                 /* Offset vertex count by draw_start to make sure we upload enough */
 968                 attrs[i].stride = buf->stride;
 969                 attrs[i].size = buf->stride * (ctx->payload_vertex.draw_start + invocation_count) + max_src_offset;
 970
 971                 /* Vertex elements are -already- GPU-visible, at
 972                  * rsrc->gpu. However, attribute buffers must be 64 aligned. If
 973                  * it is not, for now we have to duplicate the buffer. */
 974
 975                 mali_ptr effective_address = (rsrc->bo->gpu[0] + buf->buffer_offset);
 976
 977                 if (effective_address & 0x3F) {
 978                         attrs[i].elements = panfrost_upload_transient(ctx, rsrc->bo->cpu[0] + buf->buffer_offset, attrs[i].size) | 1;
 979                 } else {
 980                         attrs[i].elements = effective_address | 1;
 981                 }
 982         }
 983
 984         struct panfrost_varyings *vars = &ctx->vs->variants[ctx->vs->active_variant].varyings;
 985
 986         for (int i = 0; i < vars->varying_buffer_count; ++i) {
 987                 mali_ptr varying_address = ctx->varying_mem.gpu + ctx->varying_height;
 988
 989                 varyings[i].elements = varying_address | 1;
 990                 varyings[i].stride = vars->varyings_stride[i];
 991                 varyings[i].size = vars->varyings_stride[i] * invocation_count;
 992
 993                 /* If this varying has to be linked somewhere, do it now. See
 994                  * pan_assemble.c for the indices. TODO: Use a more generic
 995                  * linking interface */
 996
 997                 if (i == 1) {
 998                         /* gl_Position */
 999                         ctx->payload_tiler.postfix.position_varying = varying_address;
1000                 } else if (i == 2) {
1001                         /* gl_PointSize */
1002                         ctx->payload_tiler.primitive_size.pointer = varying_address;
1003                 }
1004
1005                 /* Varyings appear to need 64-byte alignment */
1006                 ctx->varying_height += ALIGN(varyings[i].size, 64);
1007
1008                 /* Ensure that we fit */
1009                 assert(ctx->varying_height < ctx->varying_mem.size);
1010         }
1011
1012         ctx->payload_vertex.postfix.attributes = panfrost_upload_transient(ctx, attrs, ctx->vertex_buffer_count * sizeof(union mali_attr));
1013
1014         mali_ptr varyings_p = panfrost_upload_transient(ctx, &varyings, vars->varying_buffer_count * sizeof(union mali_attr));
1015         ctx->payload_vertex.postfix.varyings = varyings_p;
1016         ctx->payload_tiler.postfix.varyings = varyings_p;
1017 }
1018
1019 /* Go through dirty flags and actualise them in the cmdstream. */
1020
1021 void
1022 panfrost_emit_for_draw(struct panfrost_context *ctx, bool with_vertex_data)
1023 {
1024         if (with_vertex_data) {
1025                 panfrost_emit_vertex_data(ctx);
1026         }
1027
1028         if (ctx->dirty & PAN_DIRTY_RASTERIZER) {
1029                 ctx->payload_tiler.gl_enables = ctx->rasterizer->tiler_gl_enables;
1030                 panfrost_set_framebuffer_msaa(ctx, ctx->rasterizer->base.multisample);
1031         }
1032
1033         if (ctx->occlusion_query) {
1034                 ctx->payload_tiler.gl_enables |= MALI_OCCLUSION_BOOLEAN;
1035                 ctx->payload_tiler.postfix.occlusion_counter = ctx->occlusion_query->transfer.gpu;
1036         }
1037
1038         if (ctx->dirty & PAN_DIRTY_VS) {
1039                 assert(ctx->vs);
1040
1041                 struct panfrost_shader_state *vs = &ctx->vs->variants[ctx->vs->active_variant];
1042
1043                 /* Late shader descriptor assignments */
1044                 vs->tripipe->texture_count = ctx->sampler_view_count[PIPE_SHADER_VERTEX];
1045                 vs->tripipe->sampler_count = ctx->sampler_count[PIPE_SHADER_VERTEX];
1046
1047                 /* Who knows */
1048                 vs->tripipe->midgard1.unknown1 = 0x2201;
1049
1050                 ctx->payload_vertex.postfix._shader_upper = vs->tripipe_gpu >> 4;
1051
1052                 /* Varying descriptor is tied to the vertex shader. Also the
1053                  * fragment shader, I suppose, but it's generated with the
1054                  * vertex shader so */
1055
1056                 struct panfrost_varyings *varyings = &ctx->vs->variants[ctx->vs->active_variant].varyings;
1057
1058                 ctx->payload_vertex.postfix.varying_meta = varyings->varyings_descriptor;
1059                 ctx->payload_tiler.postfix.varying_meta = varyings->varyings_descriptor_fragment;
1060         }
1061
1062         if (ctx->dirty & (PAN_DIRTY_RASTERIZER | PAN_DIRTY_VS)) {
1063                 /* Check if we need to link the gl_PointSize varying */
1064                 assert(ctx->vs);
1065                 struct panfrost_shader_state *vs = &ctx->vs->variants[ctx->vs->active_variant];
1066
1067                 bool needs_gl_point_size = vs->writes_point_size && ctx->payload_tiler.prefix.draw_mode == MALI_POINTS;
1068
1069                 if (!needs_gl_point_size) {
1070                         /* If the size is constant, write it out. Otherwise,
1071                          * don't touch primitive_size (since we would clobber
1072                          * the pointer there) */
1073
1074                         ctx->payload_tiler.primitive_size.constant = ctx->rasterizer->base.line_width;
1075                 }
1076
1077                 /* Set the flag for varying (pointer) point size if the shader needs that */
1078                 SET_BIT(ctx->payload_tiler.prefix.unknown_draw, MALI_DRAW_VARYING_SIZE, needs_gl_point_size);
1079         }
1080
1081         /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1082         if (ctx->fs)
1083                 ctx->dirty |= PAN_DIRTY_FS;
1084
1085         if (ctx->dirty & PAN_DIRTY_FS) {
1086                 assert(ctx->fs);
1087                 struct panfrost_shader_state *variant = &ctx->fs->variants[ctx->fs->active_variant];
1088
1089 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1090
1091                 COPY(shader);
1092                 COPY(attribute_count);
1093                 COPY(varying_count);
1094                 COPY(midgard1.uniform_count);
1095                 COPY(midgard1.work_count);
1096                 COPY(midgard1.unknown2);
1097
1098 #undef COPY
1099                 /* If there is a blend shader, work registers are shared */
1100
1101                 if (ctx->blend->has_blend_shader)
1102                         ctx->fragment_shader_core.midgard1.work_count = /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1103
1104                 /* Set late due to depending on render state */
1105                 /* The one at the end seems to mean "1 UBO" */
1106                 ctx->fragment_shader_core.midgard1.unknown1 = MALI_NO_ALPHA_TO_COVERAGE | 0x200 | 0x2201;
1107
1108                 /* Assign texture/sample count right before upload */
1109                 ctx->fragment_shader_core.texture_count = ctx->sampler_view_count[PIPE_SHADER_FRAGMENT];
1110                 ctx->fragment_shader_core.sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT];
1111
1112                 /* Assign the stencil refs late */
1113                 ctx->fragment_shader_core.stencil_front.ref = ctx->stencil_ref.ref_value[0];
1114                 ctx->fragment_shader_core.stencil_back.ref = ctx->stencil_ref.ref_value[1];
1115
1116                 /* CAN_DISCARD should be set if the fragment shader possibly
1117                  * contains a 'discard' instruction, or maybe other
1118                  * circumstances. It is likely this is related to optimizations
1119                  * related to forward-pixel kill, as per "Mali Performance 3:
1120                  * Is EGL_BUFFER_PRESERVED a good thing?" by Peter Harris
1121                  */
1122
1123                 if (variant->can_discard) {
1124                         ctx->fragment_shader_core.unknown2_3 |= MALI_CAN_DISCARD;
1125                         ctx->fragment_shader_core.midgard1.unknown1 &= ~MALI_NO_ALPHA_TO_COVERAGE;
1126                         ctx->fragment_shader_core.midgard1.unknown1 |= 0x4000;
1127                         ctx->fragment_shader_core.midgard1.unknown1 = 0x4200;
1128                 }
1129
1130                 if (ctx->blend->has_blend_shader)
1131                         ctx->fragment_shader_core.blend_shader = ctx->blend->blend_shader;
1132
1133                 size_t size = sizeof(struct mali_shader_meta) + sizeof(struct mali_blend_meta);
1134                 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
1135                 memcpy(transfer.cpu, &ctx->fragment_shader_core, sizeof(struct mali_shader_meta));
1136
1137                 ctx->payload_tiler.postfix._shader_upper = (transfer.gpu) >> 4;
1138
1139 #ifdef T8XX
1140                 /* Additional blend descriptor tacked on for newer systems */
1141
1142                 unsigned blend_count = 0;
1143
1144                 if (ctx->blend->has_blend_shader) {
1145                         /* For a blend shader, the bottom nibble corresponds to
1146                          * the number of work registers used, which signals the
1147                          * -existence- of a blend shader */
1148
1149                         assert(ctx->blend->blend_work_count >= 2);
1150                         blend_count |= MIN2(ctx->blend->blend_work_count, 3);
1151                 } else {
1152                         /* Otherwise, the bottom bit simply specifies if
1153                          * blending (anything other than REPLACE) is enabled */
1154
1155                         /* XXX: Less ugly way to do this? */
1156                         bool no_blending =
1157                                 (ctx->blend->equation.rgb_mode == 0x122) &&
1158                                 (ctx->blend->equation.alpha_mode == 0x122) &&
1159                                 (ctx->blend->equation.color_mask == 0xf);
1160
1161                         if (!no_blending)
1162                                 blend_count |= 0x1;
1163                 }
1164
1165                 /* Second blend equation is always a simple replace */
1166
1167                 uint64_t replace_magic = 0xf0122122;
1168                 struct mali_blend_equation replace_mode;
1169                 memcpy(&replace_mode, &replace_magic, sizeof(replace_mode));
1170
1171                 struct mali_blend_meta blend_meta[] = {
1172                         {
1173                                 .unk1 = 0x200 | blend_count,
1174                                 .blend_equation_1 = ctx->blend->equation,
1175                                 .blend_equation_2 = replace_mode
1176                         },
1177                 };
1178
1179                 if (ctx->blend->has_blend_shader)
1180                         memcpy(&blend_meta[0].blend_equation_1, &ctx->blend->blend_shader, sizeof(ctx->blend->blend_shader));
1181
1182                 memcpy(transfer.cpu + sizeof(struct mali_shader_meta), blend_meta, sizeof(blend_meta));
1183 #endif
1184         }
1185
1186         if (ctx->dirty & PAN_DIRTY_VERTEX) {
1187                 ctx->payload_vertex.postfix.attribute_meta = ctx->vertex->descriptor_ptr;
1188         }
1189
1190         if (ctx->dirty & PAN_DIRTY_SAMPLERS) {
1191                 /* Upload samplers back to back, no padding */
1192
1193                 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
1194                         if (!ctx->sampler_count[t]) continue;
1195
1196                         struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(struct mali_sampler_descriptor) * ctx->sampler_count[t]);
1197                         struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *) transfer.cpu;
1198
1199                         for (int i = 0; i < ctx->sampler_count[t]; ++i) {
1200                                 desc[i] = ctx->samplers[t][i]->hw;
1201                         }
1202
1203                         if (t == PIPE_SHADER_FRAGMENT)
1204                                 ctx->payload_tiler.postfix.sampler_descriptor = transfer.gpu;
1205                         else if (t == PIPE_SHADER_VERTEX)
1206                                 ctx->payload_vertex.postfix.sampler_descriptor = transfer.gpu;
1207                         else
1208                                 assert(0);
1209                 }
1210         }
1211
1212         if (ctx->dirty & PAN_DIRTY_TEXTURES) {
1213                 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
1214                         /* Shortcircuit */
1215                         if (!ctx->sampler_view_count[t]) continue;
1216
1217                         uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
1218
1219                         for (int i = 0; i < ctx->sampler_view_count[t]; ++i) {
1220                                 if (!ctx->sampler_views[t][i])
1221                                         continue;
1222
1223                                 struct pipe_resource *tex_rsrc = ctx->sampler_views[t][i]->base.texture;
1224                                 struct panfrost_resource *rsrc = (struct panfrost_resource *) tex_rsrc;
1225
1226                                 /* Inject the address in. */
1227                                 for (int l = 0; l < (tex_rsrc->last_level + 1); ++l)
1228                                         ctx->sampler_views[t][i]->hw.swizzled_bitmaps[l] = rsrc->bo->gpu[l];
1229
1230                                 /* Workaround maybe-errata (?) with non-mipmaps */
1231                                 int s = ctx->sampler_views[t][i]->hw.nr_mipmap_levels;
1232
1233                                 if (!rsrc->bo->is_mipmap) {
1234 #ifdef T6XX
1235                                         /* HW ERRATA, not needed after T6XX */
1236                                         ctx->sampler_views[t][i]->hw.swizzled_bitmaps[1] = rsrc->bo->gpu[0];
1237
1238                                         ctx->sampler_views[t][i]->hw.unknown3A = 1;
1239 #endif
1240                                         ctx->sampler_views[t][i]->hw.nr_mipmap_levels = 0;
1241                                 }
1242
1243                                 trampolines[i] = panfrost_upload_transient(ctx, &ctx->sampler_views[t][i]->hw, sizeof(struct mali_texture_descriptor));
1244
1245                                 /* Restore */
1246                                 ctx->sampler_views[t][i]->hw.nr_mipmap_levels = s;
1247
1248 #ifdef T6XX
1249                                 ctx->sampler_views[t][i]->hw.unknown3A = 0;
1250 #endif
1251                         }
1252
1253                         mali_ptr trampoline = panfrost_upload_transient(ctx, trampolines, sizeof(uint64_t) * ctx->sampler_view_count[t]);
1254
1255                         if (t == PIPE_SHADER_FRAGMENT)
1256                                 ctx->payload_tiler.postfix.texture_trampoline = trampoline;
1257                         else if (t == PIPE_SHADER_VERTEX)
1258                                 ctx->payload_vertex.postfix.texture_trampoline = trampoline;
1259                         else
1260                                 assert(0);
1261                 }
1262         }
1263
1264         /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1265         const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
1266
1267         float viewport_vec4[] = {
1268                 vp->scale[0],
1269                 fabsf(vp->scale[1]),
1270
1271                 vp->translate[0],
1272                 /* -1.0 * vp->translate[1] */ fabs(1.0 * vp->scale[1]) /* XXX */
1273         };
1274
1275         for (int i = 0; i < PIPE_SHADER_TYPES; ++i) {
1276                 struct panfrost_constant_buffer *buf = &ctx->constant_buffer[i];
1277
1278                 if (i == PIPE_SHADER_VERTEX || i == PIPE_SHADER_FRAGMENT) {
1279                         /* It doesn't matter if we don't use all the memory;
1280                          * we'd need a dummy UBO anyway. Compute the max */
1281
1282                         size_t size = sizeof(viewport_vec4) + buf->size;
1283                         struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
1284
1285                         /* Keep track how much we've uploaded */
1286                         off_t offset = 0;
1287
1288                         if (i == PIPE_SHADER_VERTEX) {
1289                                 /* Upload viewport */
1290                                 memcpy(transfer.cpu + offset, viewport_vec4, sizeof(viewport_vec4));
1291                                 offset += sizeof(viewport_vec4);
1292                         }
1293
1294                         /* Upload uniforms */
1295                         memcpy(transfer.cpu + offset, buf->buffer, buf->size);
1296
1297                         int uniform_count = 0;
1298
1299                         struct mali_vertex_tiler_postfix *postfix;
1300
1301                         switch (i) {
1302                         case PIPE_SHADER_VERTEX:
1303                                 uniform_count = ctx->vs->variants[ctx->vs->active_variant].uniform_count;
1304                                 postfix = &ctx->payload_vertex.postfix;
1305                                 break;
1306
1307                         case PIPE_SHADER_FRAGMENT:
1308                                 uniform_count = ctx->fs->variants[ctx->fs->active_variant].uniform_count;
1309                                 postfix = &ctx->payload_tiler.postfix;
1310                                 break;
1311
1312                         default:
1313                                 printf("Unknown shader stage %d in uniform upload\n", i);
1314                                 assert(0);
1315                         }
1316
1317                         /* Also attach the same buffer as a UBO for extended access */
1318
1319                         struct mali_uniform_buffer_meta uniform_buffers[] = {
1320                                 {
1321                                         .size = MALI_POSITIVE((2 + uniform_count)),
1322                                         .ptr = transfer.gpu >> 2,
1323                                 },
1324                         };
1325
1326                         mali_ptr ubufs = panfrost_upload_transient(ctx, uniform_buffers, sizeof(uniform_buffers));
1327                         postfix->uniforms = transfer.gpu;
1328                         postfix->uniform_buffers = ubufs;
1329
1330                         buf->dirty = 0;
1331                 }
1332         }
1333
1334         ctx->dirty = 0;
1335 }
1336
1337 /* Corresponds to exactly one draw, but does not submit anything */
1338
1339 static void
1340 panfrost_queue_draw(struct panfrost_context *ctx)
1341 {
1342         /* TODO: Expand the array? */
1343         if (ctx->draw_count >= MAX_DRAW_CALLS) {
1344                 printf("Job buffer overflow, ignoring draw\n");
1345                 assert(0);
1346         }
1347
1348         /* Handle dirty flags now */
1349         panfrost_emit_for_draw(ctx, true);
1350
1351         struct panfrost_transfer vertex = panfrost_vertex_tiler_job(ctx, false, false);
1352         struct panfrost_transfer tiler = panfrost_vertex_tiler_job(ctx, true, false);
1353
1354         ctx->u_vertex_jobs[ctx->vertex_job_count] = (struct mali_job_descriptor_header *) vertex.cpu;
1355         ctx->vertex_jobs[ctx->vertex_job_count++] = vertex.gpu;
1356
1357         ctx->u_tiler_jobs[ctx->tiler_job_count] = (struct mali_job_descriptor_header *) tiler.cpu;
1358         ctx->tiler_jobs[ctx->tiler_job_count++] = tiler.gpu;
1359
1360         ctx->draw_count++;
1361 }
1362
1363 /* At the end of the frame, the vertex and tiler jobs are linked together and
1364  * then the fragment job is plonked at the end. Set value job is first for
1365  * unknown reasons. */
1366
1367 static void
1368 panfrost_link_job_pair(struct mali_job_descriptor_header *first, mali_ptr next)
1369 {
1370         if (first->job_descriptor_size)
1371                 first->next_job_64 = (u64) (uintptr_t) next;
1372         else
1373                 first->next_job_32 = (u32) (uintptr_t) next;
1374 }
1375
1376 static void
1377 panfrost_link_jobs(struct panfrost_context *ctx)
1378 {
1379         if (ctx->draw_count) {
1380                 /* Generate the set_value_job */
1381                 panfrost_set_value_job(ctx);
1382
1383                 /* Have the first vertex job depend on the set value job */
1384                 ctx->u_vertex_jobs[0]->job_dependency_index_1 = ctx->u_set_value_job->job_index;
1385
1386                 /* SV -> V */
1387                 panfrost_link_job_pair(ctx->u_set_value_job, ctx->vertex_jobs[0]);
1388         }
1389
1390         /* V -> V/T ; T -> T/null */
1391         for (int i = 0; i < ctx->vertex_job_count; ++i) {
1392                 bool isLast = (i + 1) == ctx->vertex_job_count;
1393
1394                 panfrost_link_job_pair(ctx->u_vertex_jobs[i], isLast ? ctx->tiler_jobs[0]: ctx->vertex_jobs[i + 1]);
1395         }
1396
1397         /* T -> T/null */
1398         for (int i = 0; i < ctx->tiler_job_count; ++i) {
1399                 bool isLast = (i + 1) == ctx->tiler_job_count;
1400                 panfrost_link_job_pair(ctx->u_tiler_jobs[i], isLast ? 0 : ctx->tiler_jobs[i + 1]);
1401         }
1402 }
1403
1404 /* The entire frame is in memory -- send it off to the kernel! */
1405
1406 static void
1407 panfrost_submit_frame(struct panfrost_context *ctx, bool flush_immediate)
1408 {
1409         struct pipe_context *gallium = (struct pipe_context *) ctx;
1410         struct panfrost_screen *screen = pan_screen(gallium->screen);
1411
1412         /* Edge case if screen is cleared and nothing else */
1413         bool has_draws = ctx->draw_count > 0;
1414
1415         /* Workaround a bizarre lockup (a hardware errata?) */
1416         if (!has_draws)
1417                 flush_immediate = true;
1418
1419         /* A number of jobs are batched -- this must be linked and cleared */
1420         panfrost_link_jobs(ctx);
1421
1422         ctx->draw_count = 0;
1423         ctx->vertex_job_count = 0;
1424         ctx->tiler_job_count = 0;
1425
1426 #ifndef DRY_RUN
1427
1428         bool is_scanout = panfrost_is_scanout(ctx);
1429         int fragment_id = screen->driver->submit_vs_fs_job(ctx, has_draws, is_scanout);
1430
1431         /* If visual, we can stall a frame */
1432
1433         if (panfrost_is_scanout(ctx) && !flush_immediate)
1434                 screen->driver->force_flush_fragment(ctx);
1435
1436         screen->last_fragment_id = fragment_id;
1437         screen->last_fragment_flushed = false;
1438
1439         /* If readback, flush now (hurts the pipelined performance) */
1440         if (panfrost_is_scanout(ctx) && flush_immediate)
1441                 screen->driver->force_flush_fragment(ctx);
1442
1443 #ifdef DUMP_PERFORMANCE_COUNTERS
1444         char filename[128];
1445         snprintf(filename, sizeof(filename), "/dev/shm/frame%d.mdgprf", ++performance_counter_number);
1446         FILE *fp = fopen(filename, "wb");
1447         fwrite(screen->perf_counters.cpu,  4096, sizeof(uint32_t), fp);
1448         fclose(fp);
1449 #endif
1450
1451 #endif
1452 }
1453
1454 bool dont_scanout = false;
1455
1456 void
1457 panfrost_flush(
1458         struct pipe_context *pipe,
1459         struct pipe_fence_handle **fence,
1460         unsigned flags)
1461 {
1462         struct panfrost_context *ctx = pan_context(pipe);
1463
1464         /* If there is nothing drawn, skip the frame */
1465         if (!ctx->draw_count && !ctx->frame_cleared) return;
1466
1467         if (!ctx->frame_cleared) {
1468                 /* While there are draws, there was no clear. This is a partial
1469                  * update, which needs to be handled via the "wallpaper"
1470                  * method. We also need to fake a clear, just to get the
1471                  * FRAGMENT job correct. */
1472
1473                 panfrost_clear(&ctx->base, ctx->last_clear.buffers, ctx->last_clear.color, ctx->last_clear.depth, ctx->last_clear.stencil);
1474
1475                 panfrost_draw_wallpaper(pipe);
1476         }
1477
1478         /* Frame clear handled, reset */
1479         ctx->frame_cleared = false;
1480
1481         /* Whether to stall the pipeline for immediately correct results */
1482         bool flush_immediate = flags & PIPE_FLUSH_END_OF_FRAME;
1483
1484         /* Submit the frame itself */
1485         panfrost_submit_frame(ctx, flush_immediate);
1486
1487         /* Prepare for the next frame */
1488         panfrost_invalidate_frame(ctx);
1489 }
1490
1491 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1492
1493 static int
1494 g2m_draw_mode(enum pipe_prim_type mode)
1495 {
1496         switch (mode) {
1497                 DEFINE_CASE(POINTS);
1498                 DEFINE_CASE(LINES);
1499                 DEFINE_CASE(LINE_LOOP);
1500                 DEFINE_CASE(LINE_STRIP);
1501                 DEFINE_CASE(TRIANGLES);
1502                 DEFINE_CASE(TRIANGLE_STRIP);
1503                 DEFINE_CASE(TRIANGLE_FAN);
1504                 DEFINE_CASE(QUADS);
1505                 DEFINE_CASE(QUAD_STRIP);
1506                 DEFINE_CASE(POLYGON);
1507
1508         default:
1509                 printf("Illegal draw mode %d\n", mode);
1510                 assert(0);
1511                 return MALI_LINE_LOOP;
1512         }
1513 }
1514
1515 #undef DEFINE_CASE
1516
1517 static unsigned
1518 panfrost_translate_index_size(unsigned size)
1519 {
1520         switch (size) {
1521         case 1:
1522                 return MALI_DRAW_INDEXED_UINT8;
1523
1524         case 2:
1525                 return MALI_DRAW_INDEXED_UINT16;
1526
1527         case 4:
1528                 return MALI_DRAW_INDEXED_UINT32;
1529
1530         default:
1531                 printf("Unknown index size %d\n", size);
1532                 assert(0);
1533                 return 0;
1534         }
1535 }
1536
1537 static const uint8_t *
1538 panfrost_get_index_buffer_raw(const struct pipe_draw_info *info)
1539 {
1540         if (info->has_user_indices) {
1541                 return (const uint8_t *) info->index.user;
1542         } else {
1543                 struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
1544                 return (const uint8_t *) rsrc->bo->cpu[0];
1545         }
1546 }
1547
1548 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1549  * good for the duration of the draw (transient), could last longer */
1550
1551 static mali_ptr
1552 panfrost_get_index_buffer_mapped(struct panfrost_context *ctx, const struct pipe_draw_info *info)
1553 {
1554         struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
1555
1556         off_t offset = info->start * info->index_size;
1557
1558         if (!info->has_user_indices) {
1559                 /* Only resources can be directly mapped */
1560                 return rsrc->bo->gpu[0] + offset;
1561         } else {
1562                 /* Otherwise, we need to upload to transient memory */
1563                 const uint8_t *ibuf8 = panfrost_get_index_buffer_raw(info);
1564                 return panfrost_upload_transient(ctx, ibuf8 + offset, info->count * info->index_size);
1565         }
1566 }
1567
1568 static void
1569 panfrost_draw_vbo(
1570         struct pipe_context *pipe,
1571         const struct pipe_draw_info *info);
1572
1573 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1574         for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1575                 T idx = buffer[_idx]; \
1576                 if (idx > max_index) max_index = idx; \
1577                 if (idx < min_index) min_index = idx; \
1578         }
1579
1580 static void
1581 panfrost_draw_vbo(
1582         struct pipe_context *pipe,
1583         const struct pipe_draw_info *info)
1584 {
1585         struct panfrost_context *ctx = pan_context(pipe);
1586
1587         ctx->payload_vertex.draw_start = info->start;
1588         ctx->payload_tiler.draw_start = info->start;
1589
1590         int mode = info->mode;
1591
1592         /* Fallback for unsupported modes */
1593
1594         if (!(ctx->draw_modes & mode)) {
1595                 if (mode == PIPE_PRIM_QUADS && info->count == 4 && ctx->rasterizer && !ctx->rasterizer->base.flatshade) {
1596                         mode = PIPE_PRIM_TRIANGLE_FAN;
1597                 } else {
1598                         if (info->count < 4) {
1599                                 /* Degenerate case? */
1600                                 return;
1601                         }
1602
1603                         util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
1604                         util_primconvert_draw_vbo(ctx->primconvert, info);
1605                         return;
1606                 }
1607         }
1608
1609         ctx->payload_tiler.prefix.draw_mode = g2m_draw_mode(mode);
1610
1611         ctx->vertex_count = info->count;
1612
1613         /* For non-indexed draws, they're the same */
1614         unsigned invocation_count = ctx->vertex_count;
1615
1616         /* For higher amounts of vertices (greater than what fits in a 16-bit
1617          * short), the other value is needed, otherwise there will be bizarre
1618          * rendering artefacts. It's not clear what these values mean yet. */
1619
1620         ctx->payload_tiler.prefix.unknown_draw &= ~(0x3000 | 0x18000);
1621         ctx->payload_tiler.prefix.unknown_draw |= (mode == PIPE_PRIM_POINTS || ctx->vertex_count > 65535) ? 0x3000 : 0x18000;
1622
1623         if (info->index_size) {
1624                 /* Calculate the min/max index used so we can figure out how
1625                  * many times to invoke the vertex shader */
1626
1627                 const uint8_t *ibuf8 = panfrost_get_index_buffer_raw(info);
1628
1629                 int min_index = INT_MAX;
1630                 int max_index = 0;
1631
1632                 if (info->index_size == 1) {
1633                         CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8, info->start, info->count);
1634                 } else if (info->index_size == 2) {
1635                         const uint16_t *ibuf16 = (const uint16_t *) ibuf8;
1636                         CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16, info->start, info->count);
1637                 } else if (info->index_size == 4) {
1638                         const uint32_t *ibuf32 = (const uint32_t *) ibuf8;
1639                         CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32, info->start, info->count);
1640                 } else {
1641                         assert(0);
1642                 }
1643
1644                 /* Make sure we didn't go crazy */
1645                 assert(min_index < INT_MAX);
1646                 assert(max_index > 0);
1647                 assert(max_index > min_index);
1648
1649                 /* Use the corresponding values */
1650                 invocation_count = max_index - min_index + 1;
1651                 ctx->payload_vertex.draw_start = min_index;
1652                 ctx->payload_tiler.draw_start = min_index;
1653
1654                 ctx->payload_tiler.prefix.negative_start = -min_index;
1655                 ctx->payload_tiler.prefix.index_count = MALI_POSITIVE(info->count);
1656
1657                 //assert(!info->restart_index); /* TODO: Research */
1658                 assert(!info->index_bias);
1659                 //assert(!info->min_index); /* TODO: Use value */
1660
1661                 ctx->payload_tiler.prefix.unknown_draw |= panfrost_translate_index_size(info->index_size);
1662                 ctx->payload_tiler.prefix.indices = panfrost_get_index_buffer_mapped(ctx, info);
1663         } else {
1664                 /* Index count == vertex count, if no indexing is applied, as
1665                  * if it is internally indexed in the expected order */
1666
1667                 ctx->payload_tiler.prefix.negative_start = 0;
1668                 ctx->payload_tiler.prefix.index_count = MALI_POSITIVE(ctx->vertex_count);
1669
1670                 /* Reverse index state */
1671                 ctx->payload_tiler.prefix.unknown_draw &= ~MALI_DRAW_INDEXED_UINT32;
1672                 ctx->payload_tiler.prefix.indices = (uintptr_t) NULL;
1673         }
1674
1675         ctx->payload_vertex.prefix.invocation_count = MALI_POSITIVE(invocation_count);
1676         ctx->payload_tiler.prefix.invocation_count = MALI_POSITIVE(invocation_count);
1677
1678         /* Fire off the draw itself */
1679         panfrost_queue_draw(ctx);
1680 }
1681
1682 /* CSO state */
1683
1684 static void
1685 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
1686 {
1687         free(hwcso);
1688 }
1689
1690 static void
1691 panfrost_set_scissor(struct panfrost_context *ctx)
1692 {
1693         const struct pipe_scissor_state *ss = &ctx->scissor;
1694
1695         if (ss && ctx->rasterizer && ctx->rasterizer->base.scissor && 0) {
1696                 ctx->viewport->viewport0[0] = ss->minx;
1697                 ctx->viewport->viewport0[1] = ss->miny;
1698                 ctx->viewport->viewport1[0] = MALI_POSITIVE(ss->maxx);
1699                 ctx->viewport->viewport1[1] = MALI_POSITIVE(ss->maxy);
1700         } else {
1701                 ctx->viewport->viewport0[0] = 0;
1702                 ctx->viewport->viewport0[1] = 0;
1703                 ctx->viewport->viewport1[0] = MALI_POSITIVE(ctx->pipe_framebuffer.width);
1704                 ctx->viewport->viewport1[1] = MALI_POSITIVE(ctx->pipe_framebuffer.height);
1705         }
1706 }
1707
1708 static void *
1709 panfrost_create_rasterizer_state(
1710         struct pipe_context *pctx,
1711         const struct pipe_rasterizer_state *cso)
1712 {
1713         struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
1714
1715         so->base = *cso;
1716
1717         /* Bitmask, unknown meaning of the start value */
1718 #ifdef T8XX
1719         so->tiler_gl_enables = 0x7;
1720 #else
1721         so->tiler_gl_enables = 0x105;
1722 #endif
1723
1724         so->tiler_gl_enables |= MALI_FRONT_FACE(
1725                                         cso->front_ccw ? MALI_CCW : MALI_CW);
1726
1727         if (cso->cull_face & PIPE_FACE_FRONT)
1728                 so->tiler_gl_enables |= MALI_CULL_FACE_FRONT;
1729
1730         if (cso->cull_face & PIPE_FACE_BACK)
1731                 so->tiler_gl_enables |= MALI_CULL_FACE_BACK;
1732
1733         return so;
1734 }
1735
1736 static void
1737 panfrost_bind_rasterizer_state(
1738         struct pipe_context *pctx,
1739         void *hwcso)
1740 {
1741         struct panfrost_context *ctx = pan_context(pctx);
1742         struct pipe_rasterizer_state *cso = hwcso;
1743
1744         /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1745         if (!hwcso)
1746                 return;
1747
1748         /* If scissor test has changed, we'll need to update that now */
1749         bool update_scissor = !ctx->rasterizer || ctx->rasterizer->base.scissor != cso->scissor;
1750
1751         ctx->rasterizer = hwcso;
1752
1753         /* Actualise late changes */
1754         if (update_scissor)
1755                 panfrost_set_scissor(ctx);
1756
1757         ctx->dirty |= PAN_DIRTY_RASTERIZER;
1758 }
1759
1760 static void *
1761 panfrost_create_vertex_elements_state(
1762         struct pipe_context *pctx,
1763         unsigned num_elements,
1764         const struct pipe_vertex_element *elements)
1765 {
1766         struct panfrost_context *ctx = pan_context(pctx);
1767         struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
1768
1769         so->num_elements = num_elements;
1770         memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
1771
1772         struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_attr_meta) * num_elements, HEAP_DESCRIPTOR);
1773         so->hw = (struct mali_attr_meta *) transfer.cpu;
1774         so->descriptor_ptr = transfer.gpu;
1775
1776         /* Allocate memory for the descriptor state */
1777
1778         for (int i = 0; i < num_elements; ++i) {
1779                 so->hw[i].index = elements[i].vertex_buffer_index;
1780
1781                 enum pipe_format fmt = elements[i].src_format;
1782                 const struct util_format_description *desc = util_format_description(fmt);
1783                 so->hw[i].unknown1 = 0x2;
1784                 so->hw[i].swizzle = panfrost_get_default_swizzle(desc->nr_channels);
1785
1786                 so->hw[i].format = panfrost_find_format(desc);
1787
1788                 /* The field itself should probably be shifted over */
1789                 so->hw[i].src_offset = elements[i].src_offset;
1790         }
1791
1792         return so;
1793 }
1794
1795 static void
1796 panfrost_bind_vertex_elements_state(
1797         struct pipe_context *pctx,
1798         void *hwcso)
1799 {
1800         struct panfrost_context *ctx = pan_context(pctx);
1801
1802         ctx->vertex = hwcso;
1803         ctx->dirty |= PAN_DIRTY_VERTEX;
1804 }
1805
1806 static void
1807 panfrost_delete_vertex_elements_state(struct pipe_context *pctx, void *hwcso)
1808 {
1809         printf("Vertex elements delete leaks descriptor\n");
1810         free(hwcso);
1811 }
1812
1813 static void *
1814 panfrost_create_shader_state(
1815         struct pipe_context *pctx,
1816         const struct pipe_shader_state *cso)
1817 {
1818         struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
1819         so->base = *cso;
1820
1821         /* Token deep copy to prevent memory corruption */
1822
1823         if (cso->type == PIPE_SHADER_IR_TGSI)
1824                 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
1825
1826         return so;
1827 }
1828
1829 static void
1830 panfrost_delete_shader_state(
1831         struct pipe_context *pctx,
1832         void *so)
1833 {
1834         printf("Deleting shader state maybe leaks tokens, per-variant compiled shaders, per-variant  descriptors\n");
1835         free(so);
1836 }
1837
1838 static void *
1839 panfrost_create_sampler_state(
1840         struct pipe_context *pctx,
1841         const struct pipe_sampler_state *cso)
1842 {
1843         struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
1844         so->base = *cso;
1845
1846         /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1847
1848         struct mali_sampler_descriptor sampler_descriptor = {
1849                 .filter_mode = MALI_TEX_MIN(translate_tex_filter(cso->min_img_filter))
1850                 | MALI_TEX_MAG(translate_tex_filter(cso->mag_img_filter))
1851                 | translate_mip_filter(cso->min_mip_filter)
1852                 | 0x20,
1853
1854                 .wrap_s = translate_tex_wrap(cso->wrap_s),
1855                 .wrap_t = translate_tex_wrap(cso->wrap_t),
1856                 .wrap_r = translate_tex_wrap(cso->wrap_r),
1857                 .compare_func = panfrost_translate_alt_compare_func(cso->compare_func),
1858                 .border_color = {
1859                         cso->border_color.f[0],
1860                         cso->border_color.f[1],
1861                         cso->border_color.f[2],
1862                         cso->border_color.f[3]
1863                 },
1864                 .min_lod = FIXED_16(0.0),
1865                 .max_lod = FIXED_16(31.0),
1866                 .unknown2 = 1,
1867         };
1868
1869         so->hw = sampler_descriptor;
1870
1871         return so;
1872 }
1873
1874 static void
1875 panfrost_bind_sampler_states(
1876         struct pipe_context *pctx,
1877         enum pipe_shader_type shader,
1878         unsigned start_slot, unsigned num_sampler,
1879         void **sampler)
1880 {
1881         assert(start_slot == 0);
1882
1883         struct panfrost_context *ctx = pan_context(pctx);
1884
1885         /* XXX: Should upload, not just copy? */
1886         ctx->sampler_count[shader] = num_sampler;
1887         memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
1888
1889         ctx->dirty |= PAN_DIRTY_SAMPLERS;
1890 }
1891
1892 static bool
1893 panfrost_variant_matches(struct panfrost_context *ctx, struct panfrost_shader_state *variant)
1894 {
1895         struct pipe_alpha_state *alpha = &ctx->depth_stencil->alpha;
1896
1897         if (alpha->enabled || variant->alpha_state.enabled) {
1898                 /* Make sure enable state is at least the same */
1899                 if (alpha->enabled != variant->alpha_state.enabled) {
1900                         return false;
1901                 }
1902
1903                 /* Check that the contents of the test are the same */
1904                 bool same_func = alpha->func == variant->alpha_state.func;
1905                 bool same_ref = alpha->ref_value == variant->alpha_state.ref_value;
1906
1907                 if (!(same_func && same_ref)) {
1908                         return false;
1909                 }
1910         }
1911         /* Otherwise, we're good to go */
1912         return true;
1913 }
1914
1915 static void
1916 panfrost_bind_fs_state(
1917         struct pipe_context *pctx,
1918         void *hwcso)
1919 {
1920         struct panfrost_context *ctx = pan_context(pctx);
1921
1922         ctx->fs = hwcso;
1923
1924         if (hwcso) {
1925                 /* Match the appropriate variant */
1926
1927                 signed variant = -1;
1928
1929                 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
1930
1931                 for (unsigned i = 0; i < variants->variant_count; ++i) {
1932                         if (panfrost_variant_matches(ctx, &variants->variants[i])) {
1933                                 variant = i;
1934                                 break;
1935                         }
1936                 }
1937
1938                 if (variant == -1) {
1939                         /* No variant matched, so create a new one */
1940                         variant = variants->variant_count++;
1941                         assert(variants->variant_count < MAX_SHADER_VARIANTS);
1942
1943                         variants->variants[variant].base = hwcso;
1944                         variants->variants[variant].alpha_state = ctx->depth_stencil->alpha;
1945
1946                         /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
1947                         struct panfrost_context *ctx = pan_context(pctx);
1948                         struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_shader_meta), HEAP_DESCRIPTOR);
1949
1950                         variants->variants[variant].tripipe = (struct mali_shader_meta *) transfer.cpu;
1951                         variants->variants[variant].tripipe_gpu = transfer.gpu;
1952
1953                 }
1954
1955                 /* Select this variant */
1956                 variants->active_variant = variant;
1957
1958                 struct panfrost_shader_state *shader_state = &variants->variants[variant];
1959                 assert(panfrost_variant_matches(ctx, shader_state));
1960
1961                 /* Now we have a variant selected, so compile and go */
1962
1963                 if (!shader_state->compiled) {
1964                         panfrost_shader_compile(ctx, shader_state->tripipe, NULL, JOB_TYPE_TILER, shader_state);
1965                         shader_state->compiled = true;
1966                 }
1967         }
1968
1969         ctx->dirty |= PAN_DIRTY_FS;
1970 }
1971
1972 static void
1973 panfrost_bind_vs_state(
1974         struct pipe_context *pctx,
1975         void *hwcso)
1976 {
1977         struct panfrost_context *ctx = pan_context(pctx);
1978
1979         ctx->vs = hwcso;
1980
1981         if (hwcso) {
1982                 if (!ctx->vs->variants[0].compiled) {
1983                         ctx->vs->variants[0].base = hwcso;
1984
1985                         /* TODO DRY from above */
1986                         struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_shader_meta), HEAP_DESCRIPTOR);
1987                         ctx->vs->variants[0].tripipe = (struct mali_shader_meta *) transfer.cpu;
1988                         ctx->vs->variants[0].tripipe_gpu = transfer.gpu;
1989
1990                         panfrost_shader_compile(ctx, ctx->vs->variants[0].tripipe, NULL, JOB_TYPE_VERTEX, &ctx->vs->variants[0]);
1991                         ctx->vs->variants[0].compiled = true;
1992                 }
1993         }
1994
1995         ctx->dirty |= PAN_DIRTY_VS;
1996 }
1997
1998 static void
1999 panfrost_set_vertex_buffers(
2000         struct pipe_context *pctx,
2001         unsigned start_slot,
2002         unsigned num_buffers,
2003         const struct pipe_vertex_buffer *buffers)
2004 {
2005         struct panfrost_context *ctx = pan_context(pctx);
2006         assert(num_buffers <= PIPE_MAX_ATTRIBS);
2007
2008         /* XXX: Dirty tracking? etc */
2009         if (buffers) {
2010                 size_t sz = sizeof(buffers[0]) * num_buffers;
2011                 ctx->vertex_buffers = malloc(sz);
2012                 ctx->vertex_buffer_count = num_buffers;
2013                 memcpy(ctx->vertex_buffers, buffers, sz);
2014         } else {
2015                 if (ctx->vertex_buffers) {
2016                         free(ctx->vertex_buffers);
2017                         ctx->vertex_buffers = NULL;
2018                 }
2019
2020                 ctx->vertex_buffer_count = 0;
2021         }
2022 }
2023
2024 static void
2025 panfrost_set_constant_buffer(
2026         struct pipe_context *pctx,
2027         enum pipe_shader_type shader, uint index,
2028         const struct pipe_constant_buffer *buf)
2029 {
2030         struct panfrost_context *ctx = pan_context(pctx);
2031         struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
2032
2033         size_t sz = buf ? buf->buffer_size : 0;
2034
2035         /* Free previous buffer */
2036
2037         pbuf->dirty = true;
2038         pbuf->size = sz;
2039
2040         if (pbuf->buffer) {
2041                 free(pbuf->buffer);
2042                 pbuf->buffer = NULL;
2043         }
2044
2045         /* If unbinding, we're done */
2046
2047         if (!buf)
2048                 return;
2049
2050         /* Multiple constant buffers not yet supported */
2051         assert(index == 0);
2052
2053         const uint8_t *cpu;
2054
2055         struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer);
2056
2057         if (rsrc) {
2058                 cpu = rsrc->bo->cpu[0];
2059         } else if (buf->user_buffer) {
2060                 cpu = buf->user_buffer;
2061         } else {
2062                 printf("No constant buffer?\n");
2063                 return;
2064         }
2065
2066         /* Copy the constant buffer into the driver context for later upload */
2067
2068         pbuf->buffer = malloc(sz);
2069         memcpy(pbuf->buffer, cpu + buf->buffer_offset, sz);
2070 }
2071
2072 static void
2073 panfrost_set_stencil_ref(
2074         struct pipe_context *pctx,
2075         const struct pipe_stencil_ref *ref)
2076 {
2077         struct panfrost_context *ctx = pan_context(pctx);
2078         ctx->stencil_ref = *ref;
2079
2080         /* Shader core dirty */
2081         ctx->dirty |= PAN_DIRTY_FS;
2082 }
2083
2084 static struct pipe_sampler_view *
2085 panfrost_create_sampler_view(
2086         struct pipe_context *pctx,
2087         struct pipe_resource *texture,
2088         const struct pipe_sampler_view *template)
2089 {
2090         struct panfrost_sampler_view *so = CALLOC_STRUCT(panfrost_sampler_view);
2091         int bytes_per_pixel = util_format_get_blocksize(texture->format);
2092
2093         pipe_reference(NULL, &texture->reference);
2094
2095         struct panfrost_resource *prsrc = (struct panfrost_resource *) texture;
2096
2097         so->base = *template;
2098         so->base.texture = texture;
2099         so->base.reference.count = 1;
2100         so->base.context = pctx;
2101
2102         /* sampler_views correspond to texture descriptors, minus the texture
2103          * (data) itself. So, we serialise the descriptor here and cache it for
2104          * later. */
2105
2106         /* TODO: Other types of textures */
2107         assert(template->target == PIPE_TEXTURE_2D);
2108
2109         /* Make sure it's something with which we're familiar */
2110         assert(bytes_per_pixel >= 1 && bytes_per_pixel <= 4);
2111
2112         /* TODO: Detect from format better */
2113         const struct util_format_description *desc = util_format_description(prsrc->base.format);
2114
2115         unsigned char user_swizzle[4] = {
2116                 template->swizzle_r,
2117                 template->swizzle_g,
2118                 template->swizzle_b,
2119                 template->swizzle_a
2120         };
2121
2122         enum mali_format format = panfrost_find_format(desc);
2123
2124         struct mali_texture_descriptor texture_descriptor = {
2125                 .width = MALI_POSITIVE(texture->width0),
2126                 .height = MALI_POSITIVE(texture->height0),
2127                 .depth = MALI_POSITIVE(texture->depth0),
2128
2129                 /* TODO: Decode */
2130                 .format = {
2131                         .swizzle = panfrost_translate_swizzle_4(desc->swizzle),
2132                         .format = format,
2133
2134                         .usage1 = 0x0,
2135                         .is_not_cubemap = 1,
2136
2137                         /* 0x11 - regular texture 2d, uncompressed tiled */
2138                         /* 0x12 - regular texture 2d, uncompressed linear */
2139                         /* 0x1c - AFBC compressed (internally tiled, probably) texture 2D */
2140
2141                         .usage2 = prsrc->bo->has_afbc ? 0x1c : (prsrc->bo->tiled ? 0x11 : 0x12),
2142                 },
2143
2144                 .swizzle = panfrost_translate_swizzle_4(user_swizzle)
2145         };
2146
2147         /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2148         assert (template->u.tex.first_level == 0);
2149
2150         texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2151
2152         so->hw = texture_descriptor;
2153
2154         return (struct pipe_sampler_view *) so;
2155 }
2156
2157 static void
2158 panfrost_set_sampler_views(
2159         struct pipe_context *pctx,
2160         enum pipe_shader_type shader,
2161         unsigned start_slot, unsigned num_views,
2162         struct pipe_sampler_view **views)
2163 {
2164         struct panfrost_context *ctx = pan_context(pctx);
2165
2166         assert(start_slot == 0);
2167
2168         ctx->sampler_view_count[shader] = num_views;
2169         memcpy(ctx->sampler_views[shader], views, num_views * sizeof (void *));
2170
2171         ctx->dirty |= PAN_DIRTY_TEXTURES;
2172 }
2173
2174 static void
2175 panfrost_sampler_view_destroy(
2176         struct pipe_context *pctx,
2177         struct pipe_sampler_view *views)
2178 {
2179         //struct panfrost_context *ctx = pan_context(pctx);
2180
2181         /* TODO */
2182
2183         free(views);
2184 }
2185
2186 static void
2187 panfrost_set_framebuffer_state(struct pipe_context *pctx,
2188                                const struct pipe_framebuffer_state *fb)
2189 {
2190         struct panfrost_context *ctx = pan_context(pctx);
2191
2192         /* Flush when switching away from an FBO */
2193
2194         if (!panfrost_is_scanout(ctx)) {
2195                 panfrost_flush(pctx, NULL, 0);
2196         }
2197
2198         ctx->pipe_framebuffer.nr_cbufs = fb->nr_cbufs;
2199         ctx->pipe_framebuffer.samples = fb->samples;
2200         ctx->pipe_framebuffer.layers = fb->layers;
2201         ctx->pipe_framebuffer.width = fb->width;
2202         ctx->pipe_framebuffer.height = fb->height;
2203
2204         for (int i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
2205                 struct pipe_surface *cb = i < fb->nr_cbufs ? fb->cbufs[i] : NULL;
2206
2207                 /* check if changing cbuf */
2208                 if (ctx->pipe_framebuffer.cbufs[i] == cb) continue;
2209
2210                 if (cb && (i != 0)) {
2211                         printf("XXX: Multiple render targets not supported before t7xx!\n");
2212                         assert(0);
2213                 }
2214
2215                 /* assign new */
2216                 pipe_surface_reference(&ctx->pipe_framebuffer.cbufs[i], cb);
2217
2218                 if (!cb)
2219                         continue;
2220
2221                 ctx->vt_framebuffer = panfrost_emit_fbd(ctx);
2222                 panfrost_attach_vt_framebuffer(ctx);
2223                 panfrost_new_frag_framebuffer(ctx);
2224                 panfrost_set_scissor(ctx);
2225
2226                 struct panfrost_resource *tex = ((struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[i]->texture);
2227                 bool is_scanout = panfrost_is_scanout(ctx);
2228
2229                 if (!is_scanout && !tex->bo->has_afbc) {
2230                         /* The blob is aggressive about enabling AFBC. As such,
2231                          * it's pretty much necessary to use it here, since we
2232                          * have no traces of non-compressed FBO. */
2233
2234                         panfrost_enable_afbc(ctx, tex, false);
2235                 }
2236
2237                 if (!is_scanout && !tex->bo->has_checksum) {
2238                         /* Enable transaction elimination if we can */
2239                         panfrost_enable_checksum(ctx, tex);
2240                 }
2241         }
2242
2243         {
2244                 struct pipe_surface *zb = fb->zsbuf;
2245
2246                 if (ctx->pipe_framebuffer.zsbuf != zb) {
2247                         pipe_surface_reference(&ctx->pipe_framebuffer.zsbuf, zb);
2248
2249                         if (zb) {
2250                                 /* FBO has depth */
2251
2252                                 ctx->vt_framebuffer = panfrost_emit_fbd(ctx);
2253                                 panfrost_attach_vt_framebuffer(ctx);
2254                                 panfrost_new_frag_framebuffer(ctx);
2255                                 panfrost_set_scissor(ctx);
2256
2257                                 struct panfrost_resource *tex = ((struct panfrost_resource *) ctx->pipe_framebuffer.zsbuf->texture);
2258
2259                                 if (!tex->bo->has_afbc && !panfrost_is_scanout(ctx))
2260                                         panfrost_enable_afbc(ctx, tex, true);
2261                         }
2262                 }
2263         }
2264
2265         /* Force a clear XXX wrong? */
2266         if (ctx->last_clear.color)
2267                 panfrost_clear(&ctx->base, ctx->last_clear.buffers, ctx->last_clear.color, ctx->last_clear.depth, ctx->last_clear.stencil);
2268 }
2269
2270 static void *
2271 panfrost_create_blend_state(struct pipe_context *pipe,
2272                             const struct pipe_blend_state *blend)
2273 {
2274         struct panfrost_context *ctx = pan_context(pipe);
2275         struct panfrost_blend_state *so = CALLOC_STRUCT(panfrost_blend_state);
2276         so->base = *blend;
2277
2278         /* TODO: The following features are not yet implemented */
2279         assert(!blend->logicop_enable);
2280         assert(!blend->alpha_to_coverage);
2281         assert(!blend->alpha_to_one);
2282
2283         /* Compile the blend state, first as fixed-function if we can */
2284
2285         if (panfrost_make_fixed_blend_mode(&blend->rt[0], &so->equation, blend->rt[0].colormask, &ctx->blend_color))
2286                 return so;
2287
2288         /* If we can't, compile a blend shader instead */
2289
2290         panfrost_make_blend_shader(ctx, so, &ctx->blend_color);
2291
2292         return so;
2293 }
2294
2295 static void
2296 panfrost_bind_blend_state(struct pipe_context *pipe,
2297                           void *cso)
2298 {
2299         struct panfrost_context *ctx = pan_context(pipe);
2300         struct pipe_blend_state *blend = (struct pipe_blend_state *) cso;
2301         struct panfrost_blend_state *pblend = (struct panfrost_blend_state *) cso;
2302         ctx->blend = pblend;
2303
2304         if (!blend)
2305                 return;
2306
2307         SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_NO_DITHER, !blend->dither);
2308
2309         /* TODO: Attach color */
2310
2311         /* Shader itself is not dirty, but the shader core is */
2312         ctx->dirty |= PAN_DIRTY_FS;
2313 }
2314
2315 static void
2316 panfrost_delete_blend_state(struct pipe_context *pipe,
2317                             void *blend)
2318 {
2319         printf("Deleting blend state may leak blend shader\n");
2320         free(blend);
2321 }
2322
2323 static void
2324 panfrost_set_blend_color(struct pipe_context *pipe,
2325                          const struct pipe_blend_color *blend_color)
2326 {
2327         struct panfrost_context *ctx = pan_context(pipe);
2328
2329         /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2330
2331         if (blend_color) {
2332                 ctx->blend_color = *blend_color;
2333
2334                 /* The blend mode depends on the blend constant color, due to the
2335                  * fixed/programmable split. So, we're forced to regenerate the blend
2336                  * equation */
2337
2338                 /* TODO: Attach color */
2339         }
2340 }
2341
2342 static void *
2343 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
2344                                     const struct pipe_depth_stencil_alpha_state *depth_stencil)
2345 {
2346         return mem_dup(depth_stencil, sizeof(*depth_stencil));
2347 }
2348
2349 static void
2350 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
2351                                   void *cso)
2352 {
2353         struct panfrost_context *ctx = pan_context(pipe);
2354         struct pipe_depth_stencil_alpha_state *depth_stencil = cso;
2355         ctx->depth_stencil = depth_stencil;
2356
2357         if (!depth_stencil)
2358                 return;
2359
2360         /* Alpha does not exist in the hardware (it's not in ES3), so it's
2361          * emulated in the fragment shader */
2362
2363         if (depth_stencil->alpha.enabled) {
2364                 /* We need to trigger a new shader (maybe) */
2365                 ctx->base.bind_fs_state(&ctx->base, ctx->fs);
2366         }
2367
2368         /* Stencil state */
2369         SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_STENCIL_TEST, depth_stencil->stencil[0].enabled); /* XXX: which one? */
2370
2371         panfrost_make_stencil_state(&depth_stencil->stencil[0], &ctx->fragment_shader_core.stencil_front);
2372         ctx->fragment_shader_core.stencil_mask_front = depth_stencil->stencil[0].writemask;
2373
2374         panfrost_make_stencil_state(&depth_stencil->stencil[1], &ctx->fragment_shader_core.stencil_back);
2375         ctx->fragment_shader_core.stencil_mask_back = depth_stencil->stencil[1].writemask;
2376
2377         /* Depth state (TODO: Refactor) */
2378         SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_DEPTH_TEST, depth_stencil->depth.enabled);
2379
2380         int func = depth_stencil->depth.enabled ? depth_stencil->depth.func : PIPE_FUNC_ALWAYS;
2381
2382         ctx->fragment_shader_core.unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
2383         ctx->fragment_shader_core.unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func));
2384
2385         /* Bounds test not implemented */
2386         assert(!depth_stencil->depth.bounds_test);
2387
2388         ctx->dirty |= PAN_DIRTY_FS;
2389 }
2390
2391 static void
2392 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
2393 {
2394         free( depth );
2395 }
2396
2397 static void
2398 panfrost_set_sample_mask(struct pipe_context *pipe,
2399                          unsigned sample_mask)
2400 {
2401 }
2402
2403 static void
2404 panfrost_set_clip_state(struct pipe_context *pipe,
2405                         const struct pipe_clip_state *clip)
2406 {
2407         //struct panfrost_context *panfrost = pan_context(pipe);
2408 }
2409
2410 static void
2411 panfrost_set_viewport_states(struct pipe_context *pipe,
2412                              unsigned start_slot,
2413                              unsigned num_viewports,
2414                              const struct pipe_viewport_state *viewports)
2415 {
2416         struct panfrost_context *ctx = pan_context(pipe);
2417
2418         assert(start_slot == 0);
2419         assert(num_viewports == 1);
2420
2421         ctx->pipe_viewport = *viewports;
2422
2423 #if 0
2424         /* TODO: What if not centered? */
2425         float w = abs(viewports->scale[0]) * 2.0;
2426         float h = abs(viewports->scale[1]) * 2.0;
2427
2428         ctx->viewport.viewport1[0] = MALI_POSITIVE((int) w);
2429         ctx->viewport.viewport1[1] = MALI_POSITIVE((int) h);
2430 #endif
2431 }
2432
2433 static void
2434 panfrost_set_scissor_states(struct pipe_context *pipe,
2435                             unsigned start_slot,
2436                             unsigned num_scissors,
2437                             const struct pipe_scissor_state *scissors)
2438 {
2439         struct panfrost_context *ctx = pan_context(pipe);
2440
2441         assert(start_slot == 0);
2442         assert(num_scissors == 1);
2443
2444         ctx->scissor = *scissors;
2445
2446         panfrost_set_scissor(ctx);
2447 }
2448
2449 static void
2450 panfrost_set_polygon_stipple(struct pipe_context *pipe,
2451                              const struct pipe_poly_stipple *stipple)
2452 {
2453         //struct panfrost_context *panfrost = pan_context(pipe);
2454 }
2455
2456 static void
2457 panfrost_set_active_query_state(struct pipe_context *pipe,
2458                                 boolean enable)
2459 {
2460         //struct panfrost_context *panfrost = pan_context(pipe);
2461 }
2462
2463 static void
2464 panfrost_destroy(struct pipe_context *pipe)
2465 {
2466         struct panfrost_context *panfrost = pan_context(pipe);
2467
2468         if (panfrost->blitter)
2469                 util_blitter_destroy(panfrost->blitter);
2470 }
2471
2472 static struct pipe_query *
2473 panfrost_create_query(struct pipe_context *pipe,
2474                       unsigned type,
2475                       unsigned index)
2476 {
2477         struct panfrost_query *q = CALLOC_STRUCT(panfrost_query);
2478
2479         q->type = type;
2480         q->index = index;
2481
2482         return (struct pipe_query *) q;
2483 }
2484
2485 static void
2486 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
2487 {
2488         FREE(q);
2489 }
2490
2491 static boolean
2492 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
2493 {
2494         struct panfrost_context *ctx = pan_context(pipe);
2495         struct panfrost_query *query = (struct panfrost_query *) q;
2496
2497         switch (query->type) {
2498                 case PIPE_QUERY_OCCLUSION_PREDICATE:
2499                 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
2500                 {
2501                         /* Allocate a word for the query results to be stored */
2502                         query->transfer = panfrost_allocate_chunk(ctx, sizeof(unsigned), HEAP_DESCRIPTOR);
2503
2504                         ctx->occlusion_query = query;
2505
2506                         break;
2507                 }
2508
2509                 default:
2510                         fprintf(stderr, "Skipping query %d\n", query->type);
2511                         break;
2512         }
2513
2514         return true;
2515 }
2516
2517 static bool
2518 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
2519 {
2520         struct panfrost_context *ctx = pan_context(pipe);
2521         ctx->occlusion_query = NULL;
2522         return true;
2523 }
2524
2525 static boolean
2526 panfrost_get_query_result(struct pipe_context *pipe,
2527                           struct pipe_query *q,
2528                           boolean wait,
2529                           union pipe_query_result *vresult)
2530 {
2531         /* STUB */
2532         struct panfrost_query *query = (struct panfrost_query *) q;
2533
2534         /* We need to flush out the jobs to actually run the counter, TODO
2535          * check wait, TODO wallpaper after if needed */
2536
2537         panfrost_flush(pipe, NULL, PIPE_FLUSH_END_OF_FRAME);
2538
2539         switch (query->type) {
2540                 case PIPE_QUERY_OCCLUSION_PREDICATE:
2541                 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
2542                         /* Read back the query results */
2543                         unsigned *result = (unsigned *) query->transfer.cpu;
2544                         unsigned passed = *result;
2545
2546                         vresult->b = !!passed;
2547                         break;
2548                 }
2549                 default:
2550                         fprintf(stderr, "Skipped query get %d\n", query->type);
2551                         break;
2552         }
2553
2554         return true;
2555 }
2556
2557 static void
2558 panfrost_setup_hardware(struct panfrost_context *ctx)
2559 {
2560         struct pipe_context *gallium = (struct pipe_context *) ctx;
2561         struct panfrost_screen *screen = pan_screen(gallium->screen);
2562
2563         for (int i = 0; i < ARRAY_SIZE(ctx->transient_pools); ++i) {
2564                 /* Allocate the beginning of the transient pool */
2565                 int entry_size = (1 << 22); /* 4MB */
2566
2567                 ctx->transient_pools[i].entry_size = entry_size;
2568                 ctx->transient_pools[i].entry_count = 1;
2569
2570                 ctx->transient_pools[i].entries[0] = (struct panfrost_memory_entry *) pb_slab_alloc(&screen->slabs, entry_size, HEAP_TRANSIENT);
2571         }
2572
2573         screen->driver->allocate_slab(screen, &ctx->scratchpad, 64, false, 0, 0, 0);
2574         screen->driver->allocate_slab(screen, &ctx->varying_mem, 16384, false, 0, 0, 0);
2575         screen->driver->allocate_slab(screen, &ctx->shaders, 4096, true, PAN_ALLOCATE_EXECUTE, 0, 0);
2576         screen->driver->allocate_slab(screen, &ctx->tiler_heap, 32768, false, PAN_ALLOCATE_GROWABLE, 1, 128);
2577         screen->driver->allocate_slab(screen, &ctx->misc_0, 128, false, PAN_ALLOCATE_GROWABLE, 1, 128);
2578
2579 }
2580
2581 /* New context creation, which also does hardware initialisation since I don't
2582  * know the better way to structure this :smirk: */
2583
2584 struct pipe_context *
2585 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
2586 {
2587         struct panfrost_context *ctx = CALLOC_STRUCT(panfrost_context);
2588         memset(ctx, 0, sizeof(*ctx));
2589         struct pipe_context *gallium = (struct pipe_context *) ctx;
2590
2591         gallium->screen = screen;
2592
2593         gallium->destroy = panfrost_destroy;
2594
2595         gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
2596
2597         gallium->flush = panfrost_flush;
2598         gallium->clear = panfrost_clear;
2599         gallium->draw_vbo = panfrost_draw_vbo;
2600
2601         gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
2602         gallium->set_constant_buffer = panfrost_set_constant_buffer;
2603
2604         gallium->set_stencil_ref = panfrost_set_stencil_ref;
2605
2606         gallium->create_sampler_view = panfrost_create_sampler_view;
2607         gallium->set_sampler_views = panfrost_set_sampler_views;
2608         gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
2609
2610         gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
2611         gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
2612         gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
2613
2614         gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
2615         gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
2616         gallium->delete_vertex_elements_state = panfrost_delete_vertex_elements_state;
2617
2618         gallium->create_fs_state = panfrost_create_shader_state;
2619         gallium->delete_fs_state = panfrost_delete_shader_state;
2620         gallium->bind_fs_state = panfrost_bind_fs_state;
2621
2622         gallium->create_vs_state = panfrost_create_shader_state;
2623         gallium->delete_vs_state = panfrost_delete_shader_state;
2624         gallium->bind_vs_state = panfrost_bind_vs_state;
2625
2626         gallium->create_sampler_state = panfrost_create_sampler_state;
2627         gallium->delete_sampler_state = panfrost_generic_cso_delete;
2628         gallium->bind_sampler_states = panfrost_bind_sampler_states;
2629
2630         gallium->create_blend_state = panfrost_create_blend_state;
2631         gallium->bind_blend_state   = panfrost_bind_blend_state;
2632         gallium->delete_blend_state = panfrost_delete_blend_state;
2633
2634         gallium->set_blend_color = panfrost_set_blend_color;
2635
2636         gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
2637         gallium->bind_depth_stencil_alpha_state   = panfrost_bind_depth_stencil_state;
2638         gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
2639
2640         gallium->set_sample_mask = panfrost_set_sample_mask;
2641
2642         gallium->set_clip_state = panfrost_set_clip_state;
2643         gallium->set_viewport_states = panfrost_set_viewport_states;
2644         gallium->set_scissor_states = panfrost_set_scissor_states;
2645         gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
2646         gallium->set_active_query_state = panfrost_set_active_query_state;
2647
2648         gallium->create_query = panfrost_create_query;
2649         gallium->destroy_query = panfrost_destroy_query;
2650         gallium->begin_query = panfrost_begin_query;
2651         gallium->end_query = panfrost_end_query;
2652         gallium->get_query_result = panfrost_get_query_result;
2653
2654         panfrost_resource_context_init(gallium);
2655
2656         panfrost_setup_hardware(ctx);
2657
2658         /* XXX: leaks */
2659         gallium->stream_uploader = u_upload_create_default(gallium);
2660         gallium->const_uploader = gallium->stream_uploader;
2661         assert(gallium->stream_uploader);
2662
2663         /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2664         ctx->draw_modes = (1 << (PIPE_PRIM_POLYGON + 1)) - 1;
2665
2666         ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
2667
2668         ctx->blitter = util_blitter_create(gallium);
2669         assert(ctx->blitter);
2670
2671         /* Prepare for render! */
2672
2673         /* TODO: XXX */
2674         ctx->vt_framebuffer = panfrost_emit_fbd(ctx);
2675
2676         panfrost_emit_vertex_payload(ctx);
2677         panfrost_emit_tiler_payload(ctx);
2678         panfrost_invalidate_frame(ctx);
2679         panfrost_viewport(ctx, 0.0, 1.0, 0, 0, ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height);
2680         panfrost_default_shader_backend(ctx);
2681         panfrost_generate_space_filler_indices();
2682
2683         return gallium;
2684 }