2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
45 #include "pan_wallpaper.h"
47 static int performance_counter_number
= 0;
48 extern const char *pan_counters_base
;
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 #define SET_BIT(lval, bit, cond) \
59 /* TODO: Sample size, etc */
62 panfrost_set_framebuffer_msaa(struct panfrost_context
*ctx
, bool enabled
)
64 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, enabled
);
65 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !enabled
);
67 if (ctx
->require_sfbd
) {
68 SET_BIT(ctx
->fragment_sfbd
.format
, MALI_FRAMEBUFFER_MSAA_A
| MALI_FRAMEBUFFER_MSAA_B
, enabled
);
70 SET_BIT(ctx
->fragment_rts
[0].format
.flags
, MALI_MFBD_FORMAT_MSAA
, enabled
);
72 SET_BIT(ctx
->fragment_mfbd
.unk1
, (1 << 4) | (1 << 1), enabled
);
75 ctx
->fragment_mfbd
.rt_count_2
= enabled
? 4 : 1;
79 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
80 * indepdent between color buffers and depth/stencil). To enable, we allocate
81 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
82 * edit the fragment job here. This routine should be called ONCE per
83 * AFBC-compressed buffer, rather than on every frame. */
86 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
88 if (ctx
->require_sfbd
) {
89 DBG("AFBC not supported yet on SFBD\n");
93 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
94 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
95 /* AFBC metadata is 16 bytes per tile */
96 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
97 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
98 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
99 int stride
= bytes_per_pixel
* rsrc
->base
.width0
; /* TODO: Alignment? */
101 stride
*= 2; /* TODO: Should this be carried over? */
102 int main_size
= stride
* rsrc
->base
.height0
;
103 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
105 /* Allocate the AFBC slab itself, large enough to hold the above */
106 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
107 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
110 rsrc
->bo
->layout
= PAN_AFBC
;
112 /* Compressed textured reads use a tagged pointer to the metadata */
114 rsrc
->bo
->gpu
[0] = rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
115 rsrc
->bo
->cpu
[0] = rsrc
->bo
->afbc_slab
.cpu
;
119 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
121 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
122 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
123 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
124 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
126 /* 8 byte checksum per tile */
127 rsrc
->bo
->checksum_stride
= tile_w
* 8;
128 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
129 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
131 rsrc
->bo
->has_checksum
= true;
135 panfrost_sfbd_format_for_surface(struct pipe_surface
*surf
)
138 return 0xb84e0281; /* RGB32, no MSAA */
141 static struct mali_rt_format
142 panfrost_mfbd_format_for_surface(struct pipe_surface
*surf
)
144 /* Explode details on the format */
146 const struct util_format_description
*desc
=
147 util_format_description(surf
->texture
->format
);
149 /* Fill in accordingly */
151 struct mali_rt_format fmt
= {
154 .nr_channels
= MALI_POSITIVE(desc
->nr_channels
),
156 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
163 static bool panfrost_is_scanout(struct panfrost_context
*ctx
);
165 /* These routines link a fragment job with the bound surface, accounting for the
166 * BO layout. This routine runs per-frame */
169 panfrost_set_fragment_target_cbuf(
170 struct panfrost_context
*ctx
,
171 struct pipe_surface
*surf
,
174 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
177 util_format_get_stride(surf
->format
, surf
->texture
->width0
);
179 /* First, we set the format bits */
181 if (ctx
->require_sfbd
) {
182 ctx
->fragment_sfbd
.format
=
183 panfrost_sfbd_format_for_surface(surf
);
185 ctx
->fragment_rts
[cb
].format
=
186 panfrost_mfbd_format_for_surface(surf
);
189 /* Now, we set the layout specific pieces */
191 if (rsrc
->bo
->layout
== PAN_LINEAR
) {
192 mali_ptr framebuffer
= rsrc
->bo
->gpu
[0];
194 /* The default is upside down from OpenGL's perspective. */
195 if (panfrost_is_scanout(ctx
)) {
196 framebuffer
+= stride
* (surf
->texture
->height0
- 1);
200 if (ctx
->require_sfbd
) {
201 ctx
->fragment_sfbd
.framebuffer
= framebuffer
;
202 ctx
->fragment_sfbd
.stride
= stride
;
204 /* MFBD specifies stride in tiles */
205 ctx
->fragment_rts
[cb
].framebuffer
= framebuffer
;
206 ctx
->fragment_rts
[cb
].framebuffer_stride
= stride
/ 16;
208 } else if (rsrc
->bo
->layout
== PAN_AFBC
) {
209 /* TODO: AFBC on SFBD */
210 assert(!ctx
->require_sfbd
);
212 /* Enable AFBC for the render target */
213 ctx
->fragment_rts
[cb
].afbc
.metadata
= rsrc
->bo
->afbc_slab
.gpu
;
214 ctx
->fragment_rts
[cb
].afbc
.stride
= 0;
215 ctx
->fragment_rts
[cb
].afbc
.unk
= 0x30009;
217 ctx
->fragment_rts
[cb
].format
.flags
|= MALI_MFBD_FORMAT_AFBC
;
219 mali_ptr afbc_main
= rsrc
->bo
->afbc_slab
.gpu
+ rsrc
->bo
->afbc_metadata_size
;
220 ctx
->fragment_rts
[cb
].framebuffer
= afbc_main
;
222 /* TODO: Investigate shift */
223 ctx
->fragment_rts
[cb
].framebuffer_stride
= stride
<< 1;
225 fprintf(stderr
, "Invalid render layout (cbuf %d)", cb
);
231 panfrost_set_fragment_target(struct panfrost_context
*ctx
)
233 for (int cb
= 0; cb
< ctx
->pipe_framebuffer
.nr_cbufs
; ++cb
) {
234 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[cb
];
235 panfrost_set_fragment_target_cbuf(ctx
, surf
, cb
);
238 /* Enable depth/stencil AFBC for the framebuffer (not the render target) */
239 if (ctx
->pipe_framebuffer
.zsbuf
) {
240 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
;
242 if (rsrc
->bo
->layout
== PAN_AFBC
) {
243 if (ctx
->require_sfbd
) {
244 DBG("Depth AFBC not supported on SFBD\n");
248 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
250 ctx
->fragment_extra
.ds_afbc
.depth_stencil_afbc_metadata
= rsrc
->bo
->afbc_slab
.gpu
;
251 ctx
->fragment_extra
.ds_afbc
.depth_stencil_afbc_stride
= 0;
253 ctx
->fragment_extra
.ds_afbc
.depth_stencil
= rsrc
->bo
->afbc_slab
.gpu
+ rsrc
->bo
->afbc_metadata_size
;
255 ctx
->fragment_extra
.ds_afbc
.zero1
= 0x10009;
256 ctx
->fragment_extra
.ds_afbc
.padding
= 0x1000;
258 ctx
->fragment_extra
.unk
= 0x435; /* General 0x400 in all unks. 0x5 for depth/stencil. 0x10 for AFBC encoded depth stencil. Unclear where the 0x20 is from */
260 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_DEPTH_WRITE
;
264 /* For the special case of a depth-only FBO, we need to attach a dummy render target */
266 if (ctx
->pipe_framebuffer
.nr_cbufs
== 0) {
267 if (ctx
->require_sfbd
) {
268 DBG("Depth-only FBO not supported on SFBD\n");
272 struct mali_rt_format null_rt
= {
277 ctx
->fragment_rts
[0].format
= null_rt
;
278 ctx
->fragment_rts
[0].framebuffer
= 0;
279 ctx
->fragment_rts
[0].framebuffer_stride
= 0;
283 /* Framebuffer descriptor */
286 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
288 fb
->width
= MALI_POSITIVE(w
);
289 fb
->height
= MALI_POSITIVE(h
);
291 /* No idea why this is needed, but it's how resolution_check is
292 * calculated. It's not clear to us yet why the hardware wants this.
293 * The formula itself was discovered mostly by manual bruteforce and
294 * aggressive algebraic simplification. */
296 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
299 static struct mali_single_framebuffer
300 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
302 struct mali_single_framebuffer framebuffer
= {
304 .format
= 0x30000000,
305 .clear_flags
= 0x1000,
306 .unknown_address_0
= ctx
->scratchpad
.gpu
,
307 .unknown_address_1
= ctx
->misc_0
.gpu
,
308 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
310 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
311 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
314 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
319 static struct bifrost_framebuffer
320 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
322 struct bifrost_framebuffer framebuffer
= {
323 /* It is not yet clear what tiler_meta means or how it's
324 * calculated, but we can tell the lower 32-bits are a
325 * (monotonically increasing?) function of tile count and
326 * geometry complexity; I suspect it defines a memory size of
327 * some kind? for the tiler. It's really unclear at the
328 * moment... but to add to the confusion, the hardware is happy
329 * enough to accept a zero in this field, so we don't even have
330 * to worry about it right now.
332 * The byte (just after the 32-bit mark) is much more
333 * interesting. The higher nibble I've only ever seen as 0xF,
334 * but the lower one I've seen as 0x0 or 0xF, and it's not
335 * obvious what the difference is. But what -is- obvious is
336 * that when the lower nibble is zero, performance is severely
337 * degraded compared to when the lower nibble is set.
338 * Evidently, that nibble enables some sort of fast path,
339 * perhaps relating to caching or tile flush? Regardless, at
340 * this point there's no clear reason not to set it, aside from
341 * substantially increased memory requirements (of the misc_0
344 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
346 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
347 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
348 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
349 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
354 .rt_count_1
= MALI_POSITIVE(1),
359 /* Corresponds to unknown_address_X of SFBD */
360 .scratchpad
= ctx
->scratchpad
.gpu
,
361 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
363 /* The constant added here is, like the lower word of
364 * tiler_meta, (loosely) another product of framebuffer size
365 * and geometry complexity. It must be sufficiently large for
366 * the tiler_meta fast path to work; if it's too small, there
367 * will be DATA_INVALID_FAULTs. Conversely, it must be less
368 * than the total size of misc_0, or else there's no room. It's
369 * possible this constant configures a partition between two
370 * parts of misc_0? We haven't investigated the functionality,
371 * as these buffers are internally used by the hardware
372 * (presumably by the tiler) but not seemingly touched by the driver
375 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
377 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
378 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
384 /* Are we currently rendering to the screen (rather than an FBO)? */
387 panfrost_is_scanout(struct panfrost_context
*ctx
)
389 /* If there is no color buffer, it's an FBO */
390 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
393 /* If we're too early that no framebuffer was sent, it's scanout */
394 if (!ctx
->pipe_framebuffer
.cbufs
[0])
397 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
398 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
399 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
402 /* The above function is for generalised fbd emission, used in both fragment as
403 * well as vertex/tiler payloads. This payload is specific to fragment
407 panfrost_new_frag_framebuffer(struct panfrost_context
*ctx
)
409 if (ctx
->require_sfbd
) {
410 struct mali_single_framebuffer fb
= panfrost_emit_sfbd(ctx
);
411 memcpy(&ctx
->fragment_sfbd
, &fb
, sizeof(fb
));
413 struct bifrost_framebuffer fb
= panfrost_emit_mfbd(ctx
);
419 struct bifrost_render_target rt
= {};
421 memcpy(&ctx
->fragment_rts
[0], &rt
, sizeof(rt
));
422 memset(&ctx
->fragment_extra
, 0, sizeof(ctx
->fragment_extra
));
423 memcpy(&ctx
->fragment_mfbd
, &fb
, sizeof(fb
));
427 /* Maps float 0.0-1.0 to int 0x00-0xFF */
429 normalised_float_to_u8(float f
)
431 return (uint8_t) (int) (f
* 255.0f
);
435 panfrost_clear_sfbd(struct panfrost_job
*job
)
437 struct panfrost_context
*ctx
= job
->ctx
;
438 struct mali_single_framebuffer
*sfbd
= &ctx
->fragment_sfbd
;
440 if (job
->clear
& PIPE_CLEAR_COLOR
) {
441 sfbd
->clear_color_1
= job
->clear_color
;
442 sfbd
->clear_color_2
= job
->clear_color
;
443 sfbd
->clear_color_3
= job
->clear_color
;
444 sfbd
->clear_color_4
= job
->clear_color
;
447 if (job
->clear
& PIPE_CLEAR_DEPTH
) {
448 sfbd
->clear_depth_1
= job
->clear_depth
;
449 sfbd
->clear_depth_2
= job
->clear_depth
;
450 sfbd
->clear_depth_3
= job
->clear_depth
;
451 sfbd
->clear_depth_4
= job
->clear_depth
;
453 sfbd
->depth_buffer
= ctx
->depth_stencil_buffer
.gpu
;
454 sfbd
->depth_buffer_enable
= MALI_DEPTH_STENCIL_ENABLE
;
457 if (job
->clear
& PIPE_CLEAR_STENCIL
) {
458 sfbd
->clear_stencil
= job
->clear_stencil
;
460 sfbd
->stencil_buffer
= ctx
->depth_stencil_buffer
.gpu
;
461 sfbd
->stencil_buffer_enable
= MALI_DEPTH_STENCIL_ENABLE
;
464 /* Set flags based on what has been cleared, for the SFBD case */
465 /* XXX: What do these flags mean? */
466 int clear_flags
= 0x101100;
468 if (!(job
->clear
& ~(PIPE_CLEAR_COLOR
| PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
))) {
469 /* On a tiler like this, it's fastest to clear all three buffers at once */
471 clear_flags
|= MALI_CLEAR_FAST
;
473 clear_flags
|= MALI_CLEAR_SLOW
;
475 if (job
->clear
& PIPE_CLEAR_STENCIL
)
476 clear_flags
|= MALI_CLEAR_SLOW_STENCIL
;
479 sfbd
->clear_flags
= clear_flags
;
483 panfrost_clear_mfbd(struct panfrost_job
*job
)
485 struct panfrost_context
*ctx
= job
->ctx
;
486 struct bifrost_render_target
*buffer_color
= &ctx
->fragment_rts
[0];
487 struct bifrost_framebuffer
*buffer_ds
= &ctx
->fragment_mfbd
;
489 if (job
->clear
& PIPE_CLEAR_COLOR
) {
490 buffer_color
->clear_color_1
= job
->clear_color
;
491 buffer_color
->clear_color_2
= job
->clear_color
;
492 buffer_color
->clear_color_3
= job
->clear_color
;
493 buffer_color
->clear_color_4
= job
->clear_color
;
496 if (job
->clear
& PIPE_CLEAR_DEPTH
) {
497 buffer_ds
->clear_depth
= job
->clear_depth
;
500 if (job
->clear
& PIPE_CLEAR_STENCIL
) {
501 buffer_ds
->clear_stencil
= job
->clear_stencil
;
504 if (job
->clear
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
505 /* Setup combined 24/8 depth/stencil */
506 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
507 ctx
->fragment_extra
.unk
= 0x405;
508 ctx
->fragment_extra
.ds_linear
.depth
= ctx
->depth_stencil_buffer
.gpu
;
509 ctx
->fragment_extra
.ds_linear
.depth_stride
= ctx
->pipe_framebuffer
.width
* 4;
515 struct pipe_context
*pipe
,
517 const union pipe_color_union
*color
,
518 double depth
, unsigned stencil
)
520 struct panfrost_context
*ctx
= pan_context(pipe
);
521 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
523 if (buffers
& PIPE_CLEAR_COLOR
) {
524 /* Alpha clear only meaningful without alpha channel, TODO less ad hoc */
525 bool has_alpha
= util_format_has_alpha(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
526 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
528 uint32_t packed_color
=
529 (normalised_float_to_u8(clear_alpha
) << 24) |
530 (normalised_float_to_u8(color
->f
[2]) << 16) |
531 (normalised_float_to_u8(color
->f
[1]) << 8) |
532 (normalised_float_to_u8(color
->f
[0]) << 0);
534 job
->clear_color
= packed_color
;
538 if (buffers
& PIPE_CLEAR_DEPTH
) {
539 job
->clear_depth
= depth
;
542 if (buffers
& PIPE_CLEAR_STENCIL
) {
543 job
->clear_stencil
= stencil
;
546 job
->clear
|= buffers
;
550 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
552 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
553 struct bifrost_render_target rts_list
[] = {
558 .framebuffer
= ctx
->misc_0
.gpu
,
563 /* Allocate memory for the three components */
564 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
565 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
567 /* Opaque 1024-block */
568 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
570 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
571 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
573 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
577 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
579 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
583 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
585 mali_ptr framebuffer
= ctx
->require_sfbd
?
586 panfrost_attach_vt_sfbd(ctx
) :
587 panfrost_attach_vt_mfbd(ctx
);
589 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
590 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
594 panfrost_viewport(struct panfrost_context
*ctx
,
595 float depth_clip_near
,
596 float depth_clip_far
,
597 int viewport_x0
, int viewport_y0
,
598 int viewport_x1
, int viewport_y1
)
600 /* Clip bounds are encoded as floats. The viewport itself is encoded as
601 * (somewhat) asymmetric ints. */
603 struct mali_viewport ret
= {
604 /* By default, do no viewport clipping, i.e. clip to (-inf,
605 * inf) in each direction. Clipping to the viewport in theory
606 * should work, but in practice causes issues when we're not
607 * explicitly trying to scissor */
614 /* We always perform depth clipping (TODO: Can this be disabled?) */
616 .clip_minz
= depth_clip_near
,
617 .clip_maxz
= depth_clip_far
,
619 .viewport0
= { viewport_x0
, viewport_y0
},
620 .viewport1
= { MALI_POSITIVE(viewport_x1
), MALI_POSITIVE(viewport_y1
) },
623 memcpy(ctx
->viewport
, &ret
, sizeof(ret
));
626 /* Reset per-frame context, called on context initialisation as well as after
627 * flushing a frame */
630 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
632 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
633 DBG("Uploaded transient %d bytes\n", transient_count
);
635 /* Rotate cmdstream */
636 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
637 ctx
->cmdstream_i
= 0;
639 if (ctx
->require_sfbd
)
640 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
642 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
644 panfrost_new_frag_framebuffer(ctx
);
646 /* Reset varyings allocated */
647 ctx
->varying_height
= 0;
649 /* The transient cmdstream is dirty every frame; the only bits worth preserving
650 * (textures, shaders, etc) are in other buffers anyways */
652 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
653 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
655 /* Regenerate payloads */
656 panfrost_attach_vt_framebuffer(ctx
);
659 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
662 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
665 /* In practice, every field of these payloads should be configurable
666 * arbitrarily, which means these functions are basically catch-all's for
667 * as-of-yet unwavering unknowns */
670 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
672 struct midgard_payload_vertex_tiler payload
= {
674 .workgroups_z_shift
= 32,
675 .workgroups_x_shift_2
= 0x2,
676 .workgroups_x_shift_3
= 0x5,
678 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
681 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
685 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
687 struct midgard_payload_vertex_tiler payload
= {
689 .workgroups_z_shift
= 32,
690 .workgroups_x_shift_2
= 0x2,
691 .workgroups_x_shift_3
= 0x6,
693 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
697 /* Reserve the viewport */
698 struct panfrost_transfer t
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_viewport
), HEAP_DESCRIPTOR
);
699 ctx
->viewport
= (struct mali_viewport
*) t
.cpu
;
700 payload
.postfix
.viewport
= t
.gpu
;
702 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
706 translate_tex_wrap(enum pipe_tex_wrap w
)
709 case PIPE_TEX_WRAP_REPEAT
:
710 return MALI_WRAP_REPEAT
;
712 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
713 return MALI_WRAP_CLAMP_TO_EDGE
;
715 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
716 return MALI_WRAP_CLAMP_TO_BORDER
;
718 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
719 return MALI_WRAP_MIRRORED_REPEAT
;
728 translate_tex_filter(enum pipe_tex_filter f
)
731 case PIPE_TEX_FILTER_NEAREST
:
734 case PIPE_TEX_FILTER_LINEAR
:
744 translate_mip_filter(enum pipe_tex_mipfilter f
)
746 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
750 panfrost_translate_compare_func(enum pipe_compare_func in
)
753 case PIPE_FUNC_NEVER
:
754 return MALI_FUNC_NEVER
;
757 return MALI_FUNC_LESS
;
759 case PIPE_FUNC_EQUAL
:
760 return MALI_FUNC_EQUAL
;
762 case PIPE_FUNC_LEQUAL
:
763 return MALI_FUNC_LEQUAL
;
765 case PIPE_FUNC_GREATER
:
766 return MALI_FUNC_GREATER
;
768 case PIPE_FUNC_NOTEQUAL
:
769 return MALI_FUNC_NOTEQUAL
;
771 case PIPE_FUNC_GEQUAL
:
772 return MALI_FUNC_GEQUAL
;
774 case PIPE_FUNC_ALWAYS
:
775 return MALI_FUNC_ALWAYS
;
779 return 0; /* Unreachable */
783 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
786 case PIPE_FUNC_NEVER
:
787 return MALI_ALT_FUNC_NEVER
;
790 return MALI_ALT_FUNC_LESS
;
792 case PIPE_FUNC_EQUAL
:
793 return MALI_ALT_FUNC_EQUAL
;
795 case PIPE_FUNC_LEQUAL
:
796 return MALI_ALT_FUNC_LEQUAL
;
798 case PIPE_FUNC_GREATER
:
799 return MALI_ALT_FUNC_GREATER
;
801 case PIPE_FUNC_NOTEQUAL
:
802 return MALI_ALT_FUNC_NOTEQUAL
;
804 case PIPE_FUNC_GEQUAL
:
805 return MALI_ALT_FUNC_GEQUAL
;
807 case PIPE_FUNC_ALWAYS
:
808 return MALI_ALT_FUNC_ALWAYS
;
812 return 0; /* Unreachable */
816 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
819 case PIPE_STENCIL_OP_KEEP
:
820 return MALI_STENCIL_KEEP
;
822 case PIPE_STENCIL_OP_ZERO
:
823 return MALI_STENCIL_ZERO
;
825 case PIPE_STENCIL_OP_REPLACE
:
826 return MALI_STENCIL_REPLACE
;
828 case PIPE_STENCIL_OP_INCR
:
829 return MALI_STENCIL_INCR
;
831 case PIPE_STENCIL_OP_DECR
:
832 return MALI_STENCIL_DECR
;
834 case PIPE_STENCIL_OP_INCR_WRAP
:
835 return MALI_STENCIL_INCR_WRAP
;
837 case PIPE_STENCIL_OP_DECR_WRAP
:
838 return MALI_STENCIL_DECR_WRAP
;
840 case PIPE_STENCIL_OP_INVERT
:
841 return MALI_STENCIL_INVERT
;
845 return 0; /* Unreachable */
849 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
851 out
->ref
= 0; /* Gallium gets it from elsewhere */
853 out
->mask
= in
->valuemask
;
854 out
->func
= panfrost_translate_compare_func(in
->func
);
855 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
856 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
857 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
861 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
863 struct mali_shader_meta shader
= {
864 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
866 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
867 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
871 shader
.unknown2_4
|= 0x10;
874 struct pipe_stencil_state default_stencil
= {
876 .func
= PIPE_FUNC_ALWAYS
,
877 .fail_op
= MALI_STENCIL_KEEP
,
878 .zfail_op
= MALI_STENCIL_KEEP
,
879 .zpass_op
= MALI_STENCIL_KEEP
,
884 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
885 shader
.stencil_mask_front
= default_stencil
.writemask
;
887 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
888 shader
.stencil_mask_back
= default_stencil
.writemask
;
890 if (default_stencil
.enabled
)
891 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
893 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
896 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
897 * graphics command stream. It should be called once per draw, accordding to
898 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
899 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
902 struct panfrost_transfer
903 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
905 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
906 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
908 struct mali_job_descriptor_header job
= {
909 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
910 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
912 .job_descriptor_size
= 1,
916 /* Only non-elided tiler jobs have dependencies which are known at this point */
918 if (is_tiler
&& !is_elided_tiler
) {
919 /* Tiler jobs depend on vertex jobs */
921 job
.job_dependency_index_1
= draw_job_index
;
923 /* Tiler jobs also depend on the previous tiler job */
926 job
.job_dependency_index_2
= draw_job_index
- 1;
929 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
931 /* There's some padding hacks on 32-bit */
938 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
939 memcpy(transfer
.cpu
, &job
, sizeof(job
));
940 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
944 /* Generates a set value job. It's unclear what exactly this does, why it's
945 * necessary, and when to call it. */
948 panfrost_set_value_job(struct panfrost_context
*ctx
)
950 struct mali_job_descriptor_header job
= {
951 .job_type
= JOB_TYPE_SET_VALUE
,
952 .job_descriptor_size
= 1,
953 .job_index
= 1 + (2 * ctx
->draw_count
),
956 struct mali_payload_set_value payload
= {
957 .out
= ctx
->misc_0
.gpu
,
961 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
962 memcpy(transfer
.cpu
, &job
, sizeof(job
));
963 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
965 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
966 ctx
->set_value_job
= transfer
.gpu
;
969 /* Generate a fragment job. This should be called once per frame. (According to
970 * presentations, this is supposed to correspond to eglSwapBuffers) */
973 panfrost_fragment_job(struct panfrost_context
*ctx
)
975 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
977 /* Actualize the clear late; TODO: Fix order dependency between clear
980 if (ctx
->require_sfbd
) {
981 panfrost_clear_sfbd(job
);
983 panfrost_clear_mfbd(job
);
986 panfrost_set_fragment_target(ctx
);
988 if (ctx
->pipe_framebuffer
.nr_cbufs
== 1) {
989 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[0]->texture
;
991 if (rsrc
->bo
->has_checksum
) {
992 if (ctx
->require_sfbd
) {
993 DBG("Checksumming not supported on SFBD\n");
997 int stride
= util_format_get_stride(rsrc
->base
.format
, rsrc
->base
.width0
);
999 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
1000 ctx
->fragment_extra
.unk
|= 0x420;
1001 ctx
->fragment_extra
.checksum_stride
= rsrc
->bo
->checksum_stride
;
1002 ctx
->fragment_extra
.checksum
= rsrc
->bo
->gpu
[0] + stride
* rsrc
->base
.height0
;
1006 /* The frame is complete and therefore the framebuffer descriptor is
1007 * ready for linkage and upload */
1009 size_t sz
= ctx
->require_sfbd
? sizeof(struct mali_single_framebuffer
) : (sizeof(struct bifrost_framebuffer
) + sizeof(struct bifrost_fb_extra
) + sizeof(struct bifrost_render_target
) * 1);
1010 struct panfrost_transfer fbd_t
= panfrost_allocate_transient(ctx
, sz
);
1013 if (ctx
->require_sfbd
) {
1014 /* Upload just the SFBD all at once */
1015 memcpy(fbd_t
.cpu
, &ctx
->fragment_sfbd
, sizeof(ctx
->fragment_sfbd
));
1016 offset
+= sizeof(ctx
->fragment_sfbd
);
1018 /* Upload the MFBD header */
1019 memcpy(fbd_t
.cpu
, &ctx
->fragment_mfbd
, sizeof(ctx
->fragment_mfbd
));
1020 offset
+= sizeof(ctx
->fragment_mfbd
);
1022 /* Upload extra framebuffer info if necessary */
1023 if (ctx
->fragment_mfbd
.unk3
& MALI_MFBD_EXTRA
) {
1024 memcpy(fbd_t
.cpu
+ offset
, &ctx
->fragment_extra
, sizeof(struct bifrost_fb_extra
));
1025 offset
+= sizeof(struct bifrost_fb_extra
);
1028 /* Upload (single) render target */
1029 memcpy(fbd_t
.cpu
+ offset
, &ctx
->fragment_rts
[0], sizeof(struct bifrost_render_target
) * 1);
1032 /* Generate the fragment (frame) job */
1034 struct mali_job_descriptor_header header
= {
1035 .job_type
= JOB_TYPE_FRAGMENT
,
1038 .job_descriptor_size
= 1
1042 struct mali_payload_fragment payload
= {
1043 .min_tile_coord
= MALI_COORDINATE_TO_TILE_MIN(0, 0),
1044 .max_tile_coord
= MALI_COORDINATE_TO_TILE_MAX(ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
),
1045 .framebuffer
= fbd_t
.gpu
| (ctx
->require_sfbd
? MALI_SFBD
: MALI_MFBD
),
1048 if (!ctx
->require_sfbd
&& ctx
->fragment_mfbd
.unk3
& MALI_MFBD_EXTRA
) {
1049 /* Signal that there is an extra portion of the framebuffer
1052 payload
.framebuffer
|= 2;
1055 /* Normally, there should be no padding. However, fragment jobs are
1056 * shared with 64-bit Bifrost systems, and accordingly there is 4-bytes
1057 * of zero padding in between. */
1059 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(header
) + sizeof(payload
));
1060 memcpy(transfer
.cpu
, &header
, sizeof(header
));
1061 memcpy(transfer
.cpu
+ sizeof(header
), &payload
, sizeof(payload
));
1062 return transfer
.gpu
;
1065 /* Emits attributes and varying descriptors, which should be called every draw,
1066 * excepting some obscure circumstances */
1069 panfrost_emit_vertex_data(struct panfrost_context
*ctx
)
1071 /* TODO: Only update the dirtied buffers */
1072 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
1073 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
1075 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
1077 for (int i
= 0; i
< ctx
->vertex_buffer_count
; ++i
) {
1078 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
1079 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
1081 /* Let's figure out the layout of the attributes in memory so
1082 * we can be smart about size computation. The idea is to
1083 * figure out the maximum src_offset, which tells us the latest
1084 * spot a vertex could start. Meanwhile, we figure out the size
1085 * of the attribute memory (assuming interleaved
1086 * representation) and tack on the max src_offset for a
1087 * reasonably good upper bound on the size.
1089 * Proving correctness is left as an exercise to the reader.
1092 unsigned max_src_offset
= 0;
1094 for (unsigned j
= 0; j
< ctx
->vertex
->num_elements
; ++j
) {
1095 if (ctx
->vertex
->pipe
[j
].vertex_buffer_index
!= i
) continue;
1096 max_src_offset
= MAX2(max_src_offset
, ctx
->vertex
->pipe
[j
].src_offset
);
1099 /* Offset vertex count by draw_start to make sure we upload enough */
1100 attrs
[i
].stride
= buf
->stride
;
1101 attrs
[i
].size
= buf
->stride
* (ctx
->payload_vertex
.draw_start
+ invocation_count
) + max_src_offset
;
1103 /* Vertex elements are -already- GPU-visible, at
1104 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
1105 * it is not, for now we have to duplicate the buffer. */
1107 mali_ptr effective_address
= (rsrc
->bo
->gpu
[0] + buf
->buffer_offset
);
1109 if (effective_address
& 0x3F) {
1110 attrs
[i
].elements
= panfrost_upload_transient(ctx
, rsrc
->bo
->cpu
[0] + buf
->buffer_offset
, attrs
[i
].size
) | 1;
1112 attrs
[i
].elements
= effective_address
| 1;
1116 struct panfrost_varyings
*vars
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
1118 for (int i
= 0; i
< vars
->varying_buffer_count
; ++i
) {
1119 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
1121 varyings
[i
].elements
= varying_address
| 1;
1122 varyings
[i
].stride
= vars
->varyings_stride
[i
];
1123 varyings
[i
].size
= vars
->varyings_stride
[i
] * invocation_count
;
1125 /* If this varying has to be linked somewhere, do it now. See
1126 * pan_assemble.c for the indices. TODO: Use a more generic
1127 * linking interface */
1131 ctx
->payload_tiler
.postfix
.position_varying
= varying_address
;
1132 } else if (i
== 2) {
1134 ctx
->payload_tiler
.primitive_size
.pointer
= varying_address
;
1137 /* Varyings appear to need 64-byte alignment */
1138 ctx
->varying_height
+= ALIGN(varyings
[i
].size
, 64);
1140 /* Ensure that we fit */
1141 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
1144 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, ctx
->vertex_buffer_count
* sizeof(union mali_attr
));
1146 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, vars
->varying_buffer_count
* sizeof(union mali_attr
));
1147 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
1148 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
1151 /* Go through dirty flags and actualise them in the cmdstream. */
1154 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1156 if (with_vertex_data
) {
1157 panfrost_emit_vertex_data(ctx
);
1160 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1161 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1162 panfrost_set_framebuffer_msaa(ctx
, ctx
->rasterizer
->base
.multisample
);
1165 if (ctx
->occlusion_query
) {
1166 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1167 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1170 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1173 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1175 /* Late shader descriptor assignments */
1176 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1177 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1180 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1182 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1184 /* Varying descriptor is tied to the vertex shader. Also the
1185 * fragment shader, I suppose, but it's generated with the
1186 * vertex shader so */
1188 struct panfrost_varyings
*varyings
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
1190 ctx
->payload_vertex
.postfix
.varying_meta
= varyings
->varyings_descriptor
;
1191 ctx
->payload_tiler
.postfix
.varying_meta
= varyings
->varyings_descriptor_fragment
;
1194 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1195 /* Check if we need to link the gl_PointSize varying */
1197 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1199 bool needs_gl_point_size
= vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
1201 if (!needs_gl_point_size
) {
1202 /* If the size is constant, write it out. Otherwise,
1203 * don't touch primitive_size (since we would clobber
1204 * the pointer there) */
1206 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1209 /* Set the flag for varying (pointer) point size if the shader needs that */
1210 SET_BIT(ctx
->payload_tiler
.prefix
.unknown_draw
, MALI_DRAW_VARYING_SIZE
, needs_gl_point_size
);
1213 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1215 ctx
->dirty
|= PAN_DIRTY_FS
;
1217 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1219 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1221 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1224 COPY(attribute_count
);
1225 COPY(varying_count
);
1226 COPY(midgard1
.uniform_count
);
1227 COPY(midgard1
.work_count
);
1228 COPY(midgard1
.unknown2
);
1231 /* If there is a blend shader, work registers are shared */
1233 if (ctx
->blend
->has_blend_shader
)
1234 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1236 /* Set late due to depending on render state */
1237 /* The one at the end seems to mean "1 UBO" */
1238 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1240 /* Assign texture/sample count right before upload */
1241 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1242 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1244 /* Assign the stencil refs late */
1245 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1246 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1248 /* CAN_DISCARD should be set if the fragment shader possibly
1249 * contains a 'discard' instruction. It is likely this is
1250 * related to optimizations related to forward-pixel kill, as
1251 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1252 * thing?" by Peter Harris
1255 if (variant
->can_discard
) {
1256 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1257 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1258 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1259 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1262 /* Check if we're using the default blend descriptor (fast path) */
1265 !ctx
->blend
->has_blend_shader
&&
1266 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1267 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1268 (ctx
->blend
->equation
.color_mask
== 0xf);
1270 if (ctx
->require_sfbd
) {
1271 /* When only a single render target platform is used, the blend
1272 * information is inside the shader meta itself. We
1273 * additionally need to signal CAN_DISCARD for nontrivial blend
1274 * modes (so we're able to read back the destination buffer) */
1276 if (ctx
->blend
->has_blend_shader
) {
1277 ctx
->fragment_shader_core
.blend_shader
= ctx
->blend
->blend_shader
;
1279 memcpy(&ctx
->fragment_shader_core
.blend_equation
, &ctx
->blend
->equation
, sizeof(ctx
->blend
->equation
));
1283 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1287 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct mali_blend_meta
);
1288 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1289 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1291 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1293 if (!ctx
->require_sfbd
) {
1294 /* Additional blend descriptor tacked on for jobs using MFBD */
1296 unsigned blend_count
= 0;
1298 if (ctx
->blend
->has_blend_shader
) {
1299 /* For a blend shader, the bottom nibble corresponds to
1300 * the number of work registers used, which signals the
1301 * -existence- of a blend shader */
1303 assert(ctx
->blend
->blend_work_count
>= 2);
1304 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1306 /* Otherwise, the bottom bit simply specifies if
1307 * blending (anything other than REPLACE) is enabled */
1314 /* Second blend equation is always a simple replace */
1316 uint64_t replace_magic
= 0xf0122122;
1317 struct mali_blend_equation replace_mode
;
1318 memcpy(&replace_mode
, &replace_magic
, sizeof(replace_mode
));
1320 struct mali_blend_meta blend_meta
[] = {
1322 .unk1
= 0x200 | blend_count
,
1323 .blend_equation_1
= ctx
->blend
->equation
,
1324 .blend_equation_2
= replace_mode
1328 if (ctx
->blend
->has_blend_shader
)
1329 memcpy(&blend_meta
[0].blend_equation_1
, &ctx
->blend
->blend_shader
, sizeof(ctx
->blend
->blend_shader
));
1331 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), blend_meta
, sizeof(blend_meta
));
1335 if (ctx
->dirty
& PAN_DIRTY_VERTEX
) {
1336 ctx
->payload_vertex
.postfix
.attribute_meta
= ctx
->vertex
->descriptor_ptr
;
1339 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
1340 /* Upload samplers back to back, no padding */
1342 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1343 if (!ctx
->sampler_count
[t
]) continue;
1345 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
1346 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
1348 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
1349 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
1352 if (t
== PIPE_SHADER_FRAGMENT
)
1353 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
1354 else if (t
== PIPE_SHADER_VERTEX
)
1355 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1361 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1362 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1364 if (!ctx
->sampler_view_count
[t
]) continue;
1366 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1368 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1369 if (!ctx
->sampler_views
[t
][i
])
1372 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1373 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1375 /* Inject the address in. */
1376 for (int l
= 0; l
< (tex_rsrc
->last_level
+ 1); ++l
)
1377 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[l
] = rsrc
->bo
->gpu
[l
];
1379 /* Workaround maybe-errata (?) with non-mipmaps */
1380 int s
= ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
;
1382 if (!rsrc
->bo
->is_mipmap
) {
1384 /* HW ERRATA, not needed after t6XX */
1385 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[1] = rsrc
->bo
->gpu
[0];
1387 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 1;
1390 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= 0;
1393 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1396 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= s
;
1399 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 0;
1403 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1405 if (t
== PIPE_SHADER_FRAGMENT
)
1406 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1407 else if (t
== PIPE_SHADER_VERTEX
)
1408 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1414 /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1415 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1417 float viewport_vec4
[] = {
1419 fabsf(vp
->scale
[1]),
1422 /* -1.0 * vp->translate[1] */ fabs(1.0 * vp
->scale
[1]) /* XXX */
1425 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1426 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1428 if (i
== PIPE_SHADER_VERTEX
|| i
== PIPE_SHADER_FRAGMENT
) {
1429 /* It doesn't matter if we don't use all the memory;
1430 * we'd need a dummy UBO anyway. Compute the max */
1432 size_t size
= sizeof(viewport_vec4
) + buf
->size
;
1433 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1435 /* Keep track how much we've uploaded */
1438 if (i
== PIPE_SHADER_VERTEX
) {
1439 /* Upload viewport */
1440 memcpy(transfer
.cpu
+ offset
, viewport_vec4
, sizeof(viewport_vec4
));
1441 offset
+= sizeof(viewport_vec4
);
1444 /* Upload uniforms */
1445 memcpy(transfer
.cpu
+ offset
, buf
->buffer
, buf
->size
);
1447 int uniform_count
= 0;
1449 struct mali_vertex_tiler_postfix
*postfix
;
1452 case PIPE_SHADER_VERTEX
:
1453 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1454 postfix
= &ctx
->payload_vertex
.postfix
;
1457 case PIPE_SHADER_FRAGMENT
:
1458 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1459 postfix
= &ctx
->payload_tiler
.postfix
;
1463 DBG("Unknown shader stage %d in uniform upload\n", i
);
1467 /* Also attach the same buffer as a UBO for extended access */
1469 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1471 .size
= MALI_POSITIVE((2 + uniform_count
)),
1472 .ptr
= transfer
.gpu
>> 2,
1476 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1477 postfix
->uniforms
= transfer
.gpu
;
1478 postfix
->uniform_buffers
= ubufs
;
1487 /* Corresponds to exactly one draw, but does not submit anything */
1490 panfrost_queue_draw(struct panfrost_context
*ctx
)
1492 /* TODO: Expand the array? */
1493 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1494 DBG("Job buffer overflow, ignoring draw\n");
1498 /* Handle dirty flags now */
1499 panfrost_emit_for_draw(ctx
, true);
1501 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1502 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1504 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1505 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1507 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1508 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1513 /* At the end of the frame, the vertex and tiler jobs are linked together and
1514 * then the fragment job is plonked at the end. Set value job is first for
1515 * unknown reasons. */
1518 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1520 if (first
->job_descriptor_size
)
1521 first
->next_job_64
= (u64
) (uintptr_t) next
;
1523 first
->next_job_32
= (u32
) (uintptr_t) next
;
1527 panfrost_link_jobs(struct panfrost_context
*ctx
)
1529 if (ctx
->draw_count
) {
1530 /* Generate the set_value_job */
1531 panfrost_set_value_job(ctx
);
1533 /* Have the first vertex job depend on the set value job */
1534 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1537 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1540 /* V -> V/T ; T -> T/null */
1541 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1542 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1544 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1548 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1549 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1550 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1554 /* The entire frame is in memory -- send it off to the kernel! */
1557 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1558 struct pipe_fence_handle
**fence
)
1560 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1561 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1563 /* Edge case if screen is cleared and nothing else */
1564 bool has_draws
= ctx
->draw_count
> 0;
1566 /* Workaround a bizarre lockup (a hardware errata?) */
1568 flush_immediate
= true;
1570 /* A number of jobs are batched -- this must be linked and cleared */
1571 panfrost_link_jobs(ctx
);
1573 ctx
->draw_count
= 0;
1574 ctx
->vertex_job_count
= 0;
1575 ctx
->tiler_job_count
= 0;
1579 bool is_scanout
= panfrost_is_scanout(ctx
);
1580 int fragment_id
= screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1582 /* If visual, we can stall a frame */
1584 if (!flush_immediate
)
1585 screen
->driver
->force_flush_fragment(ctx
, fence
);
1587 screen
->last_fragment_id
= fragment_id
;
1588 screen
->last_fragment_flushed
= false;
1590 /* If readback, flush now (hurts the pipelined performance) */
1591 if (flush_immediate
)
1592 screen
->driver
->force_flush_fragment(ctx
, fence
);
1594 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1595 screen
->driver
->dump_counters(screen
);
1598 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1599 FILE *fp
= fopen(filename
, "wb");
1600 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1609 struct pipe_context
*pipe
,
1610 struct pipe_fence_handle
**fence
,
1613 struct panfrost_context
*ctx
= pan_context(pipe
);
1614 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1616 /* Nothing to do! */
1617 if (!ctx
->draw_count
&& !job
->clear
) return;
1619 /* Whether to stall the pipeline for immediately correct results */
1620 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1622 /* Submit the frame itself */
1623 panfrost_submit_frame(ctx
, flush_immediate
, fence
);
1625 /* Prepare for the next frame */
1626 panfrost_invalidate_frame(ctx
);
1629 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1632 g2m_draw_mode(enum pipe_prim_type mode
)
1635 DEFINE_CASE(POINTS
);
1637 DEFINE_CASE(LINE_LOOP
);
1638 DEFINE_CASE(LINE_STRIP
);
1639 DEFINE_CASE(TRIANGLES
);
1640 DEFINE_CASE(TRIANGLE_STRIP
);
1641 DEFINE_CASE(TRIANGLE_FAN
);
1643 DEFINE_CASE(QUAD_STRIP
);
1644 DEFINE_CASE(POLYGON
);
1647 DBG("Illegal draw mode %d\n", mode
);
1649 return MALI_LINE_LOOP
;
1656 panfrost_translate_index_size(unsigned size
)
1660 return MALI_DRAW_INDEXED_UINT8
;
1663 return MALI_DRAW_INDEXED_UINT16
;
1666 return MALI_DRAW_INDEXED_UINT32
;
1669 DBG("Unknown index size %d\n", size
);
1675 static const uint8_t *
1676 panfrost_get_index_buffer_raw(const struct pipe_draw_info
*info
)
1678 if (info
->has_user_indices
) {
1679 return (const uint8_t *) info
->index
.user
;
1681 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1682 return (const uint8_t *) rsrc
->bo
->cpu
[0];
1686 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1687 * good for the duration of the draw (transient), could last longer */
1690 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1692 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1694 off_t offset
= info
->start
* info
->index_size
;
1696 if (!info
->has_user_indices
) {
1697 /* Only resources can be directly mapped */
1698 return rsrc
->bo
->gpu
[0] + offset
;
1700 /* Otherwise, we need to upload to transient memory */
1701 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1702 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1706 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1707 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1708 T idx = buffer[_idx]; \
1709 if (idx > max_index) max_index = idx; \
1710 if (idx < min_index) min_index = idx; \
1715 struct pipe_context
*pipe
,
1716 const struct pipe_draw_info
*info
)
1718 struct panfrost_context
*ctx
= pan_context(pipe
);
1720 ctx
->payload_vertex
.draw_start
= info
->start
;
1721 ctx
->payload_tiler
.draw_start
= info
->start
;
1723 int mode
= info
->mode
;
1725 /* Fallback for unsupported modes */
1727 if (!(ctx
->draw_modes
& mode
)) {
1728 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1729 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1731 if (info
->count
< 4) {
1732 /* Degenerate case? */
1736 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1737 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1742 /* Now that we have a guaranteed terminating path, find the job.
1743 * Assignment commented out to prevent unused warning */
1745 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1747 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1749 ctx
->vertex_count
= info
->count
;
1751 /* For non-indexed draws, they're the same */
1752 unsigned invocation_count
= ctx
->vertex_count
;
1754 /* For higher amounts of vertices (greater than what fits in a 16-bit
1755 * short), the other value is needed, otherwise there will be bizarre
1756 * rendering artefacts. It's not clear what these values mean yet. */
1758 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~(0x3000 | 0x18000);
1759 ctx
->payload_tiler
.prefix
.unknown_draw
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1761 if (info
->index_size
) {
1762 /* Calculate the min/max index used so we can figure out how
1763 * many times to invoke the vertex shader */
1765 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1767 int min_index
= INT_MAX
;
1770 if (info
->index_size
== 1) {
1771 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8
, info
->start
, info
->count
);
1772 } else if (info
->index_size
== 2) {
1773 const uint16_t *ibuf16
= (const uint16_t *) ibuf8
;
1774 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16
, info
->start
, info
->count
);
1775 } else if (info
->index_size
== 4) {
1776 const uint32_t *ibuf32
= (const uint32_t *) ibuf8
;
1777 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32
, info
->start
, info
->count
);
1782 /* Make sure we didn't go crazy */
1783 assert(min_index
< INT_MAX
);
1784 assert(max_index
> 0);
1785 assert(max_index
> min_index
);
1787 /* Use the corresponding values */
1788 invocation_count
= max_index
- min_index
+ 1;
1789 ctx
->payload_vertex
.draw_start
= min_index
;
1790 ctx
->payload_tiler
.draw_start
= min_index
;
1792 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1793 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1795 //assert(!info->restart_index); /* TODO: Research */
1796 assert(!info
->index_bias
);
1797 //assert(!info->min_index); /* TODO: Use value */
1799 ctx
->payload_tiler
.prefix
.unknown_draw
|= panfrost_translate_index_size(info
->index_size
);
1800 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1802 /* Index count == vertex count, if no indexing is applied, as
1803 * if it is internally indexed in the expected order */
1805 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1806 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1808 /* Reverse index state */
1809 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~MALI_DRAW_INDEXED_UINT32
;
1810 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1813 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1814 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1816 /* Fire off the draw itself */
1817 panfrost_queue_draw(ctx
);
1823 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1829 panfrost_set_scissor(struct panfrost_context
*ctx
)
1831 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1833 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
&& 0) {
1834 ctx
->viewport
->viewport0
[0] = ss
->minx
;
1835 ctx
->viewport
->viewport0
[1] = ss
->miny
;
1836 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1837 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ss
->maxy
);
1839 ctx
->viewport
->viewport0
[0] = 0;
1840 ctx
->viewport
->viewport0
[1] = 0;
1841 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ctx
->pipe_framebuffer
.width
);
1842 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ctx
->pipe_framebuffer
.height
);
1847 panfrost_create_rasterizer_state(
1848 struct pipe_context
*pctx
,
1849 const struct pipe_rasterizer_state
*cso
)
1851 struct panfrost_context
*ctx
= pan_context(pctx
);
1852 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1856 /* Bitmask, unknown meaning of the start value */
1857 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1859 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1860 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1862 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1863 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1865 if (cso
->cull_face
& PIPE_FACE_BACK
)
1866 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1872 panfrost_bind_rasterizer_state(
1873 struct pipe_context
*pctx
,
1876 struct panfrost_context
*ctx
= pan_context(pctx
);
1877 struct pipe_rasterizer_state
*cso
= hwcso
;
1879 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1883 /* If scissor test has changed, we'll need to update that now */
1884 bool update_scissor
= !ctx
->rasterizer
|| ctx
->rasterizer
->base
.scissor
!= cso
->scissor
;
1886 ctx
->rasterizer
= hwcso
;
1888 /* Actualise late changes */
1890 panfrost_set_scissor(ctx
);
1892 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1896 panfrost_create_vertex_elements_state(
1897 struct pipe_context
*pctx
,
1898 unsigned num_elements
,
1899 const struct pipe_vertex_element
*elements
)
1901 struct panfrost_context
*ctx
= pan_context(pctx
);
1902 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1904 so
->num_elements
= num_elements
;
1905 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1907 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_attr_meta
) * num_elements
, HEAP_DESCRIPTOR
);
1908 so
->hw
= (struct mali_attr_meta
*) transfer
.cpu
;
1909 so
->descriptor_ptr
= transfer
.gpu
;
1911 /* Allocate memory for the descriptor state */
1913 for (int i
= 0; i
< num_elements
; ++i
) {
1914 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1916 enum pipe_format fmt
= elements
[i
].src_format
;
1917 const struct util_format_description
*desc
= util_format_description(fmt
);
1918 so
->hw
[i
].unknown1
= 0x2;
1919 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1921 so
->hw
[i
].format
= panfrost_find_format(desc
);
1923 /* The field itself should probably be shifted over */
1924 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1931 panfrost_bind_vertex_elements_state(
1932 struct pipe_context
*pctx
,
1935 struct panfrost_context
*ctx
= pan_context(pctx
);
1937 ctx
->vertex
= hwcso
;
1938 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1942 panfrost_delete_vertex_elements_state(struct pipe_context
*pctx
, void *hwcso
)
1944 struct panfrost_vertex_state
*so
= (struct panfrost_vertex_state
*) hwcso
;
1945 unsigned bytes
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
1946 DBG("Vertex elements delete leaks descriptor (%d bytes)\n", bytes
);
1951 panfrost_create_shader_state(
1952 struct pipe_context
*pctx
,
1953 const struct pipe_shader_state
*cso
)
1955 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1958 /* Token deep copy to prevent memory corruption */
1960 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1961 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1967 panfrost_delete_shader_state(
1968 struct pipe_context
*pctx
,
1971 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1973 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1974 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1977 unsigned leak
= cso
->variant_count
* sizeof(struct mali_shader_meta
);
1978 DBG("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak
);
1984 panfrost_create_sampler_state(
1985 struct pipe_context
*pctx
,
1986 const struct pipe_sampler_state
*cso
)
1988 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1991 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1993 struct mali_sampler_descriptor sampler_descriptor
= {
1994 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1995 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1996 | translate_mip_filter(cso
->min_mip_filter
)
1999 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
2000 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
2001 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
2002 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
2004 cso
->border_color
.f
[0],
2005 cso
->border_color
.f
[1],
2006 cso
->border_color
.f
[2],
2007 cso
->border_color
.f
[3]
2009 .min_lod
= FIXED_16(0.0),
2010 .max_lod
= FIXED_16(31.0),
2014 so
->hw
= sampler_descriptor
;
2020 panfrost_bind_sampler_states(
2021 struct pipe_context
*pctx
,
2022 enum pipe_shader_type shader
,
2023 unsigned start_slot
, unsigned num_sampler
,
2026 assert(start_slot
== 0);
2028 struct panfrost_context
*ctx
= pan_context(pctx
);
2030 /* XXX: Should upload, not just copy? */
2031 ctx
->sampler_count
[shader
] = num_sampler
;
2032 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
2034 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
2038 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
2040 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
2042 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
2043 /* Make sure enable state is at least the same */
2044 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
2048 /* Check that the contents of the test are the same */
2049 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
2050 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
2052 if (!(same_func
&& same_ref
)) {
2056 /* Otherwise, we're good to go */
2061 panfrost_bind_fs_state(
2062 struct pipe_context
*pctx
,
2065 struct panfrost_context
*ctx
= pan_context(pctx
);
2070 /* Match the appropriate variant */
2072 signed variant
= -1;
2074 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2076 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2077 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
2083 if (variant
== -1) {
2084 /* No variant matched, so create a new one */
2085 variant
= variants
->variant_count
++;
2086 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2088 variants
->variants
[variant
].base
= hwcso
;
2089 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
2091 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
2092 struct panfrost_context
*ctx
= pan_context(pctx
);
2093 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2095 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2096 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
2100 /* Select this variant */
2101 variants
->active_variant
= variant
;
2103 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2104 assert(panfrost_variant_matches(ctx
, shader_state
));
2106 /* Now we have a variant selected, so compile and go */
2108 if (!shader_state
->compiled
) {
2109 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
2110 shader_state
->compiled
= true;
2114 ctx
->dirty
|= PAN_DIRTY_FS
;
2118 panfrost_bind_vs_state(
2119 struct pipe_context
*pctx
,
2122 struct panfrost_context
*ctx
= pan_context(pctx
);
2127 if (!ctx
->vs
->variants
[0].compiled
) {
2128 ctx
->vs
->variants
[0].base
= hwcso
;
2130 /* TODO DRY from above */
2131 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2132 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2133 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
2135 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
2136 ctx
->vs
->variants
[0].compiled
= true;
2140 ctx
->dirty
|= PAN_DIRTY_VS
;
2144 panfrost_set_vertex_buffers(
2145 struct pipe_context
*pctx
,
2146 unsigned start_slot
,
2147 unsigned num_buffers
,
2148 const struct pipe_vertex_buffer
*buffers
)
2150 struct panfrost_context
*ctx
= pan_context(pctx
);
2151 assert(num_buffers
<= PIPE_MAX_ATTRIBS
);
2153 /* XXX: Dirty tracking? etc */
2155 size_t sz
= sizeof(buffers
[0]) * num_buffers
;
2156 ctx
->vertex_buffers
= malloc(sz
);
2157 ctx
->vertex_buffer_count
= num_buffers
;
2158 memcpy(ctx
->vertex_buffers
, buffers
, sz
);
2160 if (ctx
->vertex_buffers
) {
2161 free(ctx
->vertex_buffers
);
2162 ctx
->vertex_buffers
= NULL
;
2165 ctx
->vertex_buffer_count
= 0;
2170 panfrost_set_constant_buffer(
2171 struct pipe_context
*pctx
,
2172 enum pipe_shader_type shader
, uint index
,
2173 const struct pipe_constant_buffer
*buf
)
2175 struct panfrost_context
*ctx
= pan_context(pctx
);
2176 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2178 size_t sz
= buf
? buf
->buffer_size
: 0;
2180 /* Free previous buffer */
2187 pbuf
->buffer
= NULL
;
2190 /* If unbinding, we're done */
2195 /* Multiple constant buffers not yet supported */
2200 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
2203 cpu
= rsrc
->bo
->cpu
[0];
2204 } else if (buf
->user_buffer
) {
2205 cpu
= buf
->user_buffer
;
2207 DBG("No constant buffer?\n");
2211 /* Copy the constant buffer into the driver context for later upload */
2213 pbuf
->buffer
= malloc(sz
);
2214 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
2218 panfrost_set_stencil_ref(
2219 struct pipe_context
*pctx
,
2220 const struct pipe_stencil_ref
*ref
)
2222 struct panfrost_context
*ctx
= pan_context(pctx
);
2223 ctx
->stencil_ref
= *ref
;
2225 /* Shader core dirty */
2226 ctx
->dirty
|= PAN_DIRTY_FS
;
2229 static struct pipe_sampler_view
*
2230 panfrost_create_sampler_view(
2231 struct pipe_context
*pctx
,
2232 struct pipe_resource
*texture
,
2233 const struct pipe_sampler_view
*template)
2235 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
2236 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2238 pipe_reference(NULL
, &texture
->reference
);
2240 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2242 so
->base
= *template;
2243 so
->base
.texture
= texture
;
2244 so
->base
.reference
.count
= 1;
2245 so
->base
.context
= pctx
;
2247 /* sampler_views correspond to texture descriptors, minus the texture
2248 * (data) itself. So, we serialise the descriptor here and cache it for
2251 /* TODO: Other types of textures */
2252 assert(template->target
== PIPE_TEXTURE_2D
);
2254 /* Make sure it's something with which we're familiar */
2255 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2257 /* TODO: Detect from format better */
2258 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2260 unsigned char user_swizzle
[4] = {
2261 template->swizzle_r
,
2262 template->swizzle_g
,
2263 template->swizzle_b
,
2267 enum mali_format format
= panfrost_find_format(desc
);
2269 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2271 unsigned usage2_layout
= 0x10;
2273 switch (prsrc
->bo
->layout
) {
2275 usage2_layout
|= 0x8 | 0x4;
2278 usage2_layout
|= 0x1;
2281 usage2_layout
|= is_depth
? 0x1 : 0x2;
2288 struct mali_texture_descriptor texture_descriptor
= {
2289 .width
= MALI_POSITIVE(texture
->width0
),
2290 .height
= MALI_POSITIVE(texture
->height0
),
2291 .depth
= MALI_POSITIVE(texture
->depth0
),
2295 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2299 .is_not_cubemap
= 1,
2301 .usage2
= usage2_layout
2304 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2307 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2308 assert (template->u
.tex
.first_level
== 0);
2310 texture_descriptor
.nr_mipmap_levels
= template->u
.tex
.last_level
- template->u
.tex
.first_level
;
2312 so
->hw
= texture_descriptor
;
2314 return (struct pipe_sampler_view
*) so
;
2318 panfrost_set_sampler_views(
2319 struct pipe_context
*pctx
,
2320 enum pipe_shader_type shader
,
2321 unsigned start_slot
, unsigned num_views
,
2322 struct pipe_sampler_view
**views
)
2324 struct panfrost_context
*ctx
= pan_context(pctx
);
2326 assert(start_slot
== 0);
2328 ctx
->sampler_view_count
[shader
] = num_views
;
2329 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2331 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2335 panfrost_sampler_view_destroy(
2336 struct pipe_context
*pctx
,
2337 struct pipe_sampler_view
*views
)
2339 //struct panfrost_context *ctx = pan_context(pctx);
2347 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2348 const struct pipe_framebuffer_state
*fb
)
2350 struct panfrost_context
*ctx
= pan_context(pctx
);
2352 /* Flush when switching away from an FBO */
2354 if (!panfrost_is_scanout(ctx
)) {
2355 panfrost_flush(pctx
, NULL
, 0);
2358 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2359 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2360 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2361 ctx
->pipe_framebuffer
.width
= fb
->width
;
2362 ctx
->pipe_framebuffer
.height
= fb
->height
;
2364 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2365 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2367 /* check if changing cbuf */
2368 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2370 if (cb
&& (i
!= 0)) {
2371 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2376 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2381 if (ctx
->require_sfbd
)
2382 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2384 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2386 panfrost_attach_vt_framebuffer(ctx
);
2387 panfrost_new_frag_framebuffer(ctx
);
2388 panfrost_set_scissor(ctx
);
2390 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2391 bool is_scanout
= panfrost_is_scanout(ctx
);
2393 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
) {
2394 /* The blob is aggressive about enabling AFBC. As such,
2395 * it's pretty much necessary to use it here, since we
2396 * have no traces of non-compressed FBO. */
2398 panfrost_enable_afbc(ctx
, tex
, false);
2401 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2402 /* Enable transaction elimination if we can */
2403 panfrost_enable_checksum(ctx
, tex
);
2408 struct pipe_surface
*zb
= fb
->zsbuf
;
2410 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2411 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2416 if (ctx
->require_sfbd
)
2417 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2419 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2421 panfrost_attach_vt_framebuffer(ctx
);
2422 panfrost_new_frag_framebuffer(ctx
);
2423 panfrost_set_scissor(ctx
);
2425 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
);
2427 if (tex
->bo
->layout
!= PAN_AFBC
&& !panfrost_is_scanout(ctx
))
2428 panfrost_enable_afbc(ctx
, tex
, true);
2435 panfrost_create_blend_state(struct pipe_context
*pipe
,
2436 const struct pipe_blend_state
*blend
)
2438 struct panfrost_context
*ctx
= pan_context(pipe
);
2439 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2442 /* TODO: The following features are not yet implemented */
2443 assert(!blend
->logicop_enable
);
2444 assert(!blend
->alpha_to_coverage
);
2445 assert(!blend
->alpha_to_one
);
2447 /* Compile the blend state, first as fixed-function if we can */
2449 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], &so
->equation
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2452 /* If we can't, compile a blend shader instead */
2454 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2460 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2463 struct panfrost_context
*ctx
= pan_context(pipe
);
2464 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2465 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2466 ctx
->blend
= pblend
;
2471 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2473 /* TODO: Attach color */
2475 /* Shader itself is not dirty, but the shader core is */
2476 ctx
->dirty
|= PAN_DIRTY_FS
;
2480 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2483 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2485 if (so
->has_blend_shader
) {
2486 DBG("Deleting blend state leak blend shaders bytecode\n");
2493 panfrost_set_blend_color(struct pipe_context
*pipe
,
2494 const struct pipe_blend_color
*blend_color
)
2496 struct panfrost_context
*ctx
= pan_context(pipe
);
2498 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2501 ctx
->blend_color
= *blend_color
;
2503 /* The blend mode depends on the blend constant color, due to the
2504 * fixed/programmable split. So, we're forced to regenerate the blend
2507 /* TODO: Attach color */
2512 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2513 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2515 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2519 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2522 struct panfrost_context
*ctx
= pan_context(pipe
);
2523 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2524 ctx
->depth_stencil
= depth_stencil
;
2529 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2530 * emulated in the fragment shader */
2532 if (depth_stencil
->alpha
.enabled
) {
2533 /* We need to trigger a new shader (maybe) */
2534 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2538 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2540 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2541 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2543 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2544 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2546 /* Depth state (TODO: Refactor) */
2547 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2549 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2551 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2552 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2554 /* Bounds test not implemented */
2555 assert(!depth_stencil
->depth
.bounds_test
);
2557 ctx
->dirty
|= PAN_DIRTY_FS
;
2561 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2567 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2568 unsigned sample_mask
)
2573 panfrost_set_clip_state(struct pipe_context
*pipe
,
2574 const struct pipe_clip_state
*clip
)
2576 //struct panfrost_context *panfrost = pan_context(pipe);
2580 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2581 unsigned start_slot
,
2582 unsigned num_viewports
,
2583 const struct pipe_viewport_state
*viewports
)
2585 struct panfrost_context
*ctx
= pan_context(pipe
);
2587 assert(start_slot
== 0);
2588 assert(num_viewports
== 1);
2590 ctx
->pipe_viewport
= *viewports
;
2593 /* TODO: What if not centered? */
2594 float w
= abs(viewports
->scale
[0]) * 2.0;
2595 float h
= abs(viewports
->scale
[1]) * 2.0;
2597 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2598 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2603 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2604 unsigned start_slot
,
2605 unsigned num_scissors
,
2606 const struct pipe_scissor_state
*scissors
)
2608 struct panfrost_context
*ctx
= pan_context(pipe
);
2610 assert(start_slot
== 0);
2611 assert(num_scissors
== 1);
2613 ctx
->scissor
= *scissors
;
2615 panfrost_set_scissor(ctx
);
2619 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2620 const struct pipe_poly_stipple
*stipple
)
2622 //struct panfrost_context *panfrost = pan_context(pipe);
2626 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2629 //struct panfrost_context *panfrost = pan_context(pipe);
2633 panfrost_destroy(struct pipe_context
*pipe
)
2635 struct panfrost_context
*panfrost
= pan_context(pipe
);
2636 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2638 if (panfrost
->blitter
)
2639 util_blitter_destroy(panfrost
->blitter
);
2641 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2642 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2643 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2644 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2645 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2648 static struct pipe_query
*
2649 panfrost_create_query(struct pipe_context
*pipe
,
2653 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2658 return (struct pipe_query
*) q
;
2662 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2668 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2670 struct panfrost_context
*ctx
= pan_context(pipe
);
2671 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2673 switch (query
->type
) {
2674 case PIPE_QUERY_OCCLUSION_COUNTER
:
2675 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2676 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2678 /* Allocate a word for the query results to be stored */
2679 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2681 ctx
->occlusion_query
= query
;
2687 DBG("Skipping query %d\n", query
->type
);
2695 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2697 struct panfrost_context
*ctx
= pan_context(pipe
);
2698 ctx
->occlusion_query
= NULL
;
2703 panfrost_get_query_result(struct pipe_context
*pipe
,
2704 struct pipe_query
*q
,
2706 union pipe_query_result
*vresult
)
2709 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2711 /* We need to flush out the jobs to actually run the counter, TODO
2712 * check wait, TODO wallpaper after if needed */
2714 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2716 switch (query
->type
) {
2717 case PIPE_QUERY_OCCLUSION_COUNTER
:
2718 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2719 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2720 /* Read back the query results */
2721 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2722 unsigned passed
= *result
;
2724 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2725 vresult
->u64
= passed
;
2727 vresult
->b
= !!passed
;
2733 DBG("Skipped query get %d\n", query
->type
);
2741 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2743 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2744 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2746 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2747 /* Allocate the beginning of the transient pool */
2748 int entry_size
= (1 << 22); /* 4MB */
2750 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2751 ctx
->transient_pools
[i
].entry_count
= 1;
2753 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2756 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2757 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2758 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2759 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2760 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2764 /* New context creation, which also does hardware initialisation since I don't
2765 * know the better way to structure this :smirk: */
2767 struct pipe_context
*
2768 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2770 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2771 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2772 memset(ctx
, 0, sizeof(*ctx
));
2773 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2776 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2777 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means t76x or less */
2778 ctx
->require_sfbd
= gpu_id
< 0x0750; /* t76x is the first to support MFD */
2780 gallium
->screen
= screen
;
2782 gallium
->destroy
= panfrost_destroy
;
2784 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2786 gallium
->flush
= panfrost_flush
;
2787 gallium
->clear
= panfrost_clear
;
2788 gallium
->draw_vbo
= panfrost_draw_vbo
;
2790 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2791 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2793 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2795 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2796 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2797 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2799 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2800 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2801 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2803 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2804 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2805 gallium
->delete_vertex_elements_state
= panfrost_delete_vertex_elements_state
;
2807 gallium
->create_fs_state
= panfrost_create_shader_state
;
2808 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2809 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2811 gallium
->create_vs_state
= panfrost_create_shader_state
;
2812 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2813 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2815 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2816 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2817 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2819 gallium
->create_blend_state
= panfrost_create_blend_state
;
2820 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2821 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2823 gallium
->set_blend_color
= panfrost_set_blend_color
;
2825 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2826 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2827 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2829 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2831 gallium
->set_clip_state
= panfrost_set_clip_state
;
2832 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2833 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2834 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2835 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2837 gallium
->create_query
= panfrost_create_query
;
2838 gallium
->destroy_query
= panfrost_destroy_query
;
2839 gallium
->begin_query
= panfrost_begin_query
;
2840 gallium
->end_query
= panfrost_end_query
;
2841 gallium
->get_query_result
= panfrost_get_query_result
;
2843 panfrost_resource_context_init(gallium
);
2845 pscreen
->driver
->init_context(ctx
);
2847 panfrost_setup_hardware(ctx
);
2850 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2851 gallium
->const_uploader
= gallium
->stream_uploader
;
2852 assert(gallium
->stream_uploader
);
2854 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2855 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2857 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2859 ctx
->blitter
= util_blitter_create(gallium
);
2860 assert(ctx
->blitter
);
2862 /* Prepare for render! */
2864 panfrost_job_init(ctx
);
2865 panfrost_emit_vertex_payload(ctx
);
2866 panfrost_emit_tiler_payload(ctx
);
2867 panfrost_invalidate_frame(ctx
);
2868 panfrost_viewport(ctx
, 0.0, 1.0, 0, 0, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
2869 panfrost_default_shader_backend(ctx
);
2870 panfrost_generate_space_filler_indices();