2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_format.h"
31 #include "util/macros.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_memory.h"
36 #include "util/u_vbuf.h"
37 #include "util/half_float.h"
38 #include "util/u_helpers.h"
39 #include "util/u_format.h"
40 #include "util/u_prim_restart.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
49 #include "pan_tiler.h"
51 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
54 static enum mali_job_type
55 panfrost_job_type_for_pipe(enum pipe_shader_type type
)
58 case PIPE_SHADER_VERTEX
:
59 return JOB_TYPE_VERTEX
;
61 case PIPE_SHADER_FRAGMENT
:
62 /* Note: JOB_TYPE_FRAGMENT is different.
63 * JOB_TYPE_FRAGMENT actually executes the
64 * fragment shader, but JOB_TYPE_TILER is how you
66 return JOB_TYPE_TILER
;
68 case PIPE_SHADER_GEOMETRY
:
69 return JOB_TYPE_GEOMETRY
;
71 case PIPE_SHADER_COMPUTE
:
72 return JOB_TYPE_COMPUTE
;
75 unreachable("Unsupported shader stage");
79 /* Framebuffer descriptor */
82 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
84 fb
->width
= MALI_POSITIVE(w
);
85 fb
->height
= MALI_POSITIVE(h
);
87 /* No idea why this is needed, but it's how resolution_check is
88 * calculated. It's not clear to us yet why the hardware wants this.
89 * The formula itself was discovered mostly by manual bruteforce and
90 * aggressive algebraic simplification. */
92 fb
->tiler_resolution_check
= ((w
+ h
) / 3) << 4;
95 struct mali_single_framebuffer
96 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
98 struct mali_single_framebuffer framebuffer
= {
100 .format
= 0x30000000,
101 .clear_flags
= 0x1000,
102 .unknown_address_0
= ctx
->scratchpad
.bo
->gpu
,
103 .tiler_polygon_list
= ctx
->tiler_polygon_list
.bo
->gpu
,
104 .tiler_polygon_list_body
= ctx
->tiler_polygon_list
.bo
->gpu
+ 40960,
105 .tiler_hierarchy_mask
= 0xF0,
107 .tiler_heap_free
= ctx
->tiler_heap
.bo
->gpu
,
108 .tiler_heap_end
= ctx
->tiler_heap
.bo
->gpu
+ ctx
->tiler_heap
.bo
->size
,
111 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
116 struct bifrost_framebuffer
117 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
119 unsigned width
= ctx
->pipe_framebuffer
.width
;
120 unsigned height
= ctx
->pipe_framebuffer
.height
;
122 struct bifrost_framebuffer framebuffer
= {
123 .width1
= MALI_POSITIVE(width
),
124 .height1
= MALI_POSITIVE(height
),
125 .width2
= MALI_POSITIVE(width
),
126 .height2
= MALI_POSITIVE(height
),
131 .rt_count_1
= MALI_POSITIVE(1),
136 .scratchpad
= ctx
->scratchpad
.bo
->gpu
,
139 framebuffer
.tiler_hierarchy_mask
=
140 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
142 /* Compute the polygon header size and use that to offset the body */
144 unsigned header_size
= panfrost_tiler_header_size(
145 width
, height
, framebuffer
.tiler_hierarchy_mask
);
147 unsigned body_size
= panfrost_tiler_body_size(
148 width
, height
, framebuffer
.tiler_hierarchy_mask
);
152 unsigned total_size
= header_size
+ body_size
;
154 if (framebuffer
.tiler_hierarchy_mask
) {
155 assert(ctx
->tiler_polygon_list
.bo
->size
>= total_size
);
157 /* Specify allocated tiler structures */
158 framebuffer
.tiler_polygon_list
= ctx
->tiler_polygon_list
.bo
->gpu
;
160 /* Allow the entire tiler heap */
161 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.bo
->gpu
;
162 framebuffer
.tiler_heap_end
=
163 ctx
->tiler_heap
.bo
->gpu
+ ctx
->tiler_heap
.bo
->size
;
165 /* The tiler is disabled, so don't allow the tiler heap */
166 framebuffer
.tiler_heap_start
= ctx
->tiler_heap
.bo
->gpu
;
167 framebuffer
.tiler_heap_end
= framebuffer
.tiler_heap_start
;
169 /* Use a dummy polygon list */
170 framebuffer
.tiler_polygon_list
= ctx
->tiler_dummy
.bo
->gpu
;
172 /* Also, set a "tiler disabled?" flag? */
173 framebuffer
.tiler_hierarchy_mask
|= 0x1000;
176 framebuffer
.tiler_polygon_list_body
=
177 framebuffer
.tiler_polygon_list
+ header_size
;
179 framebuffer
.tiler_polygon_list_size
=
180 header_size
+ body_size
;
187 /* Are we currently rendering to the screen (rather than an FBO)? */
190 panfrost_is_scanout(struct panfrost_context
*ctx
)
192 /* If there is no color buffer, it's an FBO */
193 if (ctx
->pipe_framebuffer
.nr_cbufs
!= 1)
196 /* If we're too early that no framebuffer was sent, it's scanout */
197 if (!ctx
->pipe_framebuffer
.cbufs
[0])
200 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
201 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
202 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
207 struct pipe_context
*pipe
,
209 const union pipe_color_union
*color
,
210 double depth
, unsigned stencil
)
212 struct panfrost_context
*ctx
= pan_context(pipe
);
213 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
215 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
219 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
221 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
225 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
227 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
231 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
233 mali_ptr framebuffer
= ctx
->require_sfbd
?
234 panfrost_attach_vt_sfbd(ctx
) :
235 panfrost_attach_vt_mfbd(ctx
);
237 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
238 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
241 /* Reset per-frame context, called on context initialisation as well as after
242 * flushing a frame */
245 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
247 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
248 DBG("Uploaded transient %d bytes\n", transient_count
);
250 /* Rotate cmdstream */
251 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
252 ctx
->cmdstream_i
= 0;
254 if (ctx
->require_sfbd
)
255 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
257 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
259 /* Reset varyings allocated */
260 ctx
->varying_height
= 0;
262 /* The transient cmdstream is dirty every frame; the only bits worth preserving
263 * (textures, shaders, etc) are in other buffers anyways */
265 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
266 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
268 /* Regenerate payloads */
269 panfrost_attach_vt_framebuffer(ctx
);
272 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
275 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
278 /* In practice, every field of these payloads should be configurable
279 * arbitrarily, which means these functions are basically catch-all's for
280 * as-of-yet unwavering unknowns */
283 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
285 struct midgard_payload_vertex_tiler payload
= {
286 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
289 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
293 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
295 struct midgard_payload_vertex_tiler payload
= {
297 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
301 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
305 translate_tex_wrap(enum pipe_tex_wrap w
)
308 case PIPE_TEX_WRAP_REPEAT
:
309 return MALI_WRAP_REPEAT
;
311 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
312 return MALI_WRAP_CLAMP_TO_EDGE
;
314 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
315 return MALI_WRAP_CLAMP_TO_BORDER
;
317 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
318 return MALI_WRAP_MIRRORED_REPEAT
;
321 unreachable("Invalid wrap");
326 translate_tex_filter(enum pipe_tex_filter f
)
329 case PIPE_TEX_FILTER_NEAREST
:
332 case PIPE_TEX_FILTER_LINEAR
:
336 unreachable("Invalid filter");
341 translate_mip_filter(enum pipe_tex_mipfilter f
)
343 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
347 panfrost_translate_compare_func(enum pipe_compare_func in
)
350 case PIPE_FUNC_NEVER
:
351 return MALI_FUNC_NEVER
;
354 return MALI_FUNC_LESS
;
356 case PIPE_FUNC_EQUAL
:
357 return MALI_FUNC_EQUAL
;
359 case PIPE_FUNC_LEQUAL
:
360 return MALI_FUNC_LEQUAL
;
362 case PIPE_FUNC_GREATER
:
363 return MALI_FUNC_GREATER
;
365 case PIPE_FUNC_NOTEQUAL
:
366 return MALI_FUNC_NOTEQUAL
;
368 case PIPE_FUNC_GEQUAL
:
369 return MALI_FUNC_GEQUAL
;
371 case PIPE_FUNC_ALWAYS
:
372 return MALI_FUNC_ALWAYS
;
375 unreachable("Invalid func");
380 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
383 case PIPE_FUNC_NEVER
:
384 return MALI_ALT_FUNC_NEVER
;
387 return MALI_ALT_FUNC_LESS
;
389 case PIPE_FUNC_EQUAL
:
390 return MALI_ALT_FUNC_EQUAL
;
392 case PIPE_FUNC_LEQUAL
:
393 return MALI_ALT_FUNC_LEQUAL
;
395 case PIPE_FUNC_GREATER
:
396 return MALI_ALT_FUNC_GREATER
;
398 case PIPE_FUNC_NOTEQUAL
:
399 return MALI_ALT_FUNC_NOTEQUAL
;
401 case PIPE_FUNC_GEQUAL
:
402 return MALI_ALT_FUNC_GEQUAL
;
404 case PIPE_FUNC_ALWAYS
:
405 return MALI_ALT_FUNC_ALWAYS
;
408 unreachable("Invalid alt func");
413 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
416 case PIPE_STENCIL_OP_KEEP
:
417 return MALI_STENCIL_KEEP
;
419 case PIPE_STENCIL_OP_ZERO
:
420 return MALI_STENCIL_ZERO
;
422 case PIPE_STENCIL_OP_REPLACE
:
423 return MALI_STENCIL_REPLACE
;
425 case PIPE_STENCIL_OP_INCR
:
426 return MALI_STENCIL_INCR
;
428 case PIPE_STENCIL_OP_DECR
:
429 return MALI_STENCIL_DECR
;
431 case PIPE_STENCIL_OP_INCR_WRAP
:
432 return MALI_STENCIL_INCR_WRAP
;
434 case PIPE_STENCIL_OP_DECR_WRAP
:
435 return MALI_STENCIL_DECR_WRAP
;
437 case PIPE_STENCIL_OP_INVERT
:
438 return MALI_STENCIL_INVERT
;
441 unreachable("Invalid stencil op");
446 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
448 out
->ref
= 0; /* Gallium gets it from elsewhere */
450 out
->mask
= in
->valuemask
;
451 out
->func
= panfrost_translate_compare_func(in
->func
);
452 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
453 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
454 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
458 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
460 struct mali_shader_meta shader
= {
461 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
463 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
464 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
468 shader
.unknown2_4
|= 0x10;
471 struct pipe_stencil_state default_stencil
= {
473 .func
= PIPE_FUNC_ALWAYS
,
474 .fail_op
= MALI_STENCIL_KEEP
,
475 .zfail_op
= MALI_STENCIL_KEEP
,
476 .zpass_op
= MALI_STENCIL_KEEP
,
481 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
482 shader
.stencil_mask_front
= default_stencil
.writemask
;
484 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
485 shader
.stencil_mask_back
= default_stencil
.writemask
;
487 if (default_stencil
.enabled
)
488 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
490 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
493 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
494 * graphics command stream. It should be called once per draw, accordding to
495 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
496 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
499 struct panfrost_transfer
500 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
502 struct mali_job_descriptor_header job
= {
503 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
505 .job_descriptor_size
= 1,
509 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
511 /* There's some padding hacks on 32-bit */
518 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
520 memcpy(transfer
.cpu
, &job
, sizeof(job
));
521 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
526 panfrost_emit_varyings(
527 struct panfrost_context
*ctx
,
528 union mali_attr
*slot
,
532 mali_ptr varying_address
= ctx
->varying_mem
.bo
->gpu
+ ctx
->varying_height
;
534 /* Fill out the descriptor */
535 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
536 slot
->stride
= stride
;
537 slot
->size
= stride
* count
;
539 ctx
->varying_height
+= ALIGN_POT(slot
->size
, 64);
540 assert(ctx
->varying_height
< ctx
->varying_mem
.bo
->size
);
542 return varying_address
;
546 panfrost_emit_point_coord(union mali_attr
*slot
)
548 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
549 slot
->stride
= slot
->size
= 0;
553 panfrost_emit_varying_descriptor(
554 struct panfrost_context
*ctx
,
555 unsigned vertex_count
)
557 /* Load the shaders */
559 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
560 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
561 unsigned int num_gen_varyings
= 0;
563 /* Allocate the varying descriptor */
565 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
566 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
568 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
572 * Assign ->src_offset now that we know about all the general purpose
573 * varyings that will be used by the fragment and vertex shaders.
575 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
577 * General purpose varyings have ->index set to 0, skip other
580 if (vs
->varyings
[i
].index
)
583 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
586 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
589 /* If we have a point sprite replacement, handle that here. We
590 * have to translate location first. TODO: Flip y in shader.
591 * We're already keying ... just time crunch .. */
593 unsigned loc
= fs
->varyings_loc
[i
];
595 (loc
>= VARYING_SLOT_VAR0
) ? (loc
- VARYING_SLOT_VAR0
) :
596 (loc
== VARYING_SLOT_PNTC
) ? 8 :
599 if (~pnt_loc
&& fs
->point_sprite_mask
& (1 << pnt_loc
)) {
600 /* gl_PointCoord index by convention */
601 fs
->varyings
[i
].index
= 3;
602 fs
->reads_point_coord
= true;
604 /* Swizzle out the z/w to 0/1 */
605 fs
->varyings
[i
].format
= MALI_RG16F
;
606 fs
->varyings
[i
].swizzle
=
607 panfrost_get_default_swizzle(2);
612 if (fs
->varyings
[i
].index
)
616 * Re-use the VS general purpose varying pos if it exists,
617 * create a new one otherwise.
619 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
620 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
624 if (j
< vs
->tripipe
->varying_count
)
625 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
627 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
630 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
631 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
633 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
634 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
636 /* Buffer indices must be in this order per our convention */
637 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
640 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
643 /* fp32 vec4 gl_Position */
644 ctx
->payload_tiler
.postfix
.position_varying
=
645 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
646 sizeof(float) * 4, vertex_count
);
649 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
650 /* fp16 vec1 gl_PointSize */
651 ctx
->payload_tiler
.primitive_size
.pointer
=
652 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
656 if (fs
->reads_point_coord
) {
657 /* Special descriptor */
658 panfrost_emit_point_coord(&varyings
[idx
++]);
661 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
662 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
663 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
667 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
669 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
670 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
672 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
676 panfrost_writes_point_size(struct panfrost_context
*ctx
)
679 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
681 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
684 /* Stage the attribute descriptors so we can adjust src_offset
685 * to let BOs align nicely */
688 panfrost_stage_attributes(struct panfrost_context
*ctx
)
690 struct panfrost_vertex_state
*so
= ctx
->vertex
;
692 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
693 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
694 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
696 /* Copy as-is for the first pass */
697 memcpy(target
, so
->hw
, sz
);
699 /* Fixup offsets for the second pass. Recall that the hardware
700 * calculates attribute addresses as:
702 * addr = base + (stride * vtx) + src_offset;
704 * However, on Mali, base must be aligned to 64-bytes, so we
707 * base' = base & ~63 = base - (base & 63)
709 * To compensate when using base' (see emit_vertex_data), we have
710 * to adjust src_offset by the masked off piece:
712 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
713 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
714 * = base + (stride * vtx) + src_offset
720 unsigned start
= ctx
->payload_vertex
.draw_start
;
722 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
723 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
724 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
725 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
727 /* Adjust by the masked off bits of the offset */
728 target
[i
].src_offset
+= (addr
& 63);
730 /* Also, somewhat obscurely per-instance data needs to be
731 * offset in response to a delayed start in an indexed draw */
733 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
734 target
[i
].src_offset
-= buf
->stride
* start
;
740 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
744 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
746 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
748 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
751 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
752 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
754 struct panfrost_transfer transfer
=
755 panfrost_allocate_transient(ctx
, transfer_size
);
757 struct mali_sampler_descriptor
*desc
=
758 (struct mali_sampler_descriptor
*) transfer
.cpu
;
760 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
761 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
763 upload
= transfer
.gpu
;
766 if (t
== PIPE_SHADER_FRAGMENT
)
767 ctx
->payload_tiler
.postfix
.sampler_descriptor
= upload
;
768 else if (t
== PIPE_SHADER_VERTEX
)
769 ctx
->payload_vertex
.postfix
.sampler_descriptor
= upload
;
777 struct panfrost_context
*ctx
,
778 struct panfrost_sampler_view
*view
)
781 return (mali_ptr
) NULL
;
783 struct pipe_sampler_view
*pview
= &view
->base
;
784 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
786 /* Do we interleave an explicit stride with every element? */
788 bool has_manual_stride
=
789 view
->hw
.format
.usage2
& MALI_TEX_MANUAL_STRIDE
;
791 /* For easy access */
793 assert(pview
->target
!= PIPE_BUFFER
);
794 unsigned first_level
= pview
->u
.tex
.first_level
;
795 unsigned last_level
= pview
->u
.tex
.last_level
;
796 unsigned first_layer
= pview
->u
.tex
.first_layer
;
797 unsigned last_layer
= pview
->u
.tex
.last_layer
;
799 /* Lower-bit is set when sampling from colour AFBC */
800 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
801 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
802 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
804 /* Add the BO to the job so it's retained until the job is done. */
805 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
806 panfrost_job_add_bo(job
, rsrc
->bo
);
808 /* Inject the addresses in, interleaving mip levels, cube faces, and
809 * strides in that order */
813 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
814 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
816 view
->hw
.payload
[idx
++] =
817 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
819 if (has_manual_stride
) {
820 view
->hw
.payload
[idx
++] =
821 rsrc
->slices
[l
].stride
;
826 return panfrost_upload_transient(ctx
, &view
->hw
,
827 sizeof(struct mali_texture_descriptor
));
831 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
833 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
834 mali_ptr trampoline
= 0;
836 if (ctx
->sampler_view_count
[t
]) {
837 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
839 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
841 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
843 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
846 if (t
== PIPE_SHADER_FRAGMENT
)
847 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
848 else if (t
== PIPE_SHADER_VERTEX
)
849 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
855 struct sysval_uniform
{
863 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
864 struct sysval_uniform
*uniform
)
866 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
868 uniform
->f
[0] = vp
->scale
[0];
869 uniform
->f
[1] = vp
->scale
[1];
870 uniform
->f
[2] = vp
->scale
[2];
873 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
874 struct sysval_uniform
*uniform
)
876 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
878 uniform
->f
[0] = vp
->translate
[0];
879 uniform
->f
[1] = vp
->translate
[1];
880 uniform
->f
[2] = vp
->translate
[2];
883 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
884 enum pipe_shader_type st
,
885 unsigned int sysvalid
,
886 struct sysval_uniform
*uniform
)
888 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
889 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
890 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
891 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
894 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
897 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
898 tex
->u
.tex
.first_level
);
901 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
902 tex
->u
.tex
.first_level
);
905 uniform
->i
[dim
] = tex
->texture
->array_size
;
908 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
909 struct panfrost_shader_state
*ss
,
910 enum pipe_shader_type st
)
912 struct sysval_uniform
*uniforms
= (void *)buf
;
914 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
915 int sysval
= ss
->sysval
[i
];
917 switch (PAN_SYSVAL_TYPE(sysval
)) {
918 case PAN_SYSVAL_VIEWPORT_SCALE
:
919 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
921 case PAN_SYSVAL_VIEWPORT_OFFSET
:
922 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
924 case PAN_SYSVAL_TEXTURE_SIZE
:
925 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
935 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
937 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
938 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
941 return rsrc
->bo
->cpu
;
942 else if (cb
->user_buffer
)
943 return cb
->user_buffer
;
945 unreachable("No constant buffer");
949 panfrost_map_constant_buffer_gpu(
950 struct panfrost_context
*ctx
,
951 struct panfrost_constant_buffer
*buf
,
954 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
955 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
958 return rsrc
->bo
->gpu
;
959 else if (cb
->user_buffer
)
960 return panfrost_upload_transient(ctx
, cb
->user_buffer
, cb
->buffer_size
);
962 unreachable("No constant buffer");
965 /* Compute number of UBOs active (more specifically, compute the highest UBO
966 * number addressable -- if there are gaps, include them in the count anyway).
967 * We always include UBO #0 in the count, since we *need* uniforms enabled for
971 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
973 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
974 return 32 - __builtin_clz(mask
);
977 /* Fixes up a shader state with current state, returning a GPU address to the
981 panfrost_patch_shader_state(
982 struct panfrost_context
*ctx
,
983 struct panfrost_shader_state
*ss
,
984 enum pipe_shader_type stage
)
986 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
987 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
989 ss
->tripipe
->midgard1
.flags
= 0x220;
991 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
992 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
994 return ss
->tripipe_gpu
;
997 /* Go through dirty flags and actualise them in the cmdstream. */
1000 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1002 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1004 if (with_vertex_data
) {
1005 panfrost_emit_vertex_data(job
);
1007 /* Varyings emitted for -all- geometry */
1008 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
1009 panfrost_emit_varying_descriptor(ctx
, total_count
);
1012 bool msaa
= ctx
->rasterizer
->base
.multisample
;
1014 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1015 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1017 /* TODO: Sample size */
1018 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1019 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1022 panfrost_job_set_requirements(ctx
, job
);
1024 if (ctx
->occlusion_query
) {
1025 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1026 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1029 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1032 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1034 ctx
->payload_vertex
.postfix
._shader_upper
=
1035 panfrost_patch_shader_state(ctx
, vs
, PIPE_SHADER_VERTEX
) >> 4;
1038 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1039 /* Check if we need to link the gl_PointSize varying */
1040 if (!panfrost_writes_point_size(ctx
)) {
1041 /* If the size is constant, write it out. Otherwise,
1042 * don't touch primitive_size (since we would clobber
1043 * the pointer there) */
1045 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1049 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1051 ctx
->dirty
|= PAN_DIRTY_FS
;
1053 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1055 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1057 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
);
1059 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1062 COPY(attribute_count
);
1063 COPY(varying_count
);
1064 COPY(texture_count
);
1065 COPY(sampler_count
);
1066 COPY(sampler_count
);
1067 COPY(midgard1
.uniform_count
);
1068 COPY(midgard1
.uniform_buffer_count
);
1069 COPY(midgard1
.work_count
);
1070 COPY(midgard1
.flags
);
1071 COPY(midgard1
.unknown2
);
1075 /* Get blending setup */
1076 struct panfrost_blend_final blend
=
1077 panfrost_get_blend_for_context(ctx
, 0);
1079 /* If there is a blend shader, work registers are shared */
1081 if (blend
.is_shader
)
1082 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1084 /* Set late due to depending on render state */
1085 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
1087 /* Depending on whether it's legal to in the given shader, we
1088 * try to enable early-z testing (or forward-pixel kill?) */
1090 if (!variant
->can_discard
)
1091 flags
|= MALI_EARLY_Z
;
1093 /* Any time texturing is used, derivatives are implicitly
1094 * calculated, so we need to enable helper invocations */
1096 if (ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
])
1097 flags
|= MALI_HELPER_INVOCATIONS
;
1099 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1101 /* Assign the stencil refs late */
1102 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1103 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1105 /* CAN_DISCARD should be set if the fragment shader possibly
1106 * contains a 'discard' instruction. It is likely this is
1107 * related to optimizations related to forward-pixel kill, as
1108 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1109 * thing?" by Peter Harris
1112 if (variant
->can_discard
) {
1113 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1114 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1117 /* Check if we're using the default blend descriptor (fast path) */
1121 (blend
.equation
.equation
->rgb_mode
== 0x122) &&
1122 (blend
.equation
.equation
->alpha_mode
== 0x122) &&
1123 (blend
.equation
.equation
->color_mask
== 0xf);
1125 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1126 * *also* copied to the blend_meta appended (by convention),
1127 * but this is the field actually read by the hardware. (Or
1128 * maybe both are read...?) */
1130 if (blend
.is_shader
) {
1131 ctx
->fragment_shader_core
.blend
.shader
=
1134 ctx
->fragment_shader_core
.blend
.shader
= 0;
1137 if (ctx
->require_sfbd
) {
1138 /* When only a single render target platform is used, the blend
1139 * information is inside the shader meta itself. We
1140 * additionally need to signal CAN_DISCARD for nontrivial blend
1141 * modes (so we're able to read back the destination buffer) */
1143 if (!blend
.is_shader
) {
1144 ctx
->fragment_shader_core
.blend
.equation
=
1145 *blend
.equation
.equation
;
1146 ctx
->fragment_shader_core
.blend
.constant
=
1147 blend
.equation
.constant
;
1151 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1155 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1156 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1157 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1159 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1161 if (!ctx
->require_sfbd
) {
1162 /* Additional blend descriptor tacked on for jobs using MFBD */
1164 unsigned blend_count
= 0x200;
1166 if (blend
.is_shader
) {
1167 /* For a blend shader, the bottom nibble corresponds to
1168 * the number of work registers used, which signals the
1169 * -existence- of a blend shader */
1171 assert(blend
.shader
.work_count
>= 2);
1172 blend_count
|= MIN2(blend
.shader
.work_count
, 3);
1174 /* Otherwise, the bottom bit simply specifies if
1175 * blending (anything other than REPLACE) is enabled */
1182 struct midgard_blend_rt rts
[4];
1186 for (unsigned i
= 0; i
< 1; ++i
) {
1188 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1189 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1191 rts
[i
].flags
= blend_count
;
1194 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1196 /* TODO: sRGB in blend shaders is currently
1197 * unimplemented. Contact me (Alyssa) if you're
1198 * interested in working on this. We have
1199 * native Midgard ops for helping here, but
1200 * they're not well-understood yet. */
1202 assert(!(is_srgb
&& blend
.is_shader
));
1204 if (blend
.is_shader
) {
1205 rts
[i
].blend
.shader
= blend
.shader
.gpu
;
1207 rts
[i
].blend
.equation
= *blend
.equation
.equation
;
1208 rts
[i
].blend
.constant
= blend
.equation
.constant
;
1212 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1216 /* We stage to transient, so always dirty.. */
1217 panfrost_stage_attributes(ctx
);
1219 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1220 panfrost_upload_sampler_descriptors(ctx
);
1222 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1223 panfrost_upload_texture_descriptors(ctx
);
1225 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1227 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1228 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1230 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1231 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1232 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1234 /* Uniforms are implicitly UBO #0 */
1235 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1237 /* Allocate room for the sysval and the uniforms */
1238 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1239 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1240 size_t size
= sys_size
+ uniform_size
;
1241 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1243 /* Upload sysvals requested by the shader */
1244 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1246 /* Upload uniforms */
1248 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1249 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1252 int uniform_count
= 0;
1254 struct mali_vertex_tiler_postfix
*postfix
;
1257 case PIPE_SHADER_VERTEX
:
1258 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1259 postfix
= &ctx
->payload_vertex
.postfix
;
1262 case PIPE_SHADER_FRAGMENT
:
1263 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1264 postfix
= &ctx
->payload_tiler
.postfix
;
1268 unreachable("Invalid shader stage\n");
1271 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1274 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1275 assert(ubo_count
>= 1);
1277 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1278 struct mali_uniform_buffer_meta
*ubos
= calloc(sz
, 1);
1280 /* Upload uniforms as a UBO */
1281 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1282 ubos
[0].ptr
= transfer
.gpu
>> 2;
1284 /* The rest are honest-to-goodness UBOs */
1286 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1287 size_t sz
= buf
->cb
[ubo
].buffer_size
;
1289 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1290 bool empty
= sz
== 0;
1292 if (!enabled
|| empty
) {
1293 /* Stub out disabled UBOs to catch accesses */
1296 ubos
[ubo
].ptr
= 0xDEAD0000;
1300 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1302 unsigned bytes_per_field
= 16;
1303 unsigned aligned
= ALIGN_POT(sz
, bytes_per_field
);
1304 unsigned fields
= aligned
/ bytes_per_field
;
1306 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1307 ubos
[ubo
].ptr
= gpu
>> 2;
1310 mali_ptr ubufs
= panfrost_upload_transient(ctx
, ubos
, sz
);
1311 postfix
->uniforms
= transfer
.gpu
;
1312 postfix
->uniform_buffers
= ubufs
;
1314 buf
->dirty_mask
= 0;
1317 /* TODO: Upload the viewport somewhere more appropriate */
1319 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1320 * (somewhat) asymmetric ints. */
1321 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1323 struct mali_viewport view
= {
1324 /* By default, do no viewport clipping, i.e. clip to (-inf,
1325 * inf) in each direction. Clipping to the viewport in theory
1326 * should work, but in practice causes issues when we're not
1327 * explicitly trying to scissor */
1329 .clip_minx
= -INFINITY
,
1330 .clip_miny
= -INFINITY
,
1331 .clip_maxx
= INFINITY
,
1332 .clip_maxy
= INFINITY
,
1338 /* Always scissor to the viewport by default. */
1339 int minx
= (int) (vp
->translate
[0] - vp
->scale
[0]);
1340 int maxx
= (int) (vp
->translate
[0] + vp
->scale
[0]);
1342 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1343 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1345 /* Apply the scissor test */
1347 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1354 /* Hardware needs the min/max to be strictly ordered, so flip if we
1355 * need to. The viewport transformation in the vertex shader will
1356 * handle the negatives if we don't */
1370 /* Clamp everything positive, just in case */
1372 maxx
= MAX2(0, maxx
);
1373 maxy
= MAX2(0, maxy
);
1374 minx
= MAX2(0, minx
);
1375 miny
= MAX2(0, miny
);
1377 /* Clamp to the framebuffer size as a last check */
1379 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1380 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1382 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1383 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1385 /* Update the job, unless we're doing wallpapering (whose lack of
1386 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1387 * just... be faster :) */
1389 if (!ctx
->wallpaper_batch
)
1390 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1394 view
.viewport0
[0] = minx
;
1395 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1397 view
.viewport0
[1] = miny
;
1398 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1400 ctx
->payload_tiler
.postfix
.viewport
=
1401 panfrost_upload_transient(ctx
,
1403 sizeof(struct mali_viewport
));
1408 /* Corresponds to exactly one draw, but does not submit anything */
1411 panfrost_queue_draw(struct panfrost_context
*ctx
)
1413 /* Handle dirty flags now */
1414 panfrost_emit_for_draw(ctx
, true);
1416 /* If rasterizer discard is enable, only submit the vertex */
1418 bool rasterizer_discard
= ctx
->rasterizer
1419 && ctx
->rasterizer
->base
.rasterizer_discard
;
1421 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1422 struct panfrost_transfer tiler
;
1424 if (!rasterizer_discard
)
1425 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1427 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1429 if (rasterizer_discard
)
1430 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1431 else if (ctx
->wallpaper_batch
)
1432 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1434 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1437 /* The entire frame is in memory -- send it off to the kernel! */
1440 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1441 struct pipe_fence_handle
**fence
,
1442 struct panfrost_job
*job
)
1444 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1445 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1449 panfrost_job_submit(ctx
, job
);
1451 /* If visual, we can stall a frame */
1453 if (!flush_immediate
)
1454 panfrost_drm_force_flush_fragment(ctx
, fence
);
1456 screen
->last_fragment_flushed
= false;
1457 screen
->last_job
= job
;
1459 /* If readback, flush now (hurts the pipelined performance) */
1460 if (flush_immediate
)
1461 panfrost_drm_force_flush_fragment(ctx
, fence
);
1466 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1468 struct panfrost_context
*ctx
= pan_context(pipe
);
1470 /* Nothing to reload? TODO: MRT wallpapers */
1471 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1474 /* Check if the buffer has any content on it worth preserving */
1476 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1477 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1478 unsigned level
= surf
->u
.tex
.level
;
1480 if (!rsrc
->slices
[level
].initialized
)
1483 /* Save the batch */
1484 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1486 ctx
->wallpaper_batch
= batch
;
1487 panfrost_blit_wallpaper(ctx
);
1488 ctx
->wallpaper_batch
= NULL
;
1493 struct pipe_context
*pipe
,
1494 struct pipe_fence_handle
**fence
,
1497 struct panfrost_context
*ctx
= pan_context(pipe
);
1498 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1500 /* Nothing to do! */
1501 if (!job
->last_job
.gpu
&& !job
->clear
) return;
1504 panfrost_draw_wallpaper(&ctx
->base
);
1506 /* Whether to stall the pipeline for immediately correct results. Since
1507 * pipelined rendering is quite broken right now (to be fixed by the
1508 * panfrost_job refactor, just take the perf hit for correctness) */
1509 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1511 /* Submit the frame itself */
1512 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1514 /* Prepare for the next frame */
1515 panfrost_invalidate_frame(ctx
);
1518 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1521 g2m_draw_mode(enum pipe_prim_type mode
)
1524 DEFINE_CASE(POINTS
);
1526 DEFINE_CASE(LINE_LOOP
);
1527 DEFINE_CASE(LINE_STRIP
);
1528 DEFINE_CASE(TRIANGLES
);
1529 DEFINE_CASE(TRIANGLE_STRIP
);
1530 DEFINE_CASE(TRIANGLE_FAN
);
1532 DEFINE_CASE(QUAD_STRIP
);
1533 DEFINE_CASE(POLYGON
);
1536 unreachable("Invalid draw mode");
1543 panfrost_translate_index_size(unsigned size
)
1547 return MALI_DRAW_INDEXED_UINT8
;
1550 return MALI_DRAW_INDEXED_UINT16
;
1553 return MALI_DRAW_INDEXED_UINT32
;
1556 unreachable("Invalid index size");
1560 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1561 * good for the duration of the draw (transient), could last longer */
1564 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1566 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1568 off_t offset
= info
->start
* info
->index_size
;
1569 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1571 if (!info
->has_user_indices
) {
1572 /* Only resources can be directly mapped */
1573 panfrost_job_add_bo(batch
, rsrc
->bo
);
1574 return rsrc
->bo
->gpu
+ offset
;
1576 /* Otherwise, we need to upload to transient memory */
1577 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1578 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1583 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1585 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1587 /* Check if we're scissoring at all */
1589 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1592 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1597 struct pipe_context
*pipe
,
1598 const struct pipe_draw_info
*info
)
1600 struct panfrost_context
*ctx
= pan_context(pipe
);
1602 /* First of all, check the scissor to see if anything is drawn at all.
1603 * If it's not, we drop the draw (mostly a conformance issue;
1604 * well-behaved apps shouldn't hit this) */
1606 if (panfrost_scissor_culls_everything(ctx
))
1609 ctx
->payload_vertex
.draw_start
= info
->start
;
1610 ctx
->payload_tiler
.draw_start
= info
->start
;
1612 int mode
= info
->mode
;
1614 /* Fallback unsupported restart index */
1615 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1617 if (info
->primitive_restart
&& info
->index_size
1618 && info
->restart_index
!= primitive_index
) {
1619 util_draw_vbo_without_prim_restart(pipe
, info
);
1623 /* Fallback for unsupported modes */
1625 if (!(ctx
->draw_modes
& (1 << mode
))) {
1626 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1627 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1629 if (info
->count
< 4) {
1630 /* Degenerate case? */
1634 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1635 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1640 /* Now that we have a guaranteed terminating path, find the job.
1641 * Assignment commented out to prevent unused warning */
1643 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1645 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1647 ctx
->vertex_count
= info
->count
;
1648 ctx
->instance_count
= info
->instance_count
;
1650 /* For non-indexed draws, they're the same */
1651 unsigned vertex_count
= ctx
->vertex_count
;
1653 unsigned draw_flags
= 0;
1655 /* The draw flags interpret how primitive size is interpreted */
1657 if (panfrost_writes_point_size(ctx
))
1658 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1660 if (info
->primitive_restart
)
1661 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1663 /* For higher amounts of vertices (greater than what fits in a 16-bit
1664 * short), the other value is needed, otherwise there will be bizarre
1665 * rendering artefacts. It's not clear what these values mean yet. This
1666 * change is also needed for instancing and sometimes points (perhaps
1667 * related to dynamically setting gl_PointSize) */
1669 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1670 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1671 bool instanced
= ctx
->instance_count
> 1;
1673 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1675 /* This doesn't make much sense */
1676 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1677 draw_flags
|= 0x800;
1680 if (info
->index_size
) {
1681 /* Calculate the min/max index used so we can figure out how
1682 * many times to invoke the vertex shader */
1684 /* Fetch / calculate index bounds */
1685 unsigned min_index
= 0, max_index
= 0;
1687 if (info
->max_index
== ~0u) {
1688 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1690 min_index
= info
->min_index
;
1691 max_index
= info
->max_index
;
1694 /* Use the corresponding values */
1695 vertex_count
= max_index
- min_index
+ 1;
1696 ctx
->payload_vertex
.draw_start
= min_index
;
1697 ctx
->payload_tiler
.draw_start
= min_index
;
1699 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1700 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1702 //assert(!info->restart_index); /* TODO: Research */
1703 assert(!info
->index_bias
);
1705 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1706 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1708 /* Index count == vertex count, if no indexing is applied, as
1709 * if it is internally indexed in the expected order */
1711 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1712 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1714 /* Reverse index state */
1715 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1718 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1719 * vertex_count, 1) */
1721 panfrost_pack_work_groups_fused(
1722 &ctx
->payload_vertex
.prefix
,
1723 &ctx
->payload_tiler
.prefix
,
1724 1, vertex_count
, info
->instance_count
,
1727 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1729 /* Encode the padded vertex count */
1731 if (info
->instance_count
> 1) {
1732 /* Triangles have non-even vertex counts so they change how
1733 * padding works internally */
1736 mode
== PIPE_PRIM_TRIANGLES
||
1737 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1738 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1740 struct pan_shift_odd so
=
1741 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1743 ctx
->payload_vertex
.instance_shift
= so
.shift
;
1744 ctx
->payload_tiler
.instance_shift
= so
.shift
;
1746 ctx
->payload_vertex
.instance_odd
= so
.odd
;
1747 ctx
->payload_tiler
.instance_odd
= so
.odd
;
1749 ctx
->padded_count
= pan_expand_shift_odd(so
);
1751 ctx
->padded_count
= ctx
->vertex_count
;
1753 /* Reset instancing state */
1754 ctx
->payload_vertex
.instance_shift
= 0;
1755 ctx
->payload_vertex
.instance_odd
= 0;
1756 ctx
->payload_tiler
.instance_shift
= 0;
1757 ctx
->payload_tiler
.instance_odd
= 0;
1760 /* Fire off the draw itself */
1761 panfrost_queue_draw(ctx
);
1767 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1773 panfrost_create_rasterizer_state(
1774 struct pipe_context
*pctx
,
1775 const struct pipe_rasterizer_state
*cso
)
1777 struct panfrost_context
*ctx
= pan_context(pctx
);
1778 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1782 /* Bitmask, unknown meaning of the start value */
1783 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1786 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1788 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1789 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1791 if (cso
->cull_face
& PIPE_FACE_BACK
)
1792 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1798 panfrost_bind_rasterizer_state(
1799 struct pipe_context
*pctx
,
1802 struct panfrost_context
*ctx
= pan_context(pctx
);
1804 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1808 ctx
->rasterizer
= hwcso
;
1809 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1811 /* Point sprites are emulated */
1813 struct panfrost_shader_state
*variant
=
1814 ctx
->fs
? &ctx
->fs
->variants
[ctx
->fs
->active_variant
] : NULL
;
1816 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1817 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
1821 panfrost_create_vertex_elements_state(
1822 struct pipe_context
*pctx
,
1823 unsigned num_elements
,
1824 const struct pipe_vertex_element
*elements
)
1826 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1828 so
->num_elements
= num_elements
;
1829 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1831 /* XXX: What the cornball? This is totally, 100%, unapologetically
1832 * nonsense. And yet it somehow fixes a regression in -bshadow
1833 * (previously, we allocated the descriptor here... a newer commit
1834 * removed that allocation, and then memory corruption led to
1835 * shader_meta getting overwritten in bad ways and then the whole test
1836 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1838 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1840 for (int i
= 0; i
< num_elements
; ++i
) {
1841 so
->hw
[i
].index
= i
;
1843 enum pipe_format fmt
= elements
[i
].src_format
;
1844 const struct util_format_description
*desc
= util_format_description(fmt
);
1845 so
->hw
[i
].unknown1
= 0x2;
1846 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1848 so
->hw
[i
].format
= panfrost_find_format(desc
);
1850 /* The field itself should probably be shifted over */
1851 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1858 panfrost_bind_vertex_elements_state(
1859 struct pipe_context
*pctx
,
1862 struct panfrost_context
*ctx
= pan_context(pctx
);
1864 ctx
->vertex
= hwcso
;
1865 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1869 panfrost_create_shader_state(
1870 struct pipe_context
*pctx
,
1871 const struct pipe_shader_state
*cso
)
1873 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1876 /* Token deep copy to prevent memory corruption */
1878 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1879 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1885 panfrost_delete_shader_state(
1886 struct pipe_context
*pctx
,
1889 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1891 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1892 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1899 panfrost_create_sampler_state(
1900 struct pipe_context
*pctx
,
1901 const struct pipe_sampler_state
*cso
)
1903 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1906 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1908 struct mali_sampler_descriptor sampler_descriptor
= {
1909 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1910 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1911 | translate_mip_filter(cso
->min_mip_filter
)
1914 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1915 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1916 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1917 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1919 cso
->border_color
.f
[0],
1920 cso
->border_color
.f
[1],
1921 cso
->border_color
.f
[2],
1922 cso
->border_color
.f
[3]
1924 .min_lod
= FIXED_16(cso
->min_lod
),
1925 .max_lod
= FIXED_16(cso
->max_lod
),
1926 .seamless_cube_map
= cso
->seamless_cube_map
,
1929 /* If necessary, we disable mipmapping in the sampler descriptor by
1930 * clamping the LOD as tight as possible (from 0 to epsilon,
1931 * essentially -- remember these are fixed point numbers, so
1934 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1935 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1937 /* Enforce that there is something in the middle by adding epsilon*/
1939 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1940 sampler_descriptor
.max_lod
++;
1943 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1945 so
->hw
= sampler_descriptor
;
1951 panfrost_bind_sampler_states(
1952 struct pipe_context
*pctx
,
1953 enum pipe_shader_type shader
,
1954 unsigned start_slot
, unsigned num_sampler
,
1957 assert(start_slot
== 0);
1959 struct panfrost_context
*ctx
= pan_context(pctx
);
1961 /* XXX: Should upload, not just copy? */
1962 ctx
->sampler_count
[shader
] = num_sampler
;
1963 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1965 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1969 panfrost_variant_matches(
1970 struct panfrost_context
*ctx
,
1971 struct panfrost_shader_state
*variant
,
1972 enum pipe_shader_type type
)
1974 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1975 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1977 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1979 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1980 /* Make sure enable state is at least the same */
1981 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1985 /* Check that the contents of the test are the same */
1986 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1987 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1989 if (!(same_func
&& same_ref
)) {
1994 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1995 variant
->point_sprite_mask
)) {
1996 /* Ensure the same varyings are turned to point sprites */
1997 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
2000 /* Ensure the orientation is correct */
2002 rasterizer
->sprite_coord_mode
==
2003 PIPE_SPRITE_COORD_UPPER_LEFT
;
2005 if (variant
->point_sprite_upper_left
!= upper_left
)
2009 /* Otherwise, we're good to go */
2014 panfrost_bind_shader_state(
2015 struct pipe_context
*pctx
,
2017 enum pipe_shader_type type
)
2019 struct panfrost_context
*ctx
= pan_context(pctx
);
2021 if (type
== PIPE_SHADER_FRAGMENT
) {
2023 ctx
->dirty
|= PAN_DIRTY_FS
;
2025 assert(type
== PIPE_SHADER_VERTEX
);
2027 ctx
->dirty
|= PAN_DIRTY_VS
;
2032 /* Match the appropriate variant */
2034 signed variant
= -1;
2035 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2037 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2038 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2044 if (variant
== -1) {
2045 /* No variant matched, so create a new one */
2046 variant
= variants
->variant_count
++;
2047 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2049 struct panfrost_shader_state
*v
=
2050 &variants
->variants
[variant
];
2054 if (type
== PIPE_SHADER_FRAGMENT
) {
2055 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2057 if (ctx
->rasterizer
) {
2058 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2059 v
->point_sprite_upper_left
=
2060 ctx
->rasterizer
->base
.sprite_coord_mode
==
2061 PIPE_SPRITE_COORD_UPPER_LEFT
;
2065 /* Allocate the mapped descriptor ahead-of-time. */
2066 struct panfrost_context
*ctx
= pan_context(pctx
);
2067 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2069 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2070 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
2074 /* Select this variant */
2075 variants
->active_variant
= variant
;
2077 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2078 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2080 /* We finally have a variant, so compile it */
2082 if (!shader_state
->compiled
) {
2083 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
2084 panfrost_job_type_for_pipe(type
), shader_state
);
2086 shader_state
->compiled
= true;
2091 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2093 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2097 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2099 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2103 panfrost_set_vertex_buffers(
2104 struct pipe_context
*pctx
,
2105 unsigned start_slot
,
2106 unsigned num_buffers
,
2107 const struct pipe_vertex_buffer
*buffers
)
2109 struct panfrost_context
*ctx
= pan_context(pctx
);
2111 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2115 panfrost_set_constant_buffer(
2116 struct pipe_context
*pctx
,
2117 enum pipe_shader_type shader
, uint index
,
2118 const struct pipe_constant_buffer
*buf
)
2120 struct panfrost_context
*ctx
= pan_context(pctx
);
2121 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2123 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2125 unsigned mask
= (1 << index
);
2127 if (unlikely(!buf
)) {
2128 pbuf
->enabled_mask
&= ~mask
;
2129 pbuf
->dirty_mask
&= ~mask
;
2133 pbuf
->enabled_mask
|= mask
;
2134 pbuf
->dirty_mask
|= mask
;
2138 panfrost_set_stencil_ref(
2139 struct pipe_context
*pctx
,
2140 const struct pipe_stencil_ref
*ref
)
2142 struct panfrost_context
*ctx
= pan_context(pctx
);
2143 ctx
->stencil_ref
= *ref
;
2145 /* Shader core dirty */
2146 ctx
->dirty
|= PAN_DIRTY_FS
;
2149 static enum mali_texture_type
2150 panfrost_translate_texture_type(enum pipe_texture_target t
)
2154 case PIPE_TEXTURE_1D
:
2155 case PIPE_TEXTURE_1D_ARRAY
:
2158 case PIPE_TEXTURE_2D
:
2159 case PIPE_TEXTURE_2D_ARRAY
:
2160 case PIPE_TEXTURE_RECT
:
2163 case PIPE_TEXTURE_3D
:
2166 case PIPE_TEXTURE_CUBE
:
2167 case PIPE_TEXTURE_CUBE_ARRAY
:
2168 return MALI_TEX_CUBE
;
2171 unreachable("Unknown target");
2175 static struct pipe_sampler_view
*
2176 panfrost_create_sampler_view(
2177 struct pipe_context
*pctx
,
2178 struct pipe_resource
*texture
,
2179 const struct pipe_sampler_view
*template)
2181 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2182 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2184 pipe_reference(NULL
, &texture
->reference
);
2186 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2189 so
->base
= *template;
2190 so
->base
.texture
= texture
;
2191 so
->base
.reference
.count
= 1;
2192 so
->base
.context
= pctx
;
2194 /* sampler_views correspond to texture descriptors, minus the texture
2195 * (data) itself. So, we serialise the descriptor here and cache it for
2198 /* TODO: Detect from format better */
2199 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2201 unsigned char user_swizzle
[4] = {
2202 template->swizzle_r
,
2203 template->swizzle_g
,
2204 template->swizzle_b
,
2208 enum mali_format format
= panfrost_find_format(desc
);
2210 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2212 unsigned usage2_layout
= 0x10;
2214 switch (prsrc
->layout
) {
2216 usage2_layout
|= 0x8 | 0x4;
2219 usage2_layout
|= 0x1;
2222 usage2_layout
|= is_depth
? 0x1 : 0x2;
2229 /* Check if we need to set a custom stride by computing the "expected"
2230 * stride and comparing it to what the BO actually wants. Only applies
2231 * to linear textures, since tiled/compressed textures have strict
2232 * alignment requirements for their strides as it is */
2234 unsigned first_level
= template->u
.tex
.first_level
;
2235 unsigned last_level
= template->u
.tex
.last_level
;
2237 if (prsrc
->layout
== PAN_LINEAR
) {
2238 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2239 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2240 unsigned width
= u_minify(texture
->width0
, l
);
2241 unsigned comp_stride
= width
* bytes_per_pixel
;
2243 if (comp_stride
!= actual_stride
) {
2244 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2250 /* In the hardware, array_size refers specifically to array textures,
2251 * whereas in Gallium, it also covers cubemaps */
2253 unsigned array_size
= texture
->array_size
;
2255 if (template->target
== PIPE_TEXTURE_CUBE
) {
2256 /* TODO: Cubemap arrays */
2257 assert(array_size
== 6);
2261 struct mali_texture_descriptor texture_descriptor
= {
2262 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2263 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2264 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2265 .array_size
= MALI_POSITIVE(array_size
),
2269 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2272 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2273 .type
= panfrost_translate_texture_type(template->target
),
2275 .usage2
= usage2_layout
2278 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2281 texture_descriptor
.nr_mipmap_levels
= last_level
- first_level
;
2283 so
->hw
= texture_descriptor
;
2285 return (struct pipe_sampler_view
*) so
;
2289 panfrost_set_sampler_views(
2290 struct pipe_context
*pctx
,
2291 enum pipe_shader_type shader
,
2292 unsigned start_slot
, unsigned num_views
,
2293 struct pipe_sampler_view
**views
)
2295 struct panfrost_context
*ctx
= pan_context(pctx
);
2297 assert(start_slot
== 0);
2299 unsigned new_nr
= 0;
2300 for (unsigned i
= 0; i
< num_views
; ++i
) {
2305 ctx
->sampler_view_count
[shader
] = new_nr
;
2306 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2308 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2312 panfrost_sampler_view_destroy(
2313 struct pipe_context
*pctx
,
2314 struct pipe_sampler_view
*view
)
2316 pipe_resource_reference(&view
->texture
, NULL
);
2321 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2322 const struct pipe_framebuffer_state
*fb
)
2324 struct panfrost_context
*ctx
= pan_context(pctx
);
2326 /* Flush when switching framebuffers, but not if the framebuffer
2327 * state is being restored by u_blitter
2330 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
2331 bool is_scanout
= panfrost_is_scanout(ctx
);
2332 bool has_draws
= job
->last_job
.gpu
;
2334 if (!ctx
->wallpaper_batch
&& (!is_scanout
|| has_draws
)) {
2335 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2338 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2339 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2340 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2341 ctx
->pipe_framebuffer
.width
= fb
->width
;
2342 ctx
->pipe_framebuffer
.height
= fb
->height
;
2344 struct pipe_surface
*zb
= fb
->zsbuf
;
2345 bool needs_reattach
= false;
2347 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2348 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2350 /* check if changing cbuf */
2351 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2354 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2356 needs_reattach
|= (cb
!= NULL
);
2359 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2360 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2361 needs_reattach
|= (zb
!= NULL
);
2364 if (needs_reattach
) {
2365 if (ctx
->require_sfbd
)
2366 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2368 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2370 panfrost_attach_vt_framebuffer(ctx
);
2375 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2376 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2378 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2382 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2385 struct panfrost_context
*ctx
= pan_context(pipe
);
2386 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2387 ctx
->depth_stencil
= depth_stencil
;
2392 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2393 * emulated in the fragment shader */
2395 if (depth_stencil
->alpha
.enabled
) {
2396 /* We need to trigger a new shader (maybe) */
2397 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2401 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2403 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2404 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2406 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2407 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2409 /* Depth state (TODO: Refactor) */
2410 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2412 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2414 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2415 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2417 /* Bounds test not implemented */
2418 assert(!depth_stencil
->depth
.bounds_test
);
2420 ctx
->dirty
|= PAN_DIRTY_FS
;
2424 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2430 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2431 unsigned sample_mask
)
2436 panfrost_set_clip_state(struct pipe_context
*pipe
,
2437 const struct pipe_clip_state
*clip
)
2439 //struct panfrost_context *panfrost = pan_context(pipe);
2443 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2444 unsigned start_slot
,
2445 unsigned num_viewports
,
2446 const struct pipe_viewport_state
*viewports
)
2448 struct panfrost_context
*ctx
= pan_context(pipe
);
2450 assert(start_slot
== 0);
2451 assert(num_viewports
== 1);
2453 ctx
->pipe_viewport
= *viewports
;
2457 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2458 unsigned start_slot
,
2459 unsigned num_scissors
,
2460 const struct pipe_scissor_state
*scissors
)
2462 struct panfrost_context
*ctx
= pan_context(pipe
);
2464 assert(start_slot
== 0);
2465 assert(num_scissors
== 1);
2467 ctx
->scissor
= *scissors
;
2471 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2472 const struct pipe_poly_stipple
*stipple
)
2474 //struct panfrost_context *panfrost = pan_context(pipe);
2478 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2481 //struct panfrost_context *panfrost = pan_context(pipe);
2485 panfrost_destroy(struct pipe_context
*pipe
)
2487 struct panfrost_context
*panfrost
= pan_context(pipe
);
2488 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2490 if (panfrost
->blitter
)
2491 util_blitter_destroy(panfrost
->blitter
);
2493 if (panfrost
->blitter_wallpaper
)
2494 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2496 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2497 panfrost_drm_free_slab(screen
, &panfrost
->varying_mem
);
2498 panfrost_drm_free_slab(screen
, &panfrost
->shaders
);
2499 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2500 panfrost_drm_free_slab(screen
, &panfrost
->tiler_polygon_list
);
2501 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2503 for (int i
= 0; i
< ARRAY_SIZE(panfrost
->transient_pools
); ++i
) {
2504 struct panfrost_memory_entry
*entry
;
2505 entry
= panfrost
->transient_pools
[i
].entries
[0];
2506 pb_slab_free(&screen
->slabs
, (struct pb_slab_entry
*)entry
);
2512 static struct pipe_query
*
2513 panfrost_create_query(struct pipe_context
*pipe
,
2517 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2522 return (struct pipe_query
*) q
;
2526 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2532 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2534 struct panfrost_context
*ctx
= pan_context(pipe
);
2535 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2537 switch (query
->type
) {
2538 case PIPE_QUERY_OCCLUSION_COUNTER
:
2539 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2540 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2542 /* Allocate a word for the query results to be stored */
2543 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2545 ctx
->occlusion_query
= query
;
2551 DBG("Skipping query %d\n", query
->type
);
2559 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2561 struct panfrost_context
*ctx
= pan_context(pipe
);
2562 ctx
->occlusion_query
= NULL
;
2567 panfrost_get_query_result(struct pipe_context
*pipe
,
2568 struct pipe_query
*q
,
2570 union pipe_query_result
*vresult
)
2573 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2575 /* We need to flush out the jobs to actually run the counter, TODO
2576 * check wait, TODO wallpaper after if needed */
2578 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2580 switch (query
->type
) {
2581 case PIPE_QUERY_OCCLUSION_COUNTER
:
2582 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2583 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2584 /* Read back the query results */
2585 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2586 unsigned passed
= *result
;
2588 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2589 vresult
->u64
= passed
;
2591 vresult
->b
= !!passed
;
2597 DBG("Skipped query get %d\n", query
->type
);
2604 static struct pipe_stream_output_target
*
2605 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2606 struct pipe_resource
*prsc
,
2607 unsigned buffer_offset
,
2608 unsigned buffer_size
)
2610 struct pipe_stream_output_target
*target
;
2612 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2617 pipe_reference_init(&target
->reference
, 1);
2618 pipe_resource_reference(&target
->buffer
, prsc
);
2620 target
->context
= pctx
;
2621 target
->buffer_offset
= buffer_offset
;
2622 target
->buffer_size
= buffer_size
;
2628 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2629 struct pipe_stream_output_target
*target
)
2631 pipe_resource_reference(&target
->buffer
, NULL
);
2632 ralloc_free(target
);
2636 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2637 unsigned num_targets
,
2638 struct pipe_stream_output_target
**targets
,
2639 const unsigned *offsets
)
2645 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2647 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2648 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2650 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2651 /* Allocate the beginning of the transient pool */
2652 int entry_size
= (1 << 22); /* 4MB */
2654 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2655 ctx
->transient_pools
[i
].entry_count
= 1;
2657 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2660 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2661 panfrost_drm_allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2662 panfrost_drm_allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2663 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2664 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2665 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2668 /* New context creation, which also does hardware initialisation since I don't
2669 * know the better way to structure this :smirk: */
2671 struct pipe_context
*
2672 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2674 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2675 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2676 memset(ctx
, 0, sizeof(*ctx
));
2677 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2680 gpu_id
= panfrost_drm_query_gpu_version(pscreen
);
2682 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2683 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2685 gallium
->screen
= screen
;
2687 gallium
->destroy
= panfrost_destroy
;
2689 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2691 gallium
->flush
= panfrost_flush
;
2692 gallium
->clear
= panfrost_clear
;
2693 gallium
->draw_vbo
= panfrost_draw_vbo
;
2695 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2696 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2698 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2700 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2701 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2702 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2704 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2705 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2706 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2708 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2709 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2710 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2712 gallium
->create_fs_state
= panfrost_create_shader_state
;
2713 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2714 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2716 gallium
->create_vs_state
= panfrost_create_shader_state
;
2717 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2718 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2720 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2721 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2722 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2724 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2725 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2726 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2728 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2730 gallium
->set_clip_state
= panfrost_set_clip_state
;
2731 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2732 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2733 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2734 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2736 gallium
->create_query
= panfrost_create_query
;
2737 gallium
->destroy_query
= panfrost_destroy_query
;
2738 gallium
->begin_query
= panfrost_begin_query
;
2739 gallium
->end_query
= panfrost_end_query
;
2740 gallium
->get_query_result
= panfrost_get_query_result
;
2742 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2743 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2744 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2746 panfrost_resource_context_init(gallium
);
2747 panfrost_blend_context_init(gallium
);
2749 panfrost_drm_init_context(ctx
);
2751 panfrost_setup_hardware(ctx
);
2754 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2755 gallium
->const_uploader
= gallium
->stream_uploader
;
2756 assert(gallium
->stream_uploader
);
2758 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2759 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2761 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2763 ctx
->blitter
= util_blitter_create(gallium
);
2764 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2766 assert(ctx
->blitter
);
2767 assert(ctx
->blitter_wallpaper
);
2769 /* Prepare for render! */
2771 panfrost_job_init(ctx
);
2772 panfrost_emit_vertex_payload(ctx
);
2773 panfrost_emit_tiler_payload(ctx
);
2774 panfrost_invalidate_frame(ctx
);
2775 panfrost_default_shader_backend(ctx
);