2 * © Copyright 2018 Alyssa Rosenzweig
3 * Copyright © 2014-2017 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 #include "pan_context.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "util/u_prim_restart.h"
42 #include "indices/u_primconvert.h"
43 #include "tgsi/tgsi_parse.h"
44 #include "tgsi/tgsi_from_mesa.h"
45 #include "util/u_math.h"
47 #include "pan_screen.h"
48 #include "pan_blending.h"
49 #include "pan_blend_shaders.h"
51 #include "pan_tiler.h"
53 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
56 /* Framebuffer descriptor */
58 static struct midgard_tiler_descriptor
59 panfrost_emit_midg_tiler(
60 struct panfrost_context
*ctx
,
63 unsigned vertex_count
)
65 struct midgard_tiler_descriptor t
= {};
66 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
69 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
71 /* Compute the polygon header size and use that to offset the body */
73 unsigned header_size
= panfrost_tiler_header_size(
74 width
, height
, t
.hierarchy_mask
);
76 unsigned body_size
= panfrost_tiler_body_size(
77 width
, height
, t
.hierarchy_mask
);
81 if (t
.hierarchy_mask
) {
82 t
.polygon_list
= panfrost_job_get_polygon_list(batch
, header_size
+ body_size
);
84 /* Allow the entire tiler heap */
85 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
87 ctx
->tiler_heap
.bo
->gpu
+ ctx
->tiler_heap
.bo
->size
;
89 /* The tiler is disabled, so don't allow the tiler heap */
90 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
91 t
.heap_end
= t
.heap_start
;
93 /* Use a dummy polygon list */
94 t
.polygon_list
= ctx
->tiler_dummy
.bo
->gpu
;
96 /* Also, set a "tiler disabled?" flag? */
97 t
.hierarchy_mask
|= 0x1000;
100 t
.polygon_list_body
=
101 t
.polygon_list
+ header_size
;
103 t
.polygon_list_size
=
104 header_size
+ body_size
;
109 struct mali_single_framebuffer
110 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
112 unsigned width
= ctx
->pipe_framebuffer
.width
;
113 unsigned height
= ctx
->pipe_framebuffer
.height
;
115 struct mali_single_framebuffer framebuffer
= {
116 .width
= MALI_POSITIVE(width
),
117 .height
= MALI_POSITIVE(height
),
119 .format
= 0x30000000,
120 .clear_flags
= 0x1000,
121 .unknown_address_0
= ctx
->scratchpad
.bo
->gpu
,
122 .tiler
= panfrost_emit_midg_tiler(ctx
,
123 width
, height
, vertex_count
),
129 struct bifrost_framebuffer
130 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
132 unsigned width
= ctx
->pipe_framebuffer
.width
;
133 unsigned height
= ctx
->pipe_framebuffer
.height
;
135 struct bifrost_framebuffer framebuffer
= {
136 .unk0
= 0x1e5, /* 1e4 if no spill */
137 .width1
= MALI_POSITIVE(width
),
138 .height1
= MALI_POSITIVE(height
),
139 .width2
= MALI_POSITIVE(width
),
140 .height2
= MALI_POSITIVE(height
),
144 .rt_count_1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.nr_cbufs
),
149 .scratchpad
= ctx
->scratchpad
.bo
->gpu
,
150 .tiler
= panfrost_emit_midg_tiler(ctx
,
151 width
, height
, vertex_count
)
157 /* Are we currently rendering to the screen (rather than an FBO)? */
160 panfrost_is_scanout(struct panfrost_context
*ctx
)
162 /* If there is no color buffer, it's an FBO */
163 if (ctx
->pipe_framebuffer
.nr_cbufs
!= 1)
166 /* If we're too early that no framebuffer was sent, it's scanout */
167 if (!ctx
->pipe_framebuffer
.cbufs
[0])
170 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
171 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
172 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
177 struct pipe_context
*pipe
,
179 const union pipe_color_union
*color
,
180 double depth
, unsigned stencil
)
182 struct panfrost_context
*ctx
= pan_context(pipe
);
183 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
185 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
189 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
191 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(ctx
, ~0);
193 return panfrost_upload_transient(ctx
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
197 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
199 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(ctx
, ~0);
201 return panfrost_upload_transient(ctx
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
205 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
207 /* Skip the attach if we can */
209 if (ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
210 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
214 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
215 mali_ptr framebuffer
= screen
->require_sfbd
?
216 panfrost_attach_vt_sfbd(ctx
) :
217 panfrost_attach_vt_mfbd(ctx
);
219 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
220 ctx
->payloads
[i
].postfix
.framebuffer
= framebuffer
;
223 /* Reset per-frame context, called on context initialisation as well as after
224 * flushing a frame */
227 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
229 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
230 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
233 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
236 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
239 /* In practice, every field of these payloads should be configurable
240 * arbitrarily, which means these functions are basically catch-all's for
241 * as-of-yet unwavering unknowns */
244 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
246 /* 0x2 bit clear on 32-bit T6XX */
248 struct midgard_payload_vertex_tiler payload
= {
249 .gl_enables
= 0x4 | 0x2,
252 /* Vertex and compute are closely coupled, so share a payload */
254 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
255 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
259 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
261 struct midgard_payload_vertex_tiler payload
= {
263 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
267 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
271 translate_tex_wrap(enum pipe_tex_wrap w
)
274 case PIPE_TEX_WRAP_REPEAT
:
275 return MALI_WRAP_REPEAT
;
277 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
278 return MALI_WRAP_CLAMP_TO_EDGE
;
280 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
281 return MALI_WRAP_CLAMP_TO_BORDER
;
283 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
284 return MALI_WRAP_MIRRORED_REPEAT
;
287 unreachable("Invalid wrap");
292 panfrost_translate_compare_func(enum pipe_compare_func in
)
295 case PIPE_FUNC_NEVER
:
296 return MALI_FUNC_NEVER
;
299 return MALI_FUNC_LESS
;
301 case PIPE_FUNC_EQUAL
:
302 return MALI_FUNC_EQUAL
;
304 case PIPE_FUNC_LEQUAL
:
305 return MALI_FUNC_LEQUAL
;
307 case PIPE_FUNC_GREATER
:
308 return MALI_FUNC_GREATER
;
310 case PIPE_FUNC_NOTEQUAL
:
311 return MALI_FUNC_NOTEQUAL
;
313 case PIPE_FUNC_GEQUAL
:
314 return MALI_FUNC_GEQUAL
;
316 case PIPE_FUNC_ALWAYS
:
317 return MALI_FUNC_ALWAYS
;
320 unreachable("Invalid func");
325 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
328 case PIPE_FUNC_NEVER
:
329 return MALI_ALT_FUNC_NEVER
;
332 return MALI_ALT_FUNC_LESS
;
334 case PIPE_FUNC_EQUAL
:
335 return MALI_ALT_FUNC_EQUAL
;
337 case PIPE_FUNC_LEQUAL
:
338 return MALI_ALT_FUNC_LEQUAL
;
340 case PIPE_FUNC_GREATER
:
341 return MALI_ALT_FUNC_GREATER
;
343 case PIPE_FUNC_NOTEQUAL
:
344 return MALI_ALT_FUNC_NOTEQUAL
;
346 case PIPE_FUNC_GEQUAL
:
347 return MALI_ALT_FUNC_GEQUAL
;
349 case PIPE_FUNC_ALWAYS
:
350 return MALI_ALT_FUNC_ALWAYS
;
353 unreachable("Invalid alt func");
358 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
361 case PIPE_STENCIL_OP_KEEP
:
362 return MALI_STENCIL_KEEP
;
364 case PIPE_STENCIL_OP_ZERO
:
365 return MALI_STENCIL_ZERO
;
367 case PIPE_STENCIL_OP_REPLACE
:
368 return MALI_STENCIL_REPLACE
;
370 case PIPE_STENCIL_OP_INCR
:
371 return MALI_STENCIL_INCR
;
373 case PIPE_STENCIL_OP_DECR
:
374 return MALI_STENCIL_DECR
;
376 case PIPE_STENCIL_OP_INCR_WRAP
:
377 return MALI_STENCIL_INCR_WRAP
;
379 case PIPE_STENCIL_OP_DECR_WRAP
:
380 return MALI_STENCIL_DECR_WRAP
;
382 case PIPE_STENCIL_OP_INVERT
:
383 return MALI_STENCIL_INVERT
;
386 unreachable("Invalid stencil op");
391 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
393 out
->ref
= 0; /* Gallium gets it from elsewhere */
395 out
->mask
= in
->valuemask
;
396 out
->func
= panfrost_translate_compare_func(in
->func
);
397 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
398 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
399 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
403 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
405 struct mali_shader_meta shader
= {
406 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
408 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
409 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
412 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
413 * required (independent of 32-bit/64-bit descriptors), or why it's not
414 * used on later GPU revisions. Otherwise, all shader jobs fault on
415 * these earlier chips (perhaps this is a chicken bit of some kind).
416 * More investigation is needed. */
419 shader
.unknown2_4
|= 0x10;
422 struct pipe_stencil_state default_stencil
= {
424 .func
= PIPE_FUNC_ALWAYS
,
425 .fail_op
= MALI_STENCIL_KEEP
,
426 .zfail_op
= MALI_STENCIL_KEEP
,
427 .zpass_op
= MALI_STENCIL_KEEP
,
432 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
433 shader
.stencil_mask_front
= default_stencil
.writemask
;
435 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
436 shader
.stencil_mask_back
= default_stencil
.writemask
;
438 if (default_stencil
.enabled
)
439 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
441 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
444 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
445 * graphics command stream. It should be called once per draw, accordding to
446 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
447 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
450 struct panfrost_transfer
451 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
453 struct mali_job_descriptor_header job
= {
454 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
455 .job_descriptor_size
= 1,
458 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
460 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
461 memcpy(transfer
.cpu
, &job
, sizeof(job
));
462 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
467 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
469 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
470 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
472 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
476 panfrost_writes_point_size(struct panfrost_context
*ctx
)
478 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
479 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
481 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
484 /* Stage the attribute descriptors so we can adjust src_offset
485 * to let BOs align nicely */
488 panfrost_stage_attributes(struct panfrost_context
*ctx
)
490 struct panfrost_vertex_state
*so
= ctx
->vertex
;
492 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
493 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
494 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
496 /* Copy as-is for the first pass */
497 memcpy(target
, so
->hw
, sz
);
499 /* Fixup offsets for the second pass. Recall that the hardware
500 * calculates attribute addresses as:
502 * addr = base + (stride * vtx) + src_offset;
504 * However, on Mali, base must be aligned to 64-bytes, so we
507 * base' = base & ~63 = base - (base & 63)
509 * To compensate when using base' (see emit_vertex_data), we have
510 * to adjust src_offset by the masked off piece:
512 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
513 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
514 * = base + (stride * vtx) + src_offset
520 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
;
522 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
523 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
524 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
525 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
527 /* Adjust by the masked off bits of the offset */
528 target
[i
].src_offset
+= (addr
& 63);
530 /* Also, somewhat obscurely per-instance data needs to be
531 * offset in response to a delayed start in an indexed draw */
533 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
534 target
[i
].src_offset
-= buf
->stride
* start
;
540 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
544 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
546 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
548 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
551 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
552 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
554 struct panfrost_transfer transfer
=
555 panfrost_allocate_transient(ctx
, transfer_size
);
557 struct mali_sampler_descriptor
*desc
=
558 (struct mali_sampler_descriptor
*) transfer
.cpu
;
560 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
561 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
563 upload
= transfer
.gpu
;
566 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
571 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
, bool manual_stride
)
573 /* TODO: other linear depth textures */
574 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
576 unsigned usage2_layout
= 0x10;
578 switch (rsrc
->layout
) {
580 usage2_layout
|= 0x8 | 0x4;
583 usage2_layout
|= 0x1;
586 usage2_layout
|= is_depth
? 0x1 : 0x2;
594 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
596 return usage2_layout
;
601 struct panfrost_context
*ctx
,
602 struct panfrost_sampler_view
*view
)
607 struct pipe_sampler_view
*pview
= &view
->base
;
608 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
610 /* Do we interleave an explicit stride with every element? */
612 bool has_manual_stride
= view
->manual_stride
;
614 /* For easy access */
616 assert(pview
->target
!= PIPE_BUFFER
);
617 unsigned first_level
= pview
->u
.tex
.first_level
;
618 unsigned last_level
= pview
->u
.tex
.last_level
;
619 unsigned first_layer
= pview
->u
.tex
.first_layer
;
620 unsigned last_layer
= pview
->u
.tex
.last_layer
;
622 /* Lower-bit is set when sampling from colour AFBC */
623 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
624 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
625 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
627 /* Add the BO to the job so it's retained until the job is done. */
628 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
629 panfrost_job_add_bo(job
, rsrc
->bo
);
631 /* Add the usage flags in, since they can change across the CSO
632 * lifetime due to layout switches */
634 view
->hw
.format
.usage2
= panfrost_layout_for_texture(rsrc
, has_manual_stride
);
636 /* Inject the addresses in, interleaving mip levels, cube faces, and
637 * strides in that order */
641 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
642 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
644 view
->hw
.payload
[idx
++] =
645 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
647 if (has_manual_stride
) {
648 view
->hw
.payload
[idx
++] =
649 rsrc
->slices
[l
].stride
;
654 return panfrost_upload_transient(ctx
, &view
->hw
,
655 sizeof(struct mali_texture_descriptor
));
659 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
661 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
662 mali_ptr trampoline
= 0;
664 if (ctx
->sampler_view_count
[t
]) {
665 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
667 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
669 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
671 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
674 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
678 struct sysval_uniform
{
687 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
688 struct sysval_uniform
*uniform
)
690 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
692 uniform
->f
[0] = vp
->scale
[0];
693 uniform
->f
[1] = vp
->scale
[1];
694 uniform
->f
[2] = vp
->scale
[2];
697 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
698 struct sysval_uniform
*uniform
)
700 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
702 uniform
->f
[0] = vp
->translate
[0];
703 uniform
->f
[1] = vp
->translate
[1];
704 uniform
->f
[2] = vp
->translate
[2];
707 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
708 enum pipe_shader_type st
,
709 unsigned int sysvalid
,
710 struct sysval_uniform
*uniform
)
712 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
713 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
714 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
715 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
718 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
721 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
722 tex
->u
.tex
.first_level
);
725 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
726 tex
->u
.tex
.first_level
);
729 uniform
->i
[dim
] = tex
->texture
->array_size
;
732 static void panfrost_upload_ssbo_sysval(
733 struct panfrost_context
*ctx
,
734 enum pipe_shader_type st
,
736 struct sysval_uniform
*uniform
)
738 assert(ctx
->ssbo_mask
[st
] & (1 << ssbo_id
));
739 struct pipe_shader_buffer sb
= ctx
->ssbo
[st
][ssbo_id
];
741 /* Compute address */
742 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
743 struct panfrost_bo
*bo
= pan_resource(sb
.buffer
)->bo
;
745 panfrost_job_add_bo(batch
, bo
);
747 /* Upload address and size as sysval */
748 uniform
->du
[0] = bo
->gpu
+ sb
.buffer_offset
;
749 uniform
->u
[2] = sb
.buffer_size
;
752 static void panfrost_upload_num_work_groups_sysval(struct panfrost_context
*ctx
,
753 struct sysval_uniform
*uniform
)
755 uniform
->u
[0] = ctx
->compute_grid
->grid
[0];
756 uniform
->u
[1] = ctx
->compute_grid
->grid
[1];
757 uniform
->u
[2] = ctx
->compute_grid
->grid
[2];
760 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
761 struct panfrost_shader_state
*ss
,
762 enum pipe_shader_type st
)
764 struct sysval_uniform
*uniforms
= (void *)buf
;
766 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
767 int sysval
= ss
->sysval
[i
];
769 switch (PAN_SYSVAL_TYPE(sysval
)) {
770 case PAN_SYSVAL_VIEWPORT_SCALE
:
771 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
773 case PAN_SYSVAL_VIEWPORT_OFFSET
:
774 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
776 case PAN_SYSVAL_TEXTURE_SIZE
:
777 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
780 case PAN_SYSVAL_SSBO
:
781 panfrost_upload_ssbo_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
784 case PAN_SYSVAL_NUM_WORK_GROUPS
:
785 panfrost_upload_num_work_groups_sysval(ctx
, &uniforms
[i
]);
795 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
797 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
798 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
801 return rsrc
->bo
->cpu
;
802 else if (cb
->user_buffer
)
803 return cb
->user_buffer
;
805 unreachable("No constant buffer");
809 panfrost_map_constant_buffer_gpu(
810 struct panfrost_context
*ctx
,
811 struct panfrost_constant_buffer
*buf
,
814 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
815 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
818 return rsrc
->bo
->gpu
;
819 else if (cb
->user_buffer
)
820 return panfrost_upload_transient(ctx
, cb
->user_buffer
, cb
->buffer_size
);
822 unreachable("No constant buffer");
825 /* Compute number of UBOs active (more specifically, compute the highest UBO
826 * number addressable -- if there are gaps, include them in the count anyway).
827 * We always include UBO #0 in the count, since we *need* uniforms enabled for
831 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
833 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
834 return 32 - __builtin_clz(mask
);
837 /* Fixes up a shader state with current state, returning a GPU address to the
841 panfrost_patch_shader_state(
842 struct panfrost_context
*ctx
,
843 struct panfrost_shader_state
*ss
,
844 enum pipe_shader_type stage
,
847 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
848 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
850 ss
->tripipe
->midgard1
.flags
= 0x220;
852 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
853 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
855 /* We can't reuse over frames; that's not safe. The descriptor must be
856 * transient uploaded */
859 return panfrost_upload_transient(ctx
,
861 sizeof(struct mali_shader_meta
));
864 /* If we don't need an upload, don't bother */
870 panfrost_patch_shader_state_compute(
871 struct panfrost_context
*ctx
,
872 enum pipe_shader_type stage
,
875 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
878 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
882 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
884 ctx
->payloads
[stage
].postfix
._shader_upper
=
885 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
888 /* Go through dirty flags and actualise them in the cmdstream. */
891 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
893 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
894 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
896 panfrost_attach_vt_framebuffer(ctx
);
898 if (with_vertex_data
) {
899 panfrost_emit_vertex_data(job
);
901 /* Varyings emitted for -all- geometry */
902 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
903 panfrost_emit_varying_descriptor(ctx
, total_count
);
906 bool msaa
= ctx
->rasterizer
->base
.multisample
;
908 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
909 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
911 /* TODO: Sample size */
912 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
913 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
916 panfrost_job_set_requirements(ctx
, job
);
918 if (ctx
->occlusion_query
) {
919 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
920 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
923 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
924 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
926 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
927 /* Check if we need to link the gl_PointSize varying */
928 if (!panfrost_writes_point_size(ctx
)) {
929 /* If the size is constant, write it out. Otherwise,
930 * don't touch primitive_size (since we would clobber
931 * the pointer there) */
933 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
937 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
938 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
939 ctx
->dirty
|= PAN_DIRTY_FS
;
941 if (ctx
->dirty
& PAN_DIRTY_FS
) {
942 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
943 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
945 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
947 panfrost_job_add_bo(job
, variant
->bo
);
949 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
952 COPY(attribute_count
);
957 COPY(midgard1
.uniform_count
);
958 COPY(midgard1
.uniform_buffer_count
);
959 COPY(midgard1
.work_count
);
960 COPY(midgard1
.flags
);
961 COPY(midgard1
.unknown2
);
965 /* Get blending setup */
966 struct panfrost_blend_final blend
=
967 panfrost_get_blend_for_context(ctx
, 0);
969 /* If there is a blend shader, work registers are shared */
972 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
974 /* Set late due to depending on render state */
975 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
977 /* Depending on whether it's legal to in the given shader, we
978 * try to enable early-z testing (or forward-pixel kill?) */
980 if (!variant
->can_discard
)
981 flags
|= MALI_EARLY_Z
;
983 /* Any time texturing is used, derivatives are implicitly
984 * calculated, so we need to enable helper invocations */
986 if (variant
->helper_invocations
)
987 flags
|= MALI_HELPER_INVOCATIONS
;
989 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
991 /* Assign the stencil refs late */
993 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
994 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
995 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
997 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
998 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
1000 /* CAN_DISCARD should be set if the fragment shader possibly
1001 * contains a 'discard' instruction. It is likely this is
1002 * related to optimizations related to forward-pixel kill, as
1003 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1004 * thing?" by Peter Harris
1007 if (variant
->can_discard
) {
1008 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1009 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1012 /* Check if we're using the default blend descriptor (fast path) */
1016 (blend
.equation
.equation
->rgb_mode
== 0x122) &&
1017 (blend
.equation
.equation
->alpha_mode
== 0x122) &&
1018 (blend
.equation
.equation
->color_mask
== 0xf);
1020 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1021 * *also* copied to the blend_meta appended (by convention),
1022 * but this is the field actually read by the hardware. (Or
1023 * maybe both are read...?) */
1025 if (blend
.is_shader
) {
1026 ctx
->fragment_shader_core
.blend
.shader
=
1027 blend
.shader
.bo
->gpu
| blend
.shader
.first_tag
;
1029 ctx
->fragment_shader_core
.blend
.shader
= 0;
1032 if (screen
->require_sfbd
) {
1033 /* When only a single render target platform is used, the blend
1034 * information is inside the shader meta itself. We
1035 * additionally need to signal CAN_DISCARD for nontrivial blend
1036 * modes (so we're able to read back the destination buffer) */
1038 if (!blend
.is_shader
) {
1039 ctx
->fragment_shader_core
.blend
.equation
=
1040 *blend
.equation
.equation
;
1041 ctx
->fragment_shader_core
.blend
.constant
=
1042 blend
.equation
.constant
;
1046 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1050 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1051 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1052 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1054 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1056 if (!screen
->require_sfbd
) {
1057 /* Additional blend descriptor tacked on for jobs using MFBD */
1059 unsigned blend_count
= 0x200;
1061 if (blend
.is_shader
) {
1062 /* For a blend shader, the bottom nibble corresponds to
1063 * the number of work registers used, which signals the
1064 * -existence- of a blend shader */
1066 assert(blend
.shader
.work_count
>= 2);
1067 blend_count
|= MIN2(blend
.shader
.work_count
, 3);
1069 /* Otherwise, the bottom bit simply specifies if
1070 * blending (anything other than REPLACE) is enabled */
1077 struct midgard_blend_rt rts
[4];
1079 for (unsigned i
= 0; i
< ctx
->pipe_framebuffer
.nr_cbufs
; ++i
) {
1081 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1082 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1083 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1085 rts
[i
].flags
= blend_count
;
1088 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1090 if (!ctx
->blend
->base
.dither
)
1091 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1093 /* TODO: sRGB in blend shaders is currently
1094 * unimplemented. Contact me (Alyssa) if you're
1095 * interested in working on this. We have
1096 * native Midgard ops for helping here, but
1097 * they're not well-understood yet. */
1099 assert(!(is_srgb
&& blend
.is_shader
));
1101 if (blend
.is_shader
) {
1102 rts
[i
].blend
.shader
= blend
.shader
.bo
->gpu
| blend
.shader
.first_tag
;
1104 rts
[i
].blend
.equation
= *blend
.equation
.equation
;
1105 rts
[i
].blend
.constant
= blend
.equation
.constant
;
1109 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1113 /* We stage to transient, so always dirty.. */
1115 panfrost_stage_attributes(ctx
);
1117 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1118 panfrost_upload_sampler_descriptors(ctx
);
1120 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1121 panfrost_upload_texture_descriptors(ctx
);
1123 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1125 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1126 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1131 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1133 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1135 /* Uniforms are implicitly UBO #0 */
1136 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1138 /* Allocate room for the sysval and the uniforms */
1139 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1140 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1141 size_t size
= sys_size
+ uniform_size
;
1142 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1144 /* Upload sysvals requested by the shader */
1145 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1147 /* Upload uniforms */
1149 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1150 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1154 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1156 struct mali_vertex_tiler_postfix
*postfix
=
1157 &ctx
->payloads
[i
].postfix
;
1159 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1162 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1163 assert(ubo_count
>= 1);
1165 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1166 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1168 /* Upload uniforms as a UBO */
1169 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1170 ubos
[0].ptr
= transfer
.gpu
>> 2;
1172 /* The rest are honest-to-goodness UBOs */
1174 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1175 size_t sz
= buf
->cb
[ubo
].buffer_size
;
1177 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1178 bool empty
= sz
== 0;
1180 if (!enabled
|| empty
) {
1181 /* Stub out disabled UBOs to catch accesses */
1184 ubos
[ubo
].ptr
= 0xDEAD0000;
1188 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1190 unsigned bytes_per_field
= 16;
1191 unsigned aligned
= ALIGN_POT(sz
, bytes_per_field
);
1192 unsigned fields
= aligned
/ bytes_per_field
;
1194 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1195 ubos
[ubo
].ptr
= gpu
>> 2;
1198 mali_ptr ubufs
= panfrost_upload_transient(ctx
, ubos
, sz
);
1199 postfix
->uniforms
= transfer
.gpu
;
1200 postfix
->uniform_buffers
= ubufs
;
1202 buf
->dirty_mask
= 0;
1205 /* TODO: Upload the viewport somewhere more appropriate */
1207 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1208 * (somewhat) asymmetric ints. */
1209 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1211 struct mali_viewport view
= {
1212 /* By default, do no viewport clipping, i.e. clip to (-inf,
1213 * inf) in each direction. Clipping to the viewport in theory
1214 * should work, but in practice causes issues when we're not
1215 * explicitly trying to scissor */
1217 .clip_minx
= -INFINITY
,
1218 .clip_miny
= -INFINITY
,
1219 .clip_maxx
= INFINITY
,
1220 .clip_maxy
= INFINITY
,
1226 /* Always scissor to the viewport by default. */
1227 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1228 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1230 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1231 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1233 /* Apply the scissor test */
1235 unsigned minx
, miny
, maxx
, maxy
;
1237 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1238 minx
= MAX2(ss
->minx
, vp_minx
);
1239 miny
= MAX2(ss
->miny
, vp_miny
);
1240 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1241 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1249 /* Hardware needs the min/max to be strictly ordered, so flip if we
1250 * need to. The viewport transformation in the vertex shader will
1251 * handle the negatives if we don't */
1265 /* Clamp everything positive, just in case */
1267 maxx
= MAX2(0, maxx
);
1268 maxy
= MAX2(0, maxy
);
1269 minx
= MAX2(0, minx
);
1270 miny
= MAX2(0, miny
);
1272 /* Clamp to the framebuffer size as a last check */
1274 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1275 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1277 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1278 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1280 /* Update the job, unless we're doing wallpapering (whose lack of
1281 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1282 * just... be faster :) */
1284 if (!ctx
->wallpaper_batch
)
1285 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1289 view
.viewport0
[0] = minx
;
1290 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1292 view
.viewport0
[1] = miny
;
1293 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1295 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1296 panfrost_upload_transient(ctx
,
1298 sizeof(struct mali_viewport
));
1303 /* Corresponds to exactly one draw, but does not submit anything */
1306 panfrost_queue_draw(struct panfrost_context
*ctx
)
1308 /* Handle dirty flags now */
1309 panfrost_emit_for_draw(ctx
, true);
1311 /* If rasterizer discard is enable, only submit the vertex */
1313 bool rasterizer_discard
= ctx
->rasterizer
1314 && ctx
->rasterizer
->base
.rasterizer_discard
;
1316 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1317 struct panfrost_transfer tiler
;
1319 if (!rasterizer_discard
)
1320 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1322 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1324 if (rasterizer_discard
)
1325 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1326 else if (ctx
->wallpaper_batch
)
1327 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1329 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1332 /* The entire frame is in memory -- send it off to the kernel! */
1335 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1336 struct pipe_fence_handle
**fence
,
1337 struct panfrost_job
*job
)
1339 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1340 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1344 panfrost_job_submit(ctx
, job
);
1346 /* If visual, we can stall a frame */
1348 if (!flush_immediate
)
1349 panfrost_drm_force_flush_fragment(ctx
, fence
);
1351 screen
->last_fragment_flushed
= false;
1352 screen
->last_job
= job
;
1354 /* If readback, flush now (hurts the pipelined performance) */
1355 if (flush_immediate
)
1356 panfrost_drm_force_flush_fragment(ctx
, fence
);
1361 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1363 struct panfrost_context
*ctx
= pan_context(pipe
);
1365 /* Nothing to reload? TODO: MRT wallpapers */
1366 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1369 /* Check if the buffer has any content on it worth preserving */
1371 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1372 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1373 unsigned level
= surf
->u
.tex
.level
;
1375 if (!rsrc
->slices
[level
].initialized
)
1378 /* Save the batch */
1379 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1381 ctx
->wallpaper_batch
= batch
;
1383 /* Clamp the rendering area to the damage extent. The
1384 * KHR_partial_update() spec states that trying to render outside of
1385 * the damage region is "undefined behavior", so we should be safe.
1387 panfrost_job_intersection_scissor(batch
, rsrc
->damage
.extent
.minx
,
1388 rsrc
->damage
.extent
.miny
,
1389 rsrc
->damage
.extent
.maxx
,
1390 rsrc
->damage
.extent
.maxy
);
1392 /* FIXME: Looks like aligning on a tile is not enough, but
1393 * aligning on twice the tile size seems to works. We don't
1394 * know exactly what happens here but this deserves extra
1395 * investigation to figure it out.
1397 batch
->minx
= batch
->minx
& ~((MALI_TILE_LENGTH
* 2) - 1);
1398 batch
->miny
= batch
->miny
& ~((MALI_TILE_LENGTH
* 2) - 1);
1399 batch
->maxx
= MIN2(ALIGN_POT(batch
->maxx
, MALI_TILE_LENGTH
* 2),
1401 batch
->maxy
= MIN2(ALIGN_POT(batch
->maxy
, MALI_TILE_LENGTH
* 2),
1402 rsrc
->base
.height0
);
1404 struct pipe_scissor_state damage
;
1405 struct pipe_box rects
[4];
1407 /* Clamp the damage box to the rendering area. */
1408 damage
.minx
= MAX2(batch
->minx
, rsrc
->damage
.biggest_rect
.x
);
1409 damage
.miny
= MAX2(batch
->miny
, rsrc
->damage
.biggest_rect
.y
);
1410 damage
.maxx
= MIN2(batch
->maxx
,
1411 rsrc
->damage
.biggest_rect
.x
+
1412 rsrc
->damage
.biggest_rect
.width
);
1413 damage
.maxy
= MIN2(batch
->maxy
,
1414 rsrc
->damage
.biggest_rect
.y
+
1415 rsrc
->damage
.biggest_rect
.height
);
1417 /* One damage rectangle means we can end up with at most 4 reload
1419 * 1: left region, only exists if damage.x > 0
1420 * 2: right region, only exists if damage.x + damage.width < fb->width
1421 * 3: top region, only exists if damage.y > 0. The intersection with
1422 * the left and right regions are dropped
1423 * 4: bottom region, only exists if damage.y + damage.height < fb->height.
1424 * The intersection with the left and right regions are dropped
1426 * ____________________________
1433 * |_______|___________|______|
1435 u_box_2d(batch
->minx
, batch
->miny
, damage
.minx
- batch
->minx
,
1436 batch
->maxy
- batch
->miny
, &rects
[0]);
1437 u_box_2d(damage
.maxx
, batch
->miny
, batch
->maxx
- damage
.maxx
,
1438 batch
->maxy
- batch
->miny
, &rects
[1]);
1439 u_box_2d(damage
.minx
, batch
->miny
, damage
.maxx
- damage
.minx
,
1440 damage
.miny
- batch
->miny
, &rects
[2]);
1441 u_box_2d(damage
.minx
, damage
.maxy
, damage
.maxx
- damage
.minx
,
1442 batch
->maxy
- damage
.maxy
, &rects
[3]);
1444 for (unsigned i
= 0; i
< 4; i
++) {
1445 /* Width and height are always >= 0 even if width is declared as a
1446 * signed integer: u_box_2d() helper takes unsigned args and
1447 * panfrost_set_damage_region() is taking care of clamping
1450 if (!rects
[i
].width
|| !rects
[i
].height
)
1453 /* Blit the wallpaper in */
1454 panfrost_blit_wallpaper(ctx
, &rects
[i
]);
1456 ctx
->wallpaper_batch
= NULL
;
1461 struct pipe_context
*pipe
,
1462 struct pipe_fence_handle
**fence
,
1465 struct panfrost_context
*ctx
= pan_context(pipe
);
1466 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1468 /* Nothing to do! */
1469 if (!job
->last_job
.gpu
&& !job
->clear
) return;
1471 if (!job
->clear
&& job
->last_tiler
.gpu
)
1472 panfrost_draw_wallpaper(&ctx
->base
);
1474 /* Whether to stall the pipeline for immediately correct results. Since
1475 * pipelined rendering is quite broken right now (to be fixed by the
1476 * panfrost_job refactor, just take the perf hit for correctness) */
1477 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1479 /* Submit the frame itself */
1480 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1482 /* Prepare for the next frame */
1483 panfrost_invalidate_frame(ctx
);
1486 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1489 g2m_draw_mode(enum pipe_prim_type mode
)
1492 DEFINE_CASE(POINTS
);
1494 DEFINE_CASE(LINE_LOOP
);
1495 DEFINE_CASE(LINE_STRIP
);
1496 DEFINE_CASE(TRIANGLES
);
1497 DEFINE_CASE(TRIANGLE_STRIP
);
1498 DEFINE_CASE(TRIANGLE_FAN
);
1500 DEFINE_CASE(QUAD_STRIP
);
1501 DEFINE_CASE(POLYGON
);
1504 unreachable("Invalid draw mode");
1511 panfrost_translate_index_size(unsigned size
)
1515 return MALI_DRAW_INDEXED_UINT8
;
1518 return MALI_DRAW_INDEXED_UINT16
;
1521 return MALI_DRAW_INDEXED_UINT32
;
1524 unreachable("Invalid index size");
1528 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1529 * good for the duration of the draw (transient), could last longer */
1532 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1534 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1536 off_t offset
= info
->start
* info
->index_size
;
1537 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1539 if (!info
->has_user_indices
) {
1540 /* Only resources can be directly mapped */
1541 panfrost_job_add_bo(batch
, rsrc
->bo
);
1542 return rsrc
->bo
->gpu
+ offset
;
1544 /* Otherwise, we need to upload to transient memory */
1545 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1546 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1551 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1553 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1555 /* Check if we're scissoring at all */
1557 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1560 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1565 struct pipe_context
*pipe
,
1566 const struct pipe_draw_info
*info
)
1568 struct panfrost_context
*ctx
= pan_context(pipe
);
1570 /* First of all, check the scissor to see if anything is drawn at all.
1571 * If it's not, we drop the draw (mostly a conformance issue;
1572 * well-behaved apps shouldn't hit this) */
1574 if (panfrost_scissor_culls_everything(ctx
))
1577 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= info
->start
;
1578 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= info
->start
;
1580 int mode
= info
->mode
;
1582 /* Fallback unsupported restart index */
1583 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1585 if (info
->primitive_restart
&& info
->index_size
1586 && info
->restart_index
!= primitive_index
) {
1587 util_draw_vbo_without_prim_restart(pipe
, info
);
1591 /* Fallback for unsupported modes */
1593 if (!(ctx
->draw_modes
& (1 << mode
))) {
1594 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1595 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1597 if (info
->count
< 4) {
1598 /* Degenerate case? */
1602 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1603 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1608 /* Now that we have a guaranteed terminating path, find the job.
1609 * Assignment commented out to prevent unused warning */
1611 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1613 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1615 /* Take into account a negative bias */
1616 ctx
->vertex_count
= info
->count
+ abs(info
->index_bias
);
1617 ctx
->instance_count
= info
->instance_count
;
1619 /* For non-indexed draws, they're the same */
1620 unsigned vertex_count
= ctx
->vertex_count
;
1622 unsigned draw_flags
= 0;
1624 /* The draw flags interpret how primitive size is interpreted */
1626 if (panfrost_writes_point_size(ctx
))
1627 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1629 if (info
->primitive_restart
)
1630 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1632 /* For higher amounts of vertices (greater than what fits in a 16-bit
1633 * short), the other value is needed, otherwise there will be bizarre
1634 * rendering artefacts. It's not clear what these values mean yet. This
1635 * change is also needed for instancing and sometimes points (perhaps
1636 * related to dynamically setting gl_PointSize) */
1638 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1639 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1640 bool instanced
= ctx
->instance_count
> 1;
1642 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1644 /* This doesn't make much sense */
1645 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1646 draw_flags
|= 0x800;
1649 if (info
->index_size
) {
1650 /* Calculate the min/max index used so we can figure out how
1651 * many times to invoke the vertex shader */
1653 /* Fetch / calculate index bounds */
1654 unsigned min_index
= 0, max_index
= 0;
1656 if (info
->max_index
== ~0u) {
1657 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1659 min_index
= info
->min_index
;
1660 max_index
= info
->max_index
;
1663 /* Use the corresponding values */
1664 vertex_count
= max_index
- min_index
+ 1;
1665 ctx
->payloads
[PIPE_SHADER_VERTEX
].offset_start
= min_index
+ info
->index_bias
;
1666 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].offset_start
= min_index
+ info
->index_bias
;
1668 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= -min_index
;
1669 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1671 //assert(!info->restart_index); /* TODO: Research */
1673 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1674 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1676 /* Index count == vertex count, if no indexing is applied, as
1677 * if it is internally indexed in the expected order */
1679 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.offset_bias_correction
= 0;
1680 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1682 /* Reverse index state */
1683 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1686 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1687 * vertex_count, 1) */
1689 panfrost_pack_work_groups_fused(
1690 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1691 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1692 1, vertex_count
, info
->instance_count
,
1695 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1697 /* Encode the padded vertex count */
1699 if (info
->instance_count
> 1) {
1700 /* Triangles have non-even vertex counts so they change how
1701 * padding works internally */
1704 mode
== PIPE_PRIM_TRIANGLES
||
1705 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1706 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1708 struct pan_shift_odd so
=
1709 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1711 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1712 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1714 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1715 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1717 ctx
->padded_count
= pan_expand_shift_odd(so
);
1719 ctx
->padded_count
= ctx
->vertex_count
;
1721 /* Reset instancing state */
1722 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1723 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1724 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1725 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1728 /* Fire off the draw itself */
1729 panfrost_queue_draw(ctx
);
1735 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1741 panfrost_create_rasterizer_state(
1742 struct pipe_context
*pctx
,
1743 const struct pipe_rasterizer_state
*cso
)
1745 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1749 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1750 so
->tiler_gl_enables
= 0x7;
1753 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1755 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1756 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1758 if (cso
->cull_face
& PIPE_FACE_BACK
)
1759 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1765 panfrost_bind_rasterizer_state(
1766 struct pipe_context
*pctx
,
1769 struct panfrost_context
*ctx
= pan_context(pctx
);
1771 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1775 ctx
->rasterizer
= hwcso
;
1776 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1778 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1779 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1781 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1782 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1784 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1786 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1787 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1789 /* Point sprites are emulated */
1791 struct panfrost_shader_state
*variant
=
1792 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1794 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1795 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1799 panfrost_create_vertex_elements_state(
1800 struct pipe_context
*pctx
,
1801 unsigned num_elements
,
1802 const struct pipe_vertex_element
*elements
)
1804 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1806 so
->num_elements
= num_elements
;
1807 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1809 for (int i
= 0; i
< num_elements
; ++i
) {
1810 so
->hw
[i
].index
= i
;
1812 enum pipe_format fmt
= elements
[i
].src_format
;
1813 const struct util_format_description
*desc
= util_format_description(fmt
);
1814 so
->hw
[i
].unknown1
= 0x2;
1815 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1817 so
->hw
[i
].format
= panfrost_find_format(desc
);
1819 /* The field itself should probably be shifted over */
1820 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1827 panfrost_bind_vertex_elements_state(
1828 struct pipe_context
*pctx
,
1831 struct panfrost_context
*ctx
= pan_context(pctx
);
1833 ctx
->vertex
= hwcso
;
1834 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1838 panfrost_create_shader_state(
1839 struct pipe_context
*pctx
,
1840 const struct pipe_shader_state
*cso
)
1842 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1845 /* Token deep copy to prevent memory corruption */
1847 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1848 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1854 panfrost_delete_shader_state(
1855 struct pipe_context
*pctx
,
1858 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1860 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1861 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1864 for (unsigned i
= 0; i
< cso
->variant_count
; ++i
) {
1865 struct panfrost_shader_state
*shader_state
= &cso
->variants
[i
];
1866 panfrost_bo_unreference(pctx
->screen
, shader_state
->bo
);
1867 shader_state
->bo
= NULL
;
1874 panfrost_create_sampler_state(
1875 struct pipe_context
*pctx
,
1876 const struct pipe_sampler_state
*cso
)
1878 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1881 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1883 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1884 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1885 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1887 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1888 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1889 unsigned mip_filter
= mip_linear
?
1890 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1891 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1893 struct mali_sampler_descriptor sampler_descriptor
= {
1894 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1895 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1896 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1897 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1898 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1900 cso
->border_color
.f
[0],
1901 cso
->border_color
.f
[1],
1902 cso
->border_color
.f
[2],
1903 cso
->border_color
.f
[3]
1905 .min_lod
= FIXED_16(cso
->min_lod
),
1906 .max_lod
= FIXED_16(cso
->max_lod
),
1907 .seamless_cube_map
= cso
->seamless_cube_map
,
1910 /* If necessary, we disable mipmapping in the sampler descriptor by
1911 * clamping the LOD as tight as possible (from 0 to epsilon,
1912 * essentially -- remember these are fixed point numbers, so
1915 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1916 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1918 /* Enforce that there is something in the middle by adding epsilon*/
1920 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1921 sampler_descriptor
.max_lod
++;
1924 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1926 so
->hw
= sampler_descriptor
;
1932 panfrost_bind_sampler_states(
1933 struct pipe_context
*pctx
,
1934 enum pipe_shader_type shader
,
1935 unsigned start_slot
, unsigned num_sampler
,
1938 assert(start_slot
== 0);
1940 struct panfrost_context
*ctx
= pan_context(pctx
);
1942 /* XXX: Should upload, not just copy? */
1943 ctx
->sampler_count
[shader
] = num_sampler
;
1944 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1946 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1950 panfrost_variant_matches(
1951 struct panfrost_context
*ctx
,
1952 struct panfrost_shader_state
*variant
,
1953 enum pipe_shader_type type
)
1955 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1956 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1958 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1960 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
1961 /* Make sure enable state is at least the same */
1962 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1966 /* Check that the contents of the test are the same */
1967 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1968 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1970 if (!(same_func
&& same_ref
)) {
1975 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
1976 variant
->point_sprite_mask
)) {
1977 /* Ensure the same varyings are turned to point sprites */
1978 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
1981 /* Ensure the orientation is correct */
1983 rasterizer
->sprite_coord_mode
==
1984 PIPE_SPRITE_COORD_UPPER_LEFT
;
1986 if (variant
->point_sprite_upper_left
!= upper_left
)
1990 /* Otherwise, we're good to go */
1995 panfrost_bind_shader_state(
1996 struct pipe_context
*pctx
,
1998 enum pipe_shader_type type
)
2000 struct panfrost_context
*ctx
= pan_context(pctx
);
2002 ctx
->shader
[type
] = hwcso
;
2004 if (type
== PIPE_SHADER_FRAGMENT
)
2005 ctx
->dirty
|= PAN_DIRTY_FS
;
2007 ctx
->dirty
|= PAN_DIRTY_VS
;
2011 /* Match the appropriate variant */
2013 signed variant
= -1;
2014 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2016 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2017 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2023 if (variant
== -1) {
2024 /* No variant matched, so create a new one */
2025 variant
= variants
->variant_count
++;
2026 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2028 struct panfrost_shader_state
*v
=
2029 &variants
->variants
[variant
];
2031 if (type
== PIPE_SHADER_FRAGMENT
) {
2032 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2034 if (ctx
->rasterizer
) {
2035 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2036 v
->point_sprite_upper_left
=
2037 ctx
->rasterizer
->base
.sprite_coord_mode
==
2038 PIPE_SPRITE_COORD_UPPER_LEFT
;
2042 variants
->variants
[variant
].tripipe
= malloc(sizeof(struct mali_shader_meta
));
2046 /* Select this variant */
2047 variants
->active_variant
= variant
;
2049 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2050 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2052 /* We finally have a variant, so compile it */
2054 if (!shader_state
->compiled
) {
2055 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2056 variants
->base
.type
,
2057 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2058 variants
->base
.ir
.nir
:
2059 variants
->base
.tokens
,
2060 tgsi_processor_to_shader_stage(type
), shader_state
);
2062 shader_state
->compiled
= true;
2067 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2069 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2073 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2075 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2079 panfrost_set_vertex_buffers(
2080 struct pipe_context
*pctx
,
2081 unsigned start_slot
,
2082 unsigned num_buffers
,
2083 const struct pipe_vertex_buffer
*buffers
)
2085 struct panfrost_context
*ctx
= pan_context(pctx
);
2087 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2091 panfrost_set_constant_buffer(
2092 struct pipe_context
*pctx
,
2093 enum pipe_shader_type shader
, uint index
,
2094 const struct pipe_constant_buffer
*buf
)
2096 struct panfrost_context
*ctx
= pan_context(pctx
);
2097 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2099 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2101 unsigned mask
= (1 << index
);
2103 if (unlikely(!buf
)) {
2104 pbuf
->enabled_mask
&= ~mask
;
2105 pbuf
->dirty_mask
&= ~mask
;
2109 pbuf
->enabled_mask
|= mask
;
2110 pbuf
->dirty_mask
|= mask
;
2114 panfrost_set_stencil_ref(
2115 struct pipe_context
*pctx
,
2116 const struct pipe_stencil_ref
*ref
)
2118 struct panfrost_context
*ctx
= pan_context(pctx
);
2119 ctx
->stencil_ref
= *ref
;
2121 /* Shader core dirty */
2122 ctx
->dirty
|= PAN_DIRTY_FS
;
2125 static enum mali_texture_type
2126 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2130 case PIPE_TEXTURE_1D
:
2131 case PIPE_TEXTURE_1D_ARRAY
:
2134 case PIPE_TEXTURE_2D
:
2135 case PIPE_TEXTURE_2D_ARRAY
:
2136 case PIPE_TEXTURE_RECT
:
2139 case PIPE_TEXTURE_3D
:
2142 case PIPE_TEXTURE_CUBE
:
2143 case PIPE_TEXTURE_CUBE_ARRAY
:
2144 return MALI_TEX_CUBE
;
2147 unreachable("Unknown target");
2151 static struct pipe_sampler_view
*
2152 panfrost_create_sampler_view(
2153 struct pipe_context
*pctx
,
2154 struct pipe_resource
*texture
,
2155 const struct pipe_sampler_view
*template)
2157 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2158 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2160 pipe_reference(NULL
, &texture
->reference
);
2162 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2165 so
->base
= *template;
2166 so
->base
.texture
= texture
;
2167 so
->base
.reference
.count
= 1;
2168 so
->base
.context
= pctx
;
2170 /* sampler_views correspond to texture descriptors, minus the texture
2171 * (data) itself. So, we serialise the descriptor here and cache it for
2174 /* TODO: Detect from format better */
2175 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2177 unsigned char user_swizzle
[4] = {
2178 template->swizzle_r
,
2179 template->swizzle_g
,
2180 template->swizzle_b
,
2184 enum mali_format format
= panfrost_find_format(desc
);
2186 /* Check if we need to set a custom stride by computing the "expected"
2187 * stride and comparing it to what the BO actually wants. Only applies
2188 * to linear textures, since tiled/compressed textures have strict
2189 * alignment requirements for their strides as it is */
2191 unsigned first_level
= template->u
.tex
.first_level
;
2192 unsigned last_level
= template->u
.tex
.last_level
;
2194 if (prsrc
->layout
== PAN_LINEAR
) {
2195 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2196 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2197 unsigned width
= u_minify(texture
->width0
, l
);
2198 unsigned comp_stride
= width
* bytes_per_pixel
;
2200 if (comp_stride
!= actual_stride
) {
2201 so
->manual_stride
= true;
2207 /* In the hardware, array_size refers specifically to array textures,
2208 * whereas in Gallium, it also covers cubemaps */
2210 unsigned array_size
= texture
->array_size
;
2212 if (template->target
== PIPE_TEXTURE_CUBE
) {
2213 /* TODO: Cubemap arrays */
2214 assert(array_size
== 6);
2218 struct mali_texture_descriptor texture_descriptor
= {
2219 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2220 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2221 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2222 .array_size
= MALI_POSITIVE(array_size
),
2226 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2229 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2230 .type
= panfrost_translate_texture_type(template->target
),
2233 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2236 texture_descriptor
.nr_mipmap_levels
= last_level
- first_level
;
2238 so
->hw
= texture_descriptor
;
2240 return (struct pipe_sampler_view
*) so
;
2244 panfrost_set_sampler_views(
2245 struct pipe_context
*pctx
,
2246 enum pipe_shader_type shader
,
2247 unsigned start_slot
, unsigned num_views
,
2248 struct pipe_sampler_view
**views
)
2250 struct panfrost_context
*ctx
= pan_context(pctx
);
2252 assert(start_slot
== 0);
2254 unsigned new_nr
= 0;
2255 for (unsigned i
= 0; i
< num_views
; ++i
) {
2260 ctx
->sampler_view_count
[shader
] = new_nr
;
2261 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2263 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2267 panfrost_sampler_view_destroy(
2268 struct pipe_context
*pctx
,
2269 struct pipe_sampler_view
*view
)
2271 pipe_resource_reference(&view
->texture
, NULL
);
2276 panfrost_set_shader_buffers(
2277 struct pipe_context
*pctx
,
2278 enum pipe_shader_type shader
,
2279 unsigned start
, unsigned count
,
2280 const struct pipe_shader_buffer
*buffers
,
2281 unsigned writable_bitmask
)
2283 struct panfrost_context
*ctx
= pan_context(pctx
);
2285 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2286 buffers
, start
, count
);
2289 /* Hints that a framebuffer should use AFBC where possible */
2293 struct panfrost_screen
*screen
,
2294 const struct pipe_framebuffer_state
*fb
)
2296 /* AFBC implemenation incomplete; hide it */
2297 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2299 /* Hint AFBC to the resources bound to each color buffer */
2301 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2302 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2303 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2304 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2307 /* Also hint it to the depth buffer */
2310 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2311 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2316 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2317 const struct pipe_framebuffer_state
*fb
)
2319 struct panfrost_context
*ctx
= pan_context(pctx
);
2321 /* Flush when switching framebuffers, but not if the framebuffer
2322 * state is being restored by u_blitter
2325 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
2326 bool is_scanout
= panfrost_is_scanout(ctx
);
2327 bool has_draws
= job
->last_job
.gpu
;
2329 /* Bail out early when the current and new states are the same. */
2330 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2333 /* The wallpaper logic sets a new FB state before doing the blit and
2334 * restore the old one when it's done. Those FB states are reported to
2335 * be different because the surface they are pointing to are different,
2336 * but those surfaces actually point to the same cbufs/zbufs. In that
2337 * case we definitely don't want new FB descs to be emitted/attached
2338 * since the job is expected to be flushed just after the blit is done,
2339 * so let's just copy the new state and return here.
2341 if (ctx
->wallpaper_batch
) {
2342 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2346 if (!is_scanout
|| has_draws
)
2347 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2349 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2350 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2352 /* Invalidate the FBO job cache since we've just been assigned a new
2357 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2359 /* Given that we're rendering, we'd love to have compression */
2360 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2362 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2363 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2364 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2368 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2369 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2371 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2375 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2378 struct panfrost_context
*ctx
= pan_context(pipe
);
2379 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2380 ctx
->depth_stencil
= depth_stencil
;
2385 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2386 * emulated in the fragment shader */
2388 if (depth_stencil
->alpha
.enabled
) {
2389 /* We need to trigger a new shader (maybe) */
2390 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2394 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2396 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2397 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2399 /* If back-stencil is not enabled, use the front values */
2400 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2401 unsigned back_index
= back_enab
? 1 : 0;
2403 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2404 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2406 /* Depth state (TODO: Refactor) */
2407 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2409 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2411 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2412 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2414 /* Bounds test not implemented */
2415 assert(!depth_stencil
->depth
.bounds_test
);
2417 ctx
->dirty
|= PAN_DIRTY_FS
;
2421 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2427 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2428 unsigned sample_mask
)
2433 panfrost_set_clip_state(struct pipe_context
*pipe
,
2434 const struct pipe_clip_state
*clip
)
2436 //struct panfrost_context *panfrost = pan_context(pipe);
2440 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2441 unsigned start_slot
,
2442 unsigned num_viewports
,
2443 const struct pipe_viewport_state
*viewports
)
2445 struct panfrost_context
*ctx
= pan_context(pipe
);
2447 assert(start_slot
== 0);
2448 assert(num_viewports
== 1);
2450 ctx
->pipe_viewport
= *viewports
;
2454 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2455 unsigned start_slot
,
2456 unsigned num_scissors
,
2457 const struct pipe_scissor_state
*scissors
)
2459 struct panfrost_context
*ctx
= pan_context(pipe
);
2461 assert(start_slot
== 0);
2462 assert(num_scissors
== 1);
2464 ctx
->scissor
= *scissors
;
2468 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2469 const struct pipe_poly_stipple
*stipple
)
2471 //struct panfrost_context *panfrost = pan_context(pipe);
2475 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2478 //struct panfrost_context *panfrost = pan_context(pipe);
2482 panfrost_destroy(struct pipe_context
*pipe
)
2484 struct panfrost_context
*panfrost
= pan_context(pipe
);
2485 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2487 if (panfrost
->blitter
)
2488 util_blitter_destroy(panfrost
->blitter
);
2490 if (panfrost
->blitter_wallpaper
)
2491 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2493 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2494 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2495 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2500 static struct pipe_query
*
2501 panfrost_create_query(struct pipe_context
*pipe
,
2505 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2510 return (struct pipe_query
*) q
;
2514 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2520 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2522 struct panfrost_context
*ctx
= pan_context(pipe
);
2523 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2525 switch (query
->type
) {
2526 case PIPE_QUERY_OCCLUSION_COUNTER
:
2527 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2528 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2529 /* Allocate a word for the query results to be stored */
2530 query
->transfer
= panfrost_allocate_transient(ctx
, sizeof(unsigned));
2532 ctx
->occlusion_query
= query
;
2538 DBG("Skipping query %d\n", query
->type
);
2546 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2548 struct panfrost_context
*ctx
= pan_context(pipe
);
2549 ctx
->occlusion_query
= NULL
;
2554 panfrost_get_query_result(struct pipe_context
*pipe
,
2555 struct pipe_query
*q
,
2557 union pipe_query_result
*vresult
)
2560 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2562 /* We need to flush out the jobs to actually run the counter, TODO
2563 * check wait, TODO wallpaper after if needed */
2565 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2567 switch (query
->type
) {
2568 case PIPE_QUERY_OCCLUSION_COUNTER
:
2569 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2570 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2571 /* Read back the query results */
2572 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2573 unsigned passed
= *result
;
2575 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2576 vresult
->u64
= passed
;
2578 vresult
->b
= !!passed
;
2584 DBG("Skipped query get %d\n", query
->type
);
2591 static struct pipe_stream_output_target
*
2592 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2593 struct pipe_resource
*prsc
,
2594 unsigned buffer_offset
,
2595 unsigned buffer_size
)
2597 struct pipe_stream_output_target
*target
;
2599 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2604 pipe_reference_init(&target
->reference
, 1);
2605 pipe_resource_reference(&target
->buffer
, prsc
);
2607 target
->context
= pctx
;
2608 target
->buffer_offset
= buffer_offset
;
2609 target
->buffer_size
= buffer_size
;
2615 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2616 struct pipe_stream_output_target
*target
)
2618 pipe_resource_reference(&target
->buffer
, NULL
);
2619 ralloc_free(target
);
2623 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2624 unsigned num_targets
,
2625 struct pipe_stream_output_target
**targets
,
2626 const unsigned *offsets
)
2628 struct panfrost_context
*ctx
= pan_context(pctx
);
2629 struct panfrost_streamout
*so
= &ctx
->streamout
;
2631 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
2633 for (unsigned i
= 0; i
< num_targets
; i
++) {
2634 if (offsets
[i
] != -1)
2635 so
->offsets
[i
] = offsets
[i
];
2637 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
2640 for (unsigned i
= 0; i
< so
->num_targets
; i
++)
2641 pipe_so_target_reference(&so
->targets
[i
], NULL
);
2643 so
->num_targets
= num_targets
;
2647 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2649 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2650 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2652 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64*4, false, 0, 0, 0);
2653 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 4096, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2654 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2657 /* New context creation, which also does hardware initialisation since I don't
2658 * know the better way to structure this :smirk: */
2660 struct pipe_context
*
2661 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2663 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2664 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2665 memset(ctx
, 0, sizeof(*ctx
));
2666 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2668 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2670 gallium
->screen
= screen
;
2672 gallium
->destroy
= panfrost_destroy
;
2674 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2676 gallium
->flush
= panfrost_flush
;
2677 gallium
->clear
= panfrost_clear
;
2678 gallium
->draw_vbo
= panfrost_draw_vbo
;
2680 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2681 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2682 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2684 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2686 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2687 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2688 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2690 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2691 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2692 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2694 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2695 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2696 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2698 gallium
->create_fs_state
= panfrost_create_shader_state
;
2699 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2700 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2702 gallium
->create_vs_state
= panfrost_create_shader_state
;
2703 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2704 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2706 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2707 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2708 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2710 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2711 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2712 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2714 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2716 gallium
->set_clip_state
= panfrost_set_clip_state
;
2717 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2718 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2719 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2720 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2722 gallium
->create_query
= panfrost_create_query
;
2723 gallium
->destroy_query
= panfrost_destroy_query
;
2724 gallium
->begin_query
= panfrost_begin_query
;
2725 gallium
->end_query
= panfrost_end_query
;
2726 gallium
->get_query_result
= panfrost_get_query_result
;
2728 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2729 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2730 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2732 panfrost_resource_context_init(gallium
);
2733 panfrost_blend_context_init(gallium
);
2734 panfrost_compute_context_init(gallium
);
2736 panfrost_drm_init_context(ctx
);
2738 panfrost_setup_hardware(ctx
);
2741 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2742 gallium
->const_uploader
= gallium
->stream_uploader
;
2743 assert(gallium
->stream_uploader
);
2745 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2746 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2748 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2750 ctx
->blitter
= util_blitter_create(gallium
);
2751 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2753 assert(ctx
->blitter
);
2754 assert(ctx
->blitter_wallpaper
);
2756 /* Prepare for render! */
2758 panfrost_job_init(ctx
);
2759 panfrost_emit_vertex_payload(ctx
);
2760 panfrost_emit_tiler_payload(ctx
);
2761 panfrost_invalidate_frame(ctx
);
2762 panfrost_default_shader_backend(ctx
);