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822b5a0dfefffb22f3e19485c7c96f0b81c3391d
[mesa.git] / src / gallium / drivers / panfrost / pan_context.c
1 /*
2 * © Copyright 2018 Alyssa Rosenzweig
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 */
24
25 #include <sys/poll.h>
26 #include <errno.h>
27
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
31
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
40
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
44 #include "pan_wallpaper.h"
45
46 #ifdef DUMP_PERFORMANCE_COUNTERS
47 static int performance_counter_number = 0;
48 #endif
49
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
51 //#define DRY_RUN
52
53 #define SET_BIT(lval, bit, cond) \
54 if (cond) \
55 lval |= (bit); \
56 else \
57 lval &= ~(bit);
58
59 /* TODO: Sample size, etc */
60
61 /* True for t6XX, false for t8xx. TODO: Run-time settable for automatic
62 * hardware configuration. */
63
64 static bool is_t6xx = false;
65
66 /* If set, we'll require the use of single render-target framebuffer
67 * descriptors (SFBD), for older hardware -- specifically, <T760 hardware, If
68 * false, we'll use the MFBD no matter what. New hardware -does- retain support
69 * for SFBD, and in theory we could flip between them on a per-RT basis, but
70 * there's no real advantage to doing so */
71
72 static bool require_sfbd = false;
73
74 static void
75 panfrost_set_framebuffer_msaa(struct panfrost_context *ctx, bool enabled)
76 {
77 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_HAS_MSAA, enabled);
78 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_NO_MSAA, !enabled);
79
80 if (require_sfbd) {
81 SET_BIT(ctx->fragment_sfbd.format, MALI_FRAMEBUFFER_MSAA_A | MALI_FRAMEBUFFER_MSAA_B, enabled);
82 } else {
83 SET_BIT(ctx->fragment_rts[0].format, MALI_MFBD_FORMAT_MSAA, enabled);
84
85 SET_BIT(ctx->fragment_mfbd.unk1, (1 << 4) | (1 << 1), enabled);
86
87 /* XXX */
88 ctx->fragment_mfbd.rt_count_2 = enabled ? 4 : 1;
89 }
90 }
91
92 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
93 * indepdent between color buffers and depth/stencil). To enable, we allocate
94 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
95 * edit the fragment job here. This routine should be called ONCE per
96 * AFBC-compressed buffer, rather than on every frame. */
97
98 static void
99 panfrost_enable_afbc(struct panfrost_context *ctx, struct panfrost_resource *rsrc, bool ds)
100 {
101 if (require_sfbd) {
102 printf("AFBC not supported yet on SFBD\n");
103 assert(0);
104 }
105
106 struct pipe_context *gallium = (struct pipe_context *) ctx;
107 struct panfrost_screen *screen = pan_screen(gallium->screen);
108 /* AFBC metadata is 16 bytes per tile */
109 int tile_w = (rsrc->base.width0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
110 int tile_h = (rsrc->base.height0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
111 int bytes_per_pixel = util_format_get_blocksize(rsrc->base.format);
112 int stride = bytes_per_pixel * rsrc->base.width0; /* TODO: Alignment? */
113
114 stride *= 2; /* TODO: Should this be carried over? */
115 int main_size = stride * rsrc->base.height0;
116 rsrc->bo->afbc_metadata_size = tile_w * tile_h * 16;
117
118 /* Allocate the AFBC slab itself, large enough to hold the above */
119 screen->driver->allocate_slab(screen, &rsrc->bo->afbc_slab,
120 (rsrc->bo->afbc_metadata_size + main_size + 4095) / 4096,
121 true, 0, 0, 0);
122
123 rsrc->bo->has_afbc = true;
124
125 /* Compressed textured reads use a tagged pointer to the metadata */
126
127 rsrc->bo->gpu[0] = rsrc->bo->afbc_slab.gpu | (ds ? 0 : 1);
128 rsrc->bo->cpu[0] = rsrc->bo->afbc_slab.cpu;
129 }
130
131 static void
132 panfrost_enable_checksum(struct panfrost_context *ctx, struct panfrost_resource *rsrc)
133 {
134 struct pipe_context *gallium = (struct pipe_context *) ctx;
135 struct panfrost_screen *screen = pan_screen(gallium->screen);
136 int tile_w = (rsrc->base.width0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
137 int tile_h = (rsrc->base.height0 + (MALI_TILE_LENGTH - 1)) >> MALI_TILE_SHIFT;
138
139 /* 8 byte checksum per tile */
140 rsrc->bo->checksum_stride = tile_w * 8;
141 int pages = (((rsrc->bo->checksum_stride * tile_h) + 4095) / 4096);
142 screen->driver->allocate_slab(screen, &rsrc->bo->checksum_slab, pages, false, 0, 0, 0);
143
144 rsrc->bo->has_checksum = true;
145 }
146
147 /* ..by contrast, this routine runs for every FRAGMENT job, but does no
148 * allocation. AFBC is enabled on a per-surface basis */
149
150 static void
151 panfrost_set_fragment_afbc(struct panfrost_context *ctx)
152 {
153 for (int cb = 0; cb < ctx->pipe_framebuffer.nr_cbufs; ++cb) {
154 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[cb]->texture;
155
156 /* Non-AFBC is the default */
157 if (!rsrc->bo->has_afbc)
158 continue;
159
160 if (require_sfbd) {
161 fprintf(stderr, "Color AFBC not supported on SFBD\n");
162 assert(0);
163 }
164
165 /* Enable AFBC for the render target */
166 ctx->fragment_rts[0].afbc.metadata = rsrc->bo->afbc_slab.gpu;
167 ctx->fragment_rts[0].afbc.stride = 0;
168 ctx->fragment_rts[0].afbc.unk = 0x30009;
169
170 ctx->fragment_rts[0].format |= MALI_MFBD_FORMAT_AFBC;
171
172 /* Point rendering to our special framebuffer */
173 ctx->fragment_rts[0].framebuffer = rsrc->bo->afbc_slab.gpu + rsrc->bo->afbc_metadata_size;
174
175 /* WAT? Stride is diff from the scanout case */
176 ctx->fragment_rts[0].framebuffer_stride = ctx->pipe_framebuffer.width * 2 * 4;
177 }
178
179 /* Enable depth/stencil AFBC for the framebuffer (not the render target) */
180 if (ctx->pipe_framebuffer.zsbuf) {
181 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.zsbuf->texture;
182
183 if (rsrc->bo->has_afbc) {
184 if (require_sfbd) {
185 fprintf(stderr, "Depth AFBC not supported on SFBD\n");
186 assert(0);
187 }
188
189 ctx->fragment_mfbd.unk3 |= MALI_MFBD_EXTRA;
190
191 ctx->fragment_extra.ds_afbc.depth_stencil_afbc_metadata = rsrc->bo->afbc_slab.gpu;
192 ctx->fragment_extra.ds_afbc.depth_stencil_afbc_stride = 0;
193
194 ctx->fragment_extra.ds_afbc.depth_stencil = rsrc->bo->afbc_slab.gpu + rsrc->bo->afbc_metadata_size;
195
196 ctx->fragment_extra.ds_afbc.zero1 = 0x10009;
197 ctx->fragment_extra.ds_afbc.padding = 0x1000;
198
199 ctx->fragment_extra.unk = 0x435; /* General 0x400 in all unks. 0x5 for depth/stencil. 0x10 for AFBC encoded depth stencil. Unclear where the 0x20 is from */
200
201 ctx->fragment_mfbd.unk3 |= 0x400;
202 }
203 }
204
205 /* For the special case of a depth-only FBO, we need to attach a dummy render target */
206
207 if (ctx->pipe_framebuffer.nr_cbufs == 0) {
208 if (require_sfbd) {
209 fprintf(stderr, "Depth-only FBO not supported on SFBD\n");
210 assert(0);
211 }
212
213 ctx->fragment_rts[0].format = 0x80008000;
214 ctx->fragment_rts[0].framebuffer = 0;
215 ctx->fragment_rts[0].framebuffer_stride = 0;
216 }
217 }
218
219 /* Framebuffer descriptor */
220
221 static void
222 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer *fb, int w, int h)
223 {
224 fb->width = MALI_POSITIVE(w);
225 fb->height = MALI_POSITIVE(h);
226
227 /* No idea why this is needed, but it's how resolution_check is
228 * calculated. It's not clear to us yet why the hardware wants this.
229 * The formula itself was discovered mostly by manual bruteforce and
230 * aggressive algebraic simplification. */
231
232 fb->resolution_check = ((w + h) / 3) << 4;
233 }
234
235 static struct mali_single_framebuffer
236 panfrost_emit_sfbd(struct panfrost_context *ctx)
237 {
238 struct mali_single_framebuffer framebuffer = {
239 .unknown2 = 0x1f,
240 .format = 0x30000000,
241 .clear_flags = 0x1000,
242 .unknown_address_0 = ctx->scratchpad.gpu,
243 .unknown_address_1 = ctx->misc_0.gpu,
244 .unknown_address_2 = ctx->misc_0.gpu + 40960,
245 .tiler_flags = 0xf0,
246 .tiler_heap_free = ctx->tiler_heap.gpu,
247 .tiler_heap_end = ctx->tiler_heap.gpu + ctx->tiler_heap.size,
248 };
249
250 panfrost_set_framebuffer_resolution(&framebuffer, ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height);
251
252 return framebuffer;
253 }
254
255 static struct bifrost_framebuffer
256 panfrost_emit_mfbd(struct panfrost_context *ctx)
257 {
258 struct bifrost_framebuffer framebuffer = {
259 .tiler_meta = 0xf00000c600,
260
261 .width1 = MALI_POSITIVE(ctx->pipe_framebuffer.width),
262 .height1 = MALI_POSITIVE(ctx->pipe_framebuffer.height),
263 .width2 = MALI_POSITIVE(ctx->pipe_framebuffer.width),
264 .height2 = MALI_POSITIVE(ctx->pipe_framebuffer.height),
265
266 .unk1 = 0x1080,
267
268 /* TODO: MRT */
269 .rt_count_1 = MALI_POSITIVE(1),
270 .rt_count_2 = 4,
271
272 .unknown2 = 0x1f,
273
274 /* Presumably corresponds to unknown_address_X of SFBD */
275 .scratchpad = ctx->scratchpad.gpu,
276 .tiler_scratch_start = ctx->misc_0.gpu,
277 .tiler_scratch_middle = ctx->misc_0.gpu + /*ctx->misc_0.size*/40960, /* Size depends on the size of the framebuffer and the number of vertices */
278
279 .tiler_heap_start = ctx->tiler_heap.gpu,
280 .tiler_heap_end = ctx->tiler_heap.gpu + ctx->tiler_heap.size,
281 };
282
283 return framebuffer;
284 }
285
286 /* Are we currently rendering to the screen (rather than an FBO)? */
287
288 static bool
289 panfrost_is_scanout(struct panfrost_context *ctx)
290 {
291 /* If there is no color buffer, it's an FBO */
292 if (!ctx->pipe_framebuffer.nr_cbufs)
293 return false;
294
295 /* If we're too early that no framebuffer was sent, it's scanout */
296 if (!ctx->pipe_framebuffer.cbufs[0])
297 return true;
298
299 return ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_DISPLAY_TARGET ||
300 ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_SCANOUT ||
301 ctx->pipe_framebuffer.cbufs[0]->texture->bind & PIPE_BIND_SHARED;
302 }
303
304 /* The above function is for generalised fbd emission, used in both fragment as
305 * well as vertex/tiler payloads. This payload is specific to fragment
306 * payloads. */
307
308 static void
309 panfrost_new_frag_framebuffer(struct panfrost_context *ctx)
310 {
311 mali_ptr framebuffer;
312 int stride;
313
314 if (ctx->pipe_framebuffer.nr_cbufs > 0) {
315 framebuffer = ((struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[0]->texture)->bo->gpu[0];
316 stride = util_format_get_stride(ctx->pipe_framebuffer.cbufs[0]->format, ctx->pipe_framebuffer.width);
317 } else {
318 /* Depth-only framebuffer -> dummy RT */
319 framebuffer = 0;
320 stride = 0;
321 }
322
323 /* The default is upside down from OpenGL's perspective. */
324 if (panfrost_is_scanout(ctx)) {
325 framebuffer += stride * (ctx->pipe_framebuffer.height - 1);
326 stride = -stride;
327 }
328
329 if (require_sfbd) {
330 struct mali_single_framebuffer fb = panfrost_emit_sfbd(ctx);
331
332 fb.framebuffer = framebuffer;
333 fb.stride = stride;
334
335 fb.format = 0xb84e0281; /* RGB32, no MSAA */
336 memcpy(&ctx->fragment_sfbd, &fb, sizeof(fb));
337 } else {
338 struct bifrost_framebuffer fb = panfrost_emit_mfbd(ctx);
339
340 /* XXX: MRT case */
341 fb.rt_count_2 = 1;
342 fb.unk3 = 0x100;
343
344 struct bifrost_render_target rt = {
345 .unk1 = 0x4000000,
346 .format = 0x860a8899, /* RGBA32, no MSAA */
347 .framebuffer = framebuffer,
348 .framebuffer_stride = (stride / 16) & 0xfffffff,
349 };
350
351 memcpy(&ctx->fragment_rts[0], &rt, sizeof(rt));
352
353 memset(&ctx->fragment_extra, 0, sizeof(ctx->fragment_extra));
354 memcpy(&ctx->fragment_mfbd, &fb, sizeof(fb));
355 }
356 }
357
358 /* Maps float 0.0-1.0 to int 0x00-0xFF */
359 static uint8_t
360 normalised_float_to_u8(float f)
361 {
362 return (uint8_t) (int) (f * 255.0f);
363 }
364
365 static void
366 panfrost_clear_sfbd(struct panfrost_context *ctx,
367 bool clear_color,
368 bool clear_depth,
369 bool clear_stencil,
370 uint32_t packed_color,
371 double depth, unsigned stencil
372 )
373 {
374 struct mali_single_framebuffer *sfbd = &ctx->fragment_sfbd;
375
376 if (clear_color) {
377 sfbd->clear_color_1 = packed_color;
378 sfbd->clear_color_2 = packed_color;
379 sfbd->clear_color_3 = packed_color;
380 sfbd->clear_color_4 = packed_color;
381 }
382
383 if (clear_depth) {
384 sfbd->clear_depth_1 = depth;
385 sfbd->clear_depth_2 = depth;
386 sfbd->clear_depth_3 = depth;
387 sfbd->clear_depth_4 = depth;
388 }
389
390 if (clear_stencil) {
391 sfbd->clear_stencil = stencil;
392 }
393
394 /* Setup buffers */
395
396 if (clear_depth) {
397 sfbd->depth_buffer = ctx->depth_stencil_buffer.gpu;
398 sfbd->depth_buffer_enable = MALI_DEPTH_STENCIL_ENABLE;
399 }
400
401 if (clear_stencil) {
402 sfbd->stencil_buffer = ctx->depth_stencil_buffer.gpu;
403 sfbd->stencil_buffer_enable = MALI_DEPTH_STENCIL_ENABLE;
404 }
405
406 /* Set flags based on what has been cleared, for the SFBD case */
407 /* XXX: What do these flags mean? */
408 int clear_flags = 0x101100;
409
410 if (clear_color && clear_depth && clear_stencil) {
411 /* On a tiler like this, it's fastest to clear all three buffers at once */
412
413 clear_flags |= MALI_CLEAR_FAST;
414 } else {
415 clear_flags |= MALI_CLEAR_SLOW;
416
417 if (clear_stencil)
418 clear_flags |= MALI_CLEAR_SLOW_STENCIL;
419 }
420
421 sfbd->clear_flags = clear_flags;
422 }
423
424 static void
425 panfrost_clear_mfbd(struct panfrost_context *ctx,
426 bool clear_color,
427 bool clear_depth,
428 bool clear_stencil,
429 uint32_t packed_color,
430 double depth, unsigned stencil
431 )
432 {
433 struct bifrost_render_target *buffer_color = &ctx->fragment_rts[0];
434 struct bifrost_framebuffer *buffer_ds = &ctx->fragment_mfbd;
435
436 if (clear_color) {
437 buffer_color->clear_color_1 = packed_color;
438 buffer_color->clear_color_2 = packed_color;
439 buffer_color->clear_color_3 = packed_color;
440 buffer_color->clear_color_4 = packed_color;
441 }
442
443 if (clear_depth) {
444 buffer_ds->clear_depth = depth;
445 }
446
447 if (clear_stencil) {
448 buffer_ds->clear_stencil = stencil;
449 }
450
451 if (clear_depth || clear_stencil) {
452 /* Setup combined 24/8 depth/stencil */
453 ctx->fragment_mfbd.unk3 |= MALI_MFBD_EXTRA;
454 //ctx->fragment_extra.unk = /*0x405*/0x404;
455 ctx->fragment_extra.unk = 0x405;
456 ctx->fragment_extra.ds_linear.depth = ctx->depth_stencil_buffer.gpu;
457 ctx->fragment_extra.ds_linear.depth_stride = ctx->pipe_framebuffer.width * 4;
458 }
459 }
460
461 static void
462 panfrost_clear(
463 struct pipe_context *pipe,
464 unsigned buffers,
465 const union pipe_color_union *color,
466 double depth, unsigned stencil)
467 {
468 struct panfrost_context *ctx = pan_context(pipe);
469
470 if (!color) {
471 printf("Warning: clear color null?\n");
472 return;
473 }
474
475 /* Save settings for FBO switch */
476 ctx->last_clear.buffers = buffers;
477 ctx->last_clear.color = color;
478 ctx->last_clear.depth = depth;
479 ctx->last_clear.depth = depth;
480
481 bool clear_color = buffers & PIPE_CLEAR_COLOR;
482 bool clear_depth = buffers & PIPE_CLEAR_DEPTH;
483 bool clear_stencil = buffers & PIPE_CLEAR_STENCIL;
484
485 /* Remember that we've done something */
486 ctx->frame_cleared = true;
487
488 /* Alpha clear only meaningful without alpha channel */
489 bool has_alpha = ctx->pipe_framebuffer.nr_cbufs && util_format_has_alpha(ctx->pipe_framebuffer.cbufs[0]->format);
490 float clear_alpha = has_alpha ? color->f[3] : 1.0f;
491
492 uint32_t packed_color =
493 (normalised_float_to_u8(clear_alpha) << 24) |
494 (normalised_float_to_u8(color->f[2]) << 16) |
495 (normalised_float_to_u8(color->f[1]) << 8) |
496 (normalised_float_to_u8(color->f[0]) << 0);
497
498 if (require_sfbd) {
499 panfrost_clear_sfbd(ctx, clear_color, clear_depth, clear_stencil, packed_color, depth, stencil);
500 } else {
501 panfrost_clear_mfbd(ctx, clear_color, clear_depth, clear_stencil, packed_color, depth, stencil);
502 }
503 }
504
505 static mali_ptr
506 panfrost_attach_vt_mfbd(struct panfrost_context *ctx)
507 {
508 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
509 struct bifrost_render_target rts_list[] = {
510 {
511 .chunknown = {
512 .unk = 0x30005,
513 },
514 .framebuffer = ctx->misc_0.gpu,
515 .zero2 = 0x3,
516 },
517 };
518
519 /* Allocate memory for the three components */
520 int size = 1024 + sizeof(ctx->vt_framebuffer_mfbd) + sizeof(rts_list);
521 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
522
523 /* Opaque 1024-block */
524 rts_list[0].chunknown.pointer = transfer.gpu;
525
526 memcpy(transfer.cpu + 1024, &ctx->vt_framebuffer_mfbd, sizeof(ctx->vt_framebuffer_mfbd));
527 memcpy(transfer.cpu + 1024 + sizeof(ctx->vt_framebuffer_mfbd), rts_list, sizeof(rts_list));
528
529 return (transfer.gpu + 1024) | MALI_MFBD;
530 }
531
532 static mali_ptr
533 panfrost_attach_vt_sfbd(struct panfrost_context *ctx)
534 {
535 return panfrost_upload_transient(ctx, &ctx->vt_framebuffer_sfbd, sizeof(ctx->vt_framebuffer_sfbd)) | MALI_SFBD;
536 }
537
538 static void
539 panfrost_attach_vt_framebuffer(struct panfrost_context *ctx)
540 {
541 mali_ptr framebuffer = require_sfbd ?
542 panfrost_attach_vt_sfbd(ctx) :
543 panfrost_attach_vt_mfbd(ctx);
544
545 ctx->payload_vertex.postfix.framebuffer = framebuffer;
546 ctx->payload_tiler.postfix.framebuffer = framebuffer;
547 }
548
549 static void
550 panfrost_viewport(struct panfrost_context *ctx,
551 float depth_clip_near,
552 float depth_clip_far,
553 int viewport_x0, int viewport_y0,
554 int viewport_x1, int viewport_y1)
555 {
556 /* Clip bounds are encoded as floats. The viewport itself is encoded as
557 * (somewhat) asymmetric ints. */
558
559 struct mali_viewport ret = {
560 /* By default, do no viewport clipping, i.e. clip to (-inf,
561 * inf) in each direction. Clipping to the viewport in theory
562 * should work, but in practice causes issues when we're not
563 * explicitly trying to scissor */
564
565 .clip_minx = -inff,
566 .clip_miny = -inff,
567 .clip_maxx = inff,
568 .clip_maxy = inff,
569
570 /* We always perform depth clipping (TODO: Can this be disabled?) */
571
572 .clip_minz = depth_clip_near,
573 .clip_maxz = depth_clip_far,
574
575 .viewport0 = { viewport_x0, viewport_y0 },
576 .viewport1 = { MALI_POSITIVE(viewport_x1), MALI_POSITIVE(viewport_y1) },
577 };
578
579 memcpy(ctx->viewport, &ret, sizeof(ret));
580 }
581
582 /* Reset per-frame context, called on context initialisation as well as after
583 * flushing a frame */
584
585 static void
586 panfrost_invalidate_frame(struct panfrost_context *ctx)
587 {
588 unsigned transient_count = ctx->transient_pools[ctx->cmdstream_i].entry_index*ctx->transient_pools[0].entry_size + ctx->transient_pools[ctx->cmdstream_i].entry_offset;
589 printf("Uploaded transient %d bytes\n", transient_count);
590
591 /* Rotate cmdstream */
592 if ((++ctx->cmdstream_i) == (sizeof(ctx->transient_pools) / sizeof(ctx->transient_pools[0])))
593 ctx->cmdstream_i = 0;
594
595 if (require_sfbd)
596 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx);
597 else
598 ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx);
599
600 panfrost_new_frag_framebuffer(ctx);
601
602 /* Reset varyings allocated */
603 ctx->varying_height = 0;
604
605 /* The transient cmdstream is dirty every frame; the only bits worth preserving
606 * (textures, shaders, etc) are in other buffers anyways */
607
608 ctx->transient_pools[ctx->cmdstream_i].entry_index = 0;
609 ctx->transient_pools[ctx->cmdstream_i].entry_offset = 0;
610
611 /* Regenerate payloads */
612 panfrost_attach_vt_framebuffer(ctx);
613
614 if (ctx->rasterizer)
615 ctx->dirty |= PAN_DIRTY_RASTERIZER;
616
617 /* XXX */
618 ctx->dirty |= PAN_DIRTY_SAMPLERS | PAN_DIRTY_TEXTURES;
619 }
620
621 /* In practice, every field of these payloads should be configurable
622 * arbitrarily, which means these functions are basically catch-all's for
623 * as-of-yet unwavering unknowns */
624
625 static void
626 panfrost_emit_vertex_payload(struct panfrost_context *ctx)
627 {
628 struct midgard_payload_vertex_tiler payload = {
629 .prefix = {
630 .workgroups_z_shift = 32,
631 .workgroups_x_shift_2 = 0x2,
632 .workgroups_x_shift_3 = 0x5,
633 },
634 .gl_enables = 0x4 | (is_t6xx ? 0 : 0x2),
635 };
636
637 memcpy(&ctx->payload_vertex, &payload, sizeof(payload));
638 }
639
640 static void
641 panfrost_emit_tiler_payload(struct panfrost_context *ctx)
642 {
643 struct midgard_payload_vertex_tiler payload = {
644 .prefix = {
645 .workgroups_z_shift = 32,
646 .workgroups_x_shift_2 = 0x2,
647 .workgroups_x_shift_3 = 0x6,
648
649 .zero1 = 0xffff, /* Why is this only seen on test-quad-textured? */
650 },
651 };
652
653 /* Reserve the viewport */
654 struct panfrost_transfer t = panfrost_allocate_chunk(ctx, sizeof(struct mali_viewport), HEAP_DESCRIPTOR);
655 ctx->viewport = (struct mali_viewport *) t.cpu;
656 payload.postfix.viewport = t.gpu;
657
658 memcpy(&ctx->payload_tiler, &payload, sizeof(payload));
659 }
660
661 static unsigned
662 translate_tex_wrap(enum pipe_tex_wrap w)
663 {
664 switch (w) {
665 case PIPE_TEX_WRAP_REPEAT:
666 return MALI_WRAP_REPEAT;
667
668 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
669 return MALI_WRAP_CLAMP_TO_EDGE;
670
671 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
672 return MALI_WRAP_CLAMP_TO_BORDER;
673
674 case PIPE_TEX_WRAP_MIRROR_REPEAT:
675 return MALI_WRAP_MIRRORED_REPEAT;
676
677 default:
678 assert(0);
679 return 0;
680 }
681 }
682
683 static unsigned
684 translate_tex_filter(enum pipe_tex_filter f)
685 {
686 switch (f) {
687 case PIPE_TEX_FILTER_NEAREST:
688 return MALI_NEAREST;
689
690 case PIPE_TEX_FILTER_LINEAR:
691 return MALI_LINEAR;
692
693 default:
694 assert(0);
695 return 0;
696 }
697 }
698
699 static unsigned
700 translate_mip_filter(enum pipe_tex_mipfilter f)
701 {
702 return (f == PIPE_TEX_MIPFILTER_LINEAR) ? MALI_MIP_LINEAR : 0;
703 }
704
705 static unsigned
706 panfrost_translate_compare_func(enum pipe_compare_func in)
707 {
708 switch (in) {
709 case PIPE_FUNC_NEVER:
710 return MALI_FUNC_NEVER;
711
712 case PIPE_FUNC_LESS:
713 return MALI_FUNC_LESS;
714
715 case PIPE_FUNC_EQUAL:
716 return MALI_FUNC_EQUAL;
717
718 case PIPE_FUNC_LEQUAL:
719 return MALI_FUNC_LEQUAL;
720
721 case PIPE_FUNC_GREATER:
722 return MALI_FUNC_GREATER;
723
724 case PIPE_FUNC_NOTEQUAL:
725 return MALI_FUNC_NOTEQUAL;
726
727 case PIPE_FUNC_GEQUAL:
728 return MALI_FUNC_GEQUAL;
729
730 case PIPE_FUNC_ALWAYS:
731 return MALI_FUNC_ALWAYS;
732 }
733
734 assert (0);
735 return 0; /* Unreachable */
736 }
737
738 static unsigned
739 panfrost_translate_alt_compare_func(enum pipe_compare_func in)
740 {
741 switch (in) {
742 case PIPE_FUNC_NEVER:
743 return MALI_ALT_FUNC_NEVER;
744
745 case PIPE_FUNC_LESS:
746 return MALI_ALT_FUNC_LESS;
747
748 case PIPE_FUNC_EQUAL:
749 return MALI_ALT_FUNC_EQUAL;
750
751 case PIPE_FUNC_LEQUAL:
752 return MALI_ALT_FUNC_LEQUAL;
753
754 case PIPE_FUNC_GREATER:
755 return MALI_ALT_FUNC_GREATER;
756
757 case PIPE_FUNC_NOTEQUAL:
758 return MALI_ALT_FUNC_NOTEQUAL;
759
760 case PIPE_FUNC_GEQUAL:
761 return MALI_ALT_FUNC_GEQUAL;
762
763 case PIPE_FUNC_ALWAYS:
764 return MALI_ALT_FUNC_ALWAYS;
765 }
766
767 assert (0);
768 return 0; /* Unreachable */
769 }
770
771 static unsigned
772 panfrost_translate_stencil_op(enum pipe_stencil_op in)
773 {
774 switch (in) {
775 case PIPE_STENCIL_OP_KEEP:
776 return MALI_STENCIL_KEEP;
777
778 case PIPE_STENCIL_OP_ZERO:
779 return MALI_STENCIL_ZERO;
780
781 case PIPE_STENCIL_OP_REPLACE:
782 return MALI_STENCIL_REPLACE;
783
784 case PIPE_STENCIL_OP_INCR:
785 return MALI_STENCIL_INCR;
786
787 case PIPE_STENCIL_OP_DECR:
788 return MALI_STENCIL_DECR;
789
790 case PIPE_STENCIL_OP_INCR_WRAP:
791 return MALI_STENCIL_INCR_WRAP;
792
793 case PIPE_STENCIL_OP_DECR_WRAP:
794 return MALI_STENCIL_DECR_WRAP;
795
796 case PIPE_STENCIL_OP_INVERT:
797 return MALI_STENCIL_INVERT;
798 }
799
800 assert (0);
801 return 0; /* Unreachable */
802 }
803
804 static void
805 panfrost_make_stencil_state(const struct pipe_stencil_state *in, struct mali_stencil_test *out)
806 {
807 out->ref = 0; /* Gallium gets it from elsewhere */
808
809 out->mask = in->valuemask;
810 out->func = panfrost_translate_compare_func(in->func);
811 out->sfail = panfrost_translate_stencil_op(in->fail_op);
812 out->dpfail = panfrost_translate_stencil_op(in->zfail_op);
813 out->dppass = panfrost_translate_stencil_op(in->zpass_op);
814 }
815
816 static void
817 panfrost_default_shader_backend(struct panfrost_context *ctx)
818 {
819 struct mali_shader_meta shader = {
820 .alpha_coverage = ~MALI_ALPHA_COVERAGE(0.000000),
821
822 .unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x3010,
823 .unknown2_4 = MALI_NO_MSAA | 0x4e0,
824 };
825
826 if (is_t6xx) {
827 shader.unknown2_4 |= 0x10;
828 }
829
830 struct pipe_stencil_state default_stencil = {
831 .enabled = 0,
832 .func = PIPE_FUNC_ALWAYS,
833 .fail_op = MALI_STENCIL_KEEP,
834 .zfail_op = MALI_STENCIL_KEEP,
835 .zpass_op = MALI_STENCIL_KEEP,
836 .writemask = 0xFF,
837 .valuemask = 0xFF
838 };
839
840 panfrost_make_stencil_state(&default_stencil, &shader.stencil_front);
841 shader.stencil_mask_front = default_stencil.writemask;
842
843 panfrost_make_stencil_state(&default_stencil, &shader.stencil_back);
844 shader.stencil_mask_back = default_stencil.writemask;
845
846 if (default_stencil.enabled)
847 shader.unknown2_4 |= MALI_STENCIL_TEST;
848
849 memcpy(&ctx->fragment_shader_core, &shader, sizeof(shader));
850 }
851
852 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
853 * graphics command stream. It should be called once per draw, accordding to
854 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
855 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
856 * vertex jobs. */
857
858 struct panfrost_transfer
859 panfrost_vertex_tiler_job(struct panfrost_context *ctx, bool is_tiler, bool is_elided_tiler)
860 {
861 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
862 int draw_job_index = 1 + (2 * ctx->draw_count);
863
864 struct mali_job_descriptor_header job = {
865 .job_type = is_tiler ? JOB_TYPE_TILER : JOB_TYPE_VERTEX,
866 .job_index = draw_job_index + (is_tiler ? 1 : 0),
867 #ifdef __LP64__
868 .job_descriptor_size = 1,
869 #endif
870 };
871
872 /* Only non-elided tiler jobs have dependencies which are known at this point */
873
874 if (is_tiler && !is_elided_tiler) {
875 /* Tiler jobs depend on vertex jobs */
876
877 job.job_dependency_index_1 = draw_job_index;
878
879 /* Tiler jobs also depend on the previous tiler job */
880
881 if (ctx->draw_count)
882 job.job_dependency_index_2 = draw_job_index - 1;
883 }
884
885 struct midgard_payload_vertex_tiler *payload = is_tiler ? &ctx->payload_tiler : &ctx->payload_vertex;
886
887 /* There's some padding hacks on 32-bit */
888
889 #ifdef __LP64__
890 int offset = 0;
891 #else
892 int offset = 4;
893 #endif
894 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(job) + sizeof(*payload));
895 memcpy(transfer.cpu, &job, sizeof(job));
896 memcpy(transfer.cpu + sizeof(job) - offset, payload, sizeof(*payload));
897 return transfer;
898 }
899
900 /* Generates a set value job. It's unclear what exactly this does, why it's
901 * necessary, and when to call it. */
902
903 static void
904 panfrost_set_value_job(struct panfrost_context *ctx)
905 {
906 struct mali_job_descriptor_header job = {
907 .job_type = JOB_TYPE_SET_VALUE,
908 .job_descriptor_size = 1,
909 .job_index = 1 + (2 * ctx->draw_count),
910 };
911
912 struct mali_payload_set_value payload = {
913 .out = ctx->misc_0.gpu,
914 .unknown = 0x3,
915 };
916
917 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(job) + sizeof(payload));
918 memcpy(transfer.cpu, &job, sizeof(job));
919 memcpy(transfer.cpu + sizeof(job), &payload, sizeof(payload));
920
921 ctx->u_set_value_job = (struct mali_job_descriptor_header *) transfer.cpu;
922 ctx->set_value_job = transfer.gpu;
923 }
924
925 /* Generate a fragment job. This should be called once per frame. (According to
926 * presentations, this is supposed to correspond to eglSwapBuffers) */
927
928 mali_ptr
929 panfrost_fragment_job(struct panfrost_context *ctx)
930 {
931 /* Update fragment FBD */
932 panfrost_set_fragment_afbc(ctx);
933
934 if (ctx->pipe_framebuffer.nr_cbufs == 1) {
935 struct panfrost_resource *rsrc = (struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[0]->texture;
936
937 if (rsrc->bo->has_checksum) {
938 if (require_sfbd) {
939 fprintf(stderr, "Checksumming not supported on SFBD\n");
940 assert(0);
941 }
942
943 int stride = util_format_get_stride(rsrc->base.format, rsrc->base.width0);
944
945 ctx->fragment_mfbd.unk3 |= MALI_MFBD_EXTRA;
946 ctx->fragment_extra.unk |= 0x420;
947 ctx->fragment_extra.checksum_stride = rsrc->bo->checksum_stride;
948 ctx->fragment_extra.checksum = rsrc->bo->gpu[0] + stride * rsrc->base.height0;
949 }
950 }
951
952 /* The frame is complete and therefore the framebuffer descriptor is
953 * ready for linkage and upload */
954
955 size_t sz = require_sfbd ? sizeof(struct mali_single_framebuffer) : (sizeof(struct bifrost_framebuffer) + sizeof(struct bifrost_fb_extra) + sizeof(struct bifrost_render_target) * 1);
956 struct panfrost_transfer fbd_t = panfrost_allocate_transient(ctx, sz);
957 off_t offset = 0;
958
959 if (require_sfbd) {
960 /* Upload just the SFBD all at once */
961 memcpy(fbd_t.cpu, &ctx->fragment_sfbd, sizeof(ctx->fragment_sfbd));
962 offset += sizeof(ctx->fragment_sfbd);
963 } else {
964 /* Upload the MFBD header */
965 memcpy(fbd_t.cpu, &ctx->fragment_mfbd, sizeof(ctx->fragment_mfbd));
966 offset += sizeof(ctx->fragment_mfbd);
967
968 /* Upload extra framebuffer info if necessary */
969 if (ctx->fragment_mfbd.unk3 & MALI_MFBD_EXTRA) {
970 memcpy(fbd_t.cpu + offset, &ctx->fragment_extra, sizeof(struct bifrost_fb_extra));
971 offset += sizeof(struct bifrost_fb_extra);
972 }
973
974 /* Upload (single) render target */
975 memcpy(fbd_t.cpu + offset, &ctx->fragment_rts[0], sizeof(struct bifrost_render_target) * 1);
976 }
977
978 /* Generate the fragment (frame) job */
979
980 struct mali_job_descriptor_header header = {
981 .job_type = JOB_TYPE_FRAGMENT,
982 .job_index = 1,
983 #ifdef __LP64__
984 .job_descriptor_size = 1
985 #endif
986 };
987
988 struct mali_payload_fragment payload = {
989 .min_tile_coord = MALI_COORDINATE_TO_TILE_MIN(0, 0),
990 .max_tile_coord = MALI_COORDINATE_TO_TILE_MAX(ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height),
991 .framebuffer = fbd_t.gpu | (require_sfbd ? MALI_SFBD : MALI_MFBD),
992 };
993
994 if (!require_sfbd && ctx->fragment_mfbd.unk3 & MALI_MFBD_EXTRA) {
995 /* Signal that there is an extra portion of the framebuffer
996 * descriptor */
997
998 payload.framebuffer |= 2;
999 }
1000
1001 /* Normally, there should be no padding. However, fragment jobs are
1002 * shared with 64-bit Bifrost systems, and accordingly there is 4-bytes
1003 * of zero padding in between. */
1004
1005 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(header) + sizeof(payload));
1006 memcpy(transfer.cpu, &header, sizeof(header));
1007 memcpy(transfer.cpu + sizeof(header), &payload, sizeof(payload));
1008 return transfer.gpu;
1009 }
1010
1011 /* Emits attributes and varying descriptors, which should be called every draw,
1012 * excepting some obscure circumstances */
1013
1014 static void
1015 panfrost_emit_vertex_data(struct panfrost_context *ctx)
1016 {
1017 /* TODO: Only update the dirtied buffers */
1018 union mali_attr attrs[PIPE_MAX_ATTRIBS];
1019 union mali_attr varyings[PIPE_MAX_ATTRIBS];
1020
1021 unsigned invocation_count = MALI_NEGATIVE(ctx->payload_tiler.prefix.invocation_count);
1022
1023 for (int i = 0; i < ctx->vertex_buffer_count; ++i) {
1024 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[i];
1025 struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer.resource);
1026
1027 /* Let's figure out the layout of the attributes in memory so
1028 * we can be smart about size computation. The idea is to
1029 * figure out the maximum src_offset, which tells us the latest
1030 * spot a vertex could start. Meanwhile, we figure out the size
1031 * of the attribute memory (assuming interleaved
1032 * representation) and tack on the max src_offset for a
1033 * reasonably good upper bound on the size.
1034 *
1035 * Proving correctness is left as an exercise to the reader.
1036 */
1037
1038 unsigned max_src_offset = 0;
1039
1040 for (unsigned j = 0; j < ctx->vertex->num_elements; ++j) {
1041 if (ctx->vertex->pipe[j].vertex_buffer_index != i) continue;
1042 max_src_offset = MAX2(max_src_offset, ctx->vertex->pipe[j].src_offset);
1043 }
1044
1045 /* Offset vertex count by draw_start to make sure we upload enough */
1046 attrs[i].stride = buf->stride;
1047 attrs[i].size = buf->stride * (ctx->payload_vertex.draw_start + invocation_count) + max_src_offset;
1048
1049 /* Vertex elements are -already- GPU-visible, at
1050 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
1051 * it is not, for now we have to duplicate the buffer. */
1052
1053 mali_ptr effective_address = (rsrc->bo->gpu[0] + buf->buffer_offset);
1054
1055 if (effective_address & 0x3F) {
1056 attrs[i].elements = panfrost_upload_transient(ctx, rsrc->bo->cpu[0] + buf->buffer_offset, attrs[i].size) | 1;
1057 } else {
1058 attrs[i].elements = effective_address | 1;
1059 }
1060 }
1061
1062 struct panfrost_varyings *vars = &ctx->vs->variants[ctx->vs->active_variant].varyings;
1063
1064 for (int i = 0; i < vars->varying_buffer_count; ++i) {
1065 mali_ptr varying_address = ctx->varying_mem.gpu + ctx->varying_height;
1066
1067 varyings[i].elements = varying_address | 1;
1068 varyings[i].stride = vars->varyings_stride[i];
1069 varyings[i].size = vars->varyings_stride[i] * invocation_count;
1070
1071 /* If this varying has to be linked somewhere, do it now. See
1072 * pan_assemble.c for the indices. TODO: Use a more generic
1073 * linking interface */
1074
1075 if (i == 1) {
1076 /* gl_Position */
1077 ctx->payload_tiler.postfix.position_varying = varying_address;
1078 } else if (i == 2) {
1079 /* gl_PointSize */
1080 ctx->payload_tiler.primitive_size.pointer = varying_address;
1081 }
1082
1083 /* Varyings appear to need 64-byte alignment */
1084 ctx->varying_height += ALIGN(varyings[i].size, 64);
1085
1086 /* Ensure that we fit */
1087 assert(ctx->varying_height < ctx->varying_mem.size);
1088 }
1089
1090 ctx->payload_vertex.postfix.attributes = panfrost_upload_transient(ctx, attrs, ctx->vertex_buffer_count * sizeof(union mali_attr));
1091
1092 mali_ptr varyings_p = panfrost_upload_transient(ctx, &varyings, vars->varying_buffer_count * sizeof(union mali_attr));
1093 ctx->payload_vertex.postfix.varyings = varyings_p;
1094 ctx->payload_tiler.postfix.varyings = varyings_p;
1095 }
1096
1097 /* Go through dirty flags and actualise them in the cmdstream. */
1098
1099 void
1100 panfrost_emit_for_draw(struct panfrost_context *ctx, bool with_vertex_data)
1101 {
1102 if (with_vertex_data) {
1103 panfrost_emit_vertex_data(ctx);
1104 }
1105
1106 if (ctx->dirty & PAN_DIRTY_RASTERIZER) {
1107 ctx->payload_tiler.gl_enables = ctx->rasterizer->tiler_gl_enables;
1108 panfrost_set_framebuffer_msaa(ctx, ctx->rasterizer->base.multisample);
1109 }
1110
1111 if (ctx->occlusion_query) {
1112 ctx->payload_tiler.gl_enables |= MALI_OCCLUSION_QUERY | MALI_OCCLUSION_PRECISE;
1113 ctx->payload_tiler.postfix.occlusion_counter = ctx->occlusion_query->transfer.gpu;
1114 }
1115
1116 if (ctx->dirty & PAN_DIRTY_VS) {
1117 assert(ctx->vs);
1118
1119 struct panfrost_shader_state *vs = &ctx->vs->variants[ctx->vs->active_variant];
1120
1121 /* Late shader descriptor assignments */
1122 vs->tripipe->texture_count = ctx->sampler_view_count[PIPE_SHADER_VERTEX];
1123 vs->tripipe->sampler_count = ctx->sampler_count[PIPE_SHADER_VERTEX];
1124
1125 /* Who knows */
1126 vs->tripipe->midgard1.unknown1 = 0x2201;
1127
1128 ctx->payload_vertex.postfix._shader_upper = vs->tripipe_gpu >> 4;
1129
1130 /* Varying descriptor is tied to the vertex shader. Also the
1131 * fragment shader, I suppose, but it's generated with the
1132 * vertex shader so */
1133
1134 struct panfrost_varyings *varyings = &ctx->vs->variants[ctx->vs->active_variant].varyings;
1135
1136 ctx->payload_vertex.postfix.varying_meta = varyings->varyings_descriptor;
1137 ctx->payload_tiler.postfix.varying_meta = varyings->varyings_descriptor_fragment;
1138 }
1139
1140 if (ctx->dirty & (PAN_DIRTY_RASTERIZER | PAN_DIRTY_VS)) {
1141 /* Check if we need to link the gl_PointSize varying */
1142 assert(ctx->vs);
1143 struct panfrost_shader_state *vs = &ctx->vs->variants[ctx->vs->active_variant];
1144
1145 bool needs_gl_point_size = vs->writes_point_size && ctx->payload_tiler.prefix.draw_mode == MALI_POINTS;
1146
1147 if (!needs_gl_point_size) {
1148 /* If the size is constant, write it out. Otherwise,
1149 * don't touch primitive_size (since we would clobber
1150 * the pointer there) */
1151
1152 ctx->payload_tiler.primitive_size.constant = ctx->rasterizer->base.line_width;
1153 }
1154
1155 /* Set the flag for varying (pointer) point size if the shader needs that */
1156 SET_BIT(ctx->payload_tiler.prefix.unknown_draw, MALI_DRAW_VARYING_SIZE, needs_gl_point_size);
1157 }
1158
1159 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1160 if (ctx->fs)
1161 ctx->dirty |= PAN_DIRTY_FS;
1162
1163 if (ctx->dirty & PAN_DIRTY_FS) {
1164 assert(ctx->fs);
1165 struct panfrost_shader_state *variant = &ctx->fs->variants[ctx->fs->active_variant];
1166
1167 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1168
1169 COPY(shader);
1170 COPY(attribute_count);
1171 COPY(varying_count);
1172 COPY(midgard1.uniform_count);
1173 COPY(midgard1.work_count);
1174 COPY(midgard1.unknown2);
1175
1176 #undef COPY
1177 /* If there is a blend shader, work registers are shared */
1178
1179 if (ctx->blend->has_blend_shader)
1180 ctx->fragment_shader_core.midgard1.work_count = /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1181
1182 /* Set late due to depending on render state */
1183 /* The one at the end seems to mean "1 UBO" */
1184 ctx->fragment_shader_core.midgard1.unknown1 = MALI_NO_ALPHA_TO_COVERAGE | 0x200 | 0x2201;
1185
1186 /* Assign texture/sample count right before upload */
1187 ctx->fragment_shader_core.texture_count = ctx->sampler_view_count[PIPE_SHADER_FRAGMENT];
1188 ctx->fragment_shader_core.sampler_count = ctx->sampler_count[PIPE_SHADER_FRAGMENT];
1189
1190 /* Assign the stencil refs late */
1191 ctx->fragment_shader_core.stencil_front.ref = ctx->stencil_ref.ref_value[0];
1192 ctx->fragment_shader_core.stencil_back.ref = ctx->stencil_ref.ref_value[1];
1193
1194 /* CAN_DISCARD should be set if the fragment shader possibly
1195 * contains a 'discard' instruction. It is likely this is
1196 * related to optimizations related to forward-pixel kill, as
1197 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1198 * thing?" by Peter Harris
1199 */
1200
1201 if (variant->can_discard) {
1202 ctx->fragment_shader_core.unknown2_3 |= MALI_CAN_DISCARD;
1203 ctx->fragment_shader_core.midgard1.unknown1 &= ~MALI_NO_ALPHA_TO_COVERAGE;
1204 ctx->fragment_shader_core.midgard1.unknown1 |= 0x4000;
1205 ctx->fragment_shader_core.midgard1.unknown1 = 0x4200;
1206 }
1207
1208 /* Check if we're using the default blend descriptor (fast path) */
1209
1210 bool no_blending =
1211 !ctx->blend->has_blend_shader &&
1212 (ctx->blend->equation.rgb_mode == 0x122) &&
1213 (ctx->blend->equation.alpha_mode == 0x122) &&
1214 (ctx->blend->equation.color_mask == 0xf);
1215
1216 if (require_sfbd) {
1217 /* When only a single render target platform is used, the blend
1218 * information is inside the shader meta itself. We
1219 * additionally need to signal CAN_DISCARD for nontrivial blend
1220 * modes (so we're able to read back the destination buffer) */
1221
1222 if (ctx->blend->has_blend_shader) {
1223 ctx->fragment_shader_core.blend_shader = ctx->blend->blend_shader;
1224 } else {
1225 memcpy(&ctx->fragment_shader_core.blend_equation, &ctx->blend->equation, sizeof(ctx->blend->equation));
1226 }
1227
1228 if (!no_blending) {
1229 ctx->fragment_shader_core.unknown2_3 |= MALI_CAN_DISCARD;
1230 }
1231 }
1232
1233 size_t size = sizeof(struct mali_shader_meta) + sizeof(struct mali_blend_meta);
1234 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
1235 memcpy(transfer.cpu, &ctx->fragment_shader_core, sizeof(struct mali_shader_meta));
1236
1237 ctx->payload_tiler.postfix._shader_upper = (transfer.gpu) >> 4;
1238
1239 if (!require_sfbd) {
1240 /* Additional blend descriptor tacked on for jobs using MFBD */
1241
1242 unsigned blend_count = 0;
1243
1244 if (ctx->blend->has_blend_shader) {
1245 /* For a blend shader, the bottom nibble corresponds to
1246 * the number of work registers used, which signals the
1247 * -existence- of a blend shader */
1248
1249 assert(ctx->blend->blend_work_count >= 2);
1250 blend_count |= MIN2(ctx->blend->blend_work_count, 3);
1251 } else {
1252 /* Otherwise, the bottom bit simply specifies if
1253 * blending (anything other than REPLACE) is enabled */
1254
1255
1256 if (!no_blending)
1257 blend_count |= 0x1;
1258 }
1259
1260 /* Second blend equation is always a simple replace */
1261
1262 uint64_t replace_magic = 0xf0122122;
1263 struct mali_blend_equation replace_mode;
1264 memcpy(&replace_mode, &replace_magic, sizeof(replace_mode));
1265
1266 struct mali_blend_meta blend_meta[] = {
1267 {
1268 .unk1 = 0x200 | blend_count,
1269 .blend_equation_1 = ctx->blend->equation,
1270 .blend_equation_2 = replace_mode
1271 },
1272 };
1273
1274 if (ctx->blend->has_blend_shader)
1275 memcpy(&blend_meta[0].blend_equation_1, &ctx->blend->blend_shader, sizeof(ctx->blend->blend_shader));
1276
1277 memcpy(transfer.cpu + sizeof(struct mali_shader_meta), blend_meta, sizeof(blend_meta));
1278 }
1279 }
1280
1281 if (ctx->dirty & PAN_DIRTY_VERTEX) {
1282 ctx->payload_vertex.postfix.attribute_meta = ctx->vertex->descriptor_ptr;
1283 }
1284
1285 if (ctx->dirty & PAN_DIRTY_SAMPLERS) {
1286 /* Upload samplers back to back, no padding */
1287
1288 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
1289 if (!ctx->sampler_count[t]) continue;
1290
1291 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, sizeof(struct mali_sampler_descriptor) * ctx->sampler_count[t]);
1292 struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *) transfer.cpu;
1293
1294 for (int i = 0; i < ctx->sampler_count[t]; ++i) {
1295 desc[i] = ctx->samplers[t][i]->hw;
1296 }
1297
1298 if (t == PIPE_SHADER_FRAGMENT)
1299 ctx->payload_tiler.postfix.sampler_descriptor = transfer.gpu;
1300 else if (t == PIPE_SHADER_VERTEX)
1301 ctx->payload_vertex.postfix.sampler_descriptor = transfer.gpu;
1302 else
1303 assert(0);
1304 }
1305 }
1306
1307 if (ctx->dirty & PAN_DIRTY_TEXTURES) {
1308 for (int t = 0; t <= PIPE_SHADER_FRAGMENT; ++t) {
1309 /* Shortcircuit */
1310 if (!ctx->sampler_view_count[t]) continue;
1311
1312 uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS];
1313
1314 for (int i = 0; i < ctx->sampler_view_count[t]; ++i) {
1315 if (!ctx->sampler_views[t][i])
1316 continue;
1317
1318 struct pipe_resource *tex_rsrc = ctx->sampler_views[t][i]->base.texture;
1319 struct panfrost_resource *rsrc = (struct panfrost_resource *) tex_rsrc;
1320
1321 /* Inject the address in. */
1322 for (int l = 0; l < (tex_rsrc->last_level + 1); ++l)
1323 ctx->sampler_views[t][i]->hw.swizzled_bitmaps[l] = rsrc->bo->gpu[l];
1324
1325 /* Workaround maybe-errata (?) with non-mipmaps */
1326 int s = ctx->sampler_views[t][i]->hw.nr_mipmap_levels;
1327
1328 if (!rsrc->bo->is_mipmap) {
1329 if (is_t6xx) {
1330 /* HW ERRATA, not needed after t6XX */
1331 ctx->sampler_views[t][i]->hw.swizzled_bitmaps[1] = rsrc->bo->gpu[0];
1332
1333 ctx->sampler_views[t][i]->hw.unknown3A = 1;
1334 }
1335
1336 ctx->sampler_views[t][i]->hw.nr_mipmap_levels = 0;
1337 }
1338
1339 trampolines[i] = panfrost_upload_transient(ctx, &ctx->sampler_views[t][i]->hw, sizeof(struct mali_texture_descriptor));
1340
1341 /* Restore */
1342 ctx->sampler_views[t][i]->hw.nr_mipmap_levels = s;
1343
1344 if (is_t6xx) {
1345 ctx->sampler_views[t][i]->hw.unknown3A = 0;
1346 }
1347 }
1348
1349 mali_ptr trampoline = panfrost_upload_transient(ctx, trampolines, sizeof(uint64_t) * ctx->sampler_view_count[t]);
1350
1351 if (t == PIPE_SHADER_FRAGMENT)
1352 ctx->payload_tiler.postfix.texture_trampoline = trampoline;
1353 else if (t == PIPE_SHADER_VERTEX)
1354 ctx->payload_vertex.postfix.texture_trampoline = trampoline;
1355 else
1356 assert(0);
1357 }
1358 }
1359
1360 /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1361 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
1362
1363 float viewport_vec4[] = {
1364 vp->scale[0],
1365 fabsf(vp->scale[1]),
1366
1367 vp->translate[0],
1368 /* -1.0 * vp->translate[1] */ fabs(1.0 * vp->scale[1]) /* XXX */
1369 };
1370
1371 for (int i = 0; i < PIPE_SHADER_TYPES; ++i) {
1372 struct panfrost_constant_buffer *buf = &ctx->constant_buffer[i];
1373
1374 if (i == PIPE_SHADER_VERTEX || i == PIPE_SHADER_FRAGMENT) {
1375 /* It doesn't matter if we don't use all the memory;
1376 * we'd need a dummy UBO anyway. Compute the max */
1377
1378 size_t size = sizeof(viewport_vec4) + buf->size;
1379 struct panfrost_transfer transfer = panfrost_allocate_transient(ctx, size);
1380
1381 /* Keep track how much we've uploaded */
1382 off_t offset = 0;
1383
1384 if (i == PIPE_SHADER_VERTEX) {
1385 /* Upload viewport */
1386 memcpy(transfer.cpu + offset, viewport_vec4, sizeof(viewport_vec4));
1387 offset += sizeof(viewport_vec4);
1388 }
1389
1390 /* Upload uniforms */
1391 memcpy(transfer.cpu + offset, buf->buffer, buf->size);
1392
1393 int uniform_count = 0;
1394
1395 struct mali_vertex_tiler_postfix *postfix;
1396
1397 switch (i) {
1398 case PIPE_SHADER_VERTEX:
1399 uniform_count = ctx->vs->variants[ctx->vs->active_variant].uniform_count;
1400 postfix = &ctx->payload_vertex.postfix;
1401 break;
1402
1403 case PIPE_SHADER_FRAGMENT:
1404 uniform_count = ctx->fs->variants[ctx->fs->active_variant].uniform_count;
1405 postfix = &ctx->payload_tiler.postfix;
1406 break;
1407
1408 default:
1409 printf("Unknown shader stage %d in uniform upload\n", i);
1410 assert(0);
1411 }
1412
1413 /* Also attach the same buffer as a UBO for extended access */
1414
1415 struct mali_uniform_buffer_meta uniform_buffers[] = {
1416 {
1417 .size = MALI_POSITIVE((2 + uniform_count)),
1418 .ptr = transfer.gpu >> 2,
1419 },
1420 };
1421
1422 mali_ptr ubufs = panfrost_upload_transient(ctx, uniform_buffers, sizeof(uniform_buffers));
1423 postfix->uniforms = transfer.gpu;
1424 postfix->uniform_buffers = ubufs;
1425
1426 buf->dirty = 0;
1427 }
1428 }
1429
1430 ctx->dirty = 0;
1431 }
1432
1433 /* Corresponds to exactly one draw, but does not submit anything */
1434
1435 static void
1436 panfrost_queue_draw(struct panfrost_context *ctx)
1437 {
1438 /* TODO: Expand the array? */
1439 if (ctx->draw_count >= MAX_DRAW_CALLS) {
1440 printf("Job buffer overflow, ignoring draw\n");
1441 assert(0);
1442 }
1443
1444 /* Handle dirty flags now */
1445 panfrost_emit_for_draw(ctx, true);
1446
1447 struct panfrost_transfer vertex = panfrost_vertex_tiler_job(ctx, false, false);
1448 struct panfrost_transfer tiler = panfrost_vertex_tiler_job(ctx, true, false);
1449
1450 ctx->u_vertex_jobs[ctx->vertex_job_count] = (struct mali_job_descriptor_header *) vertex.cpu;
1451 ctx->vertex_jobs[ctx->vertex_job_count++] = vertex.gpu;
1452
1453 ctx->u_tiler_jobs[ctx->tiler_job_count] = (struct mali_job_descriptor_header *) tiler.cpu;
1454 ctx->tiler_jobs[ctx->tiler_job_count++] = tiler.gpu;
1455
1456 ctx->draw_count++;
1457 }
1458
1459 /* At the end of the frame, the vertex and tiler jobs are linked together and
1460 * then the fragment job is plonked at the end. Set value job is first for
1461 * unknown reasons. */
1462
1463 static void
1464 panfrost_link_job_pair(struct mali_job_descriptor_header *first, mali_ptr next)
1465 {
1466 if (first->job_descriptor_size)
1467 first->next_job_64 = (u64) (uintptr_t) next;
1468 else
1469 first->next_job_32 = (u32) (uintptr_t) next;
1470 }
1471
1472 static void
1473 panfrost_link_jobs(struct panfrost_context *ctx)
1474 {
1475 if (ctx->draw_count) {
1476 /* Generate the set_value_job */
1477 panfrost_set_value_job(ctx);
1478
1479 /* Have the first vertex job depend on the set value job */
1480 ctx->u_vertex_jobs[0]->job_dependency_index_1 = ctx->u_set_value_job->job_index;
1481
1482 /* SV -> V */
1483 panfrost_link_job_pair(ctx->u_set_value_job, ctx->vertex_jobs[0]);
1484 }
1485
1486 /* V -> V/T ; T -> T/null */
1487 for (int i = 0; i < ctx->vertex_job_count; ++i) {
1488 bool isLast = (i + 1) == ctx->vertex_job_count;
1489
1490 panfrost_link_job_pair(ctx->u_vertex_jobs[i], isLast ? ctx->tiler_jobs[0] : ctx->vertex_jobs[i + 1]);
1491 }
1492
1493 /* T -> T/null */
1494 for (int i = 0; i < ctx->tiler_job_count; ++i) {
1495 bool isLast = (i + 1) == ctx->tiler_job_count;
1496 panfrost_link_job_pair(ctx->u_tiler_jobs[i], isLast ? 0 : ctx->tiler_jobs[i + 1]);
1497 }
1498 }
1499
1500 /* The entire frame is in memory -- send it off to the kernel! */
1501
1502 static void
1503 panfrost_submit_frame(struct panfrost_context *ctx, bool flush_immediate)
1504 {
1505 struct pipe_context *gallium = (struct pipe_context *) ctx;
1506 struct panfrost_screen *screen = pan_screen(gallium->screen);
1507
1508 /* Edge case if screen is cleared and nothing else */
1509 bool has_draws = ctx->draw_count > 0;
1510
1511 /* Workaround a bizarre lockup (a hardware errata?) */
1512 if (!has_draws)
1513 flush_immediate = true;
1514
1515 /* A number of jobs are batched -- this must be linked and cleared */
1516 panfrost_link_jobs(ctx);
1517
1518 ctx->draw_count = 0;
1519 ctx->vertex_job_count = 0;
1520 ctx->tiler_job_count = 0;
1521
1522 #ifndef DRY_RUN
1523
1524 bool is_scanout = panfrost_is_scanout(ctx);
1525 int fragment_id = screen->driver->submit_vs_fs_job(ctx, has_draws, is_scanout);
1526
1527 /* If visual, we can stall a frame */
1528
1529 if (panfrost_is_scanout(ctx) && !flush_immediate)
1530 screen->driver->force_flush_fragment(ctx);
1531
1532 screen->last_fragment_id = fragment_id;
1533 screen->last_fragment_flushed = false;
1534
1535 /* If readback, flush now (hurts the pipelined performance) */
1536 if (panfrost_is_scanout(ctx) && flush_immediate)
1537 screen->driver->force_flush_fragment(ctx);
1538
1539 #ifdef DUMP_PERFORMANCE_COUNTERS
1540 char filename[128];
1541 snprintf(filename, sizeof(filename), "/dev/shm/frame%d.mdgprf", ++performance_counter_number);
1542 FILE *fp = fopen(filename, "wb");
1543 fwrite(screen->perf_counters.cpu, 4096, sizeof(uint32_t), fp);
1544 fclose(fp);
1545 #endif
1546
1547 #endif
1548 }
1549
1550 bool dont_scanout = false;
1551
1552 void
1553 panfrost_flush(
1554 struct pipe_context *pipe,
1555 struct pipe_fence_handle **fence,
1556 unsigned flags)
1557 {
1558 struct panfrost_context *ctx = pan_context(pipe);
1559
1560 /* If there is nothing drawn, skip the frame */
1561 if (!ctx->draw_count && !ctx->frame_cleared) return;
1562
1563 if (!ctx->frame_cleared) {
1564 /* While there are draws, there was no clear. This is a partial
1565 * update, which needs to be handled via the "wallpaper"
1566 * method. We also need to fake a clear, just to get the
1567 * FRAGMENT job correct. */
1568
1569 panfrost_clear(&ctx->base, ctx->last_clear.buffers, ctx->last_clear.color, ctx->last_clear.depth, ctx->last_clear.stencil);
1570
1571 panfrost_draw_wallpaper(pipe);
1572 }
1573
1574 /* Frame clear handled, reset */
1575 ctx->frame_cleared = false;
1576
1577 /* Whether to stall the pipeline for immediately correct results */
1578 bool flush_immediate = flags & PIPE_FLUSH_END_OF_FRAME;
1579
1580 /* Submit the frame itself */
1581 panfrost_submit_frame(ctx, flush_immediate);
1582
1583 /* Prepare for the next frame */
1584 panfrost_invalidate_frame(ctx);
1585 }
1586
1587 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1588
1589 static int
1590 g2m_draw_mode(enum pipe_prim_type mode)
1591 {
1592 switch (mode) {
1593 DEFINE_CASE(POINTS);
1594 DEFINE_CASE(LINES);
1595 DEFINE_CASE(LINE_LOOP);
1596 DEFINE_CASE(LINE_STRIP);
1597 DEFINE_CASE(TRIANGLES);
1598 DEFINE_CASE(TRIANGLE_STRIP);
1599 DEFINE_CASE(TRIANGLE_FAN);
1600 DEFINE_CASE(QUADS);
1601 DEFINE_CASE(QUAD_STRIP);
1602 DEFINE_CASE(POLYGON);
1603
1604 default:
1605 printf("Illegal draw mode %d\n", mode);
1606 assert(0);
1607 return MALI_LINE_LOOP;
1608 }
1609 }
1610
1611 #undef DEFINE_CASE
1612
1613 static unsigned
1614 panfrost_translate_index_size(unsigned size)
1615 {
1616 switch (size) {
1617 case 1:
1618 return MALI_DRAW_INDEXED_UINT8;
1619
1620 case 2:
1621 return MALI_DRAW_INDEXED_UINT16;
1622
1623 case 4:
1624 return MALI_DRAW_INDEXED_UINT32;
1625
1626 default:
1627 printf("Unknown index size %d\n", size);
1628 assert(0);
1629 return 0;
1630 }
1631 }
1632
1633 static const uint8_t *
1634 panfrost_get_index_buffer_raw(const struct pipe_draw_info *info)
1635 {
1636 if (info->has_user_indices) {
1637 return (const uint8_t *) info->index.user;
1638 } else {
1639 struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
1640 return (const uint8_t *) rsrc->bo->cpu[0];
1641 }
1642 }
1643
1644 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1645 * good for the duration of the draw (transient), could last longer */
1646
1647 static mali_ptr
1648 panfrost_get_index_buffer_mapped(struct panfrost_context *ctx, const struct pipe_draw_info *info)
1649 {
1650 struct panfrost_resource *rsrc = (struct panfrost_resource *) (info->index.resource);
1651
1652 off_t offset = info->start * info->index_size;
1653
1654 if (!info->has_user_indices) {
1655 /* Only resources can be directly mapped */
1656 return rsrc->bo->gpu[0] + offset;
1657 } else {
1658 /* Otherwise, we need to upload to transient memory */
1659 const uint8_t *ibuf8 = panfrost_get_index_buffer_raw(info);
1660 return panfrost_upload_transient(ctx, ibuf8 + offset, info->count * info->index_size);
1661 }
1662 }
1663
1664 static void
1665 panfrost_draw_vbo(
1666 struct pipe_context *pipe,
1667 const struct pipe_draw_info *info);
1668
1669 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1670 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1671 T idx = buffer[_idx]; \
1672 if (idx > max_index) max_index = idx; \
1673 if (idx < min_index) min_index = idx; \
1674 }
1675
1676 static void
1677 panfrost_draw_vbo(
1678 struct pipe_context *pipe,
1679 const struct pipe_draw_info *info)
1680 {
1681 struct panfrost_context *ctx = pan_context(pipe);
1682
1683 ctx->payload_vertex.draw_start = info->start;
1684 ctx->payload_tiler.draw_start = info->start;
1685
1686 int mode = info->mode;
1687
1688 /* Fallback for unsupported modes */
1689
1690 if (!(ctx->draw_modes & mode)) {
1691 if (mode == PIPE_PRIM_QUADS && info->count == 4 && ctx->rasterizer && !ctx->rasterizer->base.flatshade) {
1692 mode = PIPE_PRIM_TRIANGLE_FAN;
1693 } else {
1694 if (info->count < 4) {
1695 /* Degenerate case? */
1696 return;
1697 }
1698
1699 util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base);
1700 util_primconvert_draw_vbo(ctx->primconvert, info);
1701 return;
1702 }
1703 }
1704
1705 ctx->payload_tiler.prefix.draw_mode = g2m_draw_mode(mode);
1706
1707 ctx->vertex_count = info->count;
1708
1709 /* For non-indexed draws, they're the same */
1710 unsigned invocation_count = ctx->vertex_count;
1711
1712 /* For higher amounts of vertices (greater than what fits in a 16-bit
1713 * short), the other value is needed, otherwise there will be bizarre
1714 * rendering artefacts. It's not clear what these values mean yet. */
1715
1716 ctx->payload_tiler.prefix.unknown_draw &= ~(0x3000 | 0x18000);
1717 ctx->payload_tiler.prefix.unknown_draw |= (mode == PIPE_PRIM_POINTS || ctx->vertex_count > 65535) ? 0x3000 : 0x18000;
1718
1719 if (info->index_size) {
1720 /* Calculate the min/max index used so we can figure out how
1721 * many times to invoke the vertex shader */
1722
1723 const uint8_t *ibuf8 = panfrost_get_index_buffer_raw(info);
1724
1725 int min_index = INT_MAX;
1726 int max_index = 0;
1727
1728 if (info->index_size == 1) {
1729 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8, info->start, info->count);
1730 } else if (info->index_size == 2) {
1731 const uint16_t *ibuf16 = (const uint16_t *) ibuf8;
1732 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16, info->start, info->count);
1733 } else if (info->index_size == 4) {
1734 const uint32_t *ibuf32 = (const uint32_t *) ibuf8;
1735 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32, info->start, info->count);
1736 } else {
1737 assert(0);
1738 }
1739
1740 /* Make sure we didn't go crazy */
1741 assert(min_index < INT_MAX);
1742 assert(max_index > 0);
1743 assert(max_index > min_index);
1744
1745 /* Use the corresponding values */
1746 invocation_count = max_index - min_index + 1;
1747 ctx->payload_vertex.draw_start = min_index;
1748 ctx->payload_tiler.draw_start = min_index;
1749
1750 ctx->payload_tiler.prefix.negative_start = -min_index;
1751 ctx->payload_tiler.prefix.index_count = MALI_POSITIVE(info->count);
1752
1753 //assert(!info->restart_index); /* TODO: Research */
1754 assert(!info->index_bias);
1755 //assert(!info->min_index); /* TODO: Use value */
1756
1757 ctx->payload_tiler.prefix.unknown_draw |= panfrost_translate_index_size(info->index_size);
1758 ctx->payload_tiler.prefix.indices = panfrost_get_index_buffer_mapped(ctx, info);
1759 } else {
1760 /* Index count == vertex count, if no indexing is applied, as
1761 * if it is internally indexed in the expected order */
1762
1763 ctx->payload_tiler.prefix.negative_start = 0;
1764 ctx->payload_tiler.prefix.index_count = MALI_POSITIVE(ctx->vertex_count);
1765
1766 /* Reverse index state */
1767 ctx->payload_tiler.prefix.unknown_draw &= ~MALI_DRAW_INDEXED_UINT32;
1768 ctx->payload_tiler.prefix.indices = (uintptr_t) NULL;
1769 }
1770
1771 ctx->payload_vertex.prefix.invocation_count = MALI_POSITIVE(invocation_count);
1772 ctx->payload_tiler.prefix.invocation_count = MALI_POSITIVE(invocation_count);
1773
1774 /* Fire off the draw itself */
1775 panfrost_queue_draw(ctx);
1776 }
1777
1778 /* CSO state */
1779
1780 static void
1781 panfrost_generic_cso_delete(struct pipe_context *pctx, void *hwcso)
1782 {
1783 free(hwcso);
1784 }
1785
1786 static void
1787 panfrost_set_scissor(struct panfrost_context *ctx)
1788 {
1789 const struct pipe_scissor_state *ss = &ctx->scissor;
1790
1791 if (ss && ctx->rasterizer && ctx->rasterizer->base.scissor && 0) {
1792 ctx->viewport->viewport0[0] = ss->minx;
1793 ctx->viewport->viewport0[1] = ss->miny;
1794 ctx->viewport->viewport1[0] = MALI_POSITIVE(ss->maxx);
1795 ctx->viewport->viewport1[1] = MALI_POSITIVE(ss->maxy);
1796 } else {
1797 ctx->viewport->viewport0[0] = 0;
1798 ctx->viewport->viewport0[1] = 0;
1799 ctx->viewport->viewport1[0] = MALI_POSITIVE(ctx->pipe_framebuffer.width);
1800 ctx->viewport->viewport1[1] = MALI_POSITIVE(ctx->pipe_framebuffer.height);
1801 }
1802 }
1803
1804 static void *
1805 panfrost_create_rasterizer_state(
1806 struct pipe_context *pctx,
1807 const struct pipe_rasterizer_state *cso)
1808 {
1809 struct panfrost_rasterizer *so = CALLOC_STRUCT(panfrost_rasterizer);
1810
1811 so->base = *cso;
1812
1813 /* Bitmask, unknown meaning of the start value */
1814 so->tiler_gl_enables = is_t6xx ? 0x105 : 0x7;
1815
1816 so->tiler_gl_enables |= MALI_FRONT_FACE(
1817 cso->front_ccw ? MALI_CCW : MALI_CW);
1818
1819 if (cso->cull_face & PIPE_FACE_FRONT)
1820 so->tiler_gl_enables |= MALI_CULL_FACE_FRONT;
1821
1822 if (cso->cull_face & PIPE_FACE_BACK)
1823 so->tiler_gl_enables |= MALI_CULL_FACE_BACK;
1824
1825 return so;
1826 }
1827
1828 static void
1829 panfrost_bind_rasterizer_state(
1830 struct pipe_context *pctx,
1831 void *hwcso)
1832 {
1833 struct panfrost_context *ctx = pan_context(pctx);
1834 struct pipe_rasterizer_state *cso = hwcso;
1835
1836 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1837 if (!hwcso)
1838 return;
1839
1840 /* If scissor test has changed, we'll need to update that now */
1841 bool update_scissor = !ctx->rasterizer || ctx->rasterizer->base.scissor != cso->scissor;
1842
1843 ctx->rasterizer = hwcso;
1844
1845 /* Actualise late changes */
1846 if (update_scissor)
1847 panfrost_set_scissor(ctx);
1848
1849 ctx->dirty |= PAN_DIRTY_RASTERIZER;
1850 }
1851
1852 static void *
1853 panfrost_create_vertex_elements_state(
1854 struct pipe_context *pctx,
1855 unsigned num_elements,
1856 const struct pipe_vertex_element *elements)
1857 {
1858 struct panfrost_context *ctx = pan_context(pctx);
1859 struct panfrost_vertex_state *so = CALLOC_STRUCT(panfrost_vertex_state);
1860
1861 so->num_elements = num_elements;
1862 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
1863
1864 struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_attr_meta) * num_elements, HEAP_DESCRIPTOR);
1865 so->hw = (struct mali_attr_meta *) transfer.cpu;
1866 so->descriptor_ptr = transfer.gpu;
1867
1868 /* Allocate memory for the descriptor state */
1869
1870 for (int i = 0; i < num_elements; ++i) {
1871 so->hw[i].index = elements[i].vertex_buffer_index;
1872
1873 enum pipe_format fmt = elements[i].src_format;
1874 const struct util_format_description *desc = util_format_description(fmt);
1875 so->hw[i].unknown1 = 0x2;
1876 so->hw[i].swizzle = panfrost_get_default_swizzle(desc->nr_channels);
1877
1878 so->hw[i].format = panfrost_find_format(desc);
1879
1880 /* The field itself should probably be shifted over */
1881 so->hw[i].src_offset = elements[i].src_offset;
1882 }
1883
1884 return so;
1885 }
1886
1887 static void
1888 panfrost_bind_vertex_elements_state(
1889 struct pipe_context *pctx,
1890 void *hwcso)
1891 {
1892 struct panfrost_context *ctx = pan_context(pctx);
1893
1894 ctx->vertex = hwcso;
1895 ctx->dirty |= PAN_DIRTY_VERTEX;
1896 }
1897
1898 static void
1899 panfrost_delete_vertex_elements_state(struct pipe_context *pctx, void *hwcso)
1900 {
1901 struct panfrost_vertex_state *so = (struct panfrost_vertex_state *) hwcso;
1902 unsigned bytes = sizeof(struct mali_attr_meta) * so->num_elements;
1903 printf("Vertex elements delete leaks descriptor (%d bytes)\n", bytes);
1904 free(hwcso);
1905 }
1906
1907 static void *
1908 panfrost_create_shader_state(
1909 struct pipe_context *pctx,
1910 const struct pipe_shader_state *cso)
1911 {
1912 struct panfrost_shader_variants *so = CALLOC_STRUCT(panfrost_shader_variants);
1913 so->base = *cso;
1914
1915 /* Token deep copy to prevent memory corruption */
1916
1917 if (cso->type == PIPE_SHADER_IR_TGSI)
1918 so->base.tokens = tgsi_dup_tokens(so->base.tokens);
1919
1920 return so;
1921 }
1922
1923 static void
1924 panfrost_delete_shader_state(
1925 struct pipe_context *pctx,
1926 void *so)
1927 {
1928 struct panfrost_shader_variants *cso = (struct panfrost_shader_variants *) so;
1929
1930 if (cso->base.type == PIPE_SHADER_IR_TGSI) {
1931 printf("Deleting TGSI shader leaks duplicated tokens\n");
1932 }
1933
1934 unsigned leak = cso->variant_count * sizeof(struct mali_shader_meta);
1935 printf("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak);
1936
1937 free(so);
1938 }
1939
1940 static void *
1941 panfrost_create_sampler_state(
1942 struct pipe_context *pctx,
1943 const struct pipe_sampler_state *cso)
1944 {
1945 struct panfrost_sampler_state *so = CALLOC_STRUCT(panfrost_sampler_state);
1946 so->base = *cso;
1947
1948 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1949
1950 struct mali_sampler_descriptor sampler_descriptor = {
1951 .filter_mode = MALI_TEX_MIN(translate_tex_filter(cso->min_img_filter))
1952 | MALI_TEX_MAG(translate_tex_filter(cso->mag_img_filter))
1953 | translate_mip_filter(cso->min_mip_filter)
1954 | 0x20,
1955
1956 .wrap_s = translate_tex_wrap(cso->wrap_s),
1957 .wrap_t = translate_tex_wrap(cso->wrap_t),
1958 .wrap_r = translate_tex_wrap(cso->wrap_r),
1959 .compare_func = panfrost_translate_alt_compare_func(cso->compare_func),
1960 .border_color = {
1961 cso->border_color.f[0],
1962 cso->border_color.f[1],
1963 cso->border_color.f[2],
1964 cso->border_color.f[3]
1965 },
1966 .min_lod = FIXED_16(0.0),
1967 .max_lod = FIXED_16(31.0),
1968 .unknown2 = 1,
1969 };
1970
1971 so->hw = sampler_descriptor;
1972
1973 return so;
1974 }
1975
1976 static void
1977 panfrost_bind_sampler_states(
1978 struct pipe_context *pctx,
1979 enum pipe_shader_type shader,
1980 unsigned start_slot, unsigned num_sampler,
1981 void **sampler)
1982 {
1983 assert(start_slot == 0);
1984
1985 struct panfrost_context *ctx = pan_context(pctx);
1986
1987 /* XXX: Should upload, not just copy? */
1988 ctx->sampler_count[shader] = num_sampler;
1989 memcpy(ctx->samplers[shader], sampler, num_sampler * sizeof (void *));
1990
1991 ctx->dirty |= PAN_DIRTY_SAMPLERS;
1992 }
1993
1994 static bool
1995 panfrost_variant_matches(struct panfrost_context *ctx, struct panfrost_shader_state *variant)
1996 {
1997 struct pipe_alpha_state *alpha = &ctx->depth_stencil->alpha;
1998
1999 if (alpha->enabled || variant->alpha_state.enabled) {
2000 /* Make sure enable state is at least the same */
2001 if (alpha->enabled != variant->alpha_state.enabled) {
2002 return false;
2003 }
2004
2005 /* Check that the contents of the test are the same */
2006 bool same_func = alpha->func == variant->alpha_state.func;
2007 bool same_ref = alpha->ref_value == variant->alpha_state.ref_value;
2008
2009 if (!(same_func && same_ref)) {
2010 return false;
2011 }
2012 }
2013 /* Otherwise, we're good to go */
2014 return true;
2015 }
2016
2017 static void
2018 panfrost_bind_fs_state(
2019 struct pipe_context *pctx,
2020 void *hwcso)
2021 {
2022 struct panfrost_context *ctx = pan_context(pctx);
2023
2024 ctx->fs = hwcso;
2025
2026 if (hwcso) {
2027 /* Match the appropriate variant */
2028
2029 signed variant = -1;
2030
2031 struct panfrost_shader_variants *variants = (struct panfrost_shader_variants *) hwcso;
2032
2033 for (unsigned i = 0; i < variants->variant_count; ++i) {
2034 if (panfrost_variant_matches(ctx, &variants->variants[i])) {
2035 variant = i;
2036 break;
2037 }
2038 }
2039
2040 if (variant == -1) {
2041 /* No variant matched, so create a new one */
2042 variant = variants->variant_count++;
2043 assert(variants->variant_count < MAX_SHADER_VARIANTS);
2044
2045 variants->variants[variant].base = hwcso;
2046 variants->variants[variant].alpha_state = ctx->depth_stencil->alpha;
2047
2048 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
2049 struct panfrost_context *ctx = pan_context(pctx);
2050 struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_shader_meta), HEAP_DESCRIPTOR);
2051
2052 variants->variants[variant].tripipe = (struct mali_shader_meta *) transfer.cpu;
2053 variants->variants[variant].tripipe_gpu = transfer.gpu;
2054
2055 }
2056
2057 /* Select this variant */
2058 variants->active_variant = variant;
2059
2060 struct panfrost_shader_state *shader_state = &variants->variants[variant];
2061 assert(panfrost_variant_matches(ctx, shader_state));
2062
2063 /* Now we have a variant selected, so compile and go */
2064
2065 if (!shader_state->compiled) {
2066 panfrost_shader_compile(ctx, shader_state->tripipe, NULL, JOB_TYPE_TILER, shader_state);
2067 shader_state->compiled = true;
2068 }
2069 }
2070
2071 ctx->dirty |= PAN_DIRTY_FS;
2072 }
2073
2074 static void
2075 panfrost_bind_vs_state(
2076 struct pipe_context *pctx,
2077 void *hwcso)
2078 {
2079 struct panfrost_context *ctx = pan_context(pctx);
2080
2081 ctx->vs = hwcso;
2082
2083 if (hwcso) {
2084 if (!ctx->vs->variants[0].compiled) {
2085 ctx->vs->variants[0].base = hwcso;
2086
2087 /* TODO DRY from above */
2088 struct panfrost_transfer transfer = panfrost_allocate_chunk(ctx, sizeof(struct mali_shader_meta), HEAP_DESCRIPTOR);
2089 ctx->vs->variants[0].tripipe = (struct mali_shader_meta *) transfer.cpu;
2090 ctx->vs->variants[0].tripipe_gpu = transfer.gpu;
2091
2092 panfrost_shader_compile(ctx, ctx->vs->variants[0].tripipe, NULL, JOB_TYPE_VERTEX, &ctx->vs->variants[0]);
2093 ctx->vs->variants[0].compiled = true;
2094 }
2095 }
2096
2097 ctx->dirty |= PAN_DIRTY_VS;
2098 }
2099
2100 static void
2101 panfrost_set_vertex_buffers(
2102 struct pipe_context *pctx,
2103 unsigned start_slot,
2104 unsigned num_buffers,
2105 const struct pipe_vertex_buffer *buffers)
2106 {
2107 struct panfrost_context *ctx = pan_context(pctx);
2108 assert(num_buffers <= PIPE_MAX_ATTRIBS);
2109
2110 /* XXX: Dirty tracking? etc */
2111 if (buffers) {
2112 size_t sz = sizeof(buffers[0]) * num_buffers;
2113 ctx->vertex_buffers = malloc(sz);
2114 ctx->vertex_buffer_count = num_buffers;
2115 memcpy(ctx->vertex_buffers, buffers, sz);
2116 } else {
2117 if (ctx->vertex_buffers) {
2118 free(ctx->vertex_buffers);
2119 ctx->vertex_buffers = NULL;
2120 }
2121
2122 ctx->vertex_buffer_count = 0;
2123 }
2124 }
2125
2126 static void
2127 panfrost_set_constant_buffer(
2128 struct pipe_context *pctx,
2129 enum pipe_shader_type shader, uint index,
2130 const struct pipe_constant_buffer *buf)
2131 {
2132 struct panfrost_context *ctx = pan_context(pctx);
2133 struct panfrost_constant_buffer *pbuf = &ctx->constant_buffer[shader];
2134
2135 size_t sz = buf ? buf->buffer_size : 0;
2136
2137 /* Free previous buffer */
2138
2139 pbuf->dirty = true;
2140 pbuf->size = sz;
2141
2142 if (pbuf->buffer) {
2143 free(pbuf->buffer);
2144 pbuf->buffer = NULL;
2145 }
2146
2147 /* If unbinding, we're done */
2148
2149 if (!buf)
2150 return;
2151
2152 /* Multiple constant buffers not yet supported */
2153 assert(index == 0);
2154
2155 const uint8_t *cpu;
2156
2157 struct panfrost_resource *rsrc = (struct panfrost_resource *) (buf->buffer);
2158
2159 if (rsrc) {
2160 cpu = rsrc->bo->cpu[0];
2161 } else if (buf->user_buffer) {
2162 cpu = buf->user_buffer;
2163 } else {
2164 printf("No constant buffer?\n");
2165 return;
2166 }
2167
2168 /* Copy the constant buffer into the driver context for later upload */
2169
2170 pbuf->buffer = malloc(sz);
2171 memcpy(pbuf->buffer, cpu + buf->buffer_offset, sz);
2172 }
2173
2174 static void
2175 panfrost_set_stencil_ref(
2176 struct pipe_context *pctx,
2177 const struct pipe_stencil_ref *ref)
2178 {
2179 struct panfrost_context *ctx = pan_context(pctx);
2180 ctx->stencil_ref = *ref;
2181
2182 /* Shader core dirty */
2183 ctx->dirty |= PAN_DIRTY_FS;
2184 }
2185
2186 static struct pipe_sampler_view *
2187 panfrost_create_sampler_view(
2188 struct pipe_context *pctx,
2189 struct pipe_resource *texture,
2190 const struct pipe_sampler_view *template)
2191 {
2192 struct panfrost_sampler_view *so = CALLOC_STRUCT(panfrost_sampler_view);
2193 int bytes_per_pixel = util_format_get_blocksize(texture->format);
2194
2195 pipe_reference(NULL, &texture->reference);
2196
2197 struct panfrost_resource *prsrc = (struct panfrost_resource *) texture;
2198
2199 so->base = *template;
2200 so->base.texture = texture;
2201 so->base.reference.count = 1;
2202 so->base.context = pctx;
2203
2204 /* sampler_views correspond to texture descriptors, minus the texture
2205 * (data) itself. So, we serialise the descriptor here and cache it for
2206 * later. */
2207
2208 /* TODO: Other types of textures */
2209 assert(template->target == PIPE_TEXTURE_2D);
2210
2211 /* Make sure it's something with which we're familiar */
2212 assert(bytes_per_pixel >= 1 && bytes_per_pixel <= 4);
2213
2214 /* TODO: Detect from format better */
2215 const struct util_format_description *desc = util_format_description(prsrc->base.format);
2216
2217 unsigned char user_swizzle[4] = {
2218 template->swizzle_r,
2219 template->swizzle_g,
2220 template->swizzle_b,
2221 template->swizzle_a
2222 };
2223
2224 enum mali_format format = panfrost_find_format(desc);
2225
2226 struct mali_texture_descriptor texture_descriptor = {
2227 .width = MALI_POSITIVE(texture->width0),
2228 .height = MALI_POSITIVE(texture->height0),
2229 .depth = MALI_POSITIVE(texture->depth0),
2230
2231 /* TODO: Decode */
2232 .format = {
2233 .swizzle = panfrost_translate_swizzle_4(desc->swizzle),
2234 .format = format,
2235
2236 .usage1 = 0x0,
2237 .is_not_cubemap = 1,
2238
2239 /* 0x11 - regular texture 2d, uncompressed tiled */
2240 /* 0x12 - regular texture 2d, uncompressed linear */
2241 /* 0x1c - AFBC compressed (internally tiled, probably) texture 2D */
2242
2243 .usage2 = prsrc->bo->has_afbc ? 0x1c : (prsrc->bo->tiled ? 0x11 : 0x12),
2244 },
2245
2246 .swizzle = panfrost_translate_swizzle_4(user_swizzle)
2247 };
2248
2249 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2250 assert (template->u.tex.first_level == 0);
2251
2252 texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2253
2254 so->hw = texture_descriptor;
2255
2256 return (struct pipe_sampler_view *) so;
2257 }
2258
2259 static void
2260 panfrost_set_sampler_views(
2261 struct pipe_context *pctx,
2262 enum pipe_shader_type shader,
2263 unsigned start_slot, unsigned num_views,
2264 struct pipe_sampler_view **views)
2265 {
2266 struct panfrost_context *ctx = pan_context(pctx);
2267
2268 assert(start_slot == 0);
2269
2270 ctx->sampler_view_count[shader] = num_views;
2271 memcpy(ctx->sampler_views[shader], views, num_views * sizeof (void *));
2272
2273 ctx->dirty |= PAN_DIRTY_TEXTURES;
2274 }
2275
2276 static void
2277 panfrost_sampler_view_destroy(
2278 struct pipe_context *pctx,
2279 struct pipe_sampler_view *views)
2280 {
2281 //struct panfrost_context *ctx = pan_context(pctx);
2282
2283 /* TODO */
2284
2285 free(views);
2286 }
2287
2288 static void
2289 panfrost_set_framebuffer_state(struct pipe_context *pctx,
2290 const struct pipe_framebuffer_state *fb)
2291 {
2292 struct panfrost_context *ctx = pan_context(pctx);
2293
2294 /* Flush when switching away from an FBO */
2295
2296 if (!panfrost_is_scanout(ctx)) {
2297 panfrost_flush(pctx, NULL, 0);
2298 }
2299
2300 ctx->pipe_framebuffer.nr_cbufs = fb->nr_cbufs;
2301 ctx->pipe_framebuffer.samples = fb->samples;
2302 ctx->pipe_framebuffer.layers = fb->layers;
2303 ctx->pipe_framebuffer.width = fb->width;
2304 ctx->pipe_framebuffer.height = fb->height;
2305
2306 for (int i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
2307 struct pipe_surface *cb = i < fb->nr_cbufs ? fb->cbufs[i] : NULL;
2308
2309 /* check if changing cbuf */
2310 if (ctx->pipe_framebuffer.cbufs[i] == cb) continue;
2311
2312 if (cb && (i != 0)) {
2313 printf("XXX: Multiple render targets not supported before t7xx!\n");
2314 assert(0);
2315 }
2316
2317 /* assign new */
2318 pipe_surface_reference(&ctx->pipe_framebuffer.cbufs[i], cb);
2319
2320 if (!cb)
2321 continue;
2322
2323 if (require_sfbd)
2324 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx);
2325 else
2326 ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx);
2327
2328 panfrost_attach_vt_framebuffer(ctx);
2329 panfrost_new_frag_framebuffer(ctx);
2330 panfrost_set_scissor(ctx);
2331
2332 struct panfrost_resource *tex = ((struct panfrost_resource *) ctx->pipe_framebuffer.cbufs[i]->texture);
2333 bool is_scanout = panfrost_is_scanout(ctx);
2334
2335 if (!is_scanout && !tex->bo->has_afbc) {
2336 /* The blob is aggressive about enabling AFBC. As such,
2337 * it's pretty much necessary to use it here, since we
2338 * have no traces of non-compressed FBO. */
2339
2340 panfrost_enable_afbc(ctx, tex, false);
2341 }
2342
2343 if (!is_scanout && !tex->bo->has_checksum) {
2344 /* Enable transaction elimination if we can */
2345 panfrost_enable_checksum(ctx, tex);
2346 }
2347 }
2348
2349 {
2350 struct pipe_surface *zb = fb->zsbuf;
2351
2352 if (ctx->pipe_framebuffer.zsbuf != zb) {
2353 pipe_surface_reference(&ctx->pipe_framebuffer.zsbuf, zb);
2354
2355 if (zb) {
2356 /* FBO has depth */
2357
2358 if (require_sfbd)
2359 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx);
2360 else
2361 ctx->vt_framebuffer_mfbd = panfrost_emit_mfbd(ctx);
2362
2363 panfrost_attach_vt_framebuffer(ctx);
2364 panfrost_new_frag_framebuffer(ctx);
2365 panfrost_set_scissor(ctx);
2366
2367 struct panfrost_resource *tex = ((struct panfrost_resource *) ctx->pipe_framebuffer.zsbuf->texture);
2368
2369 if (!tex->bo->has_afbc && !panfrost_is_scanout(ctx))
2370 panfrost_enable_afbc(ctx, tex, true);
2371 }
2372 }
2373 }
2374
2375 /* Force a clear XXX wrong? */
2376 if (ctx->last_clear.color)
2377 panfrost_clear(&ctx->base, ctx->last_clear.buffers, ctx->last_clear.color, ctx->last_clear.depth, ctx->last_clear.stencil);
2378 }
2379
2380 static void *
2381 panfrost_create_blend_state(struct pipe_context *pipe,
2382 const struct pipe_blend_state *blend)
2383 {
2384 struct panfrost_context *ctx = pan_context(pipe);
2385 struct panfrost_blend_state *so = CALLOC_STRUCT(panfrost_blend_state);
2386 so->base = *blend;
2387
2388 /* TODO: The following features are not yet implemented */
2389 assert(!blend->logicop_enable);
2390 assert(!blend->alpha_to_coverage);
2391 assert(!blend->alpha_to_one);
2392
2393 /* Compile the blend state, first as fixed-function if we can */
2394
2395 if (panfrost_make_fixed_blend_mode(&blend->rt[0], &so->equation, blend->rt[0].colormask, &ctx->blend_color))
2396 return so;
2397
2398 /* If we can't, compile a blend shader instead */
2399
2400 panfrost_make_blend_shader(ctx, so, &ctx->blend_color);
2401
2402 return so;
2403 }
2404
2405 static void
2406 panfrost_bind_blend_state(struct pipe_context *pipe,
2407 void *cso)
2408 {
2409 struct panfrost_context *ctx = pan_context(pipe);
2410 struct pipe_blend_state *blend = (struct pipe_blend_state *) cso;
2411 struct panfrost_blend_state *pblend = (struct panfrost_blend_state *) cso;
2412 ctx->blend = pblend;
2413
2414 if (!blend)
2415 return;
2416
2417 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_NO_DITHER, !blend->dither);
2418
2419 /* TODO: Attach color */
2420
2421 /* Shader itself is not dirty, but the shader core is */
2422 ctx->dirty |= PAN_DIRTY_FS;
2423 }
2424
2425 static void
2426 panfrost_delete_blend_state(struct pipe_context *pipe,
2427 void *blend)
2428 {
2429 struct panfrost_blend_state *so = (struct panfrost_blend_state *) blend;
2430
2431 if (so->has_blend_shader) {
2432 printf("Deleting blend state leak blend shaders bytecode\n");
2433 }
2434
2435 free(blend);
2436 }
2437
2438 static void
2439 panfrost_set_blend_color(struct pipe_context *pipe,
2440 const struct pipe_blend_color *blend_color)
2441 {
2442 struct panfrost_context *ctx = pan_context(pipe);
2443
2444 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2445
2446 if (blend_color) {
2447 ctx->blend_color = *blend_color;
2448
2449 /* The blend mode depends on the blend constant color, due to the
2450 * fixed/programmable split. So, we're forced to regenerate the blend
2451 * equation */
2452
2453 /* TODO: Attach color */
2454 }
2455 }
2456
2457 static void *
2458 panfrost_create_depth_stencil_state(struct pipe_context *pipe,
2459 const struct pipe_depth_stencil_alpha_state *depth_stencil)
2460 {
2461 return mem_dup(depth_stencil, sizeof(*depth_stencil));
2462 }
2463
2464 static void
2465 panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
2466 void *cso)
2467 {
2468 struct panfrost_context *ctx = pan_context(pipe);
2469 struct pipe_depth_stencil_alpha_state *depth_stencil = cso;
2470 ctx->depth_stencil = depth_stencil;
2471
2472 if (!depth_stencil)
2473 return;
2474
2475 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2476 * emulated in the fragment shader */
2477
2478 if (depth_stencil->alpha.enabled) {
2479 /* We need to trigger a new shader (maybe) */
2480 ctx->base.bind_fs_state(&ctx->base, ctx->fs);
2481 }
2482
2483 /* Stencil state */
2484 SET_BIT(ctx->fragment_shader_core.unknown2_4, MALI_STENCIL_TEST, depth_stencil->stencil[0].enabled); /* XXX: which one? */
2485
2486 panfrost_make_stencil_state(&depth_stencil->stencil[0], &ctx->fragment_shader_core.stencil_front);
2487 ctx->fragment_shader_core.stencil_mask_front = depth_stencil->stencil[0].writemask;
2488
2489 panfrost_make_stencil_state(&depth_stencil->stencil[1], &ctx->fragment_shader_core.stencil_back);
2490 ctx->fragment_shader_core.stencil_mask_back = depth_stencil->stencil[1].writemask;
2491
2492 /* Depth state (TODO: Refactor) */
2493 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_DEPTH_TEST, depth_stencil->depth.enabled);
2494
2495 int func = depth_stencil->depth.enabled ? depth_stencil->depth.func : PIPE_FUNC_ALWAYS;
2496
2497 ctx->fragment_shader_core.unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
2498 ctx->fragment_shader_core.unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func));
2499
2500 /* Bounds test not implemented */
2501 assert(!depth_stencil->depth.bounds_test);
2502
2503 ctx->dirty |= PAN_DIRTY_FS;
2504 }
2505
2506 static void
2507 panfrost_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
2508 {
2509 free( depth );
2510 }
2511
2512 static void
2513 panfrost_set_sample_mask(struct pipe_context *pipe,
2514 unsigned sample_mask)
2515 {
2516 }
2517
2518 static void
2519 panfrost_set_clip_state(struct pipe_context *pipe,
2520 const struct pipe_clip_state *clip)
2521 {
2522 //struct panfrost_context *panfrost = pan_context(pipe);
2523 }
2524
2525 static void
2526 panfrost_set_viewport_states(struct pipe_context *pipe,
2527 unsigned start_slot,
2528 unsigned num_viewports,
2529 const struct pipe_viewport_state *viewports)
2530 {
2531 struct panfrost_context *ctx = pan_context(pipe);
2532
2533 assert(start_slot == 0);
2534 assert(num_viewports == 1);
2535
2536 ctx->pipe_viewport = *viewports;
2537
2538 #if 0
2539 /* TODO: What if not centered? */
2540 float w = abs(viewports->scale[0]) * 2.0;
2541 float h = abs(viewports->scale[1]) * 2.0;
2542
2543 ctx->viewport.viewport1[0] = MALI_POSITIVE((int) w);
2544 ctx->viewport.viewport1[1] = MALI_POSITIVE((int) h);
2545 #endif
2546 }
2547
2548 static void
2549 panfrost_set_scissor_states(struct pipe_context *pipe,
2550 unsigned start_slot,
2551 unsigned num_scissors,
2552 const struct pipe_scissor_state *scissors)
2553 {
2554 struct panfrost_context *ctx = pan_context(pipe);
2555
2556 assert(start_slot == 0);
2557 assert(num_scissors == 1);
2558
2559 ctx->scissor = *scissors;
2560
2561 panfrost_set_scissor(ctx);
2562 }
2563
2564 static void
2565 panfrost_set_polygon_stipple(struct pipe_context *pipe,
2566 const struct pipe_poly_stipple *stipple)
2567 {
2568 //struct panfrost_context *panfrost = pan_context(pipe);
2569 }
2570
2571 static void
2572 panfrost_set_active_query_state(struct pipe_context *pipe,
2573 boolean enable)
2574 {
2575 //struct panfrost_context *panfrost = pan_context(pipe);
2576 }
2577
2578 static void
2579 panfrost_destroy(struct pipe_context *pipe)
2580 {
2581 struct panfrost_context *panfrost = pan_context(pipe);
2582
2583 if (panfrost->blitter)
2584 util_blitter_destroy(panfrost->blitter);
2585 }
2586
2587 static struct pipe_query *
2588 panfrost_create_query(struct pipe_context *pipe,
2589 unsigned type,
2590 unsigned index)
2591 {
2592 struct panfrost_query *q = CALLOC_STRUCT(panfrost_query);
2593
2594 q->type = type;
2595 q->index = index;
2596
2597 return (struct pipe_query *) q;
2598 }
2599
2600 static void
2601 panfrost_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
2602 {
2603 FREE(q);
2604 }
2605
2606 static boolean
2607 panfrost_begin_query(struct pipe_context *pipe, struct pipe_query *q)
2608 {
2609 struct panfrost_context *ctx = pan_context(pipe);
2610 struct panfrost_query *query = (struct panfrost_query *) q;
2611
2612 switch (query->type) {
2613 case PIPE_QUERY_OCCLUSION_COUNTER:
2614 case PIPE_QUERY_OCCLUSION_PREDICATE:
2615 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
2616 {
2617 /* Allocate a word for the query results to be stored */
2618 query->transfer = panfrost_allocate_chunk(ctx, sizeof(unsigned), HEAP_DESCRIPTOR);
2619
2620 ctx->occlusion_query = query;
2621
2622 break;
2623 }
2624
2625 default:
2626 fprintf(stderr, "Skipping query %d\n", query->type);
2627 break;
2628 }
2629
2630 return true;
2631 }
2632
2633 static bool
2634 panfrost_end_query(struct pipe_context *pipe, struct pipe_query *q)
2635 {
2636 struct panfrost_context *ctx = pan_context(pipe);
2637 ctx->occlusion_query = NULL;
2638 return true;
2639 }
2640
2641 static boolean
2642 panfrost_get_query_result(struct pipe_context *pipe,
2643 struct pipe_query *q,
2644 boolean wait,
2645 union pipe_query_result *vresult)
2646 {
2647 /* STUB */
2648 struct panfrost_query *query = (struct panfrost_query *) q;
2649
2650 /* We need to flush out the jobs to actually run the counter, TODO
2651 * check wait, TODO wallpaper after if needed */
2652
2653 panfrost_flush(pipe, NULL, PIPE_FLUSH_END_OF_FRAME);
2654
2655 switch (query->type) {
2656 case PIPE_QUERY_OCCLUSION_COUNTER:
2657 case PIPE_QUERY_OCCLUSION_PREDICATE:
2658 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
2659 /* Read back the query results */
2660 unsigned *result = (unsigned *) query->transfer.cpu;
2661 unsigned passed = *result;
2662
2663 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) {
2664 vresult->u64 = passed;
2665 } else {
2666 vresult->b = !!passed;
2667 }
2668
2669 break;
2670 }
2671 default:
2672 fprintf(stderr, "Skipped query get %d\n", query->type);
2673 break;
2674 }
2675
2676 return true;
2677 }
2678
2679 static void
2680 panfrost_setup_hardware(struct panfrost_context *ctx)
2681 {
2682 struct pipe_context *gallium = (struct pipe_context *) ctx;
2683 struct panfrost_screen *screen = pan_screen(gallium->screen);
2684
2685 for (int i = 0; i < ARRAY_SIZE(ctx->transient_pools); ++i) {
2686 /* Allocate the beginning of the transient pool */
2687 int entry_size = (1 << 22); /* 4MB */
2688
2689 ctx->transient_pools[i].entry_size = entry_size;
2690 ctx->transient_pools[i].entry_count = 1;
2691
2692 ctx->transient_pools[i].entries[0] = (struct panfrost_memory_entry *) pb_slab_alloc(&screen->slabs, entry_size, HEAP_TRANSIENT);
2693 }
2694
2695 screen->driver->allocate_slab(screen, &ctx->scratchpad, 64, false, 0, 0, 0);
2696 screen->driver->allocate_slab(screen, &ctx->varying_mem, 16384, false, 0, 0, 0);
2697 screen->driver->allocate_slab(screen, &ctx->shaders, 4096, true, PAN_ALLOCATE_EXECUTE, 0, 0);
2698 screen->driver->allocate_slab(screen, &ctx->tiler_heap, 32768, false, PAN_ALLOCATE_GROWABLE, 1, 128);
2699 screen->driver->allocate_slab(screen, &ctx->misc_0, 128, false, PAN_ALLOCATE_GROWABLE, 1, 128);
2700
2701 }
2702
2703 /* New context creation, which also does hardware initialisation since I don't
2704 * know the better way to structure this :smirk: */
2705
2706 struct pipe_context *
2707 panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags)
2708 {
2709 struct panfrost_context *ctx = CALLOC_STRUCT(panfrost_context);
2710 memset(ctx, 0, sizeof(*ctx));
2711 struct pipe_context *gallium = (struct pipe_context *) ctx;
2712
2713 gallium->screen = screen;
2714
2715 gallium->destroy = panfrost_destroy;
2716
2717 gallium->set_framebuffer_state = panfrost_set_framebuffer_state;
2718
2719 gallium->flush = panfrost_flush;
2720 gallium->clear = panfrost_clear;
2721 gallium->draw_vbo = panfrost_draw_vbo;
2722
2723 gallium->set_vertex_buffers = panfrost_set_vertex_buffers;
2724 gallium->set_constant_buffer = panfrost_set_constant_buffer;
2725
2726 gallium->set_stencil_ref = panfrost_set_stencil_ref;
2727
2728 gallium->create_sampler_view = panfrost_create_sampler_view;
2729 gallium->set_sampler_views = panfrost_set_sampler_views;
2730 gallium->sampler_view_destroy = panfrost_sampler_view_destroy;
2731
2732 gallium->create_rasterizer_state = panfrost_create_rasterizer_state;
2733 gallium->bind_rasterizer_state = panfrost_bind_rasterizer_state;
2734 gallium->delete_rasterizer_state = panfrost_generic_cso_delete;
2735
2736 gallium->create_vertex_elements_state = panfrost_create_vertex_elements_state;
2737 gallium->bind_vertex_elements_state = panfrost_bind_vertex_elements_state;
2738 gallium->delete_vertex_elements_state = panfrost_delete_vertex_elements_state;
2739
2740 gallium->create_fs_state = panfrost_create_shader_state;
2741 gallium->delete_fs_state = panfrost_delete_shader_state;
2742 gallium->bind_fs_state = panfrost_bind_fs_state;
2743
2744 gallium->create_vs_state = panfrost_create_shader_state;
2745 gallium->delete_vs_state = panfrost_delete_shader_state;
2746 gallium->bind_vs_state = panfrost_bind_vs_state;
2747
2748 gallium->create_sampler_state = panfrost_create_sampler_state;
2749 gallium->delete_sampler_state = panfrost_generic_cso_delete;
2750 gallium->bind_sampler_states = panfrost_bind_sampler_states;
2751
2752 gallium->create_blend_state = panfrost_create_blend_state;
2753 gallium->bind_blend_state = panfrost_bind_blend_state;
2754 gallium->delete_blend_state = panfrost_delete_blend_state;
2755
2756 gallium->set_blend_color = panfrost_set_blend_color;
2757
2758 gallium->create_depth_stencil_alpha_state = panfrost_create_depth_stencil_state;
2759 gallium->bind_depth_stencil_alpha_state = panfrost_bind_depth_stencil_state;
2760 gallium->delete_depth_stencil_alpha_state = panfrost_delete_depth_stencil_state;
2761
2762 gallium->set_sample_mask = panfrost_set_sample_mask;
2763
2764 gallium->set_clip_state = panfrost_set_clip_state;
2765 gallium->set_viewport_states = panfrost_set_viewport_states;
2766 gallium->set_scissor_states = panfrost_set_scissor_states;
2767 gallium->set_polygon_stipple = panfrost_set_polygon_stipple;
2768 gallium->set_active_query_state = panfrost_set_active_query_state;
2769
2770 gallium->create_query = panfrost_create_query;
2771 gallium->destroy_query = panfrost_destroy_query;
2772 gallium->begin_query = panfrost_begin_query;
2773 gallium->end_query = panfrost_end_query;
2774 gallium->get_query_result = panfrost_get_query_result;
2775
2776 panfrost_resource_context_init(gallium);
2777
2778 panfrost_setup_hardware(ctx);
2779
2780 /* XXX: leaks */
2781 gallium->stream_uploader = u_upload_create_default(gallium);
2782 gallium->const_uploader = gallium->stream_uploader;
2783 assert(gallium->stream_uploader);
2784
2785 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2786 ctx->draw_modes = (1 << (PIPE_PRIM_POLYGON + 1)) - 1;
2787
2788 ctx->primconvert = util_primconvert_create(gallium, ctx->draw_modes);
2789
2790 ctx->blitter = util_blitter_create(gallium);
2791 assert(ctx->blitter);
2792
2793 /* Prepare for render! */
2794
2795 panfrost_emit_vertex_payload(ctx);
2796 panfrost_emit_tiler_payload(ctx);
2797 panfrost_invalidate_frame(ctx);
2798 panfrost_viewport(ctx, 0.0, 1.0, 0, 0, ctx->pipe_framebuffer.width, ctx->pipe_framebuffer.height);
2799 panfrost_default_shader_backend(ctx);
2800 panfrost_generate_space_filler_indices();
2801
2802 return gallium;
2803 }