2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_format.h"
31 #include "util/macros.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_memory.h"
36 #include "util/u_vbuf.h"
37 #include "util/half_float.h"
38 #include "util/u_helpers.h"
39 #include "util/u_format.h"
40 #include "util/u_prim_restart.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_from_mesa.h"
44 #include "util/u_math.h"
46 #include "pan_screen.h"
47 #include "pan_blending.h"
48 #include "pan_blend_shaders.h"
50 #include "pan_tiler.h"
52 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
55 /* Framebuffer descriptor */
57 static struct midgard_tiler_descriptor
58 panfrost_emit_midg_tiler(
59 struct panfrost_context
*ctx
,
62 unsigned vertex_count
)
64 struct midgard_tiler_descriptor t
= {};
67 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
69 /* Compute the polygon header size and use that to offset the body */
71 unsigned header_size
= panfrost_tiler_header_size(
72 width
, height
, t
.hierarchy_mask
);
74 unsigned body_size
= panfrost_tiler_body_size(
75 width
, height
, t
.hierarchy_mask
);
79 if (t
.hierarchy_mask
) {
80 assert(ctx
->tiler_polygon_list
.bo
->size
>= (header_size
+ body_size
));
82 /* Specify allocated tiler structures */
83 t
.polygon_list
= ctx
->tiler_polygon_list
.bo
->gpu
;
85 /* Allow the entire tiler heap */
86 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
88 ctx
->tiler_heap
.bo
->gpu
+ ctx
->tiler_heap
.bo
->size
;
90 /* The tiler is disabled, so don't allow the tiler heap */
91 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
92 t
.heap_end
= t
.heap_start
;
94 /* Use a dummy polygon list */
95 t
.polygon_list
= ctx
->tiler_dummy
.bo
->gpu
;
97 /* Also, set a "tiler disabled?" flag? */
98 t
.hierarchy_mask
|= 0x1000;
101 t
.polygon_list_body
=
102 t
.polygon_list
+ header_size
;
104 t
.polygon_list_size
=
105 header_size
+ body_size
;
110 struct mali_single_framebuffer
111 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
113 unsigned width
= ctx
->pipe_framebuffer
.width
;
114 unsigned height
= ctx
->pipe_framebuffer
.height
;
116 struct mali_single_framebuffer framebuffer
= {
117 .width
= MALI_POSITIVE(width
),
118 .height
= MALI_POSITIVE(height
),
120 .format
= 0x30000000,
121 .clear_flags
= 0x1000,
122 .unknown_address_0
= ctx
->scratchpad
.bo
->gpu
,
123 .tiler
= panfrost_emit_midg_tiler(ctx
,
124 width
, height
, vertex_count
),
130 struct bifrost_framebuffer
131 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
133 unsigned width
= ctx
->pipe_framebuffer
.width
;
134 unsigned height
= ctx
->pipe_framebuffer
.height
;
136 struct bifrost_framebuffer framebuffer
= {
137 .unk0
= 0x1e5, /* 1e4 if no spill */
138 .width1
= MALI_POSITIVE(width
),
139 .height1
= MALI_POSITIVE(height
),
140 .width2
= MALI_POSITIVE(width
),
141 .height2
= MALI_POSITIVE(height
),
145 .rt_count_1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.nr_cbufs
),
150 .scratchpad
= ctx
->scratchpad
.bo
->gpu
,
151 .tiler
= panfrost_emit_midg_tiler(ctx
,
152 width
, height
, vertex_count
)
158 /* Are we currently rendering to the screen (rather than an FBO)? */
161 panfrost_is_scanout(struct panfrost_context
*ctx
)
163 /* If there is no color buffer, it's an FBO */
164 if (ctx
->pipe_framebuffer
.nr_cbufs
!= 1)
167 /* If we're too early that no framebuffer was sent, it's scanout */
168 if (!ctx
->pipe_framebuffer
.cbufs
[0])
171 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
172 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
173 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
178 struct pipe_context
*pipe
,
180 const union pipe_color_union
*color
,
181 double depth
, unsigned stencil
)
183 struct panfrost_context
*ctx
= pan_context(pipe
);
184 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
186 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
190 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
192 struct bifrost_framebuffer mfbd
= panfrost_emit_mfbd(ctx
, ~0);
194 return panfrost_upload_transient(ctx
, &mfbd
, sizeof(mfbd
)) | MALI_MFBD
;
198 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
200 struct mali_single_framebuffer sfbd
= panfrost_emit_sfbd(ctx
, ~0);
202 return panfrost_upload_transient(ctx
, &sfbd
, sizeof(sfbd
)) | MALI_SFBD
;
206 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
, bool skippable
)
208 /* Skip the attach if we can */
210 if (skippable
&& ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
) {
211 assert(ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
215 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
216 mali_ptr framebuffer
= screen
->require_sfbd
?
217 panfrost_attach_vt_sfbd(ctx
) :
218 panfrost_attach_vt_mfbd(ctx
);
220 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
221 ctx
->payloads
[i
].postfix
.framebuffer
= framebuffer
;
224 /* Reset per-frame context, called on context initialisation as well as after
225 * flushing a frame */
228 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
230 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
231 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
234 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
237 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
240 /* In practice, every field of these payloads should be configurable
241 * arbitrarily, which means these functions are basically catch-all's for
242 * as-of-yet unwavering unknowns */
245 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
247 /* 0x2 bit clear on 32-bit T6XX */
249 struct midgard_payload_vertex_tiler payload
= {
250 .gl_enables
= 0x4 | 0x2,
253 /* Vertex and compute are closely coupled, so share a payload */
255 memcpy(&ctx
->payloads
[PIPE_SHADER_VERTEX
], &payload
, sizeof(payload
));
256 memcpy(&ctx
->payloads
[PIPE_SHADER_COMPUTE
], &payload
, sizeof(payload
));
260 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
262 struct midgard_payload_vertex_tiler payload
= {
264 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
268 memcpy(&ctx
->payloads
[PIPE_SHADER_FRAGMENT
], &payload
, sizeof(payload
));
272 translate_tex_wrap(enum pipe_tex_wrap w
)
275 case PIPE_TEX_WRAP_REPEAT
:
276 return MALI_WRAP_REPEAT
;
278 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
279 return MALI_WRAP_CLAMP_TO_EDGE
;
281 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
282 return MALI_WRAP_CLAMP_TO_BORDER
;
284 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
285 return MALI_WRAP_MIRRORED_REPEAT
;
288 unreachable("Invalid wrap");
293 panfrost_translate_compare_func(enum pipe_compare_func in
)
296 case PIPE_FUNC_NEVER
:
297 return MALI_FUNC_NEVER
;
300 return MALI_FUNC_LESS
;
302 case PIPE_FUNC_EQUAL
:
303 return MALI_FUNC_EQUAL
;
305 case PIPE_FUNC_LEQUAL
:
306 return MALI_FUNC_LEQUAL
;
308 case PIPE_FUNC_GREATER
:
309 return MALI_FUNC_GREATER
;
311 case PIPE_FUNC_NOTEQUAL
:
312 return MALI_FUNC_NOTEQUAL
;
314 case PIPE_FUNC_GEQUAL
:
315 return MALI_FUNC_GEQUAL
;
317 case PIPE_FUNC_ALWAYS
:
318 return MALI_FUNC_ALWAYS
;
321 unreachable("Invalid func");
326 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
329 case PIPE_FUNC_NEVER
:
330 return MALI_ALT_FUNC_NEVER
;
333 return MALI_ALT_FUNC_LESS
;
335 case PIPE_FUNC_EQUAL
:
336 return MALI_ALT_FUNC_EQUAL
;
338 case PIPE_FUNC_LEQUAL
:
339 return MALI_ALT_FUNC_LEQUAL
;
341 case PIPE_FUNC_GREATER
:
342 return MALI_ALT_FUNC_GREATER
;
344 case PIPE_FUNC_NOTEQUAL
:
345 return MALI_ALT_FUNC_NOTEQUAL
;
347 case PIPE_FUNC_GEQUAL
:
348 return MALI_ALT_FUNC_GEQUAL
;
350 case PIPE_FUNC_ALWAYS
:
351 return MALI_ALT_FUNC_ALWAYS
;
354 unreachable("Invalid alt func");
359 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
362 case PIPE_STENCIL_OP_KEEP
:
363 return MALI_STENCIL_KEEP
;
365 case PIPE_STENCIL_OP_ZERO
:
366 return MALI_STENCIL_ZERO
;
368 case PIPE_STENCIL_OP_REPLACE
:
369 return MALI_STENCIL_REPLACE
;
371 case PIPE_STENCIL_OP_INCR
:
372 return MALI_STENCIL_INCR
;
374 case PIPE_STENCIL_OP_DECR
:
375 return MALI_STENCIL_DECR
;
377 case PIPE_STENCIL_OP_INCR_WRAP
:
378 return MALI_STENCIL_INCR_WRAP
;
380 case PIPE_STENCIL_OP_DECR_WRAP
:
381 return MALI_STENCIL_DECR_WRAP
;
383 case PIPE_STENCIL_OP_INVERT
:
384 return MALI_STENCIL_INVERT
;
387 unreachable("Invalid stencil op");
392 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
394 out
->ref
= 0; /* Gallium gets it from elsewhere */
396 out
->mask
= in
->valuemask
;
397 out
->func
= panfrost_translate_compare_func(in
->func
);
398 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
399 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
400 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
404 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
406 struct mali_shader_meta shader
= {
407 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
409 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
410 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
413 /* unknown2_4 has 0x10 bit set on T6XX. We don't know why this is
414 * required (independent of 32-bit/64-bit descriptors), or why it's not
415 * used on later GPU revisions. Otherwise, all shader jobs fault on
416 * these earlier chips (perhaps this is a chicken bit of some kind).
417 * More investigation is needed. */
420 shader
.unknown2_4
|= 0x10;
423 struct pipe_stencil_state default_stencil
= {
425 .func
= PIPE_FUNC_ALWAYS
,
426 .fail_op
= MALI_STENCIL_KEEP
,
427 .zfail_op
= MALI_STENCIL_KEEP
,
428 .zpass_op
= MALI_STENCIL_KEEP
,
433 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
434 shader
.stencil_mask_front
= default_stencil
.writemask
;
436 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
437 shader
.stencil_mask_back
= default_stencil
.writemask
;
439 if (default_stencil
.enabled
)
440 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
442 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
445 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
446 * graphics command stream. It should be called once per draw, accordding to
447 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
448 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
451 struct panfrost_transfer
452 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
454 struct mali_job_descriptor_header job
= {
455 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
456 .job_descriptor_size
= 1,
459 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payloads
[PIPE_SHADER_FRAGMENT
] : &ctx
->payloads
[PIPE_SHADER_VERTEX
];
461 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
462 memcpy(transfer
.cpu
, &job
, sizeof(job
));
463 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
468 panfrost_emit_varyings(
469 struct panfrost_context
*ctx
,
470 union mali_attr
*slot
,
474 /* Fill out the descriptor */
475 slot
->stride
= stride
;
476 slot
->size
= stride
* count
;
477 slot
->shift
= slot
->extra_flags
= 0;
479 struct panfrost_transfer transfer
=
480 panfrost_allocate_transient(ctx
, slot
->size
);
482 slot
->elements
= transfer
.gpu
| MALI_ATTR_LINEAR
;
488 panfrost_emit_point_coord(union mali_attr
*slot
)
490 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
491 slot
->stride
= slot
->size
= slot
->shift
= slot
->extra_flags
= 0;
495 panfrost_emit_front_face(union mali_attr
*slot
)
497 slot
->elements
= MALI_VARYING_FRONT_FACING
| MALI_ATTR_INTERNAL
;
501 panfrost_emit_varying_descriptor(
502 struct panfrost_context
*ctx
,
503 unsigned vertex_count
)
505 /* Load the shaders */
507 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
508 struct panfrost_shader_state
*fs
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
509 unsigned int num_gen_varyings
= 0;
511 /* Allocate the varying descriptor */
513 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
514 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
516 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
520 * Assign ->src_offset now that we know about all the general purpose
521 * varyings that will be used by the fragment and vertex shaders.
523 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
525 * General purpose varyings have ->index set to 0, skip other
528 if (vs
->varyings
[i
].index
)
531 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
534 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
537 /* If we have a point sprite replacement, handle that here. We
538 * have to translate location first. TODO: Flip y in shader.
539 * We're already keying ... just time crunch .. */
541 unsigned loc
= fs
->varyings_loc
[i
];
543 (loc
>= VARYING_SLOT_VAR0
) ? (loc
- VARYING_SLOT_VAR0
) :
544 (loc
== VARYING_SLOT_PNTC
) ? 8 :
547 if (~pnt_loc
&& fs
->point_sprite_mask
& (1 << pnt_loc
)) {
548 /* gl_PointCoord index by convention */
549 fs
->varyings
[i
].index
= 3;
550 fs
->reads_point_coord
= true;
552 /* Swizzle out the z/w to 0/1 */
553 fs
->varyings
[i
].format
= MALI_RG16F
;
554 fs
->varyings
[i
].swizzle
=
555 panfrost_get_default_swizzle(2);
560 if (fs
->varyings
[i
].index
)
564 * Re-use the VS general purpose varying pos if it exists,
565 * create a new one otherwise.
567 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
568 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
572 if (j
< vs
->tripipe
->varying_count
)
573 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
575 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
578 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
579 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
581 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.varying_meta
= trans
.gpu
;
582 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.varying_meta
= trans
.gpu
+ vs_size
;
584 /* Buffer indices must be in this order per our convention */
585 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
588 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
591 /* fp32 vec4 gl_Position */
592 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.position_varying
=
593 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
594 sizeof(float) * 4, vertex_count
);
597 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
598 /* fp16 vec1 gl_PointSize */
599 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.pointer
=
600 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
602 } else if (fs
->reads_face
) {
603 /* Dummy to advance index */
607 if (fs
->reads_point_coord
) {
608 /* Special descriptor */
609 panfrost_emit_point_coord(&varyings
[idx
++]);
610 } else if (fs
->reads_face
) {
614 if (fs
->reads_face
) {
615 panfrost_emit_front_face(&varyings
[idx
++]);
618 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
619 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.varyings
= varyings_p
;
620 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.varyings
= varyings_p
;
624 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
626 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
627 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
629 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
633 panfrost_writes_point_size(struct panfrost_context
*ctx
)
635 assert(ctx
->shader
[PIPE_SHADER_VERTEX
]);
636 struct panfrost_shader_state
*vs
= &ctx
->shader
[PIPE_SHADER_VERTEX
]->variants
[ctx
->shader
[PIPE_SHADER_VERTEX
]->active_variant
];
638 return vs
->writes_point_size
&& ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
== MALI_POINTS
;
641 /* Stage the attribute descriptors so we can adjust src_offset
642 * to let BOs align nicely */
645 panfrost_stage_attributes(struct panfrost_context
*ctx
)
647 struct panfrost_vertex_state
*so
= ctx
->vertex
;
649 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
650 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
651 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
653 /* Copy as-is for the first pass */
654 memcpy(target
, so
->hw
, sz
);
656 /* Fixup offsets for the second pass. Recall that the hardware
657 * calculates attribute addresses as:
659 * addr = base + (stride * vtx) + src_offset;
661 * However, on Mali, base must be aligned to 64-bytes, so we
664 * base' = base & ~63 = base - (base & 63)
666 * To compensate when using base' (see emit_vertex_data), we have
667 * to adjust src_offset by the masked off piece:
669 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
670 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
671 * = base + (stride * vtx) + src_offset
677 unsigned start
= ctx
->payloads
[PIPE_SHADER_VERTEX
].draw_start
;
679 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
680 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
681 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
682 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
684 /* Adjust by the masked off bits of the offset */
685 target
[i
].src_offset
+= (addr
& 63);
687 /* Also, somewhat obscurely per-instance data needs to be
688 * offset in response to a delayed start in an indexed draw */
690 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
691 target
[i
].src_offset
-= buf
->stride
* start
;
697 ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.attribute_meta
= transfer
.gpu
;
701 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
703 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
705 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
708 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
709 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
711 struct panfrost_transfer transfer
=
712 panfrost_allocate_transient(ctx
, transfer_size
);
714 struct mali_sampler_descriptor
*desc
=
715 (struct mali_sampler_descriptor
*) transfer
.cpu
;
717 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
718 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
720 upload
= transfer
.gpu
;
723 ctx
->payloads
[t
].postfix
.sampler_descriptor
= upload
;
728 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
, bool manual_stride
)
730 /* TODO: other linear depth textures */
731 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
733 unsigned usage2_layout
= 0x10;
735 switch (rsrc
->layout
) {
737 usage2_layout
|= 0x8 | 0x4;
740 usage2_layout
|= 0x1;
743 usage2_layout
|= is_depth
? 0x1 : 0x2;
751 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
753 return usage2_layout
;
758 struct panfrost_context
*ctx
,
759 struct panfrost_sampler_view
*view
)
764 struct pipe_sampler_view
*pview
= &view
->base
;
765 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
767 /* Do we interleave an explicit stride with every element? */
769 bool has_manual_stride
= view
->manual_stride
;
771 /* For easy access */
773 assert(pview
->target
!= PIPE_BUFFER
);
774 unsigned first_level
= pview
->u
.tex
.first_level
;
775 unsigned last_level
= pview
->u
.tex
.last_level
;
776 unsigned first_layer
= pview
->u
.tex
.first_layer
;
777 unsigned last_layer
= pview
->u
.tex
.last_layer
;
779 /* Lower-bit is set when sampling from colour AFBC */
780 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
781 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
782 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
784 /* Add the BO to the job so it's retained until the job is done. */
785 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
786 panfrost_job_add_bo(job
, rsrc
->bo
);
788 /* Add the usage flags in, since they can change across the CSO
789 * lifetime due to layout switches */
791 view
->hw
.format
.usage2
= panfrost_layout_for_texture(rsrc
, has_manual_stride
);
793 /* Inject the addresses in, interleaving mip levels, cube faces, and
794 * strides in that order */
798 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
799 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
801 view
->hw
.payload
[idx
++] =
802 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
804 if (has_manual_stride
) {
805 view
->hw
.payload
[idx
++] =
806 rsrc
->slices
[l
].stride
;
811 return panfrost_upload_transient(ctx
, &view
->hw
,
812 sizeof(struct mali_texture_descriptor
));
816 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
818 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
819 mali_ptr trampoline
= 0;
821 if (ctx
->sampler_view_count
[t
]) {
822 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
824 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
826 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
828 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
831 ctx
->payloads
[t
].postfix
.texture_trampoline
= trampoline
;
835 struct sysval_uniform
{
843 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
844 struct sysval_uniform
*uniform
)
846 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
848 uniform
->f
[0] = vp
->scale
[0];
849 uniform
->f
[1] = vp
->scale
[1];
850 uniform
->f
[2] = vp
->scale
[2];
853 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
854 struct sysval_uniform
*uniform
)
856 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
858 uniform
->f
[0] = vp
->translate
[0];
859 uniform
->f
[1] = vp
->translate
[1];
860 uniform
->f
[2] = vp
->translate
[2];
863 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
864 enum pipe_shader_type st
,
865 unsigned int sysvalid
,
866 struct sysval_uniform
*uniform
)
868 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
869 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
870 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
871 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
874 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
877 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
878 tex
->u
.tex
.first_level
);
881 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
882 tex
->u
.tex
.first_level
);
885 uniform
->i
[dim
] = tex
->texture
->array_size
;
888 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
889 struct panfrost_shader_state
*ss
,
890 enum pipe_shader_type st
)
892 struct sysval_uniform
*uniforms
= (void *)buf
;
894 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
895 int sysval
= ss
->sysval
[i
];
897 switch (PAN_SYSVAL_TYPE(sysval
)) {
898 case PAN_SYSVAL_VIEWPORT_SCALE
:
899 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
901 case PAN_SYSVAL_VIEWPORT_OFFSET
:
902 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
904 case PAN_SYSVAL_TEXTURE_SIZE
:
905 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
915 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
917 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
918 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
921 return rsrc
->bo
->cpu
;
922 else if (cb
->user_buffer
)
923 return cb
->user_buffer
;
925 unreachable("No constant buffer");
929 panfrost_map_constant_buffer_gpu(
930 struct panfrost_context
*ctx
,
931 struct panfrost_constant_buffer
*buf
,
934 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
935 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
938 return rsrc
->bo
->gpu
;
939 else if (cb
->user_buffer
)
940 return panfrost_upload_transient(ctx
, cb
->user_buffer
, cb
->buffer_size
);
942 unreachable("No constant buffer");
945 /* Compute number of UBOs active (more specifically, compute the highest UBO
946 * number addressable -- if there are gaps, include them in the count anyway).
947 * We always include UBO #0 in the count, since we *need* uniforms enabled for
951 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
953 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
954 return 32 - __builtin_clz(mask
);
957 /* Fixes up a shader state with current state, returning a GPU address to the
961 panfrost_patch_shader_state(
962 struct panfrost_context
*ctx
,
963 struct panfrost_shader_state
*ss
,
964 enum pipe_shader_type stage
,
967 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
968 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
970 ss
->tripipe
->midgard1
.flags
= 0x220;
972 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
973 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
975 /* We can't reuse over frames; that's not safe. The descriptor must be
976 * transient uploaded */
979 return panfrost_upload_transient(ctx
,
981 sizeof(struct mali_shader_meta
));
984 /* If we don't need an upload, don't bother */
990 panfrost_patch_shader_state_compute(
991 struct panfrost_context
*ctx
,
992 enum pipe_shader_type stage
,
995 struct panfrost_shader_variants
*all
= ctx
->shader
[stage
];
998 ctx
->payloads
[stage
].postfix
._shader_upper
= 0;
1002 struct panfrost_shader_state
*s
= &all
->variants
[all
->active_variant
];
1004 ctx
->payloads
[stage
].postfix
._shader_upper
=
1005 panfrost_patch_shader_state(ctx
, s
, stage
, should_upload
) >> 4;
1008 /* Go through dirty flags and actualise them in the cmdstream. */
1011 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1013 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1014 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
1016 panfrost_attach_vt_framebuffer(ctx
, true);
1018 if (with_vertex_data
) {
1019 panfrost_emit_vertex_data(job
);
1021 /* Varyings emitted for -all- geometry */
1022 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
1023 panfrost_emit_varying_descriptor(ctx
, total_count
);
1026 bool msaa
= ctx
->rasterizer
->base
.multisample
;
1028 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1029 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1031 /* TODO: Sample size */
1032 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1033 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1036 panfrost_job_set_requirements(ctx
, job
);
1038 if (ctx
->occlusion_query
) {
1039 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1040 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1043 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_VERTEX
, true);
1044 panfrost_patch_shader_state_compute(ctx
, PIPE_SHADER_COMPUTE
, true);
1046 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1047 /* Check if we need to link the gl_PointSize varying */
1048 if (!panfrost_writes_point_size(ctx
)) {
1049 /* If the size is constant, write it out. Otherwise,
1050 * don't touch primitive_size (since we would clobber
1051 * the pointer there) */
1053 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1057 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1058 if (ctx
->shader
[PIPE_SHADER_FRAGMENT
])
1059 ctx
->dirty
|= PAN_DIRTY_FS
;
1061 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1062 assert(ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1063 struct panfrost_shader_state
*variant
= &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
];
1065 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
1067 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1070 COPY(attribute_count
);
1071 COPY(varying_count
);
1072 COPY(texture_count
);
1073 COPY(sampler_count
);
1074 COPY(sampler_count
);
1075 COPY(midgard1
.uniform_count
);
1076 COPY(midgard1
.uniform_buffer_count
);
1077 COPY(midgard1
.work_count
);
1078 COPY(midgard1
.flags
);
1079 COPY(midgard1
.unknown2
);
1083 /* Get blending setup */
1084 struct panfrost_blend_final blend
=
1085 panfrost_get_blend_for_context(ctx
, 0);
1087 /* If there is a blend shader, work registers are shared */
1089 if (blend
.is_shader
)
1090 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1092 /* Set late due to depending on render state */
1093 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
1095 /* Depending on whether it's legal to in the given shader, we
1096 * try to enable early-z testing (or forward-pixel kill?) */
1098 if (!variant
->can_discard
)
1099 flags
|= MALI_EARLY_Z
;
1101 /* Any time texturing is used, derivatives are implicitly
1102 * calculated, so we need to enable helper invocations */
1104 if (variant
->helper_invocations
)
1105 flags
|= MALI_HELPER_INVOCATIONS
;
1107 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1109 /* Assign the stencil refs late */
1111 unsigned front_ref
= ctx
->stencil_ref
.ref_value
[0];
1112 unsigned back_ref
= ctx
->stencil_ref
.ref_value
[1];
1113 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
1115 ctx
->fragment_shader_core
.stencil_front
.ref
= front_ref
;
1116 ctx
->fragment_shader_core
.stencil_back
.ref
= back_enab
? back_ref
: front_ref
;
1118 /* CAN_DISCARD should be set if the fragment shader possibly
1119 * contains a 'discard' instruction. It is likely this is
1120 * related to optimizations related to forward-pixel kill, as
1121 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1122 * thing?" by Peter Harris
1125 if (variant
->can_discard
) {
1126 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1127 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1130 /* Check if we're using the default blend descriptor (fast path) */
1134 (blend
.equation
.equation
->rgb_mode
== 0x122) &&
1135 (blend
.equation
.equation
->alpha_mode
== 0x122) &&
1136 (blend
.equation
.equation
->color_mask
== 0xf);
1138 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1139 * *also* copied to the blend_meta appended (by convention),
1140 * but this is the field actually read by the hardware. (Or
1141 * maybe both are read...?) */
1143 if (blend
.is_shader
) {
1144 ctx
->fragment_shader_core
.blend
.shader
=
1147 ctx
->fragment_shader_core
.blend
.shader
= 0;
1150 if (screen
->require_sfbd
) {
1151 /* When only a single render target platform is used, the blend
1152 * information is inside the shader meta itself. We
1153 * additionally need to signal CAN_DISCARD for nontrivial blend
1154 * modes (so we're able to read back the destination buffer) */
1156 if (!blend
.is_shader
) {
1157 ctx
->fragment_shader_core
.blend
.equation
=
1158 *blend
.equation
.equation
;
1159 ctx
->fragment_shader_core
.blend
.constant
=
1160 blend
.equation
.constant
;
1164 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1168 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1169 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1170 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1172 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1174 if (!screen
->require_sfbd
) {
1175 /* Additional blend descriptor tacked on for jobs using MFBD */
1177 unsigned blend_count
= 0x200;
1179 if (blend
.is_shader
) {
1180 /* For a blend shader, the bottom nibble corresponds to
1181 * the number of work registers used, which signals the
1182 * -existence- of a blend shader */
1184 assert(blend
.shader
.work_count
>= 2);
1185 blend_count
|= MIN2(blend
.shader
.work_count
, 3);
1187 /* Otherwise, the bottom bit simply specifies if
1188 * blending (anything other than REPLACE) is enabled */
1195 struct midgard_blend_rt rts
[4];
1197 for (unsigned i
= 0; i
< ctx
->pipe_framebuffer
.nr_cbufs
; ++i
) {
1199 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1200 (ctx
->pipe_framebuffer
.cbufs
[i
]) &&
1201 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1203 rts
[i
].flags
= blend_count
;
1206 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1208 if (!ctx
->blend
->base
.dither
)
1209 rts
[i
].flags
|= MALI_BLEND_NO_DITHER
;
1211 /* TODO: sRGB in blend shaders is currently
1212 * unimplemented. Contact me (Alyssa) if you're
1213 * interested in working on this. We have
1214 * native Midgard ops for helping here, but
1215 * they're not well-understood yet. */
1217 assert(!(is_srgb
&& blend
.is_shader
));
1219 if (blend
.is_shader
) {
1220 rts
[i
].blend
.shader
= blend
.shader
.gpu
;
1222 rts
[i
].blend
.equation
= *blend
.equation
.equation
;
1223 rts
[i
].blend
.constant
= blend
.equation
.constant
;
1227 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1231 /* We stage to transient, so always dirty.. */
1233 panfrost_stage_attributes(ctx
);
1235 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1236 panfrost_upload_sampler_descriptors(ctx
);
1238 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1239 panfrost_upload_texture_descriptors(ctx
);
1241 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1243 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1244 struct panfrost_shader_variants
*all
= ctx
->shader
[i
];
1249 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1251 struct panfrost_shader_state
*ss
= &all
->variants
[all
->active_variant
];
1253 /* Uniforms are implicitly UBO #0 */
1254 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1256 /* Allocate room for the sysval and the uniforms */
1257 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1258 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1259 size_t size
= sys_size
+ uniform_size
;
1260 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1262 /* Upload sysvals requested by the shader */
1263 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1265 /* Upload uniforms */
1267 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1268 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1272 ctx
->shader
[i
]->variants
[ctx
->shader
[i
]->active_variant
].uniform_count
;
1274 struct mali_vertex_tiler_postfix
*postfix
=
1275 &ctx
->payloads
[i
].postfix
;
1277 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1280 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1281 assert(ubo_count
>= 1);
1283 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1284 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1286 /* Upload uniforms as a UBO */
1287 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1288 ubos
[0].ptr
= transfer
.gpu
>> 2;
1290 /* The rest are honest-to-goodness UBOs */
1292 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1293 size_t sz
= buf
->cb
[ubo
].buffer_size
;
1295 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1296 bool empty
= sz
== 0;
1298 if (!enabled
|| empty
) {
1299 /* Stub out disabled UBOs to catch accesses */
1302 ubos
[ubo
].ptr
= 0xDEAD0000;
1306 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1308 unsigned bytes_per_field
= 16;
1309 unsigned aligned
= ALIGN_POT(sz
, bytes_per_field
);
1310 unsigned fields
= aligned
/ bytes_per_field
;
1312 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1313 ubos
[ubo
].ptr
= gpu
>> 2;
1316 mali_ptr ubufs
= panfrost_upload_transient(ctx
, ubos
, sz
);
1317 postfix
->uniforms
= transfer
.gpu
;
1318 postfix
->uniform_buffers
= ubufs
;
1320 buf
->dirty_mask
= 0;
1323 /* TODO: Upload the viewport somewhere more appropriate */
1325 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1326 * (somewhat) asymmetric ints. */
1327 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1329 struct mali_viewport view
= {
1330 /* By default, do no viewport clipping, i.e. clip to (-inf,
1331 * inf) in each direction. Clipping to the viewport in theory
1332 * should work, but in practice causes issues when we're not
1333 * explicitly trying to scissor */
1335 .clip_minx
= -INFINITY
,
1336 .clip_miny
= -INFINITY
,
1337 .clip_maxx
= INFINITY
,
1338 .clip_maxy
= INFINITY
,
1344 /* Always scissor to the viewport by default. */
1345 float vp_minx
= (int) (vp
->translate
[0] - fabsf(vp
->scale
[0]));
1346 float vp_maxx
= (int) (vp
->translate
[0] + fabsf(vp
->scale
[0]));
1348 float vp_miny
= (int) (vp
->translate
[1] - fabsf(vp
->scale
[1]));
1349 float vp_maxy
= (int) (vp
->translate
[1] + fabsf(vp
->scale
[1]));
1351 /* Apply the scissor test */
1353 unsigned minx
, miny
, maxx
, maxy
;
1355 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1356 minx
= MAX2(ss
->minx
, vp_minx
);
1357 miny
= MAX2(ss
->miny
, vp_miny
);
1358 maxx
= MIN2(ss
->maxx
, vp_maxx
);
1359 maxy
= MIN2(ss
->maxy
, vp_maxy
);
1367 /* Hardware needs the min/max to be strictly ordered, so flip if we
1368 * need to. The viewport transformation in the vertex shader will
1369 * handle the negatives if we don't */
1383 /* Clamp everything positive, just in case */
1385 maxx
= MAX2(0, maxx
);
1386 maxy
= MAX2(0, maxy
);
1387 minx
= MAX2(0, minx
);
1388 miny
= MAX2(0, miny
);
1390 /* Clamp to the framebuffer size as a last check */
1392 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1393 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1395 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1396 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1398 /* Update the job, unless we're doing wallpapering (whose lack of
1399 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1400 * just... be faster :) */
1402 if (!ctx
->wallpaper_batch
)
1403 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1407 view
.viewport0
[0] = minx
;
1408 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1410 view
.viewport0
[1] = miny
;
1411 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1413 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.viewport
=
1414 panfrost_upload_transient(ctx
,
1416 sizeof(struct mali_viewport
));
1421 /* Corresponds to exactly one draw, but does not submit anything */
1424 panfrost_queue_draw(struct panfrost_context
*ctx
)
1426 /* Handle dirty flags now */
1427 panfrost_emit_for_draw(ctx
, true);
1429 /* If rasterizer discard is enable, only submit the vertex */
1431 bool rasterizer_discard
= ctx
->rasterizer
1432 && ctx
->rasterizer
->base
.rasterizer_discard
;
1434 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1435 struct panfrost_transfer tiler
;
1437 if (!rasterizer_discard
)
1438 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1440 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1442 if (rasterizer_discard
)
1443 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1444 else if (ctx
->wallpaper_batch
)
1445 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1447 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1450 /* The entire frame is in memory -- send it off to the kernel! */
1453 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1454 struct pipe_fence_handle
**fence
,
1455 struct panfrost_job
*job
)
1457 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1458 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1462 panfrost_job_submit(ctx
, job
);
1464 /* If visual, we can stall a frame */
1466 if (!flush_immediate
)
1467 panfrost_drm_force_flush_fragment(ctx
, fence
);
1469 screen
->last_fragment_flushed
= false;
1470 screen
->last_job
= job
;
1472 /* If readback, flush now (hurts the pipelined performance) */
1473 if (flush_immediate
)
1474 panfrost_drm_force_flush_fragment(ctx
, fence
);
1479 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1481 struct panfrost_context
*ctx
= pan_context(pipe
);
1483 /* Nothing to reload? TODO: MRT wallpapers */
1484 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1487 /* Check if the buffer has any content on it worth preserving */
1489 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1490 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1491 unsigned level
= surf
->u
.tex
.level
;
1493 if (!rsrc
->slices
[level
].initialized
)
1496 /* Save the batch */
1497 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1499 ctx
->wallpaper_batch
= batch
;
1500 panfrost_blit_wallpaper(ctx
);
1501 ctx
->wallpaper_batch
= NULL
;
1506 struct pipe_context
*pipe
,
1507 struct pipe_fence_handle
**fence
,
1510 struct panfrost_context
*ctx
= pan_context(pipe
);
1511 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1513 /* Nothing to do! */
1514 if (!job
->last_job
.gpu
&& !job
->clear
) return;
1516 if (!job
->clear
&& job
->last_tiler
.gpu
)
1517 panfrost_draw_wallpaper(&ctx
->base
);
1519 /* Whether to stall the pipeline for immediately correct results. Since
1520 * pipelined rendering is quite broken right now (to be fixed by the
1521 * panfrost_job refactor, just take the perf hit for correctness) */
1522 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1524 /* Submit the frame itself */
1525 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1527 /* Prepare for the next frame */
1528 panfrost_invalidate_frame(ctx
);
1531 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1534 g2m_draw_mode(enum pipe_prim_type mode
)
1537 DEFINE_CASE(POINTS
);
1539 DEFINE_CASE(LINE_LOOP
);
1540 DEFINE_CASE(LINE_STRIP
);
1541 DEFINE_CASE(TRIANGLES
);
1542 DEFINE_CASE(TRIANGLE_STRIP
);
1543 DEFINE_CASE(TRIANGLE_FAN
);
1545 DEFINE_CASE(QUAD_STRIP
);
1546 DEFINE_CASE(POLYGON
);
1549 unreachable("Invalid draw mode");
1556 panfrost_translate_index_size(unsigned size
)
1560 return MALI_DRAW_INDEXED_UINT8
;
1563 return MALI_DRAW_INDEXED_UINT16
;
1566 return MALI_DRAW_INDEXED_UINT32
;
1569 unreachable("Invalid index size");
1573 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1574 * good for the duration of the draw (transient), could last longer */
1577 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1579 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1581 off_t offset
= info
->start
* info
->index_size
;
1582 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1584 if (!info
->has_user_indices
) {
1585 /* Only resources can be directly mapped */
1586 panfrost_job_add_bo(batch
, rsrc
->bo
);
1587 return rsrc
->bo
->gpu
+ offset
;
1589 /* Otherwise, we need to upload to transient memory */
1590 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1591 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1596 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1598 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1600 /* Check if we're scissoring at all */
1602 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1605 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1610 struct pipe_context
*pipe
,
1611 const struct pipe_draw_info
*info
)
1613 struct panfrost_context
*ctx
= pan_context(pipe
);
1615 /* First of all, check the scissor to see if anything is drawn at all.
1616 * If it's not, we drop the draw (mostly a conformance issue;
1617 * well-behaved apps shouldn't hit this) */
1619 if (panfrost_scissor_culls_everything(ctx
))
1622 ctx
->payloads
[PIPE_SHADER_VERTEX
].draw_start
= info
->start
;
1623 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].draw_start
= info
->start
;
1625 int mode
= info
->mode
;
1627 /* Fallback unsupported restart index */
1628 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1630 if (info
->primitive_restart
&& info
->index_size
1631 && info
->restart_index
!= primitive_index
) {
1632 util_draw_vbo_without_prim_restart(pipe
, info
);
1636 /* Fallback for unsupported modes */
1638 if (!(ctx
->draw_modes
& (1 << mode
))) {
1639 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1640 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1642 if (info
->count
< 4) {
1643 /* Degenerate case? */
1647 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1648 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1653 /* Now that we have a guaranteed terminating path, find the job.
1654 * Assignment commented out to prevent unused warning */
1656 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1658 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.draw_mode
= g2m_draw_mode(mode
);
1660 ctx
->vertex_count
= info
->count
;
1661 ctx
->instance_count
= info
->instance_count
;
1663 /* For non-indexed draws, they're the same */
1664 unsigned vertex_count
= ctx
->vertex_count
;
1666 unsigned draw_flags
= 0;
1668 /* The draw flags interpret how primitive size is interpreted */
1670 if (panfrost_writes_point_size(ctx
))
1671 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1673 if (info
->primitive_restart
)
1674 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1676 /* For higher amounts of vertices (greater than what fits in a 16-bit
1677 * short), the other value is needed, otherwise there will be bizarre
1678 * rendering artefacts. It's not clear what these values mean yet. This
1679 * change is also needed for instancing and sometimes points (perhaps
1680 * related to dynamically setting gl_PointSize) */
1682 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1683 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1684 bool instanced
= ctx
->instance_count
> 1;
1686 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1688 /* This doesn't make much sense */
1689 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1690 draw_flags
|= 0x800;
1693 if (info
->index_size
) {
1694 /* Calculate the min/max index used so we can figure out how
1695 * many times to invoke the vertex shader */
1697 /* Fetch / calculate index bounds */
1698 unsigned min_index
= 0, max_index
= 0;
1700 if (info
->max_index
== ~0u) {
1701 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1703 min_index
= info
->min_index
;
1704 max_index
= info
->max_index
;
1707 /* Use the corresponding values */
1708 vertex_count
= max_index
- min_index
+ 1;
1709 ctx
->payloads
[PIPE_SHADER_VERTEX
].draw_start
= min_index
;
1710 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].draw_start
= min_index
;
1712 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.negative_start
= -min_index
;
1713 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(info
->count
);
1715 //assert(!info->restart_index); /* TODO: Research */
1716 assert(!info
->index_bias
);
1718 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1719 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1721 /* Index count == vertex count, if no indexing is applied, as
1722 * if it is internally indexed in the expected order */
1724 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.negative_start
= 0;
1725 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1727 /* Reverse index state */
1728 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.indices
= (u64
) NULL
;
1731 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1732 * vertex_count, 1) */
1734 panfrost_pack_work_groups_fused(
1735 &ctx
->payloads
[PIPE_SHADER_VERTEX
].prefix
,
1736 &ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
,
1737 1, vertex_count
, info
->instance_count
,
1740 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].prefix
.unknown_draw
= draw_flags
;
1742 /* Encode the padded vertex count */
1744 if (info
->instance_count
> 1) {
1745 /* Triangles have non-even vertex counts so they change how
1746 * padding works internally */
1749 mode
== PIPE_PRIM_TRIANGLES
||
1750 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1751 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1753 struct pan_shift_odd so
=
1754 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1756 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= so
.shift
;
1757 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= so
.shift
;
1759 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= so
.odd
;
1760 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= so
.odd
;
1762 ctx
->padded_count
= pan_expand_shift_odd(so
);
1764 ctx
->padded_count
= ctx
->vertex_count
;
1766 /* Reset instancing state */
1767 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_shift
= 0;
1768 ctx
->payloads
[PIPE_SHADER_VERTEX
].instance_odd
= 0;
1769 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_shift
= 0;
1770 ctx
->payloads
[PIPE_SHADER_FRAGMENT
].instance_odd
= 0;
1773 /* Fire off the draw itself */
1774 panfrost_queue_draw(ctx
);
1780 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1786 panfrost_create_rasterizer_state(
1787 struct pipe_context
*pctx
,
1788 const struct pipe_rasterizer_state
*cso
)
1790 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1794 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1795 so
->tiler_gl_enables
= 0x7;
1798 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1800 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1801 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1803 if (cso
->cull_face
& PIPE_FACE_BACK
)
1804 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1810 panfrost_bind_rasterizer_state(
1811 struct pipe_context
*pctx
,
1814 struct panfrost_context
*ctx
= pan_context(pctx
);
1816 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1820 ctx
->rasterizer
= hwcso
;
1821 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1823 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1824 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1826 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1827 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1829 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1831 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1832 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1834 /* Point sprites are emulated */
1836 struct panfrost_shader_state
*variant
=
1837 ctx
->shader
[PIPE_SHADER_FRAGMENT
] ? &ctx
->shader
[PIPE_SHADER_FRAGMENT
]->variants
[ctx
->shader
[PIPE_SHADER_FRAGMENT
]->active_variant
] : NULL
;
1839 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1840 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
1844 panfrost_create_vertex_elements_state(
1845 struct pipe_context
*pctx
,
1846 unsigned num_elements
,
1847 const struct pipe_vertex_element
*elements
)
1849 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1851 so
->num_elements
= num_elements
;
1852 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1854 for (int i
= 0; i
< num_elements
; ++i
) {
1855 so
->hw
[i
].index
= i
;
1857 enum pipe_format fmt
= elements
[i
].src_format
;
1858 const struct util_format_description
*desc
= util_format_description(fmt
);
1859 so
->hw
[i
].unknown1
= 0x2;
1860 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1862 so
->hw
[i
].format
= panfrost_find_format(desc
);
1864 /* The field itself should probably be shifted over */
1865 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1872 panfrost_bind_vertex_elements_state(
1873 struct pipe_context
*pctx
,
1876 struct panfrost_context
*ctx
= pan_context(pctx
);
1878 ctx
->vertex
= hwcso
;
1879 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1883 panfrost_create_shader_state(
1884 struct pipe_context
*pctx
,
1885 const struct pipe_shader_state
*cso
)
1887 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1890 /* Token deep copy to prevent memory corruption */
1892 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1893 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1899 panfrost_delete_shader_state(
1900 struct pipe_context
*pctx
,
1903 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1905 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1906 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1913 panfrost_create_sampler_state(
1914 struct pipe_context
*pctx
,
1915 const struct pipe_sampler_state
*cso
)
1917 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1920 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1922 bool min_nearest
= cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1923 bool mag_nearest
= cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
1924 bool mip_linear
= cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_LINEAR
;
1926 unsigned min_filter
= min_nearest
? MALI_SAMP_MIN_NEAREST
: 0;
1927 unsigned mag_filter
= mag_nearest
? MALI_SAMP_MAG_NEAREST
: 0;
1928 unsigned mip_filter
= mip_linear
?
1929 (MALI_SAMP_MIP_LINEAR_1
| MALI_SAMP_MIP_LINEAR_2
) : 0;
1930 unsigned normalized
= cso
->normalized_coords
? MALI_SAMP_NORM_COORDS
: 0;
1932 struct mali_sampler_descriptor sampler_descriptor
= {
1933 .filter_mode
= min_filter
| mag_filter
| mip_filter
| normalized
,
1934 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1935 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1936 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1937 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1939 cso
->border_color
.f
[0],
1940 cso
->border_color
.f
[1],
1941 cso
->border_color
.f
[2],
1942 cso
->border_color
.f
[3]
1944 .min_lod
= FIXED_16(cso
->min_lod
),
1945 .max_lod
= FIXED_16(cso
->max_lod
),
1946 .seamless_cube_map
= cso
->seamless_cube_map
,
1949 /* If necessary, we disable mipmapping in the sampler descriptor by
1950 * clamping the LOD as tight as possible (from 0 to epsilon,
1951 * essentially -- remember these are fixed point numbers, so
1954 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1955 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1957 /* Enforce that there is something in the middle by adding epsilon*/
1959 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1960 sampler_descriptor
.max_lod
++;
1963 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1965 so
->hw
= sampler_descriptor
;
1971 panfrost_bind_sampler_states(
1972 struct pipe_context
*pctx
,
1973 enum pipe_shader_type shader
,
1974 unsigned start_slot
, unsigned num_sampler
,
1977 assert(start_slot
== 0);
1979 struct panfrost_context
*ctx
= pan_context(pctx
);
1981 /* XXX: Should upload, not just copy? */
1982 ctx
->sampler_count
[shader
] = num_sampler
;
1983 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1985 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1989 panfrost_variant_matches(
1990 struct panfrost_context
*ctx
,
1991 struct panfrost_shader_state
*variant
,
1992 enum pipe_shader_type type
)
1994 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
1995 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1997 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
1999 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
2000 /* Make sure enable state is at least the same */
2001 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
2005 /* Check that the contents of the test are the same */
2006 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
2007 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
2009 if (!(same_func
&& same_ref
)) {
2014 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
2015 variant
->point_sprite_mask
)) {
2016 /* Ensure the same varyings are turned to point sprites */
2017 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
2020 /* Ensure the orientation is correct */
2022 rasterizer
->sprite_coord_mode
==
2023 PIPE_SPRITE_COORD_UPPER_LEFT
;
2025 if (variant
->point_sprite_upper_left
!= upper_left
)
2029 /* Otherwise, we're good to go */
2034 panfrost_bind_shader_state(
2035 struct pipe_context
*pctx
,
2037 enum pipe_shader_type type
)
2039 struct panfrost_context
*ctx
= pan_context(pctx
);
2041 ctx
->shader
[type
] = hwcso
;
2043 if (type
== PIPE_SHADER_FRAGMENT
)
2044 ctx
->dirty
|= PAN_DIRTY_FS
;
2046 ctx
->dirty
|= PAN_DIRTY_VS
;
2050 /* Match the appropriate variant */
2052 signed variant
= -1;
2053 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2055 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2056 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2062 if (variant
== -1) {
2063 /* No variant matched, so create a new one */
2064 variant
= variants
->variant_count
++;
2065 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2067 struct panfrost_shader_state
*v
=
2068 &variants
->variants
[variant
];
2070 if (type
== PIPE_SHADER_FRAGMENT
) {
2071 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2073 if (ctx
->rasterizer
) {
2074 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2075 v
->point_sprite_upper_left
=
2076 ctx
->rasterizer
->base
.sprite_coord_mode
==
2077 PIPE_SPRITE_COORD_UPPER_LEFT
;
2081 variants
->variants
[variant
].tripipe
= malloc(sizeof(struct mali_shader_meta
));
2085 /* Select this variant */
2086 variants
->active_variant
= variant
;
2088 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2089 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2091 /* We finally have a variant, so compile it */
2093 if (!shader_state
->compiled
) {
2094 panfrost_shader_compile(ctx
, shader_state
->tripipe
,
2095 variants
->base
.type
,
2096 variants
->base
.type
== PIPE_SHADER_IR_NIR
?
2097 variants
->base
.ir
.nir
:
2098 variants
->base
.tokens
,
2099 tgsi_processor_to_shader_stage(type
), shader_state
);
2101 shader_state
->compiled
= true;
2106 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2108 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2112 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2114 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2118 panfrost_set_vertex_buffers(
2119 struct pipe_context
*pctx
,
2120 unsigned start_slot
,
2121 unsigned num_buffers
,
2122 const struct pipe_vertex_buffer
*buffers
)
2124 struct panfrost_context
*ctx
= pan_context(pctx
);
2126 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2130 panfrost_set_constant_buffer(
2131 struct pipe_context
*pctx
,
2132 enum pipe_shader_type shader
, uint index
,
2133 const struct pipe_constant_buffer
*buf
)
2135 struct panfrost_context
*ctx
= pan_context(pctx
);
2136 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2138 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2140 unsigned mask
= (1 << index
);
2142 if (unlikely(!buf
)) {
2143 pbuf
->enabled_mask
&= ~mask
;
2144 pbuf
->dirty_mask
&= ~mask
;
2148 pbuf
->enabled_mask
|= mask
;
2149 pbuf
->dirty_mask
|= mask
;
2153 panfrost_set_stencil_ref(
2154 struct pipe_context
*pctx
,
2155 const struct pipe_stencil_ref
*ref
)
2157 struct panfrost_context
*ctx
= pan_context(pctx
);
2158 ctx
->stencil_ref
= *ref
;
2160 /* Shader core dirty */
2161 ctx
->dirty
|= PAN_DIRTY_FS
;
2164 static enum mali_texture_type
2165 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2169 case PIPE_TEXTURE_1D
:
2170 case PIPE_TEXTURE_1D_ARRAY
:
2173 case PIPE_TEXTURE_2D
:
2174 case PIPE_TEXTURE_2D_ARRAY
:
2175 case PIPE_TEXTURE_RECT
:
2178 case PIPE_TEXTURE_3D
:
2181 case PIPE_TEXTURE_CUBE
:
2182 case PIPE_TEXTURE_CUBE_ARRAY
:
2183 return MALI_TEX_CUBE
;
2186 unreachable("Unknown target");
2190 static struct pipe_sampler_view
*
2191 panfrost_create_sampler_view(
2192 struct pipe_context
*pctx
,
2193 struct pipe_resource
*texture
,
2194 const struct pipe_sampler_view
*template)
2196 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2197 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2199 pipe_reference(NULL
, &texture
->reference
);
2201 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2204 so
->base
= *template;
2205 so
->base
.texture
= texture
;
2206 so
->base
.reference
.count
= 1;
2207 so
->base
.context
= pctx
;
2209 /* sampler_views correspond to texture descriptors, minus the texture
2210 * (data) itself. So, we serialise the descriptor here and cache it for
2213 /* TODO: Detect from format better */
2214 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2216 unsigned char user_swizzle
[4] = {
2217 template->swizzle_r
,
2218 template->swizzle_g
,
2219 template->swizzle_b
,
2223 enum mali_format format
= panfrost_find_format(desc
);
2225 /* Check if we need to set a custom stride by computing the "expected"
2226 * stride and comparing it to what the BO actually wants. Only applies
2227 * to linear textures, since tiled/compressed textures have strict
2228 * alignment requirements for their strides as it is */
2230 unsigned first_level
= template->u
.tex
.first_level
;
2231 unsigned last_level
= template->u
.tex
.last_level
;
2233 if (prsrc
->layout
== PAN_LINEAR
) {
2234 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2235 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2236 unsigned width
= u_minify(texture
->width0
, l
);
2237 unsigned comp_stride
= width
* bytes_per_pixel
;
2239 if (comp_stride
!= actual_stride
) {
2240 so
->manual_stride
= true;
2246 /* In the hardware, array_size refers specifically to array textures,
2247 * whereas in Gallium, it also covers cubemaps */
2249 unsigned array_size
= texture
->array_size
;
2251 if (template->target
== PIPE_TEXTURE_CUBE
) {
2252 /* TODO: Cubemap arrays */
2253 assert(array_size
== 6);
2257 struct mali_texture_descriptor texture_descriptor
= {
2258 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2259 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2260 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2261 .array_size
= MALI_POSITIVE(array_size
),
2265 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2268 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2269 .type
= panfrost_translate_texture_type(template->target
),
2272 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2275 texture_descriptor
.nr_mipmap_levels
= last_level
- first_level
;
2277 so
->hw
= texture_descriptor
;
2279 return (struct pipe_sampler_view
*) so
;
2283 panfrost_set_sampler_views(
2284 struct pipe_context
*pctx
,
2285 enum pipe_shader_type shader
,
2286 unsigned start_slot
, unsigned num_views
,
2287 struct pipe_sampler_view
**views
)
2289 struct panfrost_context
*ctx
= pan_context(pctx
);
2291 assert(start_slot
== 0);
2293 unsigned new_nr
= 0;
2294 for (unsigned i
= 0; i
< num_views
; ++i
) {
2299 ctx
->sampler_view_count
[shader
] = new_nr
;
2300 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2302 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2306 panfrost_sampler_view_destroy(
2307 struct pipe_context
*pctx
,
2308 struct pipe_sampler_view
*view
)
2310 pipe_resource_reference(&view
->texture
, NULL
);
2315 panfrost_set_shader_buffers(
2316 struct pipe_context
*pctx
,
2317 enum pipe_shader_type shader
,
2318 unsigned start
, unsigned count
,
2319 const struct pipe_shader_buffer
*buffers
,
2320 unsigned writable_bitmask
)
2322 struct panfrost_context
*ctx
= pan_context(pctx
);
2324 util_set_shader_buffers_mask(ctx
->ssbo
[shader
], &ctx
->ssbo_mask
[shader
],
2325 buffers
, start
, count
);
2328 /* Hints that a framebuffer should use AFBC where possible */
2332 struct panfrost_screen
*screen
,
2333 const struct pipe_framebuffer_state
*fb
)
2335 /* AFBC implemenation incomplete; hide it */
2336 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2338 /* Hint AFBC to the resources bound to each color buffer */
2340 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2341 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2342 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2343 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2346 /* Also hint it to the depth buffer */
2349 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2350 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2355 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2356 const struct pipe_framebuffer_state
*fb
)
2358 struct panfrost_context
*ctx
= pan_context(pctx
);
2360 /* Flush when switching framebuffers, but not if the framebuffer
2361 * state is being restored by u_blitter
2364 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
2365 bool is_scanout
= panfrost_is_scanout(ctx
);
2366 bool has_draws
= job
->last_job
.gpu
;
2368 /* Bail out early when the current and new states are the same. */
2369 if (util_framebuffer_state_equal(&ctx
->pipe_framebuffer
, fb
))
2372 /* The wallpaper logic sets a new FB state before doing the blit and
2373 * restore the old one when it's done. Those FB states are reported to
2374 * be different because the surface they are pointing to are different,
2375 * but those surfaces actually point to the same cbufs/zbufs. In that
2376 * case we definitely don't want new FB descs to be emitted/attached
2377 * since the job is expected to be flushed just after the blit is done,
2378 * so let's just copy the new state and return here.
2380 if (ctx
->wallpaper_batch
) {
2381 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2385 if (!is_scanout
|| has_draws
)
2386 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2388 assert(!ctx
->payloads
[PIPE_SHADER_VERTEX
].postfix
.framebuffer
&&
2389 !ctx
->payloads
[PIPE_SHADER_FRAGMENT
].postfix
.framebuffer
);
2391 /* Invalidate the FBO job cache since we've just been assigned a new
2396 util_copy_framebuffer_state(&ctx
->pipe_framebuffer
, fb
);
2398 /* Given that we're rendering, we'd love to have compression */
2399 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2401 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2402 for (unsigned i
= 0; i
< PIPE_SHADER_TYPES
; ++i
)
2403 ctx
->payloads
[i
].postfix
.framebuffer
= 0;
2407 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2408 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2410 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2414 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2417 struct panfrost_context
*ctx
= pan_context(pipe
);
2418 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2419 ctx
->depth_stencil
= depth_stencil
;
2424 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2425 * emulated in the fragment shader */
2427 if (depth_stencil
->alpha
.enabled
) {
2428 /* We need to trigger a new shader (maybe) */
2429 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->shader
[PIPE_SHADER_FRAGMENT
]);
2433 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
);
2435 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2436 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2438 /* If back-stencil is not enabled, use the front values */
2439 bool back_enab
= ctx
->depth_stencil
->stencil
[1].enabled
;
2440 unsigned back_index
= back_enab
? 1 : 0;
2442 panfrost_make_stencil_state(&depth_stencil
->stencil
[back_index
], &ctx
->fragment_shader_core
.stencil_back
);
2443 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[back_index
].writemask
;
2445 /* Depth state (TODO: Refactor) */
2446 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2448 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2450 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2451 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2453 /* Bounds test not implemented */
2454 assert(!depth_stencil
->depth
.bounds_test
);
2456 ctx
->dirty
|= PAN_DIRTY_FS
;
2460 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2466 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2467 unsigned sample_mask
)
2472 panfrost_set_clip_state(struct pipe_context
*pipe
,
2473 const struct pipe_clip_state
*clip
)
2475 //struct panfrost_context *panfrost = pan_context(pipe);
2479 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2480 unsigned start_slot
,
2481 unsigned num_viewports
,
2482 const struct pipe_viewport_state
*viewports
)
2484 struct panfrost_context
*ctx
= pan_context(pipe
);
2486 assert(start_slot
== 0);
2487 assert(num_viewports
== 1);
2489 ctx
->pipe_viewport
= *viewports
;
2493 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2494 unsigned start_slot
,
2495 unsigned num_scissors
,
2496 const struct pipe_scissor_state
*scissors
)
2498 struct panfrost_context
*ctx
= pan_context(pipe
);
2500 assert(start_slot
== 0);
2501 assert(num_scissors
== 1);
2503 ctx
->scissor
= *scissors
;
2507 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2508 const struct pipe_poly_stipple
*stipple
)
2510 //struct panfrost_context *panfrost = pan_context(pipe);
2514 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2517 //struct panfrost_context *panfrost = pan_context(pipe);
2521 panfrost_destroy(struct pipe_context
*pipe
)
2523 struct panfrost_context
*panfrost
= pan_context(pipe
);
2524 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2526 if (panfrost
->blitter
)
2527 util_blitter_destroy(panfrost
->blitter
);
2529 if (panfrost
->blitter_wallpaper
)
2530 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2532 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2533 panfrost_drm_free_slab(screen
, &panfrost
->shaders
);
2534 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2535 panfrost_drm_free_slab(screen
, &panfrost
->tiler_polygon_list
);
2536 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2541 static struct pipe_query
*
2542 panfrost_create_query(struct pipe_context
*pipe
,
2546 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2551 return (struct pipe_query
*) q
;
2555 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2561 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2563 struct panfrost_context
*ctx
= pan_context(pipe
);
2564 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2566 switch (query
->type
) {
2567 case PIPE_QUERY_OCCLUSION_COUNTER
:
2568 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2569 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2570 /* Allocate a word for the query results to be stored */
2571 query
->transfer
= panfrost_allocate_transient(ctx
, sizeof(unsigned));
2573 ctx
->occlusion_query
= query
;
2579 DBG("Skipping query %d\n", query
->type
);
2587 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2589 struct panfrost_context
*ctx
= pan_context(pipe
);
2590 ctx
->occlusion_query
= NULL
;
2595 panfrost_get_query_result(struct pipe_context
*pipe
,
2596 struct pipe_query
*q
,
2598 union pipe_query_result
*vresult
)
2601 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2603 /* We need to flush out the jobs to actually run the counter, TODO
2604 * check wait, TODO wallpaper after if needed */
2606 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2608 switch (query
->type
) {
2609 case PIPE_QUERY_OCCLUSION_COUNTER
:
2610 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2611 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2612 /* Read back the query results */
2613 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2614 unsigned passed
= *result
;
2616 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2617 vresult
->u64
= passed
;
2619 vresult
->b
= !!passed
;
2625 DBG("Skipped query get %d\n", query
->type
);
2632 static struct pipe_stream_output_target
*
2633 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2634 struct pipe_resource
*prsc
,
2635 unsigned buffer_offset
,
2636 unsigned buffer_size
)
2638 struct pipe_stream_output_target
*target
;
2640 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2645 pipe_reference_init(&target
->reference
, 1);
2646 pipe_resource_reference(&target
->buffer
, prsc
);
2648 target
->context
= pctx
;
2649 target
->buffer_offset
= buffer_offset
;
2650 target
->buffer_size
= buffer_size
;
2656 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2657 struct pipe_stream_output_target
*target
)
2659 pipe_resource_reference(&target
->buffer
, NULL
);
2660 ralloc_free(target
);
2664 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2665 unsigned num_targets
,
2666 struct pipe_stream_output_target
**targets
,
2667 const unsigned *offsets
)
2673 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2675 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2676 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2678 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64*4, false, 0, 0, 0);
2679 panfrost_drm_allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2680 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 4096, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2681 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2682 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2685 /* New context creation, which also does hardware initialisation since I don't
2686 * know the better way to structure this :smirk: */
2688 struct pipe_context
*
2689 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2691 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2692 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2693 memset(ctx
, 0, sizeof(*ctx
));
2694 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2696 ctx
->is_t6xx
= pscreen
->gpu_id
< 0x0700; /* Literally, "earlier than T700" */
2698 gallium
->screen
= screen
;
2700 gallium
->destroy
= panfrost_destroy
;
2702 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2704 gallium
->flush
= panfrost_flush
;
2705 gallium
->clear
= panfrost_clear
;
2706 gallium
->draw_vbo
= panfrost_draw_vbo
;
2708 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2709 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2710 gallium
->set_shader_buffers
= panfrost_set_shader_buffers
;
2712 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2714 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2715 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2716 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2718 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2719 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2720 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2722 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2723 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2724 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2726 gallium
->create_fs_state
= panfrost_create_shader_state
;
2727 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2728 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2730 gallium
->create_vs_state
= panfrost_create_shader_state
;
2731 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2732 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2734 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2735 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2736 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2738 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2739 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2740 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2742 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2744 gallium
->set_clip_state
= panfrost_set_clip_state
;
2745 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2746 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2747 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2748 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2750 gallium
->create_query
= panfrost_create_query
;
2751 gallium
->destroy_query
= panfrost_destroy_query
;
2752 gallium
->begin_query
= panfrost_begin_query
;
2753 gallium
->end_query
= panfrost_end_query
;
2754 gallium
->get_query_result
= panfrost_get_query_result
;
2756 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2757 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2758 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2760 panfrost_resource_context_init(gallium
);
2761 panfrost_blend_context_init(gallium
);
2762 panfrost_compute_context_init(gallium
);
2764 panfrost_drm_init_context(ctx
);
2766 panfrost_setup_hardware(ctx
);
2769 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2770 gallium
->const_uploader
= gallium
->stream_uploader
;
2771 assert(gallium
->stream_uploader
);
2773 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2774 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2776 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2778 ctx
->blitter
= util_blitter_create(gallium
);
2779 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2781 assert(ctx
->blitter
);
2782 assert(ctx
->blitter_wallpaper
);
2784 /* Prepare for render! */
2786 panfrost_job_init(ctx
);
2787 panfrost_emit_vertex_payload(ctx
);
2788 panfrost_emit_tiler_payload(ctx
);
2789 panfrost_invalidate_frame(ctx
);
2790 panfrost_default_shader_backend(ctx
);