2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_format.h"
31 #include "util/macros.h"
32 #include "util/u_format.h"
33 #include "util/u_inlines.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_memory.h"
36 #include "util/u_vbuf.h"
37 #include "util/half_float.h"
38 #include "util/u_helpers.h"
39 #include "util/u_format.h"
40 #include "util/u_prim_restart.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
49 #include "pan_tiler.h"
51 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
54 static enum mali_job_type
55 panfrost_job_type_for_pipe(enum pipe_shader_type type
) {
58 case PIPE_SHADER_VERTEX
:
59 return JOB_TYPE_VERTEX
;
61 case PIPE_SHADER_FRAGMENT
:
62 /* Note: JOB_TYPE_FRAGMENT is different.
63 * JOB_TYPE_FRAGMENT actually executes the
64 * fragment shader, but JOB_TYPE_TILER is how you
66 return JOB_TYPE_TILER
;
68 case PIPE_SHADER_GEOMETRY
:
69 return JOB_TYPE_GEOMETRY
;
71 case PIPE_SHADER_COMPUTE
:
72 return JOB_TYPE_COMPUTE
;
75 unreachable("Unsupported shader stage");
79 /* Framebuffer descriptor */
81 static struct midgard_tiler_descriptor
82 panfrost_emit_midg_tiler(
83 struct panfrost_context
*ctx
,
86 unsigned vertex_count
)
88 struct midgard_tiler_descriptor t
= {};
91 panfrost_choose_hierarchy_mask(width
, height
, vertex_count
);
93 /* Compute the polygon header size and use that to offset the body */
95 unsigned header_size
= panfrost_tiler_header_size(
96 width
, height
, t
.hierarchy_mask
);
98 unsigned body_size
= panfrost_tiler_body_size(
99 width
, height
, t
.hierarchy_mask
);
103 if (t
.hierarchy_mask
) {
104 assert(ctx
->tiler_polygon_list
.bo
->size
>= (header_size
+ body_size
));
106 /* Specify allocated tiler structures */
107 t
.polygon_list
= ctx
->tiler_polygon_list
.bo
->gpu
;
109 /* Allow the entire tiler heap */
110 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
112 ctx
->tiler_heap
.bo
->gpu
+ ctx
->tiler_heap
.bo
->size
;
114 /* The tiler is disabled, so don't allow the tiler heap */
115 t
.heap_start
= ctx
->tiler_heap
.bo
->gpu
;
116 t
.heap_end
= t
.heap_start
;
118 /* Use a dummy polygon list */
119 t
.polygon_list
= ctx
->tiler_dummy
.bo
->gpu
;
121 /* Also, set a "tiler disabled?" flag? */
122 t
.hierarchy_mask
|= 0x1000;
125 t
.polygon_list_body
=
126 t
.polygon_list
+ header_size
;
128 t
.polygon_list_size
=
129 header_size
+ body_size
;
134 struct mali_single_framebuffer
135 panfrost_emit_sfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
137 unsigned width
= ctx
->pipe_framebuffer
.width
;
138 unsigned height
= ctx
->pipe_framebuffer
.height
;
140 struct mali_single_framebuffer framebuffer
= {
141 .width
= MALI_POSITIVE(width
),
142 .height
= MALI_POSITIVE(height
),
144 .format
= 0x30000000,
145 .clear_flags
= 0x1000,
146 .unknown_address_0
= ctx
->scratchpad
.bo
->gpu
,
147 .tiler
= panfrost_emit_midg_tiler(ctx
,
148 width
, height
, vertex_count
),
154 struct bifrost_framebuffer
155 panfrost_emit_mfbd(struct panfrost_context
*ctx
, unsigned vertex_count
)
157 unsigned width
= ctx
->pipe_framebuffer
.width
;
158 unsigned height
= ctx
->pipe_framebuffer
.height
;
160 struct bifrost_framebuffer framebuffer
= {
161 .width1
= MALI_POSITIVE(width
),
162 .height1
= MALI_POSITIVE(height
),
163 .width2
= MALI_POSITIVE(width
),
164 .height2
= MALI_POSITIVE(height
),
169 .rt_count_1
= MALI_POSITIVE(1),
174 .scratchpad
= ctx
->scratchpad
.bo
->gpu
,
175 .tiler
= panfrost_emit_midg_tiler(ctx
,
176 width
, height
, vertex_count
)
182 /* Are we currently rendering to the screen (rather than an FBO)? */
185 panfrost_is_scanout(struct panfrost_context
*ctx
)
187 /* If there is no color buffer, it's an FBO */
188 if (ctx
->pipe_framebuffer
.nr_cbufs
!= 1)
191 /* If we're too early that no framebuffer was sent, it's scanout */
192 if (!ctx
->pipe_framebuffer
.cbufs
[0])
195 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
196 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
197 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
202 struct pipe_context
*pipe
,
204 const union pipe_color_union
*color
,
205 double depth
, unsigned stencil
)
207 struct panfrost_context
*ctx
= pan_context(pipe
);
208 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
210 panfrost_job_clear(ctx
, job
, buffers
, color
, depth
, stencil
);
214 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
216 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
)) | MALI_MFBD
;
220 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
222 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
226 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
, bool skippable
)
228 /* Skip the attach if we can */
230 if (skippable
&& ctx
->payload_vertex
.postfix
.framebuffer
) {
231 assert(ctx
->payload_tiler
.postfix
.framebuffer
);
235 mali_ptr framebuffer
= ctx
->require_sfbd
?
236 panfrost_attach_vt_sfbd(ctx
) :
237 panfrost_attach_vt_mfbd(ctx
);
239 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
240 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
243 /* Reset per-frame context, called on context initialisation as well as after
244 * flushing a frame */
247 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
249 if (ctx
->require_sfbd
)
250 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
252 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
254 /* The reference is now invalid */
255 ctx
->payload_vertex
.postfix
.framebuffer
= 0;
256 ctx
->payload_tiler
.postfix
.framebuffer
= 0;
259 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
262 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
265 /* In practice, every field of these payloads should be configurable
266 * arbitrarily, which means these functions are basically catch-all's for
267 * as-of-yet unwavering unknowns */
270 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
272 /* 0x2 bit clear on 32-bit T6XX */
274 struct midgard_payload_vertex_tiler payload
= {
275 .gl_enables
= 0x4 | 0x2,
278 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
282 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
284 struct midgard_payload_vertex_tiler payload
= {
286 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
290 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
294 translate_tex_wrap(enum pipe_tex_wrap w
)
297 case PIPE_TEX_WRAP_REPEAT
:
298 return MALI_WRAP_REPEAT
;
300 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
301 return MALI_WRAP_CLAMP_TO_EDGE
;
303 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
304 return MALI_WRAP_CLAMP_TO_BORDER
;
306 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
307 return MALI_WRAP_MIRRORED_REPEAT
;
310 unreachable("Invalid wrap");
315 translate_tex_filter(enum pipe_tex_filter f
)
318 case PIPE_TEX_FILTER_NEAREST
:
321 case PIPE_TEX_FILTER_LINEAR
:
325 unreachable("Invalid filter");
330 translate_mip_filter(enum pipe_tex_mipfilter f
)
332 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
336 panfrost_translate_compare_func(enum pipe_compare_func in
)
339 case PIPE_FUNC_NEVER
:
340 return MALI_FUNC_NEVER
;
343 return MALI_FUNC_LESS
;
345 case PIPE_FUNC_EQUAL
:
346 return MALI_FUNC_EQUAL
;
348 case PIPE_FUNC_LEQUAL
:
349 return MALI_FUNC_LEQUAL
;
351 case PIPE_FUNC_GREATER
:
352 return MALI_FUNC_GREATER
;
354 case PIPE_FUNC_NOTEQUAL
:
355 return MALI_FUNC_NOTEQUAL
;
357 case PIPE_FUNC_GEQUAL
:
358 return MALI_FUNC_GEQUAL
;
360 case PIPE_FUNC_ALWAYS
:
361 return MALI_FUNC_ALWAYS
;
364 unreachable("Invalid func");
369 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
372 case PIPE_FUNC_NEVER
:
373 return MALI_ALT_FUNC_NEVER
;
376 return MALI_ALT_FUNC_LESS
;
378 case PIPE_FUNC_EQUAL
:
379 return MALI_ALT_FUNC_EQUAL
;
381 case PIPE_FUNC_LEQUAL
:
382 return MALI_ALT_FUNC_LEQUAL
;
384 case PIPE_FUNC_GREATER
:
385 return MALI_ALT_FUNC_GREATER
;
387 case PIPE_FUNC_NOTEQUAL
:
388 return MALI_ALT_FUNC_NOTEQUAL
;
390 case PIPE_FUNC_GEQUAL
:
391 return MALI_ALT_FUNC_GEQUAL
;
393 case PIPE_FUNC_ALWAYS
:
394 return MALI_ALT_FUNC_ALWAYS
;
397 unreachable("Invalid alt func");
402 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
405 case PIPE_STENCIL_OP_KEEP
:
406 return MALI_STENCIL_KEEP
;
408 case PIPE_STENCIL_OP_ZERO
:
409 return MALI_STENCIL_ZERO
;
411 case PIPE_STENCIL_OP_REPLACE
:
412 return MALI_STENCIL_REPLACE
;
414 case PIPE_STENCIL_OP_INCR
:
415 return MALI_STENCIL_INCR
;
417 case PIPE_STENCIL_OP_DECR
:
418 return MALI_STENCIL_DECR
;
420 case PIPE_STENCIL_OP_INCR_WRAP
:
421 return MALI_STENCIL_INCR_WRAP
;
423 case PIPE_STENCIL_OP_DECR_WRAP
:
424 return MALI_STENCIL_DECR_WRAP
;
426 case PIPE_STENCIL_OP_INVERT
:
427 return MALI_STENCIL_INVERT
;
430 unreachable("Invalid stencil op");
435 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
437 out
->ref
= 0; /* Gallium gets it from elsewhere */
439 out
->mask
= in
->valuemask
;
440 out
->func
= panfrost_translate_compare_func(in
->func
);
441 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
442 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
443 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
447 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
449 struct mali_shader_meta shader
= {
450 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
452 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
453 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
456 /* unknown2_4 has 0x10 bit set on 32-bit T6XX */
458 struct pipe_stencil_state default_stencil
= {
460 .func
= PIPE_FUNC_ALWAYS
,
461 .fail_op
= MALI_STENCIL_KEEP
,
462 .zfail_op
= MALI_STENCIL_KEEP
,
463 .zpass_op
= MALI_STENCIL_KEEP
,
468 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
469 shader
.stencil_mask_front
= default_stencil
.writemask
;
471 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
472 shader
.stencil_mask_back
= default_stencil
.writemask
;
474 if (default_stencil
.enabled
)
475 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
477 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
480 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
481 * graphics command stream. It should be called once per draw, accordding to
482 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
483 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
486 struct panfrost_transfer
487 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
489 struct mali_job_descriptor_header job
= {
490 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
491 .job_descriptor_size
= 1,
494 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
496 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
497 memcpy(transfer
.cpu
, &job
, sizeof(job
));
498 memcpy(transfer
.cpu
+ sizeof(job
), payload
, sizeof(*payload
));
503 panfrost_emit_varyings(
504 struct panfrost_context
*ctx
,
505 union mali_attr
*slot
,
509 /* Fill out the descriptor */
510 slot
->stride
= stride
;
511 slot
->size
= stride
* count
;
512 slot
->shift
= slot
->extra_flags
= 0;
514 struct panfrost_transfer transfer
=
515 panfrost_allocate_transient(ctx
, slot
->size
);
517 slot
->elements
= transfer
.gpu
| MALI_ATTR_LINEAR
;
523 panfrost_emit_point_coord(union mali_attr
*slot
)
525 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
526 slot
->stride
= slot
->size
= slot
->shift
= slot
->extra_flags
= 0;
530 panfrost_emit_varying_descriptor(
531 struct panfrost_context
*ctx
,
532 unsigned vertex_count
)
534 /* Load the shaders */
536 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
537 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
538 unsigned int num_gen_varyings
= 0;
540 /* Allocate the varying descriptor */
542 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
543 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
545 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
549 * Assign ->src_offset now that we know about all the general purpose
550 * varyings that will be used by the fragment and vertex shaders.
552 for (unsigned i
= 0; i
< vs
->tripipe
->varying_count
; i
++) {
554 * General purpose varyings have ->index set to 0, skip other
557 if (vs
->varyings
[i
].index
)
560 vs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
563 for (unsigned i
= 0; i
< fs
->tripipe
->varying_count
; i
++) {
566 /* If we have a point sprite replacement, handle that here. We
567 * have to translate location first. TODO: Flip y in shader.
568 * We're already keying ... just time crunch .. */
570 unsigned loc
= fs
->varyings_loc
[i
];
572 (loc
>= VARYING_SLOT_VAR0
) ? (loc
- VARYING_SLOT_VAR0
) :
573 (loc
== VARYING_SLOT_PNTC
) ? 8 :
576 if (~pnt_loc
&& fs
->point_sprite_mask
& (1 << pnt_loc
)) {
577 /* gl_PointCoord index by convention */
578 fs
->varyings
[i
].index
= 3;
579 fs
->reads_point_coord
= true;
581 /* Swizzle out the z/w to 0/1 */
582 fs
->varyings
[i
].format
= MALI_RG16F
;
583 fs
->varyings
[i
].swizzle
=
584 panfrost_get_default_swizzle(2);
589 if (fs
->varyings
[i
].index
)
593 * Re-use the VS general purpose varying pos if it exists,
594 * create a new one otherwise.
596 for (j
= 0; j
< vs
->tripipe
->varying_count
; j
++) {
597 if (fs
->varyings_loc
[i
] == vs
->varyings_loc
[j
])
601 if (j
< vs
->tripipe
->varying_count
)
602 fs
->varyings
[i
].src_offset
= vs
->varyings
[j
].src_offset
;
604 fs
->varyings
[i
].src_offset
= 16 * (num_gen_varyings
++);
607 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
608 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
610 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
611 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
613 /* Buffer indices must be in this order per our convention */
614 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
617 panfrost_emit_varyings(ctx
, &varyings
[idx
++], num_gen_varyings
* 16,
620 /* fp32 vec4 gl_Position */
621 ctx
->payload_tiler
.postfix
.position_varying
=
622 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
623 sizeof(float) * 4, vertex_count
);
626 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
627 /* fp16 vec1 gl_PointSize */
628 ctx
->payload_tiler
.primitive_size
.pointer
=
629 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
633 if (fs
->reads_point_coord
) {
634 /* Special descriptor */
635 panfrost_emit_point_coord(&varyings
[idx
++]);
638 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
639 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
640 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
644 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
646 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
647 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
649 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
653 panfrost_writes_point_size(struct panfrost_context
*ctx
)
656 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
658 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
661 /* Stage the attribute descriptors so we can adjust src_offset
662 * to let BOs align nicely */
665 panfrost_stage_attributes(struct panfrost_context
*ctx
)
667 struct panfrost_vertex_state
*so
= ctx
->vertex
;
669 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
670 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
671 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
673 /* Copy as-is for the first pass */
674 memcpy(target
, so
->hw
, sz
);
676 /* Fixup offsets for the second pass. Recall that the hardware
677 * calculates attribute addresses as:
679 * addr = base + (stride * vtx) + src_offset;
681 * However, on Mali, base must be aligned to 64-bytes, so we
684 * base' = base & ~63 = base - (base & 63)
686 * To compensate when using base' (see emit_vertex_data), we have
687 * to adjust src_offset by the masked off piece:
689 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
690 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
691 * = base + (stride * vtx) + src_offset
697 unsigned start
= ctx
->payload_vertex
.draw_start
;
699 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
700 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
701 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[vbi
];
702 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
704 /* Adjust by the masked off bits of the offset */
705 target
[i
].src_offset
+= (addr
& 63);
707 /* Also, somewhat obscurely per-instance data needs to be
708 * offset in response to a delayed start in an indexed draw */
710 if (so
->pipe
[i
].instance_divisor
&& ctx
->instance_count
> 1 && start
) {
711 target
[i
].src_offset
-= buf
->stride
* start
;
717 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
721 panfrost_upload_sampler_descriptors(struct panfrost_context
*ctx
)
723 size_t desc_size
= sizeof(struct mali_sampler_descriptor
);
725 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
728 if (ctx
->sampler_count
[t
] && ctx
->sampler_view_count
[t
]) {
729 size_t transfer_size
= desc_size
* ctx
->sampler_count
[t
];
731 struct panfrost_transfer transfer
=
732 panfrost_allocate_transient(ctx
, transfer_size
);
734 struct mali_sampler_descriptor
*desc
=
735 (struct mali_sampler_descriptor
*) transfer
.cpu
;
737 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
)
738 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
740 upload
= transfer
.gpu
;
743 if (t
== PIPE_SHADER_FRAGMENT
)
744 ctx
->payload_tiler
.postfix
.sampler_descriptor
= upload
;
745 else if (t
== PIPE_SHADER_VERTEX
)
746 ctx
->payload_vertex
.postfix
.sampler_descriptor
= upload
;
753 panfrost_layout_for_texture(struct panfrost_resource
*rsrc
, bool manual_stride
)
755 /* TODO: other linear depth textures */
756 bool is_depth
= rsrc
->base
.format
== PIPE_FORMAT_Z32_UNORM
;
758 unsigned usage2_layout
= 0x10;
760 switch (rsrc
->layout
) {
762 usage2_layout
|= 0x8 | 0x4;
765 usage2_layout
|= 0x1;
768 usage2_layout
|= is_depth
? 0x1 : 0x2;
776 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
778 return usage2_layout
;
783 struct panfrost_context
*ctx
,
784 struct panfrost_sampler_view
*view
)
789 struct pipe_sampler_view
*pview
= &view
->base
;
790 struct panfrost_resource
*rsrc
= pan_resource(pview
->texture
);
792 /* Do we interleave an explicit stride with every element? */
794 bool has_manual_stride
= view
->manual_stride
;
796 /* For easy access */
798 assert(pview
->target
!= PIPE_BUFFER
);
799 unsigned first_level
= pview
->u
.tex
.first_level
;
800 unsigned last_level
= pview
->u
.tex
.last_level
;
801 unsigned first_layer
= pview
->u
.tex
.first_layer
;
802 unsigned last_layer
= pview
->u
.tex
.last_layer
;
804 /* Lower-bit is set when sampling from colour AFBC */
805 bool is_afbc
= rsrc
->layout
== PAN_AFBC
;
806 bool is_zs
= rsrc
->base
.bind
& PIPE_BIND_DEPTH_STENCIL
;
807 unsigned afbc_bit
= (is_afbc
&& !is_zs
) ? 1 : 0;
809 /* Add the BO to the job so it's retained until the job is done. */
810 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
811 panfrost_job_add_bo(job
, rsrc
->bo
);
813 /* Add the usage flags in, since they can change across the CSO
814 * lifetime due to layout switches */
816 view
->hw
.format
.usage2
= panfrost_layout_for_texture(rsrc
, has_manual_stride
);
818 /* Inject the addresses in, interleaving mip levels, cube faces, and
819 * strides in that order */
823 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
824 for (unsigned f
= first_layer
; f
<= last_layer
; ++f
) {
826 view
->hw
.payload
[idx
++] =
827 panfrost_get_texture_address(rsrc
, l
, f
) + afbc_bit
;
829 if (has_manual_stride
) {
830 view
->hw
.payload
[idx
++] =
831 rsrc
->slices
[l
].stride
;
836 return panfrost_upload_transient(ctx
, &view
->hw
,
837 sizeof(struct mali_texture_descriptor
));
841 panfrost_upload_texture_descriptors(struct panfrost_context
*ctx
)
843 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
844 mali_ptr trampoline
= 0;
846 if (ctx
->sampler_view_count
[t
]) {
847 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
849 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
)
851 panfrost_upload_tex(ctx
, ctx
->sampler_views
[t
][i
]);
853 trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
856 if (t
== PIPE_SHADER_FRAGMENT
)
857 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
858 else if (t
== PIPE_SHADER_VERTEX
)
859 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
865 struct sysval_uniform
{
873 static void panfrost_upload_viewport_scale_sysval(struct panfrost_context
*ctx
,
874 struct sysval_uniform
*uniform
)
876 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
878 uniform
->f
[0] = vp
->scale
[0];
879 uniform
->f
[1] = vp
->scale
[1];
880 uniform
->f
[2] = vp
->scale
[2];
883 static void panfrost_upload_viewport_offset_sysval(struct panfrost_context
*ctx
,
884 struct sysval_uniform
*uniform
)
886 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
888 uniform
->f
[0] = vp
->translate
[0];
889 uniform
->f
[1] = vp
->translate
[1];
890 uniform
->f
[2] = vp
->translate
[2];
893 static void panfrost_upload_txs_sysval(struct panfrost_context
*ctx
,
894 enum pipe_shader_type st
,
895 unsigned int sysvalid
,
896 struct sysval_uniform
*uniform
)
898 unsigned texidx
= PAN_SYSVAL_ID_TO_TXS_TEX_IDX(sysvalid
);
899 unsigned dim
= PAN_SYSVAL_ID_TO_TXS_DIM(sysvalid
);
900 bool is_array
= PAN_SYSVAL_ID_TO_TXS_IS_ARRAY(sysvalid
);
901 struct pipe_sampler_view
*tex
= &ctx
->sampler_views
[st
][texidx
]->base
;
904 uniform
->i
[0] = u_minify(tex
->texture
->width0
, tex
->u
.tex
.first_level
);
907 uniform
->i
[1] = u_minify(tex
->texture
->height0
,
908 tex
->u
.tex
.first_level
);
911 uniform
->i
[2] = u_minify(tex
->texture
->depth0
,
912 tex
->u
.tex
.first_level
);
915 uniform
->i
[dim
] = tex
->texture
->array_size
;
918 static void panfrost_upload_sysvals(struct panfrost_context
*ctx
, void *buf
,
919 struct panfrost_shader_state
*ss
,
920 enum pipe_shader_type st
)
922 struct sysval_uniform
*uniforms
= (void *)buf
;
924 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
925 int sysval
= ss
->sysval
[i
];
927 switch (PAN_SYSVAL_TYPE(sysval
)) {
928 case PAN_SYSVAL_VIEWPORT_SCALE
:
929 panfrost_upload_viewport_scale_sysval(ctx
, &uniforms
[i
]);
931 case PAN_SYSVAL_VIEWPORT_OFFSET
:
932 panfrost_upload_viewport_offset_sysval(ctx
, &uniforms
[i
]);
934 case PAN_SYSVAL_TEXTURE_SIZE
:
935 panfrost_upload_txs_sysval(ctx
, st
, PAN_SYSVAL_ID(sysval
),
945 panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer
*buf
, unsigned index
)
947 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
948 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
951 return rsrc
->bo
->cpu
;
952 else if (cb
->user_buffer
)
953 return cb
->user_buffer
;
955 unreachable("No constant buffer");
959 panfrost_map_constant_buffer_gpu(
960 struct panfrost_context
*ctx
,
961 struct panfrost_constant_buffer
*buf
,
964 struct pipe_constant_buffer
*cb
= &buf
->cb
[index
];
965 struct panfrost_resource
*rsrc
= pan_resource(cb
->buffer
);
968 return rsrc
->bo
->gpu
;
969 else if (cb
->user_buffer
)
970 return panfrost_upload_transient(ctx
, cb
->user_buffer
, cb
->buffer_size
);
972 unreachable("No constant buffer");
975 /* Compute number of UBOs active (more specifically, compute the highest UBO
976 * number addressable -- if there are gaps, include them in the count anyway).
977 * We always include UBO #0 in the count, since we *need* uniforms enabled for
981 panfrost_ubo_count(struct panfrost_context
*ctx
, enum pipe_shader_type stage
)
983 unsigned mask
= ctx
->constant_buffer
[stage
].enabled_mask
| 1;
984 return 32 - __builtin_clz(mask
);
987 /* Fixes up a shader state with current state, returning a GPU address to the
991 panfrost_patch_shader_state(
992 struct panfrost_context
*ctx
,
993 struct panfrost_shader_state
*ss
,
994 enum pipe_shader_type stage
,
997 ss
->tripipe
->texture_count
= ctx
->sampler_view_count
[stage
];
998 ss
->tripipe
->sampler_count
= ctx
->sampler_count
[stage
];
1000 ss
->tripipe
->midgard1
.flags
= 0x220;
1002 unsigned ubo_count
= panfrost_ubo_count(ctx
, stage
);
1003 ss
->tripipe
->midgard1
.uniform_buffer_count
= ubo_count
;
1005 /* We can't reuse over frames; that's not safe. The descriptor must be
1006 * transient uploaded */
1008 if (should_upload
) {
1009 return panfrost_upload_transient(ctx
,
1011 sizeof(struct mali_shader_meta
));
1014 /* If we don't need an upload, don't bother */
1019 /* Go through dirty flags and actualise them in the cmdstream. */
1022 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1024 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1026 panfrost_attach_vt_framebuffer(ctx
, true);
1028 if (with_vertex_data
) {
1029 panfrost_emit_vertex_data(job
);
1031 /* Varyings emitted for -all- geometry */
1032 unsigned total_count
= ctx
->padded_count
* ctx
->instance_count
;
1033 panfrost_emit_varying_descriptor(ctx
, total_count
);
1036 bool msaa
= ctx
->rasterizer
->base
.multisample
;
1038 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1039 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1041 /* TODO: Sample size */
1042 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
1043 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
1046 panfrost_job_set_requirements(ctx
, job
);
1048 if (ctx
->occlusion_query
) {
1049 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1050 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1053 /* TODO: Does it make sense to dirty track VS? We need the transient
1055 ctx
->dirty
|= PAN_DIRTY_VS
;
1056 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1059 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1061 ctx
->payload_vertex
.postfix
._shader_upper
=
1062 panfrost_patch_shader_state(ctx
, vs
, PIPE_SHADER_VERTEX
, true) >> 4;
1065 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1066 /* Check if we need to link the gl_PointSize varying */
1067 if (!panfrost_writes_point_size(ctx
)) {
1068 /* If the size is constant, write it out. Otherwise,
1069 * don't touch primitive_size (since we would clobber
1070 * the pointer there) */
1072 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1076 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1078 ctx
->dirty
|= PAN_DIRTY_FS
;
1080 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1082 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1084 panfrost_patch_shader_state(ctx
, variant
, PIPE_SHADER_FRAGMENT
, false);
1086 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1089 COPY(attribute_count
);
1090 COPY(varying_count
);
1091 COPY(texture_count
);
1092 COPY(sampler_count
);
1093 COPY(sampler_count
);
1094 COPY(midgard1
.uniform_count
);
1095 COPY(midgard1
.uniform_buffer_count
);
1096 COPY(midgard1
.work_count
);
1097 COPY(midgard1
.flags
);
1098 COPY(midgard1
.unknown2
);
1102 /* Get blending setup */
1103 struct panfrost_blend_final blend
=
1104 panfrost_get_blend_for_context(ctx
, 0);
1106 /* If there is a blend shader, work registers are shared */
1108 if (blend
.is_shader
)
1109 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1111 /* Set late due to depending on render state */
1112 unsigned flags
= ctx
->fragment_shader_core
.midgard1
.flags
;
1114 /* Depending on whether it's legal to in the given shader, we
1115 * try to enable early-z testing (or forward-pixel kill?) */
1117 if (!variant
->can_discard
)
1118 flags
|= MALI_EARLY_Z
;
1120 /* Any time texturing is used, derivatives are implicitly
1121 * calculated, so we need to enable helper invocations */
1123 if (ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
])
1124 flags
|= MALI_HELPER_INVOCATIONS
;
1126 ctx
->fragment_shader_core
.midgard1
.flags
= flags
;
1128 /* Assign the stencil refs late */
1129 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1130 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1132 /* CAN_DISCARD should be set if the fragment shader possibly
1133 * contains a 'discard' instruction. It is likely this is
1134 * related to optimizations related to forward-pixel kill, as
1135 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1136 * thing?" by Peter Harris
1139 if (variant
->can_discard
) {
1140 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1141 ctx
->fragment_shader_core
.midgard1
.flags
|= 0x400;
1144 /* Check if we're using the default blend descriptor (fast path) */
1148 (blend
.equation
.equation
->rgb_mode
== 0x122) &&
1149 (blend
.equation
.equation
->alpha_mode
== 0x122) &&
1150 (blend
.equation
.equation
->color_mask
== 0xf);
1152 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1153 * *also* copied to the blend_meta appended (by convention),
1154 * but this is the field actually read by the hardware. (Or
1155 * maybe both are read...?) */
1157 if (blend
.is_shader
) {
1158 ctx
->fragment_shader_core
.blend
.shader
=
1161 ctx
->fragment_shader_core
.blend
.shader
= 0;
1164 if (ctx
->require_sfbd
) {
1165 /* When only a single render target platform is used, the blend
1166 * information is inside the shader meta itself. We
1167 * additionally need to signal CAN_DISCARD for nontrivial blend
1168 * modes (so we're able to read back the destination buffer) */
1170 if (!blend
.is_shader
) {
1171 ctx
->fragment_shader_core
.blend
.equation
=
1172 *blend
.equation
.equation
;
1173 ctx
->fragment_shader_core
.blend
.constant
=
1174 blend
.equation
.constant
;
1178 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1182 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1183 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1184 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1186 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1188 if (!ctx
->require_sfbd
) {
1189 /* Additional blend descriptor tacked on for jobs using MFBD */
1191 unsigned blend_count
= 0x200;
1193 if (blend
.is_shader
) {
1194 /* For a blend shader, the bottom nibble corresponds to
1195 * the number of work registers used, which signals the
1196 * -existence- of a blend shader */
1198 assert(blend
.shader
.work_count
>= 2);
1199 blend_count
|= MIN2(blend
.shader
.work_count
, 3);
1201 /* Otherwise, the bottom bit simply specifies if
1202 * blending (anything other than REPLACE) is enabled */
1209 struct midgard_blend_rt rts
[4];
1213 for (unsigned i
= 0; i
< 1; ++i
) {
1215 (ctx
->pipe_framebuffer
.nr_cbufs
> i
) &&
1216 util_format_is_srgb(ctx
->pipe_framebuffer
.cbufs
[i
]->format
);
1218 rts
[i
].flags
= blend_count
;
1221 rts
[i
].flags
|= MALI_BLEND_SRGB
;
1223 /* TODO: sRGB in blend shaders is currently
1224 * unimplemented. Contact me (Alyssa) if you're
1225 * interested in working on this. We have
1226 * native Midgard ops for helping here, but
1227 * they're not well-understood yet. */
1229 assert(!(is_srgb
&& blend
.is_shader
));
1231 if (blend
.is_shader
) {
1232 rts
[i
].blend
.shader
= blend
.shader
.gpu
;
1234 rts
[i
].blend
.equation
= *blend
.equation
.equation
;
1235 rts
[i
].blend
.constant
= blend
.equation
.constant
;
1239 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1243 /* We stage to transient, so always dirty.. */
1244 panfrost_stage_attributes(ctx
);
1246 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
)
1247 panfrost_upload_sampler_descriptors(ctx
);
1249 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
)
1250 panfrost_upload_texture_descriptors(ctx
);
1252 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1254 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1255 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1257 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1258 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1259 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1261 /* Uniforms are implicitly UBO #0 */
1262 bool has_uniforms
= buf
->enabled_mask
& (1 << 0);
1264 /* Allocate room for the sysval and the uniforms */
1265 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1266 size_t uniform_size
= has_uniforms
? (buf
->cb
[0].buffer_size
) : 0;
1267 size_t size
= sys_size
+ uniform_size
;
1268 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1270 /* Upload sysvals requested by the shader */
1271 panfrost_upload_sysvals(ctx
, transfer
.cpu
, ss
, i
);
1273 /* Upload uniforms */
1275 const void *cpu
= panfrost_map_constant_buffer_cpu(buf
, 0);
1276 memcpy(transfer
.cpu
+ sys_size
, cpu
, uniform_size
);
1279 int uniform_count
= 0;
1281 struct mali_vertex_tiler_postfix
*postfix
;
1284 case PIPE_SHADER_VERTEX
:
1285 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1286 postfix
= &ctx
->payload_vertex
.postfix
;
1289 case PIPE_SHADER_FRAGMENT
:
1290 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1291 postfix
= &ctx
->payload_tiler
.postfix
;
1295 unreachable("Invalid shader stage\n");
1298 /* Next up, attach UBOs. UBO #0 is the uniforms we just
1301 unsigned ubo_count
= panfrost_ubo_count(ctx
, i
);
1302 assert(ubo_count
>= 1);
1304 size_t sz
= sizeof(struct mali_uniform_buffer_meta
) * ubo_count
;
1305 struct mali_uniform_buffer_meta ubos
[PAN_MAX_CONST_BUFFERS
];
1307 /* Upload uniforms as a UBO */
1308 ubos
[0].size
= MALI_POSITIVE((2 + uniform_count
));
1309 ubos
[0].ptr
= transfer
.gpu
>> 2;
1311 /* The rest are honest-to-goodness UBOs */
1313 for (unsigned ubo
= 1; ubo
< ubo_count
; ++ubo
) {
1314 size_t sz
= buf
->cb
[ubo
].buffer_size
;
1316 bool enabled
= buf
->enabled_mask
& (1 << ubo
);
1317 bool empty
= sz
== 0;
1319 if (!enabled
|| empty
) {
1320 /* Stub out disabled UBOs to catch accesses */
1323 ubos
[ubo
].ptr
= 0xDEAD0000;
1327 mali_ptr gpu
= panfrost_map_constant_buffer_gpu(ctx
, buf
, ubo
);
1329 unsigned bytes_per_field
= 16;
1330 unsigned aligned
= ALIGN_POT(sz
, bytes_per_field
);
1331 unsigned fields
= aligned
/ bytes_per_field
;
1333 ubos
[ubo
].size
= MALI_POSITIVE(fields
);
1334 ubos
[ubo
].ptr
= gpu
>> 2;
1337 mali_ptr ubufs
= panfrost_upload_transient(ctx
, ubos
, sz
);
1338 postfix
->uniforms
= transfer
.gpu
;
1339 postfix
->uniform_buffers
= ubufs
;
1341 buf
->dirty_mask
= 0;
1344 /* TODO: Upload the viewport somewhere more appropriate */
1346 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1347 * (somewhat) asymmetric ints. */
1348 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1350 struct mali_viewport view
= {
1351 /* By default, do no viewport clipping, i.e. clip to (-inf,
1352 * inf) in each direction. Clipping to the viewport in theory
1353 * should work, but in practice causes issues when we're not
1354 * explicitly trying to scissor */
1356 .clip_minx
= -INFINITY
,
1357 .clip_miny
= -INFINITY
,
1358 .clip_maxx
= INFINITY
,
1359 .clip_maxy
= INFINITY
,
1365 /* Always scissor to the viewport by default. */
1366 int minx
= (int) (vp
->translate
[0] - vp
->scale
[0]);
1367 int maxx
= (int) (vp
->translate
[0] + vp
->scale
[0]);
1369 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1370 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1372 /* Apply the scissor test */
1374 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1381 /* Hardware needs the min/max to be strictly ordered, so flip if we
1382 * need to. The viewport transformation in the vertex shader will
1383 * handle the negatives if we don't */
1397 /* Clamp everything positive, just in case */
1399 maxx
= MAX2(0, maxx
);
1400 maxy
= MAX2(0, maxy
);
1401 minx
= MAX2(0, minx
);
1402 miny
= MAX2(0, miny
);
1404 /* Clamp to the framebuffer size as a last check */
1406 minx
= MIN2(ctx
->pipe_framebuffer
.width
, minx
);
1407 maxx
= MIN2(ctx
->pipe_framebuffer
.width
, maxx
);
1409 miny
= MIN2(ctx
->pipe_framebuffer
.height
, miny
);
1410 maxy
= MIN2(ctx
->pipe_framebuffer
.height
, maxy
);
1412 /* Update the job, unless we're doing wallpapering (whose lack of
1413 * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll
1414 * just... be faster :) */
1416 if (!ctx
->wallpaper_batch
)
1417 panfrost_job_union_scissor(job
, minx
, miny
, maxx
, maxy
);
1421 view
.viewport0
[0] = minx
;
1422 view
.viewport1
[0] = MALI_POSITIVE(maxx
);
1424 view
.viewport0
[1] = miny
;
1425 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1427 ctx
->payload_tiler
.postfix
.viewport
=
1428 panfrost_upload_transient(ctx
,
1430 sizeof(struct mali_viewport
));
1435 /* Corresponds to exactly one draw, but does not submit anything */
1438 panfrost_queue_draw(struct panfrost_context
*ctx
)
1440 /* Handle dirty flags now */
1441 panfrost_emit_for_draw(ctx
, true);
1443 /* If rasterizer discard is enable, only submit the vertex */
1445 bool rasterizer_discard
= ctx
->rasterizer
1446 && ctx
->rasterizer
->base
.rasterizer_discard
;
1448 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1449 struct panfrost_transfer tiler
;
1451 if (!rasterizer_discard
)
1452 tiler
= panfrost_vertex_tiler_job(ctx
, true);
1454 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1456 if (rasterizer_discard
)
1457 panfrost_scoreboard_queue_vertex_job(batch
, vertex
, FALSE
);
1458 else if (ctx
->wallpaper_batch
)
1459 panfrost_scoreboard_queue_fused_job_prepend(batch
, vertex
, tiler
);
1461 panfrost_scoreboard_queue_fused_job(batch
, vertex
, tiler
);
1464 /* The entire frame is in memory -- send it off to the kernel! */
1467 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1468 struct pipe_fence_handle
**fence
,
1469 struct panfrost_job
*job
)
1471 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1472 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1476 panfrost_job_submit(ctx
, job
);
1478 /* If visual, we can stall a frame */
1480 if (!flush_immediate
)
1481 panfrost_drm_force_flush_fragment(ctx
, fence
);
1483 screen
->last_fragment_flushed
= false;
1484 screen
->last_job
= job
;
1486 /* If readback, flush now (hurts the pipelined performance) */
1487 if (flush_immediate
)
1488 panfrost_drm_force_flush_fragment(ctx
, fence
);
1493 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1495 struct panfrost_context
*ctx
= pan_context(pipe
);
1497 /* Nothing to reload? TODO: MRT wallpapers */
1498 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1501 /* Check if the buffer has any content on it worth preserving */
1503 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[0];
1504 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
1505 unsigned level
= surf
->u
.tex
.level
;
1507 if (!rsrc
->slices
[level
].initialized
)
1510 /* Save the batch */
1511 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1513 ctx
->wallpaper_batch
= batch
;
1514 panfrost_blit_wallpaper(ctx
);
1515 ctx
->wallpaper_batch
= NULL
;
1520 struct pipe_context
*pipe
,
1521 struct pipe_fence_handle
**fence
,
1524 struct panfrost_context
*ctx
= pan_context(pipe
);
1525 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1527 /* Nothing to do! */
1528 if (!job
->last_job
.gpu
&& !job
->clear
) return;
1531 panfrost_draw_wallpaper(&ctx
->base
);
1533 /* Whether to stall the pipeline for immediately correct results. Since
1534 * pipelined rendering is quite broken right now (to be fixed by the
1535 * panfrost_job refactor, just take the perf hit for correctness) */
1536 bool flush_immediate
= /*flags & PIPE_FLUSH_END_OF_FRAME*/true;
1538 /* Submit the frame itself */
1539 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1541 /* Prepare for the next frame */
1542 panfrost_invalidate_frame(ctx
);
1545 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1548 g2m_draw_mode(enum pipe_prim_type mode
)
1551 DEFINE_CASE(POINTS
);
1553 DEFINE_CASE(LINE_LOOP
);
1554 DEFINE_CASE(LINE_STRIP
);
1555 DEFINE_CASE(TRIANGLES
);
1556 DEFINE_CASE(TRIANGLE_STRIP
);
1557 DEFINE_CASE(TRIANGLE_FAN
);
1559 DEFINE_CASE(QUAD_STRIP
);
1560 DEFINE_CASE(POLYGON
);
1563 unreachable("Invalid draw mode");
1570 panfrost_translate_index_size(unsigned size
)
1574 return MALI_DRAW_INDEXED_UINT8
;
1577 return MALI_DRAW_INDEXED_UINT16
;
1580 return MALI_DRAW_INDEXED_UINT32
;
1583 unreachable("Invalid index size");
1587 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1588 * good for the duration of the draw (transient), could last longer */
1591 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1593 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1595 off_t offset
= info
->start
* info
->index_size
;
1596 struct panfrost_job
*batch
= panfrost_get_job_for_fbo(ctx
);
1598 if (!info
->has_user_indices
) {
1599 /* Only resources can be directly mapped */
1600 panfrost_job_add_bo(batch
, rsrc
->bo
);
1601 return rsrc
->bo
->gpu
+ offset
;
1603 /* Otherwise, we need to upload to transient memory */
1604 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1605 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1610 panfrost_scissor_culls_everything(struct panfrost_context
*ctx
)
1612 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1614 /* Check if we're scissoring at all */
1616 if (!(ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
))
1619 return (ss
->minx
== ss
->maxx
) || (ss
->miny
== ss
->maxy
);
1624 struct pipe_context
*pipe
,
1625 const struct pipe_draw_info
*info
)
1627 struct panfrost_context
*ctx
= pan_context(pipe
);
1629 /* First of all, check the scissor to see if anything is drawn at all.
1630 * If it's not, we drop the draw (mostly a conformance issue;
1631 * well-behaved apps shouldn't hit this) */
1633 if (panfrost_scissor_culls_everything(ctx
))
1636 ctx
->payload_vertex
.draw_start
= info
->start
;
1637 ctx
->payload_tiler
.draw_start
= info
->start
;
1639 int mode
= info
->mode
;
1641 /* Fallback unsupported restart index */
1642 unsigned primitive_index
= (1 << (info
->index_size
* 8)) - 1;
1644 if (info
->primitive_restart
&& info
->index_size
1645 && info
->restart_index
!= primitive_index
) {
1646 util_draw_vbo_without_prim_restart(pipe
, info
);
1650 /* Fallback for unsupported modes */
1652 if (!(ctx
->draw_modes
& (1 << mode
))) {
1653 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1654 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1656 if (info
->count
< 4) {
1657 /* Degenerate case? */
1661 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1662 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1667 /* Now that we have a guaranteed terminating path, find the job.
1668 * Assignment commented out to prevent unused warning */
1670 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1672 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1674 ctx
->vertex_count
= info
->count
;
1675 ctx
->instance_count
= info
->instance_count
;
1677 /* For non-indexed draws, they're the same */
1678 unsigned vertex_count
= ctx
->vertex_count
;
1680 unsigned draw_flags
= 0;
1682 /* The draw flags interpret how primitive size is interpreted */
1684 if (panfrost_writes_point_size(ctx
))
1685 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1687 if (info
->primitive_restart
)
1688 draw_flags
|= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX
;
1690 /* For higher amounts of vertices (greater than what fits in a 16-bit
1691 * short), the other value is needed, otherwise there will be bizarre
1692 * rendering artefacts. It's not clear what these values mean yet. This
1693 * change is also needed for instancing and sometimes points (perhaps
1694 * related to dynamically setting gl_PointSize) */
1696 bool is_points
= mode
== PIPE_PRIM_POINTS
;
1697 bool many_verts
= ctx
->vertex_count
> 0xFFFF;
1698 bool instanced
= ctx
->instance_count
> 1;
1700 draw_flags
|= (is_points
|| many_verts
|| instanced
) ? 0x3000 : 0x18000;
1702 /* This doesn't make much sense */
1703 if (mode
== PIPE_PRIM_LINE_STRIP
) {
1704 draw_flags
|= 0x800;
1707 if (info
->index_size
) {
1708 /* Calculate the min/max index used so we can figure out how
1709 * many times to invoke the vertex shader */
1711 /* Fetch / calculate index bounds */
1712 unsigned min_index
= 0, max_index
= 0;
1714 if (info
->max_index
== ~0u) {
1715 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1717 min_index
= info
->min_index
;
1718 max_index
= info
->max_index
;
1721 /* Use the corresponding values */
1722 vertex_count
= max_index
- min_index
+ 1;
1723 ctx
->payload_vertex
.draw_start
= min_index
;
1724 ctx
->payload_tiler
.draw_start
= min_index
;
1726 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1727 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1729 //assert(!info->restart_index); /* TODO: Research */
1730 assert(!info
->index_bias
);
1732 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1733 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1735 /* Index count == vertex count, if no indexing is applied, as
1736 * if it is internally indexed in the expected order */
1738 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1739 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1741 /* Reverse index state */
1742 ctx
->payload_tiler
.prefix
.indices
= (u64
) NULL
;
1745 /* Dispatch "compute jobs" for the vertex/tiler pair as (1,
1746 * vertex_count, 1) */
1748 panfrost_pack_work_groups_fused(
1749 &ctx
->payload_vertex
.prefix
,
1750 &ctx
->payload_tiler
.prefix
,
1751 1, vertex_count
, info
->instance_count
,
1754 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1756 /* Encode the padded vertex count */
1758 if (info
->instance_count
> 1) {
1759 /* Triangles have non-even vertex counts so they change how
1760 * padding works internally */
1763 mode
== PIPE_PRIM_TRIANGLES
||
1764 mode
== PIPE_PRIM_TRIANGLE_STRIP
||
1765 mode
== PIPE_PRIM_TRIANGLE_FAN
;
1767 struct pan_shift_odd so
=
1768 panfrost_padded_vertex_count(vertex_count
, !is_triangle
);
1770 ctx
->payload_vertex
.instance_shift
= so
.shift
;
1771 ctx
->payload_tiler
.instance_shift
= so
.shift
;
1773 ctx
->payload_vertex
.instance_odd
= so
.odd
;
1774 ctx
->payload_tiler
.instance_odd
= so
.odd
;
1776 ctx
->padded_count
= pan_expand_shift_odd(so
);
1778 ctx
->padded_count
= ctx
->vertex_count
;
1780 /* Reset instancing state */
1781 ctx
->payload_vertex
.instance_shift
= 0;
1782 ctx
->payload_vertex
.instance_odd
= 0;
1783 ctx
->payload_tiler
.instance_shift
= 0;
1784 ctx
->payload_tiler
.instance_odd
= 0;
1787 /* Fire off the draw itself */
1788 panfrost_queue_draw(ctx
);
1794 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1800 panfrost_create_rasterizer_state(
1801 struct pipe_context
*pctx
,
1802 const struct pipe_rasterizer_state
*cso
)
1804 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1808 /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
1809 so
->tiler_gl_enables
= 0x7;
1812 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1814 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1815 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1817 if (cso
->cull_face
& PIPE_FACE_BACK
)
1818 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1824 panfrost_bind_rasterizer_state(
1825 struct pipe_context
*pctx
,
1828 struct panfrost_context
*ctx
= pan_context(pctx
);
1830 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1834 ctx
->rasterizer
= hwcso
;
1835 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1837 ctx
->fragment_shader_core
.depth_units
= ctx
->rasterizer
->base
.offset_units
;
1838 ctx
->fragment_shader_core
.depth_factor
= ctx
->rasterizer
->base
.offset_scale
;
1840 /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */
1841 assert(ctx
->rasterizer
->base
.offset_clamp
== 0.0);
1843 /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */
1845 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_A
, ctx
->rasterizer
->base
.offset_tri
);
1846 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_DEPTH_RANGE_B
, ctx
->rasterizer
->base
.offset_tri
);
1848 /* Point sprites are emulated */
1850 struct panfrost_shader_state
*variant
=
1851 ctx
->fs
? &ctx
->fs
->variants
[ctx
->fs
->active_variant
] : NULL
;
1853 if (ctx
->rasterizer
->base
.sprite_coord_enable
|| (variant
&& variant
->point_sprite_mask
))
1854 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
1858 panfrost_create_vertex_elements_state(
1859 struct pipe_context
*pctx
,
1860 unsigned num_elements
,
1861 const struct pipe_vertex_element
*elements
)
1863 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1865 so
->num_elements
= num_elements
;
1866 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1868 for (int i
= 0; i
< num_elements
; ++i
) {
1869 so
->hw
[i
].index
= i
;
1871 enum pipe_format fmt
= elements
[i
].src_format
;
1872 const struct util_format_description
*desc
= util_format_description(fmt
);
1873 so
->hw
[i
].unknown1
= 0x2;
1874 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1876 so
->hw
[i
].format
= panfrost_find_format(desc
);
1878 /* The field itself should probably be shifted over */
1879 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1886 panfrost_bind_vertex_elements_state(
1887 struct pipe_context
*pctx
,
1890 struct panfrost_context
*ctx
= pan_context(pctx
);
1892 ctx
->vertex
= hwcso
;
1893 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1897 panfrost_create_shader_state(
1898 struct pipe_context
*pctx
,
1899 const struct pipe_shader_state
*cso
)
1901 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1904 /* Token deep copy to prevent memory corruption */
1906 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1907 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1913 panfrost_delete_shader_state(
1914 struct pipe_context
*pctx
,
1917 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1919 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1920 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1927 panfrost_create_sampler_state(
1928 struct pipe_context
*pctx
,
1929 const struct pipe_sampler_state
*cso
)
1931 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1934 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1936 struct mali_sampler_descriptor sampler_descriptor
= {
1937 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1938 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1939 | translate_mip_filter(cso
->min_mip_filter
)
1942 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1943 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1944 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1945 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1947 cso
->border_color
.f
[0],
1948 cso
->border_color
.f
[1],
1949 cso
->border_color
.f
[2],
1950 cso
->border_color
.f
[3]
1952 .min_lod
= FIXED_16(cso
->min_lod
),
1953 .max_lod
= FIXED_16(cso
->max_lod
),
1954 .seamless_cube_map
= cso
->seamless_cube_map
,
1957 /* If necessary, we disable mipmapping in the sampler descriptor by
1958 * clamping the LOD as tight as possible (from 0 to epsilon,
1959 * essentially -- remember these are fixed point numbers, so
1962 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
)
1963 sampler_descriptor
.max_lod
= sampler_descriptor
.min_lod
;
1965 /* Enforce that there is something in the middle by adding epsilon*/
1967 if (sampler_descriptor
.min_lod
== sampler_descriptor
.max_lod
)
1968 sampler_descriptor
.max_lod
++;
1971 assert(sampler_descriptor
.max_lod
> sampler_descriptor
.min_lod
);
1973 so
->hw
= sampler_descriptor
;
1979 panfrost_bind_sampler_states(
1980 struct pipe_context
*pctx
,
1981 enum pipe_shader_type shader
,
1982 unsigned start_slot
, unsigned num_sampler
,
1985 assert(start_slot
== 0);
1987 struct panfrost_context
*ctx
= pan_context(pctx
);
1989 /* XXX: Should upload, not just copy? */
1990 ctx
->sampler_count
[shader
] = num_sampler
;
1991 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1993 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1997 panfrost_variant_matches(
1998 struct panfrost_context
*ctx
,
1999 struct panfrost_shader_state
*variant
,
2000 enum pipe_shader_type type
)
2002 struct pipe_rasterizer_state
*rasterizer
= &ctx
->rasterizer
->base
;
2003 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
2005 bool is_fragment
= (type
== PIPE_SHADER_FRAGMENT
);
2007 if (is_fragment
&& (alpha
->enabled
|| variant
->alpha_state
.enabled
)) {
2008 /* Make sure enable state is at least the same */
2009 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
2013 /* Check that the contents of the test are the same */
2014 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
2015 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
2017 if (!(same_func
&& same_ref
)) {
2022 if (is_fragment
&& rasterizer
&& (rasterizer
->sprite_coord_enable
|
2023 variant
->point_sprite_mask
)) {
2024 /* Ensure the same varyings are turned to point sprites */
2025 if (rasterizer
->sprite_coord_enable
!= variant
->point_sprite_mask
)
2028 /* Ensure the orientation is correct */
2030 rasterizer
->sprite_coord_mode
==
2031 PIPE_SPRITE_COORD_UPPER_LEFT
;
2033 if (variant
->point_sprite_upper_left
!= upper_left
)
2037 /* Otherwise, we're good to go */
2042 panfrost_bind_shader_state(
2043 struct pipe_context
*pctx
,
2045 enum pipe_shader_type type
)
2047 struct panfrost_context
*ctx
= pan_context(pctx
);
2049 if (type
== PIPE_SHADER_FRAGMENT
) {
2051 ctx
->dirty
|= PAN_DIRTY_FS
;
2053 assert(type
== PIPE_SHADER_VERTEX
);
2055 ctx
->dirty
|= PAN_DIRTY_VS
;
2060 /* Match the appropriate variant */
2062 signed variant
= -1;
2063 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2065 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2066 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
], type
)) {
2072 if (variant
== -1) {
2073 /* No variant matched, so create a new one */
2074 variant
= variants
->variant_count
++;
2075 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2077 struct panfrost_shader_state
*v
=
2078 &variants
->variants
[variant
];
2082 if (type
== PIPE_SHADER_FRAGMENT
) {
2083 v
->alpha_state
= ctx
->depth_stencil
->alpha
;
2085 if (ctx
->rasterizer
) {
2086 v
->point_sprite_mask
= ctx
->rasterizer
->base
.sprite_coord_enable
;
2087 v
->point_sprite_upper_left
=
2088 ctx
->rasterizer
->base
.sprite_coord_mode
==
2089 PIPE_SPRITE_COORD_UPPER_LEFT
;
2093 variants
->variants
[variant
].tripipe
= malloc(sizeof(struct mali_shader_meta
));
2097 /* Select this variant */
2098 variants
->active_variant
= variant
;
2100 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2101 assert(panfrost_variant_matches(ctx
, shader_state
, type
));
2103 /* We finally have a variant, so compile it */
2105 if (!shader_state
->compiled
) {
2106 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
,
2107 panfrost_job_type_for_pipe(type
), shader_state
);
2109 shader_state
->compiled
= true;
2114 panfrost_bind_vs_state(struct pipe_context
*pctx
, void *hwcso
)
2116 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_VERTEX
);
2120 panfrost_bind_fs_state(struct pipe_context
*pctx
, void *hwcso
)
2122 panfrost_bind_shader_state(pctx
, hwcso
, PIPE_SHADER_FRAGMENT
);
2126 panfrost_set_vertex_buffers(
2127 struct pipe_context
*pctx
,
2128 unsigned start_slot
,
2129 unsigned num_buffers
,
2130 const struct pipe_vertex_buffer
*buffers
)
2132 struct panfrost_context
*ctx
= pan_context(pctx
);
2134 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
2138 panfrost_set_constant_buffer(
2139 struct pipe_context
*pctx
,
2140 enum pipe_shader_type shader
, uint index
,
2141 const struct pipe_constant_buffer
*buf
)
2143 struct panfrost_context
*ctx
= pan_context(pctx
);
2144 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2146 util_copy_constant_buffer(&pbuf
->cb
[index
], buf
);
2148 unsigned mask
= (1 << index
);
2150 if (unlikely(!buf
)) {
2151 pbuf
->enabled_mask
&= ~mask
;
2152 pbuf
->dirty_mask
&= ~mask
;
2156 pbuf
->enabled_mask
|= mask
;
2157 pbuf
->dirty_mask
|= mask
;
2161 panfrost_set_stencil_ref(
2162 struct pipe_context
*pctx
,
2163 const struct pipe_stencil_ref
*ref
)
2165 struct panfrost_context
*ctx
= pan_context(pctx
);
2166 ctx
->stencil_ref
= *ref
;
2168 /* Shader core dirty */
2169 ctx
->dirty
|= PAN_DIRTY_FS
;
2172 static enum mali_texture_type
2173 panfrost_translate_texture_type(enum pipe_texture_target t
) {
2177 case PIPE_TEXTURE_1D
:
2178 case PIPE_TEXTURE_1D_ARRAY
:
2181 case PIPE_TEXTURE_2D
:
2182 case PIPE_TEXTURE_2D_ARRAY
:
2183 case PIPE_TEXTURE_RECT
:
2186 case PIPE_TEXTURE_3D
:
2189 case PIPE_TEXTURE_CUBE
:
2190 case PIPE_TEXTURE_CUBE_ARRAY
:
2191 return MALI_TEX_CUBE
;
2194 unreachable("Unknown target");
2198 static struct pipe_sampler_view
*
2199 panfrost_create_sampler_view(
2200 struct pipe_context
*pctx
,
2201 struct pipe_resource
*texture
,
2202 const struct pipe_sampler_view
*template)
2204 struct panfrost_sampler_view
*so
= rzalloc(pctx
, struct panfrost_sampler_view
);
2205 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2207 pipe_reference(NULL
, &texture
->reference
);
2209 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2212 so
->base
= *template;
2213 so
->base
.texture
= texture
;
2214 so
->base
.reference
.count
= 1;
2215 so
->base
.context
= pctx
;
2217 /* sampler_views correspond to texture descriptors, minus the texture
2218 * (data) itself. So, we serialise the descriptor here and cache it for
2221 /* TODO: Detect from format better */
2222 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2224 unsigned char user_swizzle
[4] = {
2225 template->swizzle_r
,
2226 template->swizzle_g
,
2227 template->swizzle_b
,
2231 enum mali_format format
= panfrost_find_format(desc
);
2233 /* Check if we need to set a custom stride by computing the "expected"
2234 * stride and comparing it to what the BO actually wants. Only applies
2235 * to linear textures, since tiled/compressed textures have strict
2236 * alignment requirements for their strides as it is */
2238 unsigned first_level
= template->u
.tex
.first_level
;
2239 unsigned last_level
= template->u
.tex
.last_level
;
2241 if (prsrc
->layout
== PAN_LINEAR
) {
2242 for (unsigned l
= first_level
; l
<= last_level
; ++l
) {
2243 unsigned actual_stride
= prsrc
->slices
[l
].stride
;
2244 unsigned width
= u_minify(texture
->width0
, l
);
2245 unsigned comp_stride
= width
* bytes_per_pixel
;
2247 if (comp_stride
!= actual_stride
) {
2248 so
->manual_stride
= true;
2254 /* In the hardware, array_size refers specifically to array textures,
2255 * whereas in Gallium, it also covers cubemaps */
2257 unsigned array_size
= texture
->array_size
;
2259 if (template->target
== PIPE_TEXTURE_CUBE
) {
2260 /* TODO: Cubemap arrays */
2261 assert(array_size
== 6);
2265 struct mali_texture_descriptor texture_descriptor
= {
2266 .width
= MALI_POSITIVE(u_minify(texture
->width0
, first_level
)),
2267 .height
= MALI_POSITIVE(u_minify(texture
->height0
, first_level
)),
2268 .depth
= MALI_POSITIVE(u_minify(texture
->depth0
, first_level
)),
2269 .array_size
= MALI_POSITIVE(array_size
),
2273 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2276 .srgb
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
,
2277 .type
= panfrost_translate_texture_type(template->target
),
2280 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2283 texture_descriptor
.nr_mipmap_levels
= last_level
- first_level
;
2285 so
->hw
= texture_descriptor
;
2287 return (struct pipe_sampler_view
*) so
;
2291 panfrost_set_sampler_views(
2292 struct pipe_context
*pctx
,
2293 enum pipe_shader_type shader
,
2294 unsigned start_slot
, unsigned num_views
,
2295 struct pipe_sampler_view
**views
)
2297 struct panfrost_context
*ctx
= pan_context(pctx
);
2299 assert(start_slot
== 0);
2301 unsigned new_nr
= 0;
2302 for (unsigned i
= 0; i
< num_views
; ++i
) {
2307 ctx
->sampler_view_count
[shader
] = new_nr
;
2308 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2310 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2314 panfrost_sampler_view_destroy(
2315 struct pipe_context
*pctx
,
2316 struct pipe_sampler_view
*view
)
2318 pipe_resource_reference(&view
->texture
, NULL
);
2322 /* Hints that a framebuffer should use AFBC where possible */
2326 struct panfrost_screen
*screen
,
2327 const struct pipe_framebuffer_state
*fb
)
2329 /* AFBC implemenation incomplete; hide it */
2330 if (!(pan_debug
& PAN_DBG_AFBC
)) return;
2332 /* Hint AFBC to the resources bound to each color buffer */
2334 for (unsigned i
= 0; i
< fb
->nr_cbufs
; ++i
) {
2335 struct pipe_surface
*surf
= fb
->cbufs
[i
];
2336 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
2337 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2340 /* Also hint it to the depth buffer */
2343 struct panfrost_resource
*rsrc
= pan_resource(fb
->zsbuf
->texture
);
2344 panfrost_resource_hint_layout(screen
, rsrc
, PAN_AFBC
, 1);
2349 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2350 const struct pipe_framebuffer_state
*fb
)
2352 struct panfrost_context
*ctx
= pan_context(pctx
);
2354 /* Flush when switching framebuffers, but not if the framebuffer
2355 * state is being restored by u_blitter
2358 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
2359 bool is_scanout
= panfrost_is_scanout(ctx
);
2360 bool has_draws
= job
->last_job
.gpu
;
2362 if (!ctx
->wallpaper_batch
&& (!is_scanout
|| has_draws
)) {
2363 panfrost_flush(pctx
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2366 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2367 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2368 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2369 ctx
->pipe_framebuffer
.width
= fb
->width
;
2370 ctx
->pipe_framebuffer
.height
= fb
->height
;
2372 struct pipe_surface
*zb
= fb
->zsbuf
;
2373 bool needs_reattach
= false;
2375 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2376 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2378 /* check if changing cbuf */
2379 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2382 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2384 needs_reattach
|= (cb
!= NULL
);
2387 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2388 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2389 needs_reattach
|= (zb
!= NULL
);
2392 if (needs_reattach
) {
2393 /* Given that we're rendering, we'd love to have compression */
2394 struct panfrost_screen
*screen
= pan_screen(ctx
->base
.screen
);
2396 panfrost_hint_afbc(screen
, &ctx
->pipe_framebuffer
);
2398 if (ctx
->require_sfbd
)
2399 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
, ~0);
2401 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
, ~0);
2403 panfrost_attach_vt_framebuffer(ctx
, false);
2408 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2409 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2411 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2415 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2418 struct panfrost_context
*ctx
= pan_context(pipe
);
2419 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2420 ctx
->depth_stencil
= depth_stencil
;
2425 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2426 * emulated in the fragment shader */
2428 if (depth_stencil
->alpha
.enabled
) {
2429 /* We need to trigger a new shader (maybe) */
2430 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2434 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2436 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2437 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2439 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2440 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2442 /* Depth state (TODO: Refactor) */
2443 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2445 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2447 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2448 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2450 /* Bounds test not implemented */
2451 assert(!depth_stencil
->depth
.bounds_test
);
2453 ctx
->dirty
|= PAN_DIRTY_FS
;
2457 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2463 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2464 unsigned sample_mask
)
2469 panfrost_set_clip_state(struct pipe_context
*pipe
,
2470 const struct pipe_clip_state
*clip
)
2472 //struct panfrost_context *panfrost = pan_context(pipe);
2476 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2477 unsigned start_slot
,
2478 unsigned num_viewports
,
2479 const struct pipe_viewport_state
*viewports
)
2481 struct panfrost_context
*ctx
= pan_context(pipe
);
2483 assert(start_slot
== 0);
2484 assert(num_viewports
== 1);
2486 ctx
->pipe_viewport
= *viewports
;
2490 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2491 unsigned start_slot
,
2492 unsigned num_scissors
,
2493 const struct pipe_scissor_state
*scissors
)
2495 struct panfrost_context
*ctx
= pan_context(pipe
);
2497 assert(start_slot
== 0);
2498 assert(num_scissors
== 1);
2500 ctx
->scissor
= *scissors
;
2504 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2505 const struct pipe_poly_stipple
*stipple
)
2507 //struct panfrost_context *panfrost = pan_context(pipe);
2511 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2514 //struct panfrost_context *panfrost = pan_context(pipe);
2518 panfrost_destroy(struct pipe_context
*pipe
)
2520 struct panfrost_context
*panfrost
= pan_context(pipe
);
2521 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2523 if (panfrost
->blitter
)
2524 util_blitter_destroy(panfrost
->blitter
);
2526 if (panfrost
->blitter_wallpaper
)
2527 util_blitter_destroy(panfrost
->blitter_wallpaper
);
2529 panfrost_drm_free_slab(screen
, &panfrost
->scratchpad
);
2530 panfrost_drm_free_slab(screen
, &panfrost
->shaders
);
2531 panfrost_drm_free_slab(screen
, &panfrost
->tiler_heap
);
2532 panfrost_drm_free_slab(screen
, &panfrost
->tiler_polygon_list
);
2533 panfrost_drm_free_slab(screen
, &panfrost
->tiler_dummy
);
2538 static struct pipe_query
*
2539 panfrost_create_query(struct pipe_context
*pipe
,
2543 struct panfrost_query
*q
= rzalloc(pipe
, struct panfrost_query
);
2548 return (struct pipe_query
*) q
;
2552 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2558 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2560 struct panfrost_context
*ctx
= pan_context(pipe
);
2561 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2563 switch (query
->type
) {
2564 case PIPE_QUERY_OCCLUSION_COUNTER
:
2565 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2566 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2567 /* Allocate a word for the query results to be stored */
2568 query
->transfer
= panfrost_allocate_transient(ctx
, sizeof(unsigned));
2570 ctx
->occlusion_query
= query
;
2576 DBG("Skipping query %d\n", query
->type
);
2584 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2586 struct panfrost_context
*ctx
= pan_context(pipe
);
2587 ctx
->occlusion_query
= NULL
;
2592 panfrost_get_query_result(struct pipe_context
*pipe
,
2593 struct pipe_query
*q
,
2595 union pipe_query_result
*vresult
)
2598 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2600 /* We need to flush out the jobs to actually run the counter, TODO
2601 * check wait, TODO wallpaper after if needed */
2603 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2605 switch (query
->type
) {
2606 case PIPE_QUERY_OCCLUSION_COUNTER
:
2607 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2608 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2609 /* Read back the query results */
2610 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2611 unsigned passed
= *result
;
2613 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2614 vresult
->u64
= passed
;
2616 vresult
->b
= !!passed
;
2622 DBG("Skipped query get %d\n", query
->type
);
2629 static struct pipe_stream_output_target
*
2630 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2631 struct pipe_resource
*prsc
,
2632 unsigned buffer_offset
,
2633 unsigned buffer_size
)
2635 struct pipe_stream_output_target
*target
;
2637 target
= rzalloc(pctx
, struct pipe_stream_output_target
);
2642 pipe_reference_init(&target
->reference
, 1);
2643 pipe_resource_reference(&target
->buffer
, prsc
);
2645 target
->context
= pctx
;
2646 target
->buffer_offset
= buffer_offset
;
2647 target
->buffer_size
= buffer_size
;
2653 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2654 struct pipe_stream_output_target
*target
)
2656 pipe_resource_reference(&target
->buffer
, NULL
);
2657 ralloc_free(target
);
2661 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2662 unsigned num_targets
,
2663 struct pipe_stream_output_target
**targets
,
2664 const unsigned *offsets
)
2670 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2672 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2673 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2675 panfrost_drm_allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2676 panfrost_drm_allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2677 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2678 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_polygon_list
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2679 panfrost_drm_allocate_slab(screen
, &ctx
->tiler_dummy
, 1, false, PAN_ALLOCATE_INVISIBLE
, 0, 0);
2682 /* New context creation, which also does hardware initialisation since I don't
2683 * know the better way to structure this :smirk: */
2685 struct pipe_context
*
2686 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2688 struct panfrost_context
*ctx
= rzalloc(screen
, struct panfrost_context
);
2689 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2690 memset(ctx
, 0, sizeof(*ctx
));
2691 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2693 ctx
->is_t6xx
= pscreen
->gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2694 ctx
->require_sfbd
= pscreen
->gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2696 gallium
->screen
= screen
;
2698 gallium
->destroy
= panfrost_destroy
;
2700 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2702 gallium
->flush
= panfrost_flush
;
2703 gallium
->clear
= panfrost_clear
;
2704 gallium
->draw_vbo
= panfrost_draw_vbo
;
2706 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2707 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2709 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2711 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2712 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2713 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2715 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2716 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2717 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2719 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2720 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2721 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2723 gallium
->create_fs_state
= panfrost_create_shader_state
;
2724 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2725 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2727 gallium
->create_vs_state
= panfrost_create_shader_state
;
2728 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2729 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2731 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2732 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2733 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2735 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2736 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2737 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2739 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2741 gallium
->set_clip_state
= panfrost_set_clip_state
;
2742 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2743 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2744 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2745 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2747 gallium
->create_query
= panfrost_create_query
;
2748 gallium
->destroy_query
= panfrost_destroy_query
;
2749 gallium
->begin_query
= panfrost_begin_query
;
2750 gallium
->end_query
= panfrost_end_query
;
2751 gallium
->get_query_result
= panfrost_get_query_result
;
2753 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2754 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2755 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2757 panfrost_resource_context_init(gallium
);
2758 panfrost_blend_context_init(gallium
);
2760 panfrost_drm_init_context(ctx
);
2762 panfrost_setup_hardware(ctx
);
2765 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2766 gallium
->const_uploader
= gallium
->stream_uploader
;
2767 assert(gallium
->stream_uploader
);
2769 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2770 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2772 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2774 ctx
->blitter
= util_blitter_create(gallium
);
2775 ctx
->blitter_wallpaper
= util_blitter_create(gallium
);
2777 assert(ctx
->blitter
);
2778 assert(ctx
->blitter_wallpaper
);
2780 /* Prepare for render! */
2782 panfrost_job_init(ctx
);
2783 panfrost_emit_vertex_payload(ctx
);
2784 panfrost_emit_tiler_payload(ctx
);
2785 panfrost_invalidate_frame(ctx
);
2786 panfrost_default_shader_backend(ctx
);