2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
45 #include "pan_wallpaper.h"
47 static int performance_counter_number
= 0;
48 extern const char *pan_counters_base
;
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
54 * indepdent between color buffers and depth/stencil). To enable, we allocate
55 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
56 * edit the fragment job here. This routine should be called ONCE per
57 * AFBC-compressed buffer, rather than on every frame. */
60 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
62 if (ctx
->require_sfbd
) {
63 DBG("AFBC not supported yet on SFBD\n");
67 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
68 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
69 /* AFBC metadata is 16 bytes per tile */
70 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
71 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
72 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
73 int stride
= bytes_per_pixel
* ALIGN(rsrc
->base
.width0
, 16);
75 stride
*= 2; /* TODO: Should this be carried over? */
76 int main_size
= stride
* rsrc
->base
.height0
;
77 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
79 /* Allocate the AFBC slab itself, large enough to hold the above */
80 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
81 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
84 rsrc
->bo
->layout
= PAN_AFBC
;
86 /* Compressed textured reads use a tagged pointer to the metadata */
88 rsrc
->bo
->gpu
= rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
89 rsrc
->bo
->cpu
= rsrc
->bo
->afbc_slab
.cpu
;
90 rsrc
->bo
->gem_handle
= rsrc
->bo
->afbc_slab
.gem_handle
;
94 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
96 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
97 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
98 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
99 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
101 /* 8 byte checksum per tile */
102 rsrc
->bo
->checksum_stride
= tile_w
* 8;
103 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
104 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
106 rsrc
->bo
->has_checksum
= true;
109 /* Framebuffer descriptor */
112 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
114 fb
->width
= MALI_POSITIVE(w
);
115 fb
->height
= MALI_POSITIVE(h
);
117 /* No idea why this is needed, but it's how resolution_check is
118 * calculated. It's not clear to us yet why the hardware wants this.
119 * The formula itself was discovered mostly by manual bruteforce and
120 * aggressive algebraic simplification. */
122 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
125 struct mali_single_framebuffer
126 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
128 struct mali_single_framebuffer framebuffer
= {
130 .format
= 0x30000000,
131 .clear_flags
= 0x1000,
132 .unknown_address_0
= ctx
->scratchpad
.gpu
,
133 .unknown_address_1
= ctx
->misc_0
.gpu
,
134 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
136 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
137 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
140 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
145 struct bifrost_framebuffer
146 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
148 struct bifrost_framebuffer framebuffer
= {
149 /* It is not yet clear what tiler_meta means or how it's
150 * calculated, but we can tell the lower 32-bits are a
151 * (monotonically increasing?) function of tile count and
152 * geometry complexity; I suspect it defines a memory size of
153 * some kind? for the tiler. It's really unclear at the
154 * moment... but to add to the confusion, the hardware is happy
155 * enough to accept a zero in this field, so we don't even have
156 * to worry about it right now.
158 * The byte (just after the 32-bit mark) is much more
159 * interesting. The higher nibble I've only ever seen as 0xF,
160 * but the lower one I've seen as 0x0 or 0xF, and it's not
161 * obvious what the difference is. But what -is- obvious is
162 * that when the lower nibble is zero, performance is severely
163 * degraded compared to when the lower nibble is set.
164 * Evidently, that nibble enables some sort of fast path,
165 * perhaps relating to caching or tile flush? Regardless, at
166 * this point there's no clear reason not to set it, aside from
167 * substantially increased memory requirements (of the misc_0
170 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
172 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
173 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
174 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
175 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
180 .rt_count_1
= MALI_POSITIVE(1),
185 /* Corresponds to unknown_address_X of SFBD */
186 .scratchpad
= ctx
->scratchpad
.gpu
,
187 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
189 /* The constant added here is, like the lower word of
190 * tiler_meta, (loosely) another product of framebuffer size
191 * and geometry complexity. It must be sufficiently large for
192 * the tiler_meta fast path to work; if it's too small, there
193 * will be DATA_INVALID_FAULTs. Conversely, it must be less
194 * than the total size of misc_0, or else there's no room. It's
195 * possible this constant configures a partition between two
196 * parts of misc_0? We haven't investigated the functionality,
197 * as these buffers are internally used by the hardware
198 * (presumably by the tiler) but not seemingly touched by the driver
201 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
203 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
204 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
210 /* Are we currently rendering to the screen (rather than an FBO)? */
213 panfrost_is_scanout(struct panfrost_context
*ctx
)
215 /* If there is no color buffer, it's an FBO */
216 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
219 /* If we're too early that no framebuffer was sent, it's scanout */
220 if (!ctx
->pipe_framebuffer
.cbufs
[0])
223 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
224 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
225 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
228 /* Maps float 0.0-1.0 to int 0x00-0xFF */
230 normalised_float_to_u8(float f
)
232 return (uint8_t) (int) (f
* 255.0f
);
237 struct pipe_context
*pipe
,
239 const union pipe_color_union
*color
,
240 double depth
, unsigned stencil
)
242 struct panfrost_context
*ctx
= pan_context(pipe
);
243 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
245 if (buffers
& PIPE_CLEAR_COLOR
) {
246 /* Alpha clear only meaningful without alpha channel, TODO less ad hoc */
247 bool has_alpha
= util_format_has_alpha(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
248 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
250 uint32_t packed_color
=
251 (normalised_float_to_u8(clear_alpha
) << 24) |
252 (normalised_float_to_u8(color
->f
[2]) << 16) |
253 (normalised_float_to_u8(color
->f
[1]) << 8) |
254 (normalised_float_to_u8(color
->f
[0]) << 0);
256 job
->clear_color
= packed_color
;
260 if (buffers
& PIPE_CLEAR_DEPTH
) {
261 job
->clear_depth
= depth
;
264 if (buffers
& PIPE_CLEAR_STENCIL
) {
265 job
->clear_stencil
= stencil
;
268 job
->clear
|= buffers
;
272 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
274 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
275 struct bifrost_render_target rts_list
[] = {
280 .framebuffer
= ctx
->misc_0
.gpu
,
285 /* Allocate memory for the three components */
286 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
287 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
289 /* Opaque 1024-block */
290 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
292 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
293 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
295 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
299 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
301 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
305 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
307 mali_ptr framebuffer
= ctx
->require_sfbd
?
308 panfrost_attach_vt_sfbd(ctx
) :
309 panfrost_attach_vt_mfbd(ctx
);
311 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
312 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
315 /* Reset per-frame context, called on context initialisation as well as after
316 * flushing a frame */
319 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
321 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
322 DBG("Uploaded transient %d bytes\n", transient_count
);
324 /* Rotate cmdstream */
325 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
326 ctx
->cmdstream_i
= 0;
328 if (ctx
->require_sfbd
)
329 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
331 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
333 /* Reset varyings allocated */
334 ctx
->varying_height
= 0;
336 /* The transient cmdstream is dirty every frame; the only bits worth preserving
337 * (textures, shaders, etc) are in other buffers anyways */
339 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
340 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
342 /* Regenerate payloads */
343 panfrost_attach_vt_framebuffer(ctx
);
346 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
349 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
352 /* In practice, every field of these payloads should be configurable
353 * arbitrarily, which means these functions are basically catch-all's for
354 * as-of-yet unwavering unknowns */
357 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
359 struct midgard_payload_vertex_tiler payload
= {
361 .workgroups_z_shift
= 32,
362 .workgroups_x_shift_2
= 0x2,
363 .workgroups_x_shift_3
= 0x5,
365 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
368 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
372 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
374 struct midgard_payload_vertex_tiler payload
= {
376 .workgroups_z_shift
= 32,
377 .workgroups_x_shift_2
= 0x2,
378 .workgroups_x_shift_3
= 0x6,
380 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
384 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
388 translate_tex_wrap(enum pipe_tex_wrap w
)
391 case PIPE_TEX_WRAP_REPEAT
:
392 return MALI_WRAP_REPEAT
;
394 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
395 return MALI_WRAP_CLAMP_TO_EDGE
;
397 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
398 return MALI_WRAP_CLAMP_TO_BORDER
;
400 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
401 return MALI_WRAP_MIRRORED_REPEAT
;
410 translate_tex_filter(enum pipe_tex_filter f
)
413 case PIPE_TEX_FILTER_NEAREST
:
416 case PIPE_TEX_FILTER_LINEAR
:
426 translate_mip_filter(enum pipe_tex_mipfilter f
)
428 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
432 panfrost_translate_compare_func(enum pipe_compare_func in
)
435 case PIPE_FUNC_NEVER
:
436 return MALI_FUNC_NEVER
;
439 return MALI_FUNC_LESS
;
441 case PIPE_FUNC_EQUAL
:
442 return MALI_FUNC_EQUAL
;
444 case PIPE_FUNC_LEQUAL
:
445 return MALI_FUNC_LEQUAL
;
447 case PIPE_FUNC_GREATER
:
448 return MALI_FUNC_GREATER
;
450 case PIPE_FUNC_NOTEQUAL
:
451 return MALI_FUNC_NOTEQUAL
;
453 case PIPE_FUNC_GEQUAL
:
454 return MALI_FUNC_GEQUAL
;
456 case PIPE_FUNC_ALWAYS
:
457 return MALI_FUNC_ALWAYS
;
461 return 0; /* Unreachable */
465 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
468 case PIPE_FUNC_NEVER
:
469 return MALI_ALT_FUNC_NEVER
;
472 return MALI_ALT_FUNC_LESS
;
474 case PIPE_FUNC_EQUAL
:
475 return MALI_ALT_FUNC_EQUAL
;
477 case PIPE_FUNC_LEQUAL
:
478 return MALI_ALT_FUNC_LEQUAL
;
480 case PIPE_FUNC_GREATER
:
481 return MALI_ALT_FUNC_GREATER
;
483 case PIPE_FUNC_NOTEQUAL
:
484 return MALI_ALT_FUNC_NOTEQUAL
;
486 case PIPE_FUNC_GEQUAL
:
487 return MALI_ALT_FUNC_GEQUAL
;
489 case PIPE_FUNC_ALWAYS
:
490 return MALI_ALT_FUNC_ALWAYS
;
494 return 0; /* Unreachable */
498 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
501 case PIPE_STENCIL_OP_KEEP
:
502 return MALI_STENCIL_KEEP
;
504 case PIPE_STENCIL_OP_ZERO
:
505 return MALI_STENCIL_ZERO
;
507 case PIPE_STENCIL_OP_REPLACE
:
508 return MALI_STENCIL_REPLACE
;
510 case PIPE_STENCIL_OP_INCR
:
511 return MALI_STENCIL_INCR
;
513 case PIPE_STENCIL_OP_DECR
:
514 return MALI_STENCIL_DECR
;
516 case PIPE_STENCIL_OP_INCR_WRAP
:
517 return MALI_STENCIL_INCR_WRAP
;
519 case PIPE_STENCIL_OP_DECR_WRAP
:
520 return MALI_STENCIL_DECR_WRAP
;
522 case PIPE_STENCIL_OP_INVERT
:
523 return MALI_STENCIL_INVERT
;
527 return 0; /* Unreachable */
531 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
533 out
->ref
= 0; /* Gallium gets it from elsewhere */
535 out
->mask
= in
->valuemask
;
536 out
->func
= panfrost_translate_compare_func(in
->func
);
537 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
538 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
539 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
543 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
545 struct mali_shader_meta shader
= {
546 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
548 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
549 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
553 shader
.unknown2_4
|= 0x10;
556 struct pipe_stencil_state default_stencil
= {
558 .func
= PIPE_FUNC_ALWAYS
,
559 .fail_op
= MALI_STENCIL_KEEP
,
560 .zfail_op
= MALI_STENCIL_KEEP
,
561 .zpass_op
= MALI_STENCIL_KEEP
,
566 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
567 shader
.stencil_mask_front
= default_stencil
.writemask
;
569 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
570 shader
.stencil_mask_back
= default_stencil
.writemask
;
572 if (default_stencil
.enabled
)
573 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
575 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
578 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
579 * graphics command stream. It should be called once per draw, accordding to
580 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
581 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
584 struct panfrost_transfer
585 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
587 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
588 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
590 struct mali_job_descriptor_header job
= {
591 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
592 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
594 .job_descriptor_size
= 1,
598 /* Only non-elided tiler jobs have dependencies which are known at this point */
600 if (is_tiler
&& !is_elided_tiler
) {
601 /* Tiler jobs depend on vertex jobs */
603 job
.job_dependency_index_1
= draw_job_index
;
605 /* Tiler jobs also depend on the previous tiler job */
608 job
.job_dependency_index_2
= draw_job_index
- 1;
611 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
613 /* There's some padding hacks on 32-bit */
620 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
621 memcpy(transfer
.cpu
, &job
, sizeof(job
));
622 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
626 /* Generates a set value job. It's unclear what exactly this does, why it's
627 * necessary, and when to call it. */
630 panfrost_set_value_job(struct panfrost_context
*ctx
)
632 struct mali_job_descriptor_header job
= {
633 .job_type
= JOB_TYPE_SET_VALUE
,
634 .job_descriptor_size
= 1,
635 .job_index
= 1 + (2 * ctx
->draw_count
),
638 struct mali_payload_set_value payload
= {
639 .out
= ctx
->misc_0
.gpu
,
643 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
644 memcpy(transfer
.cpu
, &job
, sizeof(job
));
645 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
647 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
648 ctx
->set_value_job
= transfer
.gpu
;
652 panfrost_emit_varyings(
653 struct panfrost_context
*ctx
,
654 union mali_attr
*slot
,
658 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
660 /* Fill out the descriptor */
661 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
662 slot
->stride
= stride
;
663 slot
->size
= stride
* count
;
665 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
666 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
668 return varying_address
;
672 panfrost_emit_point_coord(union mali_attr
*slot
)
674 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
675 slot
->stride
= slot
->size
= 0;
679 panfrost_emit_varying_descriptor(
680 struct panfrost_context
*ctx
,
681 unsigned invocation_count
)
683 /* Load the shaders */
685 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
686 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
688 /* Allocate the varying descriptor */
690 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
691 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
693 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
696 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
697 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
699 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
700 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
702 /* Buffer indices must be in this order per our convention */
703 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
706 /* General varyings -- use the VS's, since those are more likely to be
707 * accurate on desktop */
709 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
710 vs
->general_varying_stride
, invocation_count
);
712 /* fp32 vec4 gl_Position */
713 ctx
->payload_tiler
.postfix
.position_varying
=
714 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
715 sizeof(float) * 4, invocation_count
);
718 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
719 /* fp16 vec1 gl_PointSize */
720 ctx
->payload_tiler
.primitive_size
.pointer
=
721 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
722 2, invocation_count
);
725 if (fs
->reads_point_coord
) {
726 /* Special descriptor */
727 panfrost_emit_point_coord(&varyings
[idx
++]);
730 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
731 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
732 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
735 /* Emits attributes and varying descriptors, which should be called every draw,
736 * excepting some obscure circumstances */
739 panfrost_emit_vertex_data(struct panfrost_context
*ctx
)
741 /* TODO: Only update the dirtied buffers */
742 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
744 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
746 for (int i
= 0; i
< ctx
->vertex_buffer_count
; ++i
) {
747 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
748 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
750 /* Let's figure out the layout of the attributes in memory so
751 * we can be smart about size computation. The idea is to
752 * figure out the maximum src_offset, which tells us the latest
753 * spot a vertex could start. Meanwhile, we figure out the size
754 * of the attribute memory (assuming interleaved
755 * representation) and tack on the max src_offset for a
756 * reasonably good upper bound on the size.
758 * Proving correctness is left as an exercise to the reader.
761 unsigned max_src_offset
= 0;
763 for (unsigned j
= 0; j
< ctx
->vertex
->num_elements
; ++j
) {
764 if (ctx
->vertex
->pipe
[j
].vertex_buffer_index
!= i
) continue;
765 max_src_offset
= MAX2(max_src_offset
, ctx
->vertex
->pipe
[j
].src_offset
);
768 /* Offset vertex count by draw_start to make sure we upload enough */
769 attrs
[i
].stride
= buf
->stride
;
770 attrs
[i
].size
= buf
->stride
* (ctx
->payload_vertex
.draw_start
+ invocation_count
) + max_src_offset
;
772 /* Vertex elements are -already- GPU-visible, at
773 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
774 * it is not, for now we have to duplicate the buffer. */
776 mali_ptr effective_address
= rsrc
? (rsrc
->bo
->gpu
+ buf
->buffer_offset
) : 0;
778 if (effective_address
) {
779 attrs
[i
].elements
= panfrost_upload_transient(ctx
, rsrc
->bo
->cpu
+ buf
->buffer_offset
, attrs
[i
].size
) | MALI_ATTR_LINEAR
;
780 } else if (effective_address
) {
781 attrs
[i
].elements
= effective_address
| MALI_ATTR_LINEAR
;
787 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, ctx
->vertex_buffer_count
* sizeof(union mali_attr
));
789 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
792 /* Go through dirty flags and actualise them in the cmdstream. */
795 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
797 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
799 if (with_vertex_data
) {
800 panfrost_emit_vertex_data(ctx
);
803 bool msaa
= ctx
->rasterizer
->base
.multisample
;
805 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
806 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
808 /* TODO: Sample size */
809 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
810 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
813 /* Enable job requirements at draw-time */
816 job
->requirements
|= PAN_REQ_MSAA
;
818 if (ctx
->depth_stencil
->depth
.writemask
)
819 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
821 if (ctx
->occlusion_query
) {
822 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
823 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
826 if (ctx
->dirty
& PAN_DIRTY_VS
) {
829 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
831 /* Late shader descriptor assignments */
833 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
834 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
837 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
839 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
842 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
843 /* Check if we need to link the gl_PointSize varying */
845 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
847 bool needs_gl_point_size
= vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
849 if (!needs_gl_point_size
) {
850 /* If the size is constant, write it out. Otherwise,
851 * don't touch primitive_size (since we would clobber
852 * the pointer there) */
854 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
857 /* Set the flag for varying (pointer) point size if the shader needs that */
858 SET_BIT(ctx
->payload_tiler
.prefix
.unknown_draw
, MALI_DRAW_VARYING_SIZE
, needs_gl_point_size
);
861 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
863 ctx
->dirty
|= PAN_DIRTY_FS
;
865 if (ctx
->dirty
& PAN_DIRTY_FS
) {
867 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
869 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
872 COPY(attribute_count
);
874 COPY(midgard1
.uniform_count
);
875 COPY(midgard1
.work_count
);
876 COPY(midgard1
.unknown2
);
879 /* If there is a blend shader, work registers are shared */
881 if (ctx
->blend
->has_blend_shader
)
882 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
884 /* Set late due to depending on render state */
885 /* The one at the end seems to mean "1 UBO" */
886 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
888 /* Assign texture/sample count right before upload */
889 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
890 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
892 /* Assign the stencil refs late */
893 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
894 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
896 /* CAN_DISCARD should be set if the fragment shader possibly
897 * contains a 'discard' instruction. It is likely this is
898 * related to optimizations related to forward-pixel kill, as
899 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
900 * thing?" by Peter Harris
903 if (variant
->can_discard
) {
904 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
905 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
906 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
907 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
910 /* Check if we're using the default blend descriptor (fast path) */
913 !ctx
->blend
->has_blend_shader
&&
914 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
915 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
916 (ctx
->blend
->equation
.color_mask
== 0xf);
918 if (ctx
->require_sfbd
) {
919 /* When only a single render target platform is used, the blend
920 * information is inside the shader meta itself. We
921 * additionally need to signal CAN_DISCARD for nontrivial blend
922 * modes (so we're able to read back the destination buffer) */
924 if (ctx
->blend
->has_blend_shader
) {
925 ctx
->fragment_shader_core
.blend_shader
= ctx
->blend
->blend_shader
;
927 memcpy(&ctx
->fragment_shader_core
.blend_equation
, &ctx
->blend
->equation
, sizeof(ctx
->blend
->equation
));
931 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
935 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct mali_blend_meta
);
936 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
937 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
939 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
941 if (!ctx
->require_sfbd
) {
942 /* Additional blend descriptor tacked on for jobs using MFBD */
944 unsigned blend_count
= 0;
946 if (ctx
->blend
->has_blend_shader
) {
947 /* For a blend shader, the bottom nibble corresponds to
948 * the number of work registers used, which signals the
949 * -existence- of a blend shader */
951 assert(ctx
->blend
->blend_work_count
>= 2);
952 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
954 /* Otherwise, the bottom bit simply specifies if
955 * blending (anything other than REPLACE) is enabled */
962 /* Second blend equation is always a simple replace */
964 uint64_t replace_magic
= 0xf0122122;
965 struct mali_blend_equation replace_mode
;
966 memcpy(&replace_mode
, &replace_magic
, sizeof(replace_mode
));
968 struct mali_blend_meta blend_meta
[] = {
970 .unk1
= 0x200 | blend_count
,
971 .blend_equation_1
= ctx
->blend
->equation
,
972 .blend_equation_2
= replace_mode
976 if (ctx
->blend
->has_blend_shader
)
977 memcpy(&blend_meta
[0].blend_equation_1
, &ctx
->blend
->blend_shader
, sizeof(ctx
->blend
->blend_shader
));
979 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), blend_meta
, sizeof(blend_meta
));
983 if (ctx
->dirty
& PAN_DIRTY_VERTEX
) {
984 ctx
->payload_vertex
.postfix
.attribute_meta
= ctx
->vertex
->descriptor_ptr
;
987 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
988 /* Upload samplers back to back, no padding */
990 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
991 if (!ctx
->sampler_count
[t
]) continue;
993 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
994 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
996 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
997 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
1000 if (t
== PIPE_SHADER_FRAGMENT
)
1001 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
1002 else if (t
== PIPE_SHADER_VERTEX
)
1003 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1009 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1010 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1012 if (!ctx
->sampler_view_count
[t
]) continue;
1014 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1016 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1017 if (!ctx
->sampler_views
[t
][i
])
1020 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1021 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1023 /* Inject the addresses in, interleaving cube
1024 * faces and mip levels appropriately. */
1026 for (int l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
1027 for (int f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
1028 unsigned idx
= (l
* tex_rsrc
->array_size
) + f
;
1030 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[idx
] =
1032 rsrc
->bo
->slices
[l
].offset
+
1033 f
* rsrc
->bo
->cubemap_stride
;
1037 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1040 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1042 if (t
== PIPE_SHADER_FRAGMENT
)
1043 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1044 else if (t
== PIPE_SHADER_VERTEX
)
1045 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1051 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1053 /* For flipped-Y buffers (signaled by negative scale), the translate is
1054 * flipped as well */
1056 bool invert_y
= vp
->scale
[1] < 0.0;
1057 float translate_y
= vp
->translate
[1];
1060 translate_y
= ctx
->pipe_framebuffer
.height
- translate_y
;
1062 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1063 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1065 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1066 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1067 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1069 /* Allocate room for the sysval and the uniforms */
1070 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1071 size_t size
= sys_size
+ buf
->size
;
1072 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1074 /* Upload sysvals requested by the shader */
1075 float *uniforms
= (float *) transfer
.cpu
;
1076 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1077 int sysval
= ss
->sysval
[i
];
1079 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1080 uniforms
[4*i
+ 0] = vp
->scale
[0];
1081 uniforms
[4*i
+ 1] = fabsf(vp
->scale
[1]);
1082 uniforms
[4*i
+ 2] = vp
->scale
[2];
1083 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1084 uniforms
[4*i
+ 0] = vp
->translate
[0];
1085 uniforms
[4*i
+ 1] = translate_y
;
1086 uniforms
[4*i
+ 2] = vp
->translate
[2];
1092 /* Upload uniforms */
1093 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1095 int uniform_count
= 0;
1097 struct mali_vertex_tiler_postfix
*postfix
;
1100 case PIPE_SHADER_VERTEX
:
1101 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1102 postfix
= &ctx
->payload_vertex
.postfix
;
1105 case PIPE_SHADER_FRAGMENT
:
1106 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1107 postfix
= &ctx
->payload_tiler
.postfix
;
1111 DBG("Unknown shader stage %d in uniform upload\n", i
);
1115 /* Also attach the same buffer as a UBO for extended access */
1117 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1119 .size
= MALI_POSITIVE((2 + uniform_count
)),
1120 .ptr
= transfer
.gpu
>> 2,
1124 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1125 postfix
->uniforms
= transfer
.gpu
;
1126 postfix
->uniform_buffers
= ubufs
;
1131 /* TODO: Upload the viewport somewhere more appropriate */
1133 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1134 * (somewhat) asymmetric ints. */
1135 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1137 struct mali_viewport view
= {
1138 /* By default, do no viewport clipping, i.e. clip to (-inf,
1139 * inf) in each direction. Clipping to the viewport in theory
1140 * should work, but in practice causes issues when we're not
1141 * explicitly trying to scissor */
1152 /* Always scissor to the viewport by default. */
1153 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1154 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1156 view
.viewport0
[1] = (int) (translate_y
- fabs(vp
->scale
[1]));
1157 view
.viewport1
[1] = MALI_POSITIVE((int) (translate_y
+ fabs(vp
->scale
[1])));
1159 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1160 /* Invert scissor if needed */
1161 unsigned miny
= invert_y
?
1162 ctx
->pipe_framebuffer
.height
- ss
->maxy
: ss
->miny
;
1164 unsigned maxy
= invert_y
?
1165 ctx
->pipe_framebuffer
.height
- ss
->miny
: ss
->maxy
;
1167 /* Set the actual scissor */
1168 view
.viewport0
[0] = ss
->minx
;
1169 view
.viewport0
[1] = miny
;
1170 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1171 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1174 ctx
->payload_tiler
.postfix
.viewport
=
1175 panfrost_upload_transient(ctx
,
1177 sizeof(struct mali_viewport
));
1182 /* Corresponds to exactly one draw, but does not submit anything */
1185 panfrost_queue_draw(struct panfrost_context
*ctx
)
1187 /* TODO: Expand the array? */
1188 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1189 DBG("Job buffer overflow, ignoring draw\n");
1193 /* Handle dirty flags now */
1194 panfrost_emit_for_draw(ctx
, true);
1196 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1197 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1199 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1200 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1202 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1203 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1208 /* At the end of the frame, the vertex and tiler jobs are linked together and
1209 * then the fragment job is plonked at the end. Set value job is first for
1210 * unknown reasons. */
1213 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1215 if (first
->job_descriptor_size
)
1216 first
->next_job_64
= (u64
) (uintptr_t) next
;
1218 first
->next_job_32
= (u32
) (uintptr_t) next
;
1222 panfrost_link_jobs(struct panfrost_context
*ctx
)
1224 if (ctx
->draw_count
) {
1225 /* Generate the set_value_job */
1226 panfrost_set_value_job(ctx
);
1228 /* Have the first vertex job depend on the set value job */
1229 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1232 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1235 /* V -> V/T ; T -> T/null */
1236 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1237 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1239 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1243 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1244 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1245 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1249 /* The entire frame is in memory -- send it off to the kernel! */
1252 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1253 struct pipe_fence_handle
**fence
)
1255 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1256 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1258 /* Edge case if screen is cleared and nothing else */
1259 bool has_draws
= ctx
->draw_count
> 0;
1261 /* Workaround a bizarre lockup (a hardware errata?) */
1263 flush_immediate
= true;
1265 /* A number of jobs are batched -- this must be linked and cleared */
1266 panfrost_link_jobs(ctx
);
1268 ctx
->draw_count
= 0;
1269 ctx
->vertex_job_count
= 0;
1270 ctx
->tiler_job_count
= 0;
1274 bool is_scanout
= panfrost_is_scanout(ctx
);
1275 int fragment_id
= screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1277 /* If visual, we can stall a frame */
1279 if (!flush_immediate
)
1280 screen
->driver
->force_flush_fragment(ctx
, fence
);
1282 screen
->last_fragment_id
= fragment_id
;
1283 screen
->last_fragment_flushed
= false;
1285 /* If readback, flush now (hurts the pipelined performance) */
1286 if (flush_immediate
)
1287 screen
->driver
->force_flush_fragment(ctx
, fence
);
1289 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1290 screen
->driver
->dump_counters(screen
);
1293 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1294 FILE *fp
= fopen(filename
, "wb");
1295 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1304 struct pipe_context
*pipe
,
1305 struct pipe_fence_handle
**fence
,
1308 struct panfrost_context
*ctx
= pan_context(pipe
);
1309 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1311 /* Nothing to do! */
1312 if (!ctx
->draw_count
&& !job
->clear
) return;
1314 /* Whether to stall the pipeline for immediately correct results */
1315 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1317 /* Submit the frame itself */
1318 panfrost_submit_frame(ctx
, flush_immediate
, fence
);
1320 /* Prepare for the next frame */
1321 panfrost_invalidate_frame(ctx
);
1324 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1327 g2m_draw_mode(enum pipe_prim_type mode
)
1330 DEFINE_CASE(POINTS
);
1332 DEFINE_CASE(LINE_LOOP
);
1333 DEFINE_CASE(LINE_STRIP
);
1334 DEFINE_CASE(TRIANGLES
);
1335 DEFINE_CASE(TRIANGLE_STRIP
);
1336 DEFINE_CASE(TRIANGLE_FAN
);
1338 DEFINE_CASE(QUAD_STRIP
);
1339 DEFINE_CASE(POLYGON
);
1342 DBG("Illegal draw mode %d\n", mode
);
1344 return MALI_LINE_LOOP
;
1351 panfrost_translate_index_size(unsigned size
)
1355 return MALI_DRAW_INDEXED_UINT8
;
1358 return MALI_DRAW_INDEXED_UINT16
;
1361 return MALI_DRAW_INDEXED_UINT32
;
1364 DBG("Unknown index size %d\n", size
);
1370 static const uint8_t *
1371 panfrost_get_index_buffer_raw(const struct pipe_draw_info
*info
)
1373 if (info
->has_user_indices
) {
1374 return (const uint8_t *) info
->index
.user
;
1376 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1377 return (const uint8_t *) rsrc
->bo
->cpu
;
1381 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1382 * good for the duration of the draw (transient), could last longer */
1385 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1387 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1389 off_t offset
= info
->start
* info
->index_size
;
1391 if (!info
->has_user_indices
) {
1392 /* Only resources can be directly mapped */
1393 return rsrc
->bo
->gpu
+ offset
;
1395 /* Otherwise, we need to upload to transient memory */
1396 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1397 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1401 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1402 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1403 T idx = buffer[_idx]; \
1404 if (idx > max_index) max_index = idx; \
1405 if (idx < min_index) min_index = idx; \
1410 struct pipe_context
*pipe
,
1411 const struct pipe_draw_info
*info
)
1413 struct panfrost_context
*ctx
= pan_context(pipe
);
1415 ctx
->payload_vertex
.draw_start
= info
->start
;
1416 ctx
->payload_tiler
.draw_start
= info
->start
;
1418 int mode
= info
->mode
;
1420 /* Fallback for unsupported modes */
1422 if (!(ctx
->draw_modes
& (1 << mode
))) {
1423 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1424 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1426 if (info
->count
< 4) {
1427 /* Degenerate case? */
1431 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1432 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1437 /* Now that we have a guaranteed terminating path, find the job.
1438 * Assignment commented out to prevent unused warning */
1440 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1442 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1444 ctx
->vertex_count
= info
->count
;
1446 /* For non-indexed draws, they're the same */
1447 unsigned invocation_count
= ctx
->vertex_count
;
1449 /* For higher amounts of vertices (greater than what fits in a 16-bit
1450 * short), the other value is needed, otherwise there will be bizarre
1451 * rendering artefacts. It's not clear what these values mean yet. */
1453 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~(0x3000 | 0x18000);
1454 ctx
->payload_tiler
.prefix
.unknown_draw
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1456 /* Clean index state */
1457 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~MALI_DRAW_INDEXED_UINT32
;
1459 if (info
->index_size
) {
1460 /* Calculate the min/max index used so we can figure out how
1461 * many times to invoke the vertex shader */
1463 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1465 unsigned min_index
= UINT_MAX
;
1466 unsigned max_index
= 0;
1468 if (info
->index_size
== 1) {
1469 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8
, info
->start
, info
->count
);
1470 } else if (info
->index_size
== 2) {
1471 const uint16_t *ibuf16
= (const uint16_t *) ibuf8
;
1472 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16
, info
->start
, info
->count
);
1473 } else if (info
->index_size
== 4) {
1474 const uint32_t *ibuf32
= (const uint32_t *) ibuf8
;
1475 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32
, info
->start
, info
->count
);
1480 /* Make sure we didn't go crazy */
1481 assert(min_index
< UINT_MAX
);
1482 assert(max_index
>= min_index
);
1484 /* Use the corresponding values */
1485 invocation_count
= max_index
- min_index
+ 1;
1486 ctx
->payload_vertex
.draw_start
= min_index
;
1487 ctx
->payload_tiler
.draw_start
= min_index
;
1489 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1490 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1492 //assert(!info->restart_index); /* TODO: Research */
1493 assert(!info
->index_bias
);
1494 //assert(!info->min_index); /* TODO: Use value */
1496 ctx
->payload_tiler
.prefix
.unknown_draw
|= panfrost_translate_index_size(info
->index_size
);
1497 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1499 /* Index count == vertex count, if no indexing is applied, as
1500 * if it is internally indexed in the expected order */
1502 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1503 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1505 /* Reverse index state */
1506 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1509 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1510 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1512 /* Fire off the draw itself */
1513 panfrost_queue_draw(ctx
);
1519 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1525 panfrost_create_rasterizer_state(
1526 struct pipe_context
*pctx
,
1527 const struct pipe_rasterizer_state
*cso
)
1529 struct panfrost_context
*ctx
= pan_context(pctx
);
1530 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1534 /* Bitmask, unknown meaning of the start value */
1535 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1537 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1538 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1540 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1541 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1543 if (cso
->cull_face
& PIPE_FACE_BACK
)
1544 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1550 panfrost_bind_rasterizer_state(
1551 struct pipe_context
*pctx
,
1554 struct panfrost_context
*ctx
= pan_context(pctx
);
1556 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1560 ctx
->rasterizer
= hwcso
;
1561 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1565 panfrost_create_vertex_elements_state(
1566 struct pipe_context
*pctx
,
1567 unsigned num_elements
,
1568 const struct pipe_vertex_element
*elements
)
1570 struct panfrost_context
*ctx
= pan_context(pctx
);
1571 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1573 so
->num_elements
= num_elements
;
1574 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1576 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_attr_meta
) * num_elements
, HEAP_DESCRIPTOR
);
1577 so
->hw
= (struct mali_attr_meta
*) transfer
.cpu
;
1578 so
->descriptor_ptr
= transfer
.gpu
;
1580 /* Allocate memory for the descriptor state */
1582 for (int i
= 0; i
< num_elements
; ++i
) {
1583 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1585 enum pipe_format fmt
= elements
[i
].src_format
;
1586 const struct util_format_description
*desc
= util_format_description(fmt
);
1587 so
->hw
[i
].unknown1
= 0x2;
1588 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1590 so
->hw
[i
].format
= panfrost_find_format(desc
);
1592 /* The field itself should probably be shifted over */
1593 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1600 panfrost_bind_vertex_elements_state(
1601 struct pipe_context
*pctx
,
1604 struct panfrost_context
*ctx
= pan_context(pctx
);
1606 ctx
->vertex
= hwcso
;
1607 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1611 panfrost_delete_vertex_elements_state(struct pipe_context
*pctx
, void *hwcso
)
1613 struct panfrost_vertex_state
*so
= (struct panfrost_vertex_state
*) hwcso
;
1614 unsigned bytes
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
1615 DBG("Vertex elements delete leaks descriptor (%d bytes)\n", bytes
);
1620 panfrost_create_shader_state(
1621 struct pipe_context
*pctx
,
1622 const struct pipe_shader_state
*cso
)
1624 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1627 /* Token deep copy to prevent memory corruption */
1629 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1630 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1636 panfrost_delete_shader_state(
1637 struct pipe_context
*pctx
,
1640 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1642 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1643 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1646 unsigned leak
= cso
->variant_count
* sizeof(struct mali_shader_meta
);
1647 DBG("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak
);
1653 panfrost_create_sampler_state(
1654 struct pipe_context
*pctx
,
1655 const struct pipe_sampler_state
*cso
)
1657 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1660 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1662 struct mali_sampler_descriptor sampler_descriptor
= {
1663 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1664 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1665 | translate_mip_filter(cso
->min_mip_filter
)
1668 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1669 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1670 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1671 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1673 cso
->border_color
.f
[0],
1674 cso
->border_color
.f
[1],
1675 cso
->border_color
.f
[2],
1676 cso
->border_color
.f
[3]
1678 .min_lod
= FIXED_16(cso
->min_lod
),
1679 .max_lod
= FIXED_16(cso
->max_lod
),
1683 so
->hw
= sampler_descriptor
;
1689 panfrost_bind_sampler_states(
1690 struct pipe_context
*pctx
,
1691 enum pipe_shader_type shader
,
1692 unsigned start_slot
, unsigned num_sampler
,
1695 assert(start_slot
== 0);
1697 struct panfrost_context
*ctx
= pan_context(pctx
);
1699 /* XXX: Should upload, not just copy? */
1700 ctx
->sampler_count
[shader
] = num_sampler
;
1701 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1703 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1707 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1709 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1711 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1712 /* Make sure enable state is at least the same */
1713 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1717 /* Check that the contents of the test are the same */
1718 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1719 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1721 if (!(same_func
&& same_ref
)) {
1725 /* Otherwise, we're good to go */
1730 panfrost_bind_fs_state(
1731 struct pipe_context
*pctx
,
1734 struct panfrost_context
*ctx
= pan_context(pctx
);
1739 /* Match the appropriate variant */
1741 signed variant
= -1;
1743 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1745 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1746 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
1752 if (variant
== -1) {
1753 /* No variant matched, so create a new one */
1754 variant
= variants
->variant_count
++;
1755 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1757 variants
->variants
[variant
].base
= hwcso
;
1758 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1760 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
1761 struct panfrost_context
*ctx
= pan_context(pctx
);
1762 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1764 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1765 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1769 /* Select this variant */
1770 variants
->active_variant
= variant
;
1772 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1773 assert(panfrost_variant_matches(ctx
, shader_state
));
1775 /* Now we have a variant selected, so compile and go */
1777 if (!shader_state
->compiled
) {
1778 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
1779 shader_state
->compiled
= true;
1783 ctx
->dirty
|= PAN_DIRTY_FS
;
1787 panfrost_bind_vs_state(
1788 struct pipe_context
*pctx
,
1791 struct panfrost_context
*ctx
= pan_context(pctx
);
1796 if (!ctx
->vs
->variants
[0].compiled
) {
1797 ctx
->vs
->variants
[0].base
= hwcso
;
1799 /* TODO DRY from above */
1800 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1801 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1802 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
1804 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
1805 ctx
->vs
->variants
[0].compiled
= true;
1809 ctx
->dirty
|= PAN_DIRTY_VS
;
1813 panfrost_set_vertex_buffers(
1814 struct pipe_context
*pctx
,
1815 unsigned start_slot
,
1816 unsigned num_buffers
,
1817 const struct pipe_vertex_buffer
*buffers
)
1819 struct panfrost_context
*ctx
= pan_context(pctx
);
1820 assert(num_buffers
<= PIPE_MAX_ATTRIBS
);
1822 /* XXX: Dirty tracking? etc */
1824 size_t sz
= sizeof(buffers
[0]) * num_buffers
;
1825 ctx
->vertex_buffers
= malloc(sz
);
1826 ctx
->vertex_buffer_count
= num_buffers
;
1827 memcpy(ctx
->vertex_buffers
, buffers
, sz
);
1829 if (ctx
->vertex_buffers
) {
1830 free(ctx
->vertex_buffers
);
1831 ctx
->vertex_buffers
= NULL
;
1834 ctx
->vertex_buffer_count
= 0;
1839 panfrost_set_constant_buffer(
1840 struct pipe_context
*pctx
,
1841 enum pipe_shader_type shader
, uint index
,
1842 const struct pipe_constant_buffer
*buf
)
1844 struct panfrost_context
*ctx
= pan_context(pctx
);
1845 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1847 size_t sz
= buf
? buf
->buffer_size
: 0;
1849 /* Free previous buffer */
1856 pbuf
->buffer
= NULL
;
1859 /* If unbinding, we're done */
1864 /* Multiple constant buffers not yet supported */
1869 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1872 cpu
= rsrc
->bo
->cpu
;
1873 } else if (buf
->user_buffer
) {
1874 cpu
= buf
->user_buffer
;
1876 DBG("No constant buffer?\n");
1880 /* Copy the constant buffer into the driver context for later upload */
1882 pbuf
->buffer
= malloc(sz
);
1883 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1887 panfrost_set_stencil_ref(
1888 struct pipe_context
*pctx
,
1889 const struct pipe_stencil_ref
*ref
)
1891 struct panfrost_context
*ctx
= pan_context(pctx
);
1892 ctx
->stencil_ref
= *ref
;
1894 /* Shader core dirty */
1895 ctx
->dirty
|= PAN_DIRTY_FS
;
1898 static struct pipe_sampler_view
*
1899 panfrost_create_sampler_view(
1900 struct pipe_context
*pctx
,
1901 struct pipe_resource
*texture
,
1902 const struct pipe_sampler_view
*template)
1904 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1905 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1907 pipe_reference(NULL
, &texture
->reference
);
1909 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1911 so
->base
= *template;
1912 so
->base
.texture
= texture
;
1913 so
->base
.reference
.count
= 1;
1914 so
->base
.context
= pctx
;
1916 /* sampler_views correspond to texture descriptors, minus the texture
1917 * (data) itself. So, we serialise the descriptor here and cache it for
1920 /* Make sure it's something with which we're familiar */
1921 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1923 /* TODO: Detect from format better */
1924 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1926 unsigned char user_swizzle
[4] = {
1927 template->swizzle_r
,
1928 template->swizzle_g
,
1929 template->swizzle_b
,
1933 enum mali_format format
= panfrost_find_format(desc
);
1935 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
1937 unsigned usage2_layout
= 0x10;
1939 switch (prsrc
->bo
->layout
) {
1941 usage2_layout
|= 0x8 | 0x4;
1944 usage2_layout
|= 0x1;
1947 usage2_layout
|= is_depth
? 0x1 : 0x2;
1954 struct mali_texture_descriptor texture_descriptor
= {
1955 .width
= MALI_POSITIVE(texture
->width0
),
1956 .height
= MALI_POSITIVE(texture
->height0
),
1957 .depth
= MALI_POSITIVE(texture
->depth0
),
1961 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
1965 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
1967 .usage2
= usage2_layout
1970 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
1973 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
1974 assert (template->u
.tex
.first_level
== 0);
1976 /* Disable mipmapping for now to avoid regressions while automipmapping
1977 * is being implemented. TODO: Remove me once automipmaps work */
1979 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
1980 texture_descriptor
.nr_mipmap_levels
= 0;
1982 so
->hw
= texture_descriptor
;
1984 return (struct pipe_sampler_view
*) so
;
1988 panfrost_set_sampler_views(
1989 struct pipe_context
*pctx
,
1990 enum pipe_shader_type shader
,
1991 unsigned start_slot
, unsigned num_views
,
1992 struct pipe_sampler_view
**views
)
1994 struct panfrost_context
*ctx
= pan_context(pctx
);
1996 assert(start_slot
== 0);
1998 ctx
->sampler_view_count
[shader
] = num_views
;
1999 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2001 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2005 panfrost_sampler_view_destroy(
2006 struct pipe_context
*pctx
,
2007 struct pipe_sampler_view
*views
)
2009 //struct panfrost_context *ctx = pan_context(pctx);
2017 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2018 const struct pipe_framebuffer_state
*fb
)
2020 struct panfrost_context
*ctx
= pan_context(pctx
);
2022 /* Flush when switching away from an FBO */
2024 if (!panfrost_is_scanout(ctx
)) {
2025 panfrost_flush(pctx
, NULL
, 0);
2028 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2029 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2030 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2031 ctx
->pipe_framebuffer
.width
= fb
->width
;
2032 ctx
->pipe_framebuffer
.height
= fb
->height
;
2034 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2035 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2037 /* check if changing cbuf */
2038 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2040 if (cb
&& (i
!= 0)) {
2041 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2046 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2051 if (ctx
->require_sfbd
)
2052 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2054 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2056 panfrost_attach_vt_framebuffer(ctx
);
2058 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2059 bool is_scanout
= panfrost_is_scanout(ctx
);
2061 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
) {
2062 /* The blob is aggressive about enabling AFBC. As such,
2063 * it's pretty much necessary to use it here, since we
2064 * have no traces of non-compressed FBO. */
2066 panfrost_enable_afbc(ctx
, tex
, false);
2069 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2070 /* Enable transaction elimination if we can */
2071 panfrost_enable_checksum(ctx
, tex
);
2076 struct pipe_surface
*zb
= fb
->zsbuf
;
2078 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2079 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2084 if (ctx
->require_sfbd
)
2085 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2087 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2089 panfrost_attach_vt_framebuffer(ctx
);
2091 /* Keep the depth FBO linear */
2098 panfrost_create_blend_state(struct pipe_context
*pipe
,
2099 const struct pipe_blend_state
*blend
)
2101 struct panfrost_context
*ctx
= pan_context(pipe
);
2102 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2105 /* TODO: The following features are not yet implemented */
2106 assert(!blend
->logicop_enable
);
2107 assert(!blend
->alpha_to_coverage
);
2108 assert(!blend
->alpha_to_one
);
2110 /* Compile the blend state, first as fixed-function if we can */
2112 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], &so
->equation
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2115 /* If we can't, compile a blend shader instead */
2117 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2123 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2126 struct panfrost_context
*ctx
= pan_context(pipe
);
2127 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2128 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2129 ctx
->blend
= pblend
;
2134 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2136 /* TODO: Attach color */
2138 /* Shader itself is not dirty, but the shader core is */
2139 ctx
->dirty
|= PAN_DIRTY_FS
;
2143 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2146 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2148 if (so
->has_blend_shader
) {
2149 DBG("Deleting blend state leak blend shaders bytecode\n");
2156 panfrost_set_blend_color(struct pipe_context
*pipe
,
2157 const struct pipe_blend_color
*blend_color
)
2159 struct panfrost_context
*ctx
= pan_context(pipe
);
2161 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2164 ctx
->blend_color
= *blend_color
;
2166 /* The blend mode depends on the blend constant color, due to the
2167 * fixed/programmable split. So, we're forced to regenerate the blend
2170 /* TODO: Attach color */
2175 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2176 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2178 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2182 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2185 struct panfrost_context
*ctx
= pan_context(pipe
);
2186 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2187 ctx
->depth_stencil
= depth_stencil
;
2192 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2193 * emulated in the fragment shader */
2195 if (depth_stencil
->alpha
.enabled
) {
2196 /* We need to trigger a new shader (maybe) */
2197 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2201 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2203 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2204 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2206 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2207 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2209 /* Depth state (TODO: Refactor) */
2210 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2212 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2214 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2215 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2217 /* Bounds test not implemented */
2218 assert(!depth_stencil
->depth
.bounds_test
);
2220 ctx
->dirty
|= PAN_DIRTY_FS
;
2224 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2230 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2231 unsigned sample_mask
)
2236 panfrost_set_clip_state(struct pipe_context
*pipe
,
2237 const struct pipe_clip_state
*clip
)
2239 //struct panfrost_context *panfrost = pan_context(pipe);
2243 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2244 unsigned start_slot
,
2245 unsigned num_viewports
,
2246 const struct pipe_viewport_state
*viewports
)
2248 struct panfrost_context
*ctx
= pan_context(pipe
);
2250 assert(start_slot
== 0);
2251 assert(num_viewports
== 1);
2253 ctx
->pipe_viewport
= *viewports
;
2256 /* TODO: What if not centered? */
2257 float w
= abs(viewports
->scale
[0]) * 2.0;
2258 float h
= abs(viewports
->scale
[1]) * 2.0;
2260 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2261 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2266 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2267 unsigned start_slot
,
2268 unsigned num_scissors
,
2269 const struct pipe_scissor_state
*scissors
)
2271 struct panfrost_context
*ctx
= pan_context(pipe
);
2273 assert(start_slot
== 0);
2274 assert(num_scissors
== 1);
2276 ctx
->scissor
= *scissors
;
2280 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2281 const struct pipe_poly_stipple
*stipple
)
2283 //struct panfrost_context *panfrost = pan_context(pipe);
2287 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2290 //struct panfrost_context *panfrost = pan_context(pipe);
2294 panfrost_destroy(struct pipe_context
*pipe
)
2296 struct panfrost_context
*panfrost
= pan_context(pipe
);
2297 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2299 if (panfrost
->blitter
)
2300 util_blitter_destroy(panfrost
->blitter
);
2302 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2303 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2304 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2305 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2306 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2309 static struct pipe_query
*
2310 panfrost_create_query(struct pipe_context
*pipe
,
2314 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2319 return (struct pipe_query
*) q
;
2323 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2329 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2331 struct panfrost_context
*ctx
= pan_context(pipe
);
2332 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2334 switch (query
->type
) {
2335 case PIPE_QUERY_OCCLUSION_COUNTER
:
2336 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2337 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2339 /* Allocate a word for the query results to be stored */
2340 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2342 ctx
->occlusion_query
= query
;
2348 DBG("Skipping query %d\n", query
->type
);
2356 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2358 struct panfrost_context
*ctx
= pan_context(pipe
);
2359 ctx
->occlusion_query
= NULL
;
2364 panfrost_get_query_result(struct pipe_context
*pipe
,
2365 struct pipe_query
*q
,
2367 union pipe_query_result
*vresult
)
2370 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2372 /* We need to flush out the jobs to actually run the counter, TODO
2373 * check wait, TODO wallpaper after if needed */
2375 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2377 switch (query
->type
) {
2378 case PIPE_QUERY_OCCLUSION_COUNTER
:
2379 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2380 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2381 /* Read back the query results */
2382 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2383 unsigned passed
= *result
;
2385 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2386 vresult
->u64
= passed
;
2388 vresult
->b
= !!passed
;
2394 DBG("Skipped query get %d\n", query
->type
);
2401 static struct pipe_stream_output_target
*
2402 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2403 struct pipe_resource
*prsc
,
2404 unsigned buffer_offset
,
2405 unsigned buffer_size
)
2407 struct pipe_stream_output_target
*target
;
2409 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2414 pipe_reference_init(&target
->reference
, 1);
2415 pipe_resource_reference(&target
->buffer
, prsc
);
2417 target
->context
= pctx
;
2418 target
->buffer_offset
= buffer_offset
;
2419 target
->buffer_size
= buffer_size
;
2425 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2426 struct pipe_stream_output_target
*target
)
2428 pipe_resource_reference(&target
->buffer
, NULL
);
2433 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2434 unsigned num_targets
,
2435 struct pipe_stream_output_target
**targets
,
2436 const unsigned *offsets
)
2442 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2444 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2445 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2447 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2448 /* Allocate the beginning of the transient pool */
2449 int entry_size
= (1 << 22); /* 4MB */
2451 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2452 ctx
->transient_pools
[i
].entry_count
= 1;
2454 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2457 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2458 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2459 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2460 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2461 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2465 /* New context creation, which also does hardware initialisation since I don't
2466 * know the better way to structure this :smirk: */
2468 struct pipe_context
*
2469 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2471 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2472 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2473 memset(ctx
, 0, sizeof(*ctx
));
2474 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2477 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2479 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2480 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2482 gallium
->screen
= screen
;
2484 gallium
->destroy
= panfrost_destroy
;
2486 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2488 gallium
->flush
= panfrost_flush
;
2489 gallium
->clear
= panfrost_clear
;
2490 gallium
->draw_vbo
= panfrost_draw_vbo
;
2492 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2493 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2495 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2497 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2498 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2499 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2501 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2502 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2503 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2505 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2506 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2507 gallium
->delete_vertex_elements_state
= panfrost_delete_vertex_elements_state
;
2509 gallium
->create_fs_state
= panfrost_create_shader_state
;
2510 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2511 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2513 gallium
->create_vs_state
= panfrost_create_shader_state
;
2514 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2515 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2517 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2518 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2519 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2521 gallium
->create_blend_state
= panfrost_create_blend_state
;
2522 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2523 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2525 gallium
->set_blend_color
= panfrost_set_blend_color
;
2527 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2528 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2529 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2531 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2533 gallium
->set_clip_state
= panfrost_set_clip_state
;
2534 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2535 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2536 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2537 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2539 gallium
->create_query
= panfrost_create_query
;
2540 gallium
->destroy_query
= panfrost_destroy_query
;
2541 gallium
->begin_query
= panfrost_begin_query
;
2542 gallium
->end_query
= panfrost_end_query
;
2543 gallium
->get_query_result
= panfrost_get_query_result
;
2545 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2546 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2547 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2549 panfrost_resource_context_init(gallium
);
2551 pscreen
->driver
->init_context(ctx
);
2553 panfrost_setup_hardware(ctx
);
2556 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2557 gallium
->const_uploader
= gallium
->stream_uploader
;
2558 assert(gallium
->stream_uploader
);
2560 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2561 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2563 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2565 ctx
->blitter
= util_blitter_create(gallium
);
2566 assert(ctx
->blitter
);
2568 /* Prepare for render! */
2570 panfrost_job_init(ctx
);
2571 panfrost_emit_vertex_payload(ctx
);
2572 panfrost_emit_tiler_payload(ctx
);
2573 panfrost_invalidate_frame(ctx
);
2574 panfrost_default_shader_backend(ctx
);
2575 panfrost_generate_space_filler_indices();