2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
50 static int performance_counter_number
= 0;
51 extern const char *pan_counters_base
;
53 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
56 /* Can a given format support AFBC? Not all can. */
59 panfrost_can_afbc(enum pipe_format format
)
61 const struct util_format_description
*desc
=
62 util_format_description(format
);
64 if (util_format_is_rgba8_variant(desc
))
67 /* TODO: AFBC of other formats */
72 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
73 * indepdent between color buffers and depth/stencil). To enable, we allocate
74 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
75 * edit the fragment job here. This routine should be called ONCE per
76 * AFBC-compressed buffer, rather than on every frame. */
79 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
81 if (ctx
->require_sfbd
) {
82 DBG("AFBC not supported yet on SFBD\n");
86 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
87 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
88 /* AFBC metadata is 16 bytes per tile */
89 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
90 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
91 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
92 int stride
= bytes_per_pixel
* ALIGN(rsrc
->base
.width0
, 16);
94 stride
*= 2; /* TODO: Should this be carried over? */
95 int main_size
= stride
* rsrc
->base
.height0
;
96 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
98 /* Allocate the AFBC slab itself, large enough to hold the above */
99 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
100 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
103 rsrc
->bo
->layout
= PAN_AFBC
;
105 /* Compressed textured reads use a tagged pointer to the metadata */
107 rsrc
->bo
->gpu
= rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
108 rsrc
->bo
->cpu
= rsrc
->bo
->afbc_slab
.cpu
;
109 rsrc
->bo
->gem_handle
= rsrc
->bo
->afbc_slab
.gem_handle
;
113 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
115 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
116 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
117 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
118 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
120 /* 8 byte checksum per tile */
121 rsrc
->bo
->checksum_stride
= tile_w
* 8;
122 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
123 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
125 rsrc
->bo
->has_checksum
= true;
128 /* Framebuffer descriptor */
131 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
133 fb
->width
= MALI_POSITIVE(w
);
134 fb
->height
= MALI_POSITIVE(h
);
136 /* No idea why this is needed, but it's how resolution_check is
137 * calculated. It's not clear to us yet why the hardware wants this.
138 * The formula itself was discovered mostly by manual bruteforce and
139 * aggressive algebraic simplification. */
141 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
144 struct mali_single_framebuffer
145 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
147 struct mali_single_framebuffer framebuffer
= {
149 .format
= 0x30000000,
150 .clear_flags
= 0x1000,
151 .unknown_address_0
= ctx
->scratchpad
.gpu
,
152 .unknown_address_1
= ctx
->misc_0
.gpu
,
153 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
155 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
156 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
159 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
164 struct bifrost_framebuffer
165 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
167 struct bifrost_framebuffer framebuffer
= {
168 /* It is not yet clear what tiler_meta means or how it's
169 * calculated, but we can tell the lower 32-bits are a
170 * (monotonically increasing?) function of tile count and
171 * geometry complexity; I suspect it defines a memory size of
172 * some kind? for the tiler. It's really unclear at the
173 * moment... but to add to the confusion, the hardware is happy
174 * enough to accept a zero in this field, so we don't even have
175 * to worry about it right now.
177 * The byte (just after the 32-bit mark) is much more
178 * interesting. The higher nibble I've only ever seen as 0xF,
179 * but the lower one I've seen as 0x0 or 0xF, and it's not
180 * obvious what the difference is. But what -is- obvious is
181 * that when the lower nibble is zero, performance is severely
182 * degraded compared to when the lower nibble is set.
183 * Evidently, that nibble enables some sort of fast path,
184 * perhaps relating to caching or tile flush? Regardless, at
185 * this point there's no clear reason not to set it, aside from
186 * substantially increased memory requirements (of the misc_0
189 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
191 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
192 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
193 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
194 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
199 .rt_count_1
= MALI_POSITIVE(1),
204 /* Corresponds to unknown_address_X of SFBD */
205 .scratchpad
= ctx
->scratchpad
.gpu
,
206 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
208 /* The constant added here is, like the lower word of
209 * tiler_meta, (loosely) another product of framebuffer size
210 * and geometry complexity. It must be sufficiently large for
211 * the tiler_meta fast path to work; if it's too small, there
212 * will be DATA_INVALID_FAULTs. Conversely, it must be less
213 * than the total size of misc_0, or else there's no room. It's
214 * possible this constant configures a partition between two
215 * parts of misc_0? We haven't investigated the functionality,
216 * as these buffers are internally used by the hardware
217 * (presumably by the tiler) but not seemingly touched by the driver
220 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
222 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
223 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
229 /* Are we currently rendering to the screen (rather than an FBO)? */
232 panfrost_is_scanout(struct panfrost_context
*ctx
)
234 /* If there is no color buffer, it's an FBO */
235 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
238 /* If we're too early that no framebuffer was sent, it's scanout */
239 if (!ctx
->pipe_framebuffer
.cbufs
[0])
242 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
243 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
244 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
248 pan_pack_color(const union pipe_color_union
*color
, enum pipe_format format
)
250 /* Alpha magicked to 1.0 if there is no alpha */
252 bool has_alpha
= util_format_has_alpha(format
);
253 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
255 /* Packed color depends on the framebuffer format */
257 const struct util_format_description
*desc
=
258 util_format_description(format
);
260 if (util_format_is_rgba8_variant(desc
)) {
261 return (float_to_ubyte(clear_alpha
) << 24) |
262 (float_to_ubyte(color
->f
[2]) << 16) |
263 (float_to_ubyte(color
->f
[1]) << 8) |
264 (float_to_ubyte(color
->f
[0]) << 0);
265 } else if (format
== PIPE_FORMAT_B5G6R5_UNORM
) {
266 /* First, we convert the components to R5, G6, B5 separately */
267 unsigned r5
= CLAMP(color
->f
[0], 0.0, 1.0) * 31.0;
268 unsigned g6
= CLAMP(color
->f
[1], 0.0, 1.0) * 63.0;
269 unsigned b5
= CLAMP(color
->f
[2], 0.0, 1.0) * 31.0;
271 /* Then we pack into a sparse u32. TODO: Why these shifts? */
272 return (b5
<< 25) | (g6
<< 14) | (r5
<< 5);
283 struct pipe_context
*pipe
,
285 const union pipe_color_union
*color
,
286 double depth
, unsigned stencil
)
288 struct panfrost_context
*ctx
= pan_context(pipe
);
289 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
291 if (buffers
& PIPE_CLEAR_COLOR
) {
292 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[0]->format
;
293 job
->clear_color
= pan_pack_color(color
, format
);
296 if (buffers
& PIPE_CLEAR_DEPTH
) {
297 job
->clear_depth
= depth
;
300 if (buffers
& PIPE_CLEAR_STENCIL
) {
301 job
->clear_stencil
= stencil
;
304 job
->clear
|= buffers
;
308 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
310 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
311 struct bifrost_render_target rts_list
[] = {
316 .framebuffer
= ctx
->misc_0
.gpu
,
321 /* Allocate memory for the three components */
322 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
323 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
325 /* Opaque 1024-block */
326 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
328 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
329 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
331 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
335 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
337 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
341 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
343 mali_ptr framebuffer
= ctx
->require_sfbd
?
344 panfrost_attach_vt_sfbd(ctx
) :
345 panfrost_attach_vt_mfbd(ctx
);
347 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
348 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
351 /* Reset per-frame context, called on context initialisation as well as after
352 * flushing a frame */
355 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
357 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
358 DBG("Uploaded transient %d bytes\n", transient_count
);
360 /* Rotate cmdstream */
361 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
362 ctx
->cmdstream_i
= 0;
364 if (ctx
->require_sfbd
)
365 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
367 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
369 /* Reset varyings allocated */
370 ctx
->varying_height
= 0;
372 /* The transient cmdstream is dirty every frame; the only bits worth preserving
373 * (textures, shaders, etc) are in other buffers anyways */
375 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
376 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
378 /* Regenerate payloads */
379 panfrost_attach_vt_framebuffer(ctx
);
382 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
385 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
387 /* Reset job counters */
389 ctx
->vertex_job_count
= 0;
390 ctx
->tiler_job_count
= 0;
393 /* In practice, every field of these payloads should be configurable
394 * arbitrarily, which means these functions are basically catch-all's for
395 * as-of-yet unwavering unknowns */
398 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
400 struct midgard_payload_vertex_tiler payload
= {
402 .workgroups_z_shift
= 32,
403 .workgroups_x_shift_2
= 0x2,
404 .workgroups_x_shift_3
= 0x5,
406 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
409 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
413 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
415 struct midgard_payload_vertex_tiler payload
= {
417 .workgroups_z_shift
= 32,
418 .workgroups_x_shift_2
= 0x2,
419 .workgroups_x_shift_3
= 0x6,
421 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
425 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
429 translate_tex_wrap(enum pipe_tex_wrap w
)
432 case PIPE_TEX_WRAP_REPEAT
:
433 return MALI_WRAP_REPEAT
;
435 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
436 return MALI_WRAP_CLAMP_TO_EDGE
;
438 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
439 return MALI_WRAP_CLAMP_TO_BORDER
;
441 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
442 return MALI_WRAP_MIRRORED_REPEAT
;
445 unreachable("Invalid wrap");
450 translate_tex_filter(enum pipe_tex_filter f
)
453 case PIPE_TEX_FILTER_NEAREST
:
456 case PIPE_TEX_FILTER_LINEAR
:
460 unreachable("Invalid filter");
465 translate_mip_filter(enum pipe_tex_mipfilter f
)
467 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
471 panfrost_translate_compare_func(enum pipe_compare_func in
)
474 case PIPE_FUNC_NEVER
:
475 return MALI_FUNC_NEVER
;
478 return MALI_FUNC_LESS
;
480 case PIPE_FUNC_EQUAL
:
481 return MALI_FUNC_EQUAL
;
483 case PIPE_FUNC_LEQUAL
:
484 return MALI_FUNC_LEQUAL
;
486 case PIPE_FUNC_GREATER
:
487 return MALI_FUNC_GREATER
;
489 case PIPE_FUNC_NOTEQUAL
:
490 return MALI_FUNC_NOTEQUAL
;
492 case PIPE_FUNC_GEQUAL
:
493 return MALI_FUNC_GEQUAL
;
495 case PIPE_FUNC_ALWAYS
:
496 return MALI_FUNC_ALWAYS
;
499 unreachable("Invalid func");
504 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
507 case PIPE_FUNC_NEVER
:
508 return MALI_ALT_FUNC_NEVER
;
511 return MALI_ALT_FUNC_LESS
;
513 case PIPE_FUNC_EQUAL
:
514 return MALI_ALT_FUNC_EQUAL
;
516 case PIPE_FUNC_LEQUAL
:
517 return MALI_ALT_FUNC_LEQUAL
;
519 case PIPE_FUNC_GREATER
:
520 return MALI_ALT_FUNC_GREATER
;
522 case PIPE_FUNC_NOTEQUAL
:
523 return MALI_ALT_FUNC_NOTEQUAL
;
525 case PIPE_FUNC_GEQUAL
:
526 return MALI_ALT_FUNC_GEQUAL
;
528 case PIPE_FUNC_ALWAYS
:
529 return MALI_ALT_FUNC_ALWAYS
;
532 unreachable("Invalid alt func");
537 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
540 case PIPE_STENCIL_OP_KEEP
:
541 return MALI_STENCIL_KEEP
;
543 case PIPE_STENCIL_OP_ZERO
:
544 return MALI_STENCIL_ZERO
;
546 case PIPE_STENCIL_OP_REPLACE
:
547 return MALI_STENCIL_REPLACE
;
549 case PIPE_STENCIL_OP_INCR
:
550 return MALI_STENCIL_INCR
;
552 case PIPE_STENCIL_OP_DECR
:
553 return MALI_STENCIL_DECR
;
555 case PIPE_STENCIL_OP_INCR_WRAP
:
556 return MALI_STENCIL_INCR_WRAP
;
558 case PIPE_STENCIL_OP_DECR_WRAP
:
559 return MALI_STENCIL_DECR_WRAP
;
561 case PIPE_STENCIL_OP_INVERT
:
562 return MALI_STENCIL_INVERT
;
565 unreachable("Invalid stencil op");
570 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
572 out
->ref
= 0; /* Gallium gets it from elsewhere */
574 out
->mask
= in
->valuemask
;
575 out
->func
= panfrost_translate_compare_func(in
->func
);
576 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
577 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
578 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
582 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
584 struct mali_shader_meta shader
= {
585 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
587 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
588 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
592 shader
.unknown2_4
|= 0x10;
595 struct pipe_stencil_state default_stencil
= {
597 .func
= PIPE_FUNC_ALWAYS
,
598 .fail_op
= MALI_STENCIL_KEEP
,
599 .zfail_op
= MALI_STENCIL_KEEP
,
600 .zpass_op
= MALI_STENCIL_KEEP
,
605 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
606 shader
.stencil_mask_front
= default_stencil
.writemask
;
608 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
609 shader
.stencil_mask_back
= default_stencil
.writemask
;
611 if (default_stencil
.enabled
)
612 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
614 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
618 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
620 if (first
->job_descriptor_size
)
621 first
->next_job_64
= (u64
) (uintptr_t) next
;
623 first
->next_job_32
= (u32
) (uintptr_t) next
;
626 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
627 * graphics command stream. It should be called once per draw, accordding to
628 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
629 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
632 struct panfrost_transfer
633 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
)
635 /* Each draw call corresponds to two jobs, and the set-value job is first */
636 int draw_job_index
= 1 + (2 * ctx
->draw_count
) + 1;
638 struct mali_job_descriptor_header job
= {
639 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
640 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
642 .job_descriptor_size
= 1,
646 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
648 /* There's some padding hacks on 32-bit */
655 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
658 /* Tiler jobs depend on vertex jobs */
660 job
.job_dependency_index_1
= draw_job_index
;
662 /* Tiler jobs also depend on the previous tiler job */
664 if (ctx
->draw_count
) {
665 job
.job_dependency_index_2
= draw_job_index
- 1;
666 /* Previous tiler job points to this tiler job */
667 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
669 /* The only vertex job so far points to first tiler job */
670 panfrost_link_job_pair(ctx
->u_vertex_jobs
[0], transfer
.gpu
);
673 if (ctx
->draw_count
) {
674 /* Previous vertex job points to this vertex job */
675 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->draw_count
- 1], transfer
.gpu
);
677 /* Last vertex job points to first tiler job */
678 panfrost_link_job_pair(&job
, ctx
->tiler_jobs
[0]);
680 /* Have the first vertex job depend on the set value job */
681 job
.job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
682 panfrost_link_job_pair(ctx
->u_set_value_job
, transfer
.gpu
);
686 memcpy(transfer
.cpu
, &job
, sizeof(job
));
687 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
691 /* Generates a set value job. It's unclear what exactly this does, why it's
692 * necessary, and when to call it. */
695 panfrost_set_value_job(struct panfrost_context
*ctx
)
697 struct mali_job_descriptor_header job
= {
698 .job_type
= JOB_TYPE_SET_VALUE
,
699 .job_descriptor_size
= 1,
703 struct mali_payload_set_value payload
= {
704 .out
= ctx
->misc_0
.gpu
,
708 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
709 memcpy(transfer
.cpu
, &job
, sizeof(job
));
710 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
712 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
713 ctx
->set_value_job
= transfer
.gpu
;
717 panfrost_emit_varyings(
718 struct panfrost_context
*ctx
,
719 union mali_attr
*slot
,
723 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
725 /* Fill out the descriptor */
726 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
727 slot
->stride
= stride
;
728 slot
->size
= stride
* count
;
730 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
731 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
733 return varying_address
;
737 panfrost_emit_point_coord(union mali_attr
*slot
)
739 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
740 slot
->stride
= slot
->size
= 0;
744 panfrost_emit_varying_descriptor(
745 struct panfrost_context
*ctx
,
746 unsigned invocation_count
)
748 /* Load the shaders */
750 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
751 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
753 /* Allocate the varying descriptor */
755 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
756 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
758 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
761 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
762 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
764 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
765 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
767 /* Buffer indices must be in this order per our convention */
768 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
771 /* General varyings -- use the VS's, since those are more likely to be
772 * accurate on desktop */
774 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
775 vs
->general_varying_stride
, invocation_count
);
777 /* fp32 vec4 gl_Position */
778 ctx
->payload_tiler
.postfix
.position_varying
=
779 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
780 sizeof(float) * 4, invocation_count
);
783 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
784 /* fp16 vec1 gl_PointSize */
785 ctx
->payload_tiler
.primitive_size
.pointer
=
786 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
787 2, invocation_count
);
790 if (fs
->reads_point_coord
) {
791 /* Special descriptor */
792 panfrost_emit_point_coord(&varyings
[idx
++]);
795 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
796 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
797 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
801 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
803 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
804 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
806 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
809 /* Emits attributes and varying descriptors, which should be called every draw,
810 * excepting some obscure circumstances */
813 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
815 /* Staged mali_attr, and index into them. i =/= k, depending on the
816 * vertex buffer mask */
817 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
820 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
822 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
823 if (!(ctx
->vb_mask
& (1 << i
))) continue;
825 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
826 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
830 /* Align to 64 bytes by masking off the lower bits. This
831 * will be adjusted back when we fixup the src_offset in
834 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
836 /* Offset vertex count by draw_start to make sure we upload enough */
837 attrs
[k
].stride
= buf
->stride
;
838 attrs
[k
].size
= rsrc
->base
.width0
;
840 panfrost_job_add_bo(job
, rsrc
->bo
);
841 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
846 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
848 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
852 panfrost_writes_point_size(struct panfrost_context
*ctx
)
855 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
857 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
860 /* Stage the attribute descriptors so we can adjust src_offset
861 * to let BOs align nicely */
864 panfrost_stage_attributes(struct panfrost_context
*ctx
)
866 struct panfrost_vertex_state
*so
= ctx
->vertex
;
868 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
869 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
870 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
872 /* Copy as-is for the first pass */
873 memcpy(target
, so
->hw
, sz
);
875 /* Fixup offsets for the second pass. Recall that the hardware
876 * calculates attribute addresses as:
878 * addr = base + (stride * vtx) + src_offset;
880 * However, on Mali, base must be aligned to 64-bytes, so we
883 * base' = base & ~63 = base - (base & 63)
885 * To compensate when using base' (see emit_vertex_data), we have
886 * to adjust src_offset by the masked off piece:
888 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
889 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
890 * = base + (stride * vtx) + src_offset
896 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
897 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
898 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
900 /* Adjust by the masked off bits of the offset */
901 target
[i
].src_offset
+= (addr
& 63);
904 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
907 /* Go through dirty flags and actualise them in the cmdstream. */
910 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
912 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
914 if (with_vertex_data
) {
915 panfrost_emit_vertex_data(ctx
, job
);
918 bool msaa
= ctx
->rasterizer
->base
.multisample
;
920 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
921 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
923 /* TODO: Sample size */
924 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
925 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
928 /* Enable job requirements at draw-time */
931 job
->requirements
|= PAN_REQ_MSAA
;
933 if (ctx
->depth_stencil
->depth
.writemask
)
934 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
936 if (ctx
->occlusion_query
) {
937 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
938 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
941 if (ctx
->dirty
& PAN_DIRTY_VS
) {
944 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
946 /* Late shader descriptor assignments */
948 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
949 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
952 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
954 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
957 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
958 /* Check if we need to link the gl_PointSize varying */
959 if (!panfrost_writes_point_size(ctx
)) {
960 /* If the size is constant, write it out. Otherwise,
961 * don't touch primitive_size (since we would clobber
962 * the pointer there) */
964 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
968 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
970 ctx
->dirty
|= PAN_DIRTY_FS
;
972 if (ctx
->dirty
& PAN_DIRTY_FS
) {
974 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
976 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
979 COPY(attribute_count
);
981 COPY(midgard1
.uniform_count
);
982 COPY(midgard1
.work_count
);
983 COPY(midgard1
.unknown2
);
986 /* If there is a blend shader, work registers are shared */
988 if (ctx
->blend
->has_blend_shader
)
989 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
991 /* Set late due to depending on render state */
992 /* The one at the end seems to mean "1 UBO" */
993 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
995 /* Assign texture/sample count right before upload */
996 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
997 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
999 /* Assign the stencil refs late */
1000 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1001 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1003 /* CAN_DISCARD should be set if the fragment shader possibly
1004 * contains a 'discard' instruction. It is likely this is
1005 * related to optimizations related to forward-pixel kill, as
1006 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1007 * thing?" by Peter Harris
1010 if (variant
->can_discard
) {
1011 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1012 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1013 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1014 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1017 /* Check if we're using the default blend descriptor (fast path) */
1020 !ctx
->blend
->has_blend_shader
&&
1021 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1022 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1023 (ctx
->blend
->equation
.color_mask
== 0xf);
1025 /* Even on MFBD, the shader descriptor gets blend shaders. It's
1026 * *also* copied to the blend_meta appended (by convention),
1027 * but this is the field actually read by the hardware. (Or
1028 * maybe both are read...?) */
1030 if (ctx
->blend
->has_blend_shader
) {
1031 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1034 if (ctx
->require_sfbd
) {
1035 /* When only a single render target platform is used, the blend
1036 * information is inside the shader meta itself. We
1037 * additionally need to signal CAN_DISCARD for nontrivial blend
1038 * modes (so we're able to read back the destination buffer) */
1040 if (!ctx
->blend
->has_blend_shader
) {
1041 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1042 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1046 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1050 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1051 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1052 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1054 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1056 if (!ctx
->require_sfbd
) {
1057 /* Additional blend descriptor tacked on for jobs using MFBD */
1059 unsigned blend_count
= 0x200;
1061 if (ctx
->blend
->has_blend_shader
) {
1062 /* For a blend shader, the bottom nibble corresponds to
1063 * the number of work registers used, which signals the
1064 * -existence- of a blend shader */
1066 assert(ctx
->blend
->blend_work_count
>= 2);
1067 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1069 /* Otherwise, the bottom bit simply specifies if
1070 * blending (anything other than REPLACE) is enabled */
1077 struct midgard_blend_rt rts
[4];
1081 for (unsigned i
= 0; i
< 1; ++i
) {
1082 rts
[i
].flags
= blend_count
;
1084 if (ctx
->blend
->has_blend_shader
) {
1085 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1087 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1088 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1092 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1096 /* We stage to transient, so always dirty.. */
1097 panfrost_stage_attributes(ctx
);
1099 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
1100 /* Upload samplers back to back, no padding */
1102 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1103 if (!ctx
->sampler_count
[t
]) continue;
1105 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
1106 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
1108 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
1109 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
1112 if (t
== PIPE_SHADER_FRAGMENT
)
1113 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
1114 else if (t
== PIPE_SHADER_VERTEX
)
1115 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1121 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1122 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1124 if (!ctx
->sampler_view_count
[t
]) continue;
1126 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1128 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1129 if (!ctx
->sampler_views
[t
][i
])
1132 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1133 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1135 /* Inject the addresses in, interleaving cube
1136 * faces and mip levels appropriately. */
1138 for (int l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
1139 for (int f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
1140 unsigned idx
= (l
* tex_rsrc
->array_size
) + f
;
1142 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[idx
] =
1144 rsrc
->bo
->slices
[l
].offset
+
1145 f
* rsrc
->bo
->cubemap_stride
;
1149 /* Inject the strides */
1150 unsigned usage2
= ctx
->sampler_views
[t
][i
]->hw
.format
.usage2
;
1152 if (usage2
& MALI_TEX_MANUAL_STRIDE
) {
1153 unsigned idx
= tex_rsrc
->last_level
* tex_rsrc
->array_size
;
1154 idx
+= tex_rsrc
->array_size
;
1156 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[idx
] =
1157 rsrc
->bo
->slices
[0].stride
;
1160 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1163 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1165 if (t
== PIPE_SHADER_FRAGMENT
)
1166 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1167 else if (t
== PIPE_SHADER_VERTEX
)
1168 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1174 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1176 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1177 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1179 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1180 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1181 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1183 /* Allocate room for the sysval and the uniforms */
1184 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1185 size_t size
= sys_size
+ buf
->size
;
1186 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1188 /* Upload sysvals requested by the shader */
1189 float *uniforms
= (float *) transfer
.cpu
;
1190 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1191 int sysval
= ss
->sysval
[i
];
1193 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1194 uniforms
[4*i
+ 0] = vp
->scale
[0];
1195 uniforms
[4*i
+ 1] = vp
->scale
[1];
1196 uniforms
[4*i
+ 2] = vp
->scale
[2];
1197 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1198 uniforms
[4*i
+ 0] = vp
->translate
[0];
1199 uniforms
[4*i
+ 1] = vp
->translate
[1];
1200 uniforms
[4*i
+ 2] = vp
->translate
[2];
1206 /* Upload uniforms */
1207 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1209 int uniform_count
= 0;
1211 struct mali_vertex_tiler_postfix
*postfix
;
1214 case PIPE_SHADER_VERTEX
:
1215 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1216 postfix
= &ctx
->payload_vertex
.postfix
;
1219 case PIPE_SHADER_FRAGMENT
:
1220 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1221 postfix
= &ctx
->payload_tiler
.postfix
;
1225 unreachable("Invalid shader stage\n");
1228 /* Also attach the same buffer as a UBO for extended access */
1230 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1232 .size
= MALI_POSITIVE((2 + uniform_count
)),
1233 .ptr
= transfer
.gpu
>> 2,
1237 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1238 postfix
->uniforms
= transfer
.gpu
;
1239 postfix
->uniform_buffers
= ubufs
;
1244 /* TODO: Upload the viewport somewhere more appropriate */
1246 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1247 * (somewhat) asymmetric ints. */
1248 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1250 struct mali_viewport view
= {
1251 /* By default, do no viewport clipping, i.e. clip to (-inf,
1252 * inf) in each direction. Clipping to the viewport in theory
1253 * should work, but in practice causes issues when we're not
1254 * explicitly trying to scissor */
1265 /* Always scissor to the viewport by default. */
1266 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1267 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1269 int miny
= (int) (vp
->translate
[1] - vp
->scale
[1]);
1270 int maxy
= (int) (vp
->translate
[1] + vp
->scale
[1]);
1272 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1273 view
.viewport0
[0] = ss
->minx
;
1274 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1280 /* Hardware needs the min/max to be strictly ordered, so flip if we
1288 view
.viewport0
[1] = miny
;
1289 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1291 ctx
->payload_tiler
.postfix
.viewport
=
1292 panfrost_upload_transient(ctx
,
1294 sizeof(struct mali_viewport
));
1299 /* Corresponds to exactly one draw, but does not submit anything */
1302 panfrost_queue_draw(struct panfrost_context
*ctx
)
1304 /* TODO: Expand the array? */
1305 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1306 DBG("Job buffer overflow, ignoring draw\n");
1310 /* Handle dirty flags now */
1311 panfrost_emit_for_draw(ctx
, true);
1313 /* We need a set_value job before any other draw jobs */
1314 if (ctx
->draw_count
== 0)
1315 panfrost_set_value_job(ctx
);
1317 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false);
1318 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1319 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1321 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true);
1322 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1323 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1328 /* The entire frame is in memory -- send it off to the kernel! */
1331 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1332 struct pipe_fence_handle
**fence
,
1333 struct panfrost_job
*job
)
1335 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1336 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1338 /* Edge case if screen is cleared and nothing else */
1339 bool has_draws
= ctx
->draw_count
> 0;
1341 /* Workaround a bizarre lockup (a hardware errata?) */
1343 flush_immediate
= true;
1347 bool is_scanout
= panfrost_is_scanout(ctx
);
1348 screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1350 /* If visual, we can stall a frame */
1352 if (!flush_immediate
)
1353 screen
->driver
->force_flush_fragment(ctx
, fence
);
1355 screen
->last_fragment_flushed
= false;
1356 screen
->last_job
= job
;
1358 /* If readback, flush now (hurts the pipelined performance) */
1359 if (flush_immediate
)
1360 screen
->driver
->force_flush_fragment(ctx
, fence
);
1362 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1363 screen
->driver
->dump_counters(screen
);
1366 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1367 FILE *fp
= fopen(filename
, "wb");
1368 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1376 panfrost_draw_wallpaper(struct pipe_context
*pipe
)
1378 struct panfrost_context
*ctx
= pan_context(pipe
);
1379 struct pipe_blit_info binfo
= { };
1381 /* Nothing to reload? */
1382 if (ctx
->pipe_framebuffer
.cbufs
[0] == NULL
)
1385 util_blitter_save_vertex_buffer_slot(ctx
->blitter
, ctx
->vertex_buffers
);
1386 util_blitter_save_vertex_elements(ctx
->blitter
, ctx
->vertex
);
1387 util_blitter_save_vertex_shader(ctx
->blitter
, ctx
->vs
);
1388 util_blitter_save_rasterizer(ctx
->blitter
, ctx
->rasterizer
);
1389 util_blitter_save_viewport(ctx
->blitter
, &ctx
->pipe_viewport
);
1390 util_blitter_save_scissor(ctx
->blitter
, &ctx
->scissor
);
1391 util_blitter_save_fragment_shader(ctx
->blitter
, ctx
->fs
);
1392 util_blitter_save_blend(ctx
->blitter
, ctx
->blend
);
1393 util_blitter_save_depth_stencil_alpha(ctx
->blitter
, ctx
->depth_stencil
);
1394 util_blitter_save_stencil_ref(ctx
->blitter
, &ctx
->stencil_ref
);
1395 util_blitter_save_so_targets(ctx
->blitter
, 0, NULL
);
1398 // util_blitter_save_sample_mask(ctx->blitter, vc4->sample_mask);
1400 util_blitter_save_framebuffer(ctx
->blitter
, &ctx
->pipe_framebuffer
);
1401 util_blitter_save_fragment_sampler_states(ctx
->blitter
,
1402 ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
],
1403 (void **)(&ctx
->samplers
[PIPE_SHADER_FRAGMENT
]));
1404 util_blitter_save_fragment_sampler_views(ctx
->blitter
,
1405 ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
],
1406 (struct pipe_sampler_view
**)&ctx
->sampler_views
[PIPE_SHADER_FRAGMENT
]);
1409 binfo
.src
.resource
= binfo
.dst
.resource
= ctx
->pipe_framebuffer
.cbufs
[0]->texture
;
1410 binfo
.src
.level
= binfo
.dst
.level
= 0;
1411 binfo
.src
.box
.x
= binfo
.dst
.box
.x
= 0;
1412 binfo
.src
.box
.y
= binfo
.dst
.box
.y
= 0;
1413 binfo
.src
.box
.width
= binfo
.dst
.box
.width
= ctx
->pipe_framebuffer
.width
;
1414 binfo
.src
.box
.height
= binfo
.dst
.box
.height
= ctx
->pipe_framebuffer
.height
;
1416 /* This avoids an assert due to missing nir_texop_txb support */
1417 //binfo.src.box.depth = binfo.dst.box.depth = 1;
1419 binfo
.src
.format
= binfo
.dst
.format
= ctx
->pipe_framebuffer
.cbufs
[0]->texture
->format
;
1421 assert(ctx
->pipe_framebuffer
.nr_cbufs
== 1);
1422 binfo
.mask
= PIPE_MASK_RGBA
;
1423 binfo
.filter
= PIPE_TEX_FILTER_LINEAR
;
1424 binfo
.scissor_enable
= FALSE
;
1426 util_blitter_blit(ctx
->blitter
, &binfo
);
1428 /* We are flushing all queued draws and we know that no more jobs will
1429 * be added until the next frame.
1430 * We also know that the last jobs are the wallpaper jobs, and they
1431 * need to be linked so they execute right after the set_value job.
1434 /* set_value job to wallpaper vertex job */
1435 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[ctx
->vertex_job_count
- 1]);
1436 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1438 /* wallpaper vertex job to first vertex job */
1439 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1], ctx
->vertex_jobs
[0]);
1440 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1442 /* last vertex job to wallpaper tiler job */
1443 panfrost_link_job_pair(ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 2], ctx
->tiler_jobs
[ctx
->tiler_job_count
- 1]);
1444 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_1
= ctx
->u_vertex_jobs
[ctx
->vertex_job_count
- 1]->job_index
;
1445 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_dependency_index_2
= 0;
1447 /* wallpaper tiler job to first tiler job */
1448 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1], ctx
->tiler_jobs
[0]);
1449 ctx
->u_tiler_jobs
[0]->job_dependency_index_1
= ctx
->u_vertex_jobs
[0]->job_index
;
1450 ctx
->u_tiler_jobs
[0]->job_dependency_index_2
= ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 1]->job_index
;
1452 /* last tiler job to NULL */
1453 panfrost_link_job_pair(ctx
->u_tiler_jobs
[ctx
->tiler_job_count
- 2], 0);
1458 struct pipe_context
*pipe
,
1459 struct pipe_fence_handle
**fence
,
1462 struct panfrost_context
*ctx
= pan_context(pipe
);
1463 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1465 /* Nothing to do! */
1466 if (!ctx
->draw_count
&& !job
->clear
) return;
1469 panfrost_draw_wallpaper(&ctx
->base
);
1471 /* Whether to stall the pipeline for immediately correct results */
1472 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1474 /* Submit the frame itself */
1475 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1477 /* Prepare for the next frame */
1478 panfrost_invalidate_frame(ctx
);
1481 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1484 g2m_draw_mode(enum pipe_prim_type mode
)
1487 DEFINE_CASE(POINTS
);
1489 DEFINE_CASE(LINE_LOOP
);
1490 DEFINE_CASE(LINE_STRIP
);
1491 DEFINE_CASE(TRIANGLES
);
1492 DEFINE_CASE(TRIANGLE_STRIP
);
1493 DEFINE_CASE(TRIANGLE_FAN
);
1495 DEFINE_CASE(QUAD_STRIP
);
1496 DEFINE_CASE(POLYGON
);
1499 unreachable("Invalid draw mode");
1506 panfrost_translate_index_size(unsigned size
)
1510 return MALI_DRAW_INDEXED_UINT8
;
1513 return MALI_DRAW_INDEXED_UINT16
;
1516 return MALI_DRAW_INDEXED_UINT32
;
1519 unreachable("Invalid index size");
1523 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1524 * good for the duration of the draw (transient), could last longer */
1527 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1529 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1531 off_t offset
= info
->start
* info
->index_size
;
1533 if (!info
->has_user_indices
) {
1534 /* Only resources can be directly mapped */
1535 return rsrc
->bo
->gpu
+ offset
;
1537 /* Otherwise, we need to upload to transient memory */
1538 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1539 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1545 struct pipe_context
*pipe
,
1546 const struct pipe_draw_info
*info
)
1548 struct panfrost_context
*ctx
= pan_context(pipe
);
1550 ctx
->payload_vertex
.draw_start
= info
->start
;
1551 ctx
->payload_tiler
.draw_start
= info
->start
;
1553 int mode
= info
->mode
;
1555 /* Fallback for unsupported modes */
1557 if (!(ctx
->draw_modes
& (1 << mode
))) {
1558 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1559 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1561 if (info
->count
< 4) {
1562 /* Degenerate case? */
1566 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1567 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1572 /* Now that we have a guaranteed terminating path, find the job.
1573 * Assignment commented out to prevent unused warning */
1575 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1577 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1579 ctx
->vertex_count
= info
->count
;
1581 /* For non-indexed draws, they're the same */
1582 unsigned invocation_count
= ctx
->vertex_count
;
1584 unsigned draw_flags
= 0;
1586 /* The draw flags interpret how primitive size is interpreted */
1588 if (panfrost_writes_point_size(ctx
))
1589 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1591 /* For higher amounts of vertices (greater than what fits in a 16-bit
1592 * short), the other value is needed, otherwise there will be bizarre
1593 * rendering artefacts. It's not clear what these values mean yet. */
1595 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1597 if (info
->index_size
) {
1598 /* Calculate the min/max index used so we can figure out how
1599 * many times to invoke the vertex shader */
1601 /* Fetch / calculate index bounds */
1602 unsigned min_index
= 0, max_index
= 0;
1604 if (info
->max_index
== ~0u) {
1605 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1607 min_index
= info
->min_index
;
1608 max_index
= info
->max_index
;
1611 /* Use the corresponding values */
1612 invocation_count
= max_index
- min_index
+ 1;
1613 ctx
->payload_vertex
.draw_start
= min_index
;
1614 ctx
->payload_tiler
.draw_start
= min_index
;
1616 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1617 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1619 //assert(!info->restart_index); /* TODO: Research */
1620 assert(!info
->index_bias
);
1622 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1623 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1625 /* Index count == vertex count, if no indexing is applied, as
1626 * if it is internally indexed in the expected order */
1628 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1629 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1631 /* Reverse index state */
1632 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1635 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1636 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1637 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1639 /* Fire off the draw itself */
1640 panfrost_queue_draw(ctx
);
1646 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1652 panfrost_create_rasterizer_state(
1653 struct pipe_context
*pctx
,
1654 const struct pipe_rasterizer_state
*cso
)
1656 struct panfrost_context
*ctx
= pan_context(pctx
);
1657 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1661 /* Bitmask, unknown meaning of the start value */
1662 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1665 so
->tiler_gl_enables
|= MALI_FRONT_CCW_TOP
;
1667 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1668 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1670 if (cso
->cull_face
& PIPE_FACE_BACK
)
1671 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1677 panfrost_bind_rasterizer_state(
1678 struct pipe_context
*pctx
,
1681 struct panfrost_context
*ctx
= pan_context(pctx
);
1683 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1687 ctx
->rasterizer
= hwcso
;
1688 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1692 panfrost_create_vertex_elements_state(
1693 struct pipe_context
*pctx
,
1694 unsigned num_elements
,
1695 const struct pipe_vertex_element
*elements
)
1697 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1699 so
->num_elements
= num_elements
;
1700 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1702 /* XXX: What the cornball? This is totally, 100%, unapologetically
1703 * nonsense. And yet it somehow fixes a regression in -bshadow
1704 * (previously, we allocated the descriptor here... a newer commit
1705 * removed that allocation, and then memory corruption led to
1706 * shader_meta getting overwritten in bad ways and then the whole test
1707 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1709 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1711 for (int i
= 0; i
< num_elements
; ++i
) {
1712 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1714 enum pipe_format fmt
= elements
[i
].src_format
;
1715 const struct util_format_description
*desc
= util_format_description(fmt
);
1716 so
->hw
[i
].unknown1
= 0x2;
1717 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1719 so
->hw
[i
].format
= panfrost_find_format(desc
);
1721 /* The field itself should probably be shifted over */
1722 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1729 panfrost_bind_vertex_elements_state(
1730 struct pipe_context
*pctx
,
1733 struct panfrost_context
*ctx
= pan_context(pctx
);
1735 ctx
->vertex
= hwcso
;
1736 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1740 panfrost_create_shader_state(
1741 struct pipe_context
*pctx
,
1742 const struct pipe_shader_state
*cso
)
1744 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1747 /* Token deep copy to prevent memory corruption */
1749 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1750 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1756 panfrost_delete_shader_state(
1757 struct pipe_context
*pctx
,
1760 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1762 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1763 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1770 panfrost_create_sampler_state(
1771 struct pipe_context
*pctx
,
1772 const struct pipe_sampler_state
*cso
)
1774 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1777 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1779 struct mali_sampler_descriptor sampler_descriptor
= {
1780 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1781 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1782 | translate_mip_filter(cso
->min_mip_filter
)
1785 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1786 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1787 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1788 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1790 cso
->border_color
.f
[0],
1791 cso
->border_color
.f
[1],
1792 cso
->border_color
.f
[2],
1793 cso
->border_color
.f
[3]
1795 .min_lod
= FIXED_16(cso
->min_lod
),
1796 .max_lod
= FIXED_16(cso
->max_lod
),
1800 so
->hw
= sampler_descriptor
;
1806 panfrost_bind_sampler_states(
1807 struct pipe_context
*pctx
,
1808 enum pipe_shader_type shader
,
1809 unsigned start_slot
, unsigned num_sampler
,
1812 assert(start_slot
== 0);
1814 struct panfrost_context
*ctx
= pan_context(pctx
);
1816 /* XXX: Should upload, not just copy? */
1817 ctx
->sampler_count
[shader
] = num_sampler
;
1818 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1820 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1824 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1826 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1828 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1829 /* Make sure enable state is at least the same */
1830 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1834 /* Check that the contents of the test are the same */
1835 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1836 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1838 if (!(same_func
&& same_ref
)) {
1842 /* Otherwise, we're good to go */
1847 panfrost_bind_fs_state(
1848 struct pipe_context
*pctx
,
1851 struct panfrost_context
*ctx
= pan_context(pctx
);
1856 /* Match the appropriate variant */
1858 signed variant
= -1;
1860 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1862 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1863 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
1869 if (variant
== -1) {
1870 /* No variant matched, so create a new one */
1871 variant
= variants
->variant_count
++;
1872 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1874 variants
->variants
[variant
].base
= hwcso
;
1875 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1877 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
1878 struct panfrost_context
*ctx
= pan_context(pctx
);
1879 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1881 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1882 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1886 /* Select this variant */
1887 variants
->active_variant
= variant
;
1889 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1890 assert(panfrost_variant_matches(ctx
, shader_state
));
1892 /* Now we have a variant selected, so compile and go */
1894 if (!shader_state
->compiled
) {
1895 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
1896 shader_state
->compiled
= true;
1900 ctx
->dirty
|= PAN_DIRTY_FS
;
1904 panfrost_bind_vs_state(
1905 struct pipe_context
*pctx
,
1908 struct panfrost_context
*ctx
= pan_context(pctx
);
1913 if (!ctx
->vs
->variants
[0].compiled
) {
1914 ctx
->vs
->variants
[0].base
= hwcso
;
1916 /* TODO DRY from above */
1917 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1918 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1919 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
1921 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
1922 ctx
->vs
->variants
[0].compiled
= true;
1926 ctx
->dirty
|= PAN_DIRTY_VS
;
1930 panfrost_set_vertex_buffers(
1931 struct pipe_context
*pctx
,
1932 unsigned start_slot
,
1933 unsigned num_buffers
,
1934 const struct pipe_vertex_buffer
*buffers
)
1936 struct panfrost_context
*ctx
= pan_context(pctx
);
1938 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1942 panfrost_set_constant_buffer(
1943 struct pipe_context
*pctx
,
1944 enum pipe_shader_type shader
, uint index
,
1945 const struct pipe_constant_buffer
*buf
)
1947 struct panfrost_context
*ctx
= pan_context(pctx
);
1948 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1950 size_t sz
= buf
? buf
->buffer_size
: 0;
1952 /* Free previous buffer */
1959 pbuf
->buffer
= NULL
;
1962 /* If unbinding, we're done */
1967 /* Multiple constant buffers not yet supported */
1972 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1975 cpu
= rsrc
->bo
->cpu
;
1976 } else if (buf
->user_buffer
) {
1977 cpu
= buf
->user_buffer
;
1979 DBG("No constant buffer?\n");
1983 /* Copy the constant buffer into the driver context for later upload */
1985 pbuf
->buffer
= malloc(sz
);
1986 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1990 panfrost_set_stencil_ref(
1991 struct pipe_context
*pctx
,
1992 const struct pipe_stencil_ref
*ref
)
1994 struct panfrost_context
*ctx
= pan_context(pctx
);
1995 ctx
->stencil_ref
= *ref
;
1997 /* Shader core dirty */
1998 ctx
->dirty
|= PAN_DIRTY_FS
;
2001 static struct pipe_sampler_view
*
2002 panfrost_create_sampler_view(
2003 struct pipe_context
*pctx
,
2004 struct pipe_resource
*texture
,
2005 const struct pipe_sampler_view
*template)
2007 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
2008 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2010 pipe_reference(NULL
, &texture
->reference
);
2012 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2015 so
->base
= *template;
2016 so
->base
.texture
= texture
;
2017 so
->base
.reference
.count
= 1;
2018 so
->base
.context
= pctx
;
2020 /* sampler_views correspond to texture descriptors, minus the texture
2021 * (data) itself. So, we serialise the descriptor here and cache it for
2024 /* Make sure it's something with which we're familiar */
2025 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2027 /* TODO: Detect from format better */
2028 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2030 unsigned char user_swizzle
[4] = {
2031 template->swizzle_r
,
2032 template->swizzle_g
,
2033 template->swizzle_b
,
2037 enum mali_format format
= panfrost_find_format(desc
);
2039 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2041 unsigned usage2_layout
= 0x10;
2043 switch (prsrc
->bo
->layout
) {
2045 usage2_layout
|= 0x8 | 0x4;
2048 usage2_layout
|= 0x1;
2051 usage2_layout
|= is_depth
? 0x1 : 0x2;
2058 /* Check if we need to set a custom stride by computing the "expected"
2059 * stride and comparing it to what the BO actually wants. Only applies
2060 * to linear textures TODO: Mipmap? */
2062 unsigned actual_stride
= prsrc
->bo
->slices
[0].stride
;
2064 if (prsrc
->bo
->layout
== PAN_LINEAR
&&
2065 template->u
.tex
.last_level
== 0 &&
2066 template->u
.tex
.first_level
== 0 &&
2067 (texture
->width0
* bytes_per_pixel
) != actual_stride
) {
2068 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2071 struct mali_texture_descriptor texture_descriptor
= {
2072 .width
= MALI_POSITIVE(texture
->width0
),
2073 .height
= MALI_POSITIVE(texture
->height0
),
2074 .depth
= MALI_POSITIVE(texture
->depth0
),
2078 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2082 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
2084 .usage2
= usage2_layout
2087 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2090 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2091 assert (template->u
.tex
.first_level
== 0);
2093 /* Disable mipmapping for now to avoid regressions while automipmapping
2094 * is being implemented. TODO: Remove me once automipmaps work */
2096 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2097 texture_descriptor
.nr_mipmap_levels
= 0;
2099 so
->hw
= texture_descriptor
;
2101 return (struct pipe_sampler_view
*) so
;
2105 panfrost_set_sampler_views(
2106 struct pipe_context
*pctx
,
2107 enum pipe_shader_type shader
,
2108 unsigned start_slot
, unsigned num_views
,
2109 struct pipe_sampler_view
**views
)
2111 struct panfrost_context
*ctx
= pan_context(pctx
);
2113 assert(start_slot
== 0);
2115 ctx
->sampler_view_count
[shader
] = num_views
;
2116 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2118 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2122 panfrost_sampler_view_destroy(
2123 struct pipe_context
*pctx
,
2124 struct pipe_sampler_view
*view
)
2126 pipe_resource_reference(&view
->texture
, NULL
);
2131 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2132 const struct pipe_framebuffer_state
*fb
)
2134 struct panfrost_context
*ctx
= pan_context(pctx
);
2136 /* Flush when switching away from an FBO, but not if the framebuffer
2137 * state is being restored by u_blitter
2140 if (!panfrost_is_scanout(ctx
) && !ctx
->blitter
->running
) {
2141 panfrost_flush(pctx
, NULL
, 0);
2144 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2145 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2146 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2147 ctx
->pipe_framebuffer
.width
= fb
->width
;
2148 ctx
->pipe_framebuffer
.height
= fb
->height
;
2150 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2151 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2153 /* check if changing cbuf */
2154 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2156 if (cb
&& (i
!= 0)) {
2157 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2162 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2167 if (ctx
->require_sfbd
)
2168 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2170 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2172 panfrost_attach_vt_framebuffer(ctx
);
2174 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2175 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2176 bool is_scanout
= panfrost_is_scanout(ctx
);
2178 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& panfrost_can_afbc(format
)) {
2179 /* The blob is aggressive about enabling AFBC. As such,
2180 * it's pretty much necessary to use it here, since we
2181 * have no traces of non-compressed FBO. */
2183 panfrost_enable_afbc(ctx
, tex
, false);
2186 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2187 /* Enable transaction elimination if we can */
2188 panfrost_enable_checksum(ctx
, tex
);
2193 struct pipe_surface
*zb
= fb
->zsbuf
;
2195 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2196 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2201 if (ctx
->require_sfbd
)
2202 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2204 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2206 panfrost_attach_vt_framebuffer(ctx
);
2208 /* Keep the depth FBO linear */
2215 panfrost_create_blend_state(struct pipe_context
*pipe
,
2216 const struct pipe_blend_state
*blend
)
2218 struct panfrost_context
*ctx
= pan_context(pipe
);
2219 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2222 /* TODO: The following features are not yet implemented */
2223 assert(!blend
->logicop_enable
);
2224 assert(!blend
->alpha_to_coverage
);
2225 assert(!blend
->alpha_to_one
);
2227 /* Compile the blend state, first as fixed-function if we can */
2229 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2232 /* If we can't, compile a blend shader instead */
2234 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2240 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2243 struct panfrost_context
*ctx
= pan_context(pipe
);
2244 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2245 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2246 ctx
->blend
= pblend
;
2251 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2253 /* TODO: Attach color */
2255 /* Shader itself is not dirty, but the shader core is */
2256 ctx
->dirty
|= PAN_DIRTY_FS
;
2260 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2263 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2265 if (so
->has_blend_shader
) {
2266 DBG("Deleting blend state leak blend shaders bytecode\n");
2273 panfrost_set_blend_color(struct pipe_context
*pipe
,
2274 const struct pipe_blend_color
*blend_color
)
2276 struct panfrost_context
*ctx
= pan_context(pipe
);
2278 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2281 ctx
->blend_color
= *blend_color
;
2283 /* The blend mode depends on the blend constant color, due to the
2284 * fixed/programmable split. So, we're forced to regenerate the blend
2287 /* TODO: Attach color */
2292 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2293 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2295 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2299 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2302 struct panfrost_context
*ctx
= pan_context(pipe
);
2303 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2304 ctx
->depth_stencil
= depth_stencil
;
2309 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2310 * emulated in the fragment shader */
2312 if (depth_stencil
->alpha
.enabled
) {
2313 /* We need to trigger a new shader (maybe) */
2314 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2318 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2320 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2321 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2323 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2324 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2326 /* Depth state (TODO: Refactor) */
2327 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2329 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2331 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2332 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2334 /* Bounds test not implemented */
2335 assert(!depth_stencil
->depth
.bounds_test
);
2337 ctx
->dirty
|= PAN_DIRTY_FS
;
2341 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2347 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2348 unsigned sample_mask
)
2353 panfrost_set_clip_state(struct pipe_context
*pipe
,
2354 const struct pipe_clip_state
*clip
)
2356 //struct panfrost_context *panfrost = pan_context(pipe);
2360 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2361 unsigned start_slot
,
2362 unsigned num_viewports
,
2363 const struct pipe_viewport_state
*viewports
)
2365 struct panfrost_context
*ctx
= pan_context(pipe
);
2367 assert(start_slot
== 0);
2368 assert(num_viewports
== 1);
2370 ctx
->pipe_viewport
= *viewports
;
2374 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2375 unsigned start_slot
,
2376 unsigned num_scissors
,
2377 const struct pipe_scissor_state
*scissors
)
2379 struct panfrost_context
*ctx
= pan_context(pipe
);
2381 assert(start_slot
== 0);
2382 assert(num_scissors
== 1);
2384 ctx
->scissor
= *scissors
;
2388 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2389 const struct pipe_poly_stipple
*stipple
)
2391 //struct panfrost_context *panfrost = pan_context(pipe);
2395 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2398 //struct panfrost_context *panfrost = pan_context(pipe);
2402 panfrost_destroy(struct pipe_context
*pipe
)
2404 struct panfrost_context
*panfrost
= pan_context(pipe
);
2405 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2407 if (panfrost
->blitter
)
2408 util_blitter_destroy(panfrost
->blitter
);
2410 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2411 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2412 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2413 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2414 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2417 static struct pipe_query
*
2418 panfrost_create_query(struct pipe_context
*pipe
,
2422 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2427 return (struct pipe_query
*) q
;
2431 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2437 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2439 struct panfrost_context
*ctx
= pan_context(pipe
);
2440 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2442 switch (query
->type
) {
2443 case PIPE_QUERY_OCCLUSION_COUNTER
:
2444 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2445 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2447 /* Allocate a word for the query results to be stored */
2448 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2450 ctx
->occlusion_query
= query
;
2456 DBG("Skipping query %d\n", query
->type
);
2464 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2466 struct panfrost_context
*ctx
= pan_context(pipe
);
2467 ctx
->occlusion_query
= NULL
;
2472 panfrost_get_query_result(struct pipe_context
*pipe
,
2473 struct pipe_query
*q
,
2475 union pipe_query_result
*vresult
)
2478 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2480 /* We need to flush out the jobs to actually run the counter, TODO
2481 * check wait, TODO wallpaper after if needed */
2483 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2485 switch (query
->type
) {
2486 case PIPE_QUERY_OCCLUSION_COUNTER
:
2487 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2488 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2489 /* Read back the query results */
2490 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2491 unsigned passed
= *result
;
2493 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2494 vresult
->u64
= passed
;
2496 vresult
->b
= !!passed
;
2502 DBG("Skipped query get %d\n", query
->type
);
2509 static struct pipe_stream_output_target
*
2510 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2511 struct pipe_resource
*prsc
,
2512 unsigned buffer_offset
,
2513 unsigned buffer_size
)
2515 struct pipe_stream_output_target
*target
;
2517 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2522 pipe_reference_init(&target
->reference
, 1);
2523 pipe_resource_reference(&target
->buffer
, prsc
);
2525 target
->context
= pctx
;
2526 target
->buffer_offset
= buffer_offset
;
2527 target
->buffer_size
= buffer_size
;
2533 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2534 struct pipe_stream_output_target
*target
)
2536 pipe_resource_reference(&target
->buffer
, NULL
);
2541 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2542 unsigned num_targets
,
2543 struct pipe_stream_output_target
**targets
,
2544 const unsigned *offsets
)
2550 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2552 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2553 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2555 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2556 /* Allocate the beginning of the transient pool */
2557 int entry_size
= (1 << 22); /* 4MB */
2559 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2560 ctx
->transient_pools
[i
].entry_count
= 1;
2562 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2565 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2566 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2567 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2568 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2569 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2573 /* New context creation, which also does hardware initialisation since I don't
2574 * know the better way to structure this :smirk: */
2576 struct pipe_context
*
2577 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2579 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2580 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2581 memset(ctx
, 0, sizeof(*ctx
));
2582 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2585 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2587 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2588 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2590 gallium
->screen
= screen
;
2592 gallium
->destroy
= panfrost_destroy
;
2594 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2596 gallium
->flush
= panfrost_flush
;
2597 gallium
->clear
= panfrost_clear
;
2598 gallium
->draw_vbo
= panfrost_draw_vbo
;
2600 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2601 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2603 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2605 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2606 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2607 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2609 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2610 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2611 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2613 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2614 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2615 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2617 gallium
->create_fs_state
= panfrost_create_shader_state
;
2618 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2619 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2621 gallium
->create_vs_state
= panfrost_create_shader_state
;
2622 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2623 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2625 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2626 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2627 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2629 gallium
->create_blend_state
= panfrost_create_blend_state
;
2630 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2631 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2633 gallium
->set_blend_color
= panfrost_set_blend_color
;
2635 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2636 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2637 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2639 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2641 gallium
->set_clip_state
= panfrost_set_clip_state
;
2642 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2643 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2644 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2645 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2647 gallium
->create_query
= panfrost_create_query
;
2648 gallium
->destroy_query
= panfrost_destroy_query
;
2649 gallium
->begin_query
= panfrost_begin_query
;
2650 gallium
->end_query
= panfrost_end_query
;
2651 gallium
->get_query_result
= panfrost_get_query_result
;
2653 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2654 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2655 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2657 panfrost_resource_context_init(gallium
);
2659 pscreen
->driver
->init_context(ctx
);
2661 panfrost_setup_hardware(ctx
);
2664 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2665 gallium
->const_uploader
= gallium
->stream_uploader
;
2666 assert(gallium
->stream_uploader
);
2668 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2669 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2671 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2673 ctx
->blitter
= util_blitter_create(gallium
);
2674 assert(ctx
->blitter
);
2676 /* Prepare for render! */
2678 panfrost_job_init(ctx
);
2679 panfrost_emit_vertex_payload(ctx
);
2680 panfrost_emit_tiler_payload(ctx
);
2681 panfrost_invalidate_frame(ctx
);
2682 panfrost_default_shader_backend(ctx
);
2683 panfrost_generate_space_filler_indices();