2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "util/u_math.h"
45 #include "pan_screen.h"
46 #include "pan_blending.h"
47 #include "pan_blend_shaders.h"
49 #include "pan_wallpaper.h"
51 static int performance_counter_number
= 0;
52 extern const char *pan_counters_base
;
54 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
57 /* Can a given format support AFBC? Not all can. */
60 panfrost_can_afbc(enum pipe_format format
)
62 const struct util_format_description
*desc
=
63 util_format_description(format
);
65 if (util_format_is_rgba8_variant(desc
))
68 /* TODO: AFBC of other formats */
73 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
74 * indepdent between color buffers and depth/stencil). To enable, we allocate
75 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
76 * edit the fragment job here. This routine should be called ONCE per
77 * AFBC-compressed buffer, rather than on every frame. */
80 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
82 if (ctx
->require_sfbd
) {
83 DBG("AFBC not supported yet on SFBD\n");
87 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
88 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
89 /* AFBC metadata is 16 bytes per tile */
90 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
91 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
92 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
93 int stride
= bytes_per_pixel
* ALIGN(rsrc
->base
.width0
, 16);
95 stride
*= 2; /* TODO: Should this be carried over? */
96 int main_size
= stride
* rsrc
->base
.height0
;
97 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
99 /* Allocate the AFBC slab itself, large enough to hold the above */
100 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
101 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
104 rsrc
->bo
->layout
= PAN_AFBC
;
106 /* Compressed textured reads use a tagged pointer to the metadata */
108 rsrc
->bo
->gpu
= rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
109 rsrc
->bo
->cpu
= rsrc
->bo
->afbc_slab
.cpu
;
110 rsrc
->bo
->gem_handle
= rsrc
->bo
->afbc_slab
.gem_handle
;
114 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
116 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
117 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
118 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
119 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
121 /* 8 byte checksum per tile */
122 rsrc
->bo
->checksum_stride
= tile_w
* 8;
123 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
124 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
126 rsrc
->bo
->has_checksum
= true;
129 /* Framebuffer descriptor */
132 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
134 fb
->width
= MALI_POSITIVE(w
);
135 fb
->height
= MALI_POSITIVE(h
);
137 /* No idea why this is needed, but it's how resolution_check is
138 * calculated. It's not clear to us yet why the hardware wants this.
139 * The formula itself was discovered mostly by manual bruteforce and
140 * aggressive algebraic simplification. */
142 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
145 struct mali_single_framebuffer
146 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
148 struct mali_single_framebuffer framebuffer
= {
150 .format
= 0x30000000,
151 .clear_flags
= 0x1000,
152 .unknown_address_0
= ctx
->scratchpad
.gpu
,
153 .unknown_address_1
= ctx
->misc_0
.gpu
,
154 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
156 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
157 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
160 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
165 struct bifrost_framebuffer
166 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
168 struct bifrost_framebuffer framebuffer
= {
169 /* It is not yet clear what tiler_meta means or how it's
170 * calculated, but we can tell the lower 32-bits are a
171 * (monotonically increasing?) function of tile count and
172 * geometry complexity; I suspect it defines a memory size of
173 * some kind? for the tiler. It's really unclear at the
174 * moment... but to add to the confusion, the hardware is happy
175 * enough to accept a zero in this field, so we don't even have
176 * to worry about it right now.
178 * The byte (just after the 32-bit mark) is much more
179 * interesting. The higher nibble I've only ever seen as 0xF,
180 * but the lower one I've seen as 0x0 or 0xF, and it's not
181 * obvious what the difference is. But what -is- obvious is
182 * that when the lower nibble is zero, performance is severely
183 * degraded compared to when the lower nibble is set.
184 * Evidently, that nibble enables some sort of fast path,
185 * perhaps relating to caching or tile flush? Regardless, at
186 * this point there's no clear reason not to set it, aside from
187 * substantially increased memory requirements (of the misc_0
190 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
192 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
193 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
194 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
195 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
200 .rt_count_1
= MALI_POSITIVE(1),
205 /* Corresponds to unknown_address_X of SFBD */
206 .scratchpad
= ctx
->scratchpad
.gpu
,
207 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
209 /* The constant added here is, like the lower word of
210 * tiler_meta, (loosely) another product of framebuffer size
211 * and geometry complexity. It must be sufficiently large for
212 * the tiler_meta fast path to work; if it's too small, there
213 * will be DATA_INVALID_FAULTs. Conversely, it must be less
214 * than the total size of misc_0, or else there's no room. It's
215 * possible this constant configures a partition between two
216 * parts of misc_0? We haven't investigated the functionality,
217 * as these buffers are internally used by the hardware
218 * (presumably by the tiler) but not seemingly touched by the driver
221 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
223 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
224 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
230 /* Are we currently rendering to the screen (rather than an FBO)? */
233 panfrost_is_scanout(struct panfrost_context
*ctx
)
235 /* If there is no color buffer, it's an FBO */
236 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
239 /* If we're too early that no framebuffer was sent, it's scanout */
240 if (!ctx
->pipe_framebuffer
.cbufs
[0])
243 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
244 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
245 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
249 pan_pack_color(const union pipe_color_union
*color
, enum pipe_format format
)
251 /* Alpha magicked to 1.0 if there is no alpha */
253 bool has_alpha
= util_format_has_alpha(format
);
254 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
256 /* Packed color depends on the framebuffer format */
258 const struct util_format_description
*desc
=
259 util_format_description(format
);
261 if (util_format_is_rgba8_variant(desc
)) {
262 return (float_to_ubyte(clear_alpha
) << 24) |
263 (float_to_ubyte(color
->f
[2]) << 16) |
264 (float_to_ubyte(color
->f
[1]) << 8) |
265 (float_to_ubyte(color
->f
[0]) << 0);
266 } else if (format
== PIPE_FORMAT_B5G6R5_UNORM
) {
267 /* First, we convert the components to R5, G6, B5 separately */
268 unsigned r5
= CLAMP(color
->f
[0], 0.0, 1.0) * 31.0;
269 unsigned g6
= CLAMP(color
->f
[1], 0.0, 1.0) * 63.0;
270 unsigned b5
= CLAMP(color
->f
[2], 0.0, 1.0) * 31.0;
272 /* Then we pack into a sparse u32. TODO: Why these shifts? */
273 return (b5
<< 25) | (g6
<< 14) | (r5
<< 5);
284 struct pipe_context
*pipe
,
286 const union pipe_color_union
*color
,
287 double depth
, unsigned stencil
)
289 struct panfrost_context
*ctx
= pan_context(pipe
);
290 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
292 if (buffers
& PIPE_CLEAR_COLOR
) {
293 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[0]->format
;
294 job
->clear_color
= pan_pack_color(color
, format
);
297 if (buffers
& PIPE_CLEAR_DEPTH
) {
298 job
->clear_depth
= depth
;
301 if (buffers
& PIPE_CLEAR_STENCIL
) {
302 job
->clear_stencil
= stencil
;
305 job
->clear
|= buffers
;
309 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
311 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
312 struct bifrost_render_target rts_list
[] = {
317 .framebuffer
= ctx
->misc_0
.gpu
,
322 /* Allocate memory for the three components */
323 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
324 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
326 /* Opaque 1024-block */
327 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
329 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
330 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
332 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
336 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
338 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
342 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
344 mali_ptr framebuffer
= ctx
->require_sfbd
?
345 panfrost_attach_vt_sfbd(ctx
) :
346 panfrost_attach_vt_mfbd(ctx
);
348 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
349 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
352 /* Reset per-frame context, called on context initialisation as well as after
353 * flushing a frame */
356 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
358 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
359 DBG("Uploaded transient %d bytes\n", transient_count
);
361 /* Rotate cmdstream */
362 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
363 ctx
->cmdstream_i
= 0;
365 if (ctx
->require_sfbd
)
366 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
368 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
370 /* Reset varyings allocated */
371 ctx
->varying_height
= 0;
373 /* The transient cmdstream is dirty every frame; the only bits worth preserving
374 * (textures, shaders, etc) are in other buffers anyways */
376 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
377 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
379 /* Regenerate payloads */
380 panfrost_attach_vt_framebuffer(ctx
);
383 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
386 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
389 /* In practice, every field of these payloads should be configurable
390 * arbitrarily, which means these functions are basically catch-all's for
391 * as-of-yet unwavering unknowns */
394 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
396 struct midgard_payload_vertex_tiler payload
= {
398 .workgroups_z_shift
= 32,
399 .workgroups_x_shift_2
= 0x2,
400 .workgroups_x_shift_3
= 0x5,
402 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
405 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
409 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
411 struct midgard_payload_vertex_tiler payload
= {
413 .workgroups_z_shift
= 32,
414 .workgroups_x_shift_2
= 0x2,
415 .workgroups_x_shift_3
= 0x6,
417 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
421 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
425 translate_tex_wrap(enum pipe_tex_wrap w
)
428 case PIPE_TEX_WRAP_REPEAT
:
429 return MALI_WRAP_REPEAT
;
431 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
432 return MALI_WRAP_CLAMP_TO_EDGE
;
434 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
435 return MALI_WRAP_CLAMP_TO_BORDER
;
437 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
438 return MALI_WRAP_MIRRORED_REPEAT
;
441 unreachable("Invalid wrap");
446 translate_tex_filter(enum pipe_tex_filter f
)
449 case PIPE_TEX_FILTER_NEAREST
:
452 case PIPE_TEX_FILTER_LINEAR
:
456 unreachable("Invalid filter");
461 translate_mip_filter(enum pipe_tex_mipfilter f
)
463 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
467 panfrost_translate_compare_func(enum pipe_compare_func in
)
470 case PIPE_FUNC_NEVER
:
471 return MALI_FUNC_NEVER
;
474 return MALI_FUNC_LESS
;
476 case PIPE_FUNC_EQUAL
:
477 return MALI_FUNC_EQUAL
;
479 case PIPE_FUNC_LEQUAL
:
480 return MALI_FUNC_LEQUAL
;
482 case PIPE_FUNC_GREATER
:
483 return MALI_FUNC_GREATER
;
485 case PIPE_FUNC_NOTEQUAL
:
486 return MALI_FUNC_NOTEQUAL
;
488 case PIPE_FUNC_GEQUAL
:
489 return MALI_FUNC_GEQUAL
;
491 case PIPE_FUNC_ALWAYS
:
492 return MALI_FUNC_ALWAYS
;
495 unreachable("Invalid func");
500 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
503 case PIPE_FUNC_NEVER
:
504 return MALI_ALT_FUNC_NEVER
;
507 return MALI_ALT_FUNC_LESS
;
509 case PIPE_FUNC_EQUAL
:
510 return MALI_ALT_FUNC_EQUAL
;
512 case PIPE_FUNC_LEQUAL
:
513 return MALI_ALT_FUNC_LEQUAL
;
515 case PIPE_FUNC_GREATER
:
516 return MALI_ALT_FUNC_GREATER
;
518 case PIPE_FUNC_NOTEQUAL
:
519 return MALI_ALT_FUNC_NOTEQUAL
;
521 case PIPE_FUNC_GEQUAL
:
522 return MALI_ALT_FUNC_GEQUAL
;
524 case PIPE_FUNC_ALWAYS
:
525 return MALI_ALT_FUNC_ALWAYS
;
528 unreachable("Invalid alt func");
533 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
536 case PIPE_STENCIL_OP_KEEP
:
537 return MALI_STENCIL_KEEP
;
539 case PIPE_STENCIL_OP_ZERO
:
540 return MALI_STENCIL_ZERO
;
542 case PIPE_STENCIL_OP_REPLACE
:
543 return MALI_STENCIL_REPLACE
;
545 case PIPE_STENCIL_OP_INCR
:
546 return MALI_STENCIL_INCR
;
548 case PIPE_STENCIL_OP_DECR
:
549 return MALI_STENCIL_DECR
;
551 case PIPE_STENCIL_OP_INCR_WRAP
:
552 return MALI_STENCIL_INCR_WRAP
;
554 case PIPE_STENCIL_OP_DECR_WRAP
:
555 return MALI_STENCIL_DECR_WRAP
;
557 case PIPE_STENCIL_OP_INVERT
:
558 return MALI_STENCIL_INVERT
;
561 unreachable("Invalid stencil op");
566 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
568 out
->ref
= 0; /* Gallium gets it from elsewhere */
570 out
->mask
= in
->valuemask
;
571 out
->func
= panfrost_translate_compare_func(in
->func
);
572 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
573 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
574 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
578 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
580 struct mali_shader_meta shader
= {
581 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
583 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
584 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
588 shader
.unknown2_4
|= 0x10;
591 struct pipe_stencil_state default_stencil
= {
593 .func
= PIPE_FUNC_ALWAYS
,
594 .fail_op
= MALI_STENCIL_KEEP
,
595 .zfail_op
= MALI_STENCIL_KEEP
,
596 .zpass_op
= MALI_STENCIL_KEEP
,
601 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
602 shader
.stencil_mask_front
= default_stencil
.writemask
;
604 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
605 shader
.stencil_mask_back
= default_stencil
.writemask
;
607 if (default_stencil
.enabled
)
608 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
610 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
613 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
614 * graphics command stream. It should be called once per draw, accordding to
615 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
616 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
619 struct panfrost_transfer
620 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
622 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
623 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
625 struct mali_job_descriptor_header job
= {
626 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
627 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
629 .job_descriptor_size
= 1,
633 /* Only non-elided tiler jobs have dependencies which are known at this point */
635 if (is_tiler
&& !is_elided_tiler
) {
636 /* Tiler jobs depend on vertex jobs */
638 job
.job_dependency_index_1
= draw_job_index
;
640 /* Tiler jobs also depend on the previous tiler job */
643 job
.job_dependency_index_2
= draw_job_index
- 1;
646 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
648 /* There's some padding hacks on 32-bit */
655 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
656 memcpy(transfer
.cpu
, &job
, sizeof(job
));
657 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
661 /* Generates a set value job. It's unclear what exactly this does, why it's
662 * necessary, and when to call it. */
665 panfrost_set_value_job(struct panfrost_context
*ctx
)
667 struct mali_job_descriptor_header job
= {
668 .job_type
= JOB_TYPE_SET_VALUE
,
669 .job_descriptor_size
= 1,
670 .job_index
= 1 + (2 * ctx
->draw_count
),
673 struct mali_payload_set_value payload
= {
674 .out
= ctx
->misc_0
.gpu
,
678 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
679 memcpy(transfer
.cpu
, &job
, sizeof(job
));
680 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
682 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
683 ctx
->set_value_job
= transfer
.gpu
;
687 panfrost_emit_varyings(
688 struct panfrost_context
*ctx
,
689 union mali_attr
*slot
,
693 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
695 /* Fill out the descriptor */
696 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
697 slot
->stride
= stride
;
698 slot
->size
= stride
* count
;
700 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
701 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
703 return varying_address
;
707 panfrost_emit_point_coord(union mali_attr
*slot
)
709 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
710 slot
->stride
= slot
->size
= 0;
714 panfrost_emit_varying_descriptor(
715 struct panfrost_context
*ctx
,
716 unsigned invocation_count
)
718 /* Load the shaders */
720 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
721 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
723 /* Allocate the varying descriptor */
725 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
726 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
728 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
731 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
732 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
734 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
735 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
737 /* Buffer indices must be in this order per our convention */
738 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
741 /* General varyings -- use the VS's, since those are more likely to be
742 * accurate on desktop */
744 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
745 vs
->general_varying_stride
, invocation_count
);
747 /* fp32 vec4 gl_Position */
748 ctx
->payload_tiler
.postfix
.position_varying
=
749 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
750 sizeof(float) * 4, invocation_count
);
753 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
754 /* fp16 vec1 gl_PointSize */
755 ctx
->payload_tiler
.primitive_size
.pointer
=
756 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
757 2, invocation_count
);
760 if (fs
->reads_point_coord
) {
761 /* Special descriptor */
762 panfrost_emit_point_coord(&varyings
[idx
++]);
765 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
766 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
767 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
771 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
773 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
774 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
776 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
779 /* Emits attributes and varying descriptors, which should be called every draw,
780 * excepting some obscure circumstances */
783 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
785 /* Staged mali_attr, and index into them. i =/= k, depending on the
786 * vertex buffer mask */
787 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
790 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
792 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
793 if (!(ctx
->vb_mask
& (1 << i
))) continue;
795 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
796 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
800 /* Align to 64 bytes by masking off the lower bits. This
801 * will be adjusted back when we fixup the src_offset in
804 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
806 /* Offset vertex count by draw_start to make sure we upload enough */
807 attrs
[k
].stride
= buf
->stride
;
808 attrs
[k
].size
= rsrc
->base
.width0
;
810 panfrost_job_add_bo(job
, rsrc
->bo
);
811 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
816 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
818 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
822 panfrost_writes_point_size(struct panfrost_context
*ctx
)
825 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
827 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
830 /* Stage the attribute descriptors so we can adjust src_offset
831 * to let BOs align nicely */
834 panfrost_stage_attributes(struct panfrost_context
*ctx
)
836 struct panfrost_vertex_state
*so
= ctx
->vertex
;
838 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
839 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
840 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
842 /* Copy as-is for the first pass */
843 memcpy(target
, so
->hw
, sz
);
845 /* Fixup offsets for the second pass. Recall that the hardware
846 * calculates attribute addresses as:
848 * addr = base + (stride * vtx) + src_offset;
850 * However, on Mali, base must be aligned to 64-bytes, so we
853 * base' = base & ~63 = base - (base & 63)
855 * To compensate when using base' (see emit_vertex_data), we have
856 * to adjust src_offset by the masked off piece:
858 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
859 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
860 * = base + (stride * vtx) + src_offset
866 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
867 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
868 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
870 /* Adjust by the masked off bits of the offset */
871 target
[i
].src_offset
+= (addr
& 63);
874 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
877 /* Go through dirty flags and actualise them in the cmdstream. */
880 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
882 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
884 if (with_vertex_data
) {
885 panfrost_emit_vertex_data(ctx
, job
);
888 bool msaa
= ctx
->rasterizer
->base
.multisample
;
890 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
891 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
893 /* TODO: Sample size */
894 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
895 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
898 /* Enable job requirements at draw-time */
901 job
->requirements
|= PAN_REQ_MSAA
;
903 if (ctx
->depth_stencil
->depth
.writemask
)
904 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
906 if (ctx
->occlusion_query
) {
907 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
908 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
911 if (ctx
->dirty
& PAN_DIRTY_VS
) {
914 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
916 /* Late shader descriptor assignments */
918 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
919 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
922 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
924 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
927 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
928 /* Check if we need to link the gl_PointSize varying */
929 if (!panfrost_writes_point_size(ctx
)) {
930 /* If the size is constant, write it out. Otherwise,
931 * don't touch primitive_size (since we would clobber
932 * the pointer there) */
934 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
938 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
940 ctx
->dirty
|= PAN_DIRTY_FS
;
942 if (ctx
->dirty
& PAN_DIRTY_FS
) {
944 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
946 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
949 COPY(attribute_count
);
951 COPY(midgard1
.uniform_count
);
952 COPY(midgard1
.work_count
);
953 COPY(midgard1
.unknown2
);
956 /* If there is a blend shader, work registers are shared */
958 if (ctx
->blend
->has_blend_shader
)
959 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
961 /* Set late due to depending on render state */
962 /* The one at the end seems to mean "1 UBO" */
963 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
965 /* Assign texture/sample count right before upload */
966 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
967 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
969 /* Assign the stencil refs late */
970 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
971 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
973 /* CAN_DISCARD should be set if the fragment shader possibly
974 * contains a 'discard' instruction. It is likely this is
975 * related to optimizations related to forward-pixel kill, as
976 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
977 * thing?" by Peter Harris
980 if (variant
->can_discard
) {
981 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
982 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
983 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
984 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
987 /* Check if we're using the default blend descriptor (fast path) */
990 !ctx
->blend
->has_blend_shader
&&
991 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
992 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
993 (ctx
->blend
->equation
.color_mask
== 0xf);
995 /* Even on MFBD, the shader descriptor gets blend shaders. It's
996 * *also* copied to the blend_meta appended (by convention),
997 * but this is the field actually read by the hardware. (Or
998 * maybe both are read...?) */
1000 if (ctx
->blend
->has_blend_shader
) {
1001 ctx
->fragment_shader_core
.blend
.shader
= ctx
->blend
->blend_shader
;
1004 if (ctx
->require_sfbd
) {
1005 /* When only a single render target platform is used, the blend
1006 * information is inside the shader meta itself. We
1007 * additionally need to signal CAN_DISCARD for nontrivial blend
1008 * modes (so we're able to read back the destination buffer) */
1010 if (!ctx
->blend
->has_blend_shader
) {
1011 ctx
->fragment_shader_core
.blend
.equation
= ctx
->blend
->equation
;
1012 ctx
->fragment_shader_core
.blend
.constant
= ctx
->blend
->constant
;
1016 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1020 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct midgard_blend_rt
);
1021 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1022 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1024 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1026 if (!ctx
->require_sfbd
) {
1027 /* Additional blend descriptor tacked on for jobs using MFBD */
1029 unsigned blend_count
= 0x200;
1031 if (ctx
->blend
->has_blend_shader
) {
1032 /* For a blend shader, the bottom nibble corresponds to
1033 * the number of work registers used, which signals the
1034 * -existence- of a blend shader */
1036 assert(ctx
->blend
->blend_work_count
>= 2);
1037 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1039 /* Otherwise, the bottom bit simply specifies if
1040 * blending (anything other than REPLACE) is enabled */
1047 struct midgard_blend_rt rts
[4];
1051 for (unsigned i
= 0; i
< 1; ++i
) {
1052 rts
[i
].flags
= blend_count
;
1054 if (ctx
->blend
->has_blend_shader
) {
1055 rts
[i
].blend
.shader
= ctx
->blend
->blend_shader
;
1057 rts
[i
].blend
.equation
= ctx
->blend
->equation
;
1058 rts
[i
].blend
.constant
= ctx
->blend
->constant
;
1062 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), rts
, sizeof(rts
[0]) * 1);
1066 /* We stage to transient, so always dirty.. */
1067 panfrost_stage_attributes(ctx
);
1069 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
1070 /* Upload samplers back to back, no padding */
1072 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1073 if (!ctx
->sampler_count
[t
]) continue;
1075 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
1076 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
1078 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
1079 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
1082 if (t
== PIPE_SHADER_FRAGMENT
)
1083 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
1084 else if (t
== PIPE_SHADER_VERTEX
)
1085 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1091 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1092 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1094 if (!ctx
->sampler_view_count
[t
]) continue;
1096 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1098 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1099 if (!ctx
->sampler_views
[t
][i
])
1102 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1103 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1105 /* Inject the addresses in, interleaving cube
1106 * faces and mip levels appropriately. */
1108 for (int l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
1109 for (int f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
1110 unsigned idx
= (l
* tex_rsrc
->array_size
) + f
;
1112 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[idx
] =
1114 rsrc
->bo
->slices
[l
].offset
+
1115 f
* rsrc
->bo
->cubemap_stride
;
1119 /* Inject the strides */
1120 unsigned usage2
= ctx
->sampler_views
[t
][i
]->hw
.format
.usage2
;
1122 if (usage2
& MALI_TEX_MANUAL_STRIDE
) {
1123 unsigned idx
= tex_rsrc
->last_level
* tex_rsrc
->array_size
;
1124 idx
+= tex_rsrc
->array_size
;
1126 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[idx
] =
1127 rsrc
->bo
->slices
[0].stride
;
1130 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1133 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1135 if (t
== PIPE_SHADER_FRAGMENT
)
1136 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1137 else if (t
== PIPE_SHADER_VERTEX
)
1138 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1144 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1146 /* For flipped-Y buffers (signaled by negative scale), the translate is
1147 * flipped as well */
1149 bool invert_y
= vp
->scale
[1] < 0.0;
1150 float translate_y
= vp
->translate
[1];
1153 translate_y
= ctx
->pipe_framebuffer
.height
- translate_y
;
1155 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1156 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1158 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1159 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1160 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1162 /* Allocate room for the sysval and the uniforms */
1163 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1164 size_t size
= sys_size
+ buf
->size
;
1165 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1167 /* Upload sysvals requested by the shader */
1168 float *uniforms
= (float *) transfer
.cpu
;
1169 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1170 int sysval
= ss
->sysval
[i
];
1172 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1173 uniforms
[4*i
+ 0] = vp
->scale
[0];
1174 uniforms
[4*i
+ 1] = fabsf(vp
->scale
[1]);
1175 uniforms
[4*i
+ 2] = vp
->scale
[2];
1176 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1177 uniforms
[4*i
+ 0] = vp
->translate
[0];
1178 uniforms
[4*i
+ 1] = translate_y
;
1179 uniforms
[4*i
+ 2] = vp
->translate
[2];
1185 /* Upload uniforms */
1186 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1188 int uniform_count
= 0;
1190 struct mali_vertex_tiler_postfix
*postfix
;
1193 case PIPE_SHADER_VERTEX
:
1194 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1195 postfix
= &ctx
->payload_vertex
.postfix
;
1198 case PIPE_SHADER_FRAGMENT
:
1199 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1200 postfix
= &ctx
->payload_tiler
.postfix
;
1204 unreachable("Invalid shader stage\n");
1207 /* Also attach the same buffer as a UBO for extended access */
1209 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1211 .size
= MALI_POSITIVE((2 + uniform_count
)),
1212 .ptr
= transfer
.gpu
>> 2,
1216 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1217 postfix
->uniforms
= transfer
.gpu
;
1218 postfix
->uniform_buffers
= ubufs
;
1223 /* TODO: Upload the viewport somewhere more appropriate */
1225 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1226 * (somewhat) asymmetric ints. */
1227 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1229 struct mali_viewport view
= {
1230 /* By default, do no viewport clipping, i.e. clip to (-inf,
1231 * inf) in each direction. Clipping to the viewport in theory
1232 * should work, but in practice causes issues when we're not
1233 * explicitly trying to scissor */
1244 /* Always scissor to the viewport by default. */
1245 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1246 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1248 view
.viewport0
[1] = (int) (translate_y
- fabs(vp
->scale
[1]));
1249 view
.viewport1
[1] = MALI_POSITIVE((int) (translate_y
+ fabs(vp
->scale
[1])));
1251 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1252 /* Invert scissor if needed */
1253 unsigned miny
= invert_y
?
1254 ctx
->pipe_framebuffer
.height
- ss
->maxy
: ss
->miny
;
1256 unsigned maxy
= invert_y
?
1257 ctx
->pipe_framebuffer
.height
- ss
->miny
: ss
->maxy
;
1259 /* Set the actual scissor */
1260 view
.viewport0
[0] = ss
->minx
;
1261 view
.viewport0
[1] = miny
;
1262 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1263 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1266 ctx
->payload_tiler
.postfix
.viewport
=
1267 panfrost_upload_transient(ctx
,
1269 sizeof(struct mali_viewport
));
1274 /* Corresponds to exactly one draw, but does not submit anything */
1277 panfrost_queue_draw(struct panfrost_context
*ctx
)
1279 /* TODO: Expand the array? */
1280 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1281 DBG("Job buffer overflow, ignoring draw\n");
1285 /* Handle dirty flags now */
1286 panfrost_emit_for_draw(ctx
, true);
1288 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1289 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1291 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1292 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1294 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1295 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1300 /* At the end of the frame, the vertex and tiler jobs are linked together and
1301 * then the fragment job is plonked at the end. Set value job is first for
1302 * unknown reasons. */
1305 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1307 if (first
->job_descriptor_size
)
1308 first
->next_job_64
= (u64
) (uintptr_t) next
;
1310 first
->next_job_32
= (u32
) (uintptr_t) next
;
1314 panfrost_link_jobs(struct panfrost_context
*ctx
)
1316 if (ctx
->draw_count
) {
1317 /* Generate the set_value_job */
1318 panfrost_set_value_job(ctx
);
1320 /* Have the first vertex job depend on the set value job */
1321 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1324 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1327 /* V -> V/T ; T -> T/null */
1328 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1329 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1331 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1335 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1336 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1337 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1341 /* The entire frame is in memory -- send it off to the kernel! */
1344 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1345 struct pipe_fence_handle
**fence
,
1346 struct panfrost_job
*job
)
1348 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1349 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1351 /* Edge case if screen is cleared and nothing else */
1352 bool has_draws
= ctx
->draw_count
> 0;
1354 /* Workaround a bizarre lockup (a hardware errata?) */
1356 flush_immediate
= true;
1358 /* A number of jobs are batched -- this must be linked and cleared */
1359 panfrost_link_jobs(ctx
);
1361 ctx
->draw_count
= 0;
1362 ctx
->vertex_job_count
= 0;
1363 ctx
->tiler_job_count
= 0;
1367 bool is_scanout
= panfrost_is_scanout(ctx
);
1368 screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1370 /* If visual, we can stall a frame */
1372 if (!flush_immediate
)
1373 screen
->driver
->force_flush_fragment(ctx
, fence
);
1375 screen
->last_fragment_flushed
= false;
1376 screen
->last_job
= job
;
1378 /* If readback, flush now (hurts the pipelined performance) */
1379 if (flush_immediate
)
1380 screen
->driver
->force_flush_fragment(ctx
, fence
);
1382 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1383 screen
->driver
->dump_counters(screen
);
1386 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1387 FILE *fp
= fopen(filename
, "wb");
1388 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1397 struct pipe_context
*pipe
,
1398 struct pipe_fence_handle
**fence
,
1401 struct panfrost_context
*ctx
= pan_context(pipe
);
1402 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1404 /* Nothing to do! */
1405 if (!ctx
->draw_count
&& !job
->clear
) return;
1407 /* Whether to stall the pipeline for immediately correct results */
1408 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1410 /* Submit the frame itself */
1411 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1413 /* Prepare for the next frame */
1414 panfrost_invalidate_frame(ctx
);
1417 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1420 g2m_draw_mode(enum pipe_prim_type mode
)
1423 DEFINE_CASE(POINTS
);
1425 DEFINE_CASE(LINE_LOOP
);
1426 DEFINE_CASE(LINE_STRIP
);
1427 DEFINE_CASE(TRIANGLES
);
1428 DEFINE_CASE(TRIANGLE_STRIP
);
1429 DEFINE_CASE(TRIANGLE_FAN
);
1431 DEFINE_CASE(QUAD_STRIP
);
1432 DEFINE_CASE(POLYGON
);
1435 unreachable("Invalid draw mode");
1442 panfrost_translate_index_size(unsigned size
)
1446 return MALI_DRAW_INDEXED_UINT8
;
1449 return MALI_DRAW_INDEXED_UINT16
;
1452 return MALI_DRAW_INDEXED_UINT32
;
1455 unreachable("Invalid index size");
1459 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1460 * good for the duration of the draw (transient), could last longer */
1463 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1465 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1467 off_t offset
= info
->start
* info
->index_size
;
1469 if (!info
->has_user_indices
) {
1470 /* Only resources can be directly mapped */
1471 return rsrc
->bo
->gpu
+ offset
;
1473 /* Otherwise, we need to upload to transient memory */
1474 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1475 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1481 struct pipe_context
*pipe
,
1482 const struct pipe_draw_info
*info
)
1484 struct panfrost_context
*ctx
= pan_context(pipe
);
1486 ctx
->payload_vertex
.draw_start
= info
->start
;
1487 ctx
->payload_tiler
.draw_start
= info
->start
;
1489 int mode
= info
->mode
;
1491 /* Fallback for unsupported modes */
1493 if (!(ctx
->draw_modes
& (1 << mode
))) {
1494 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1495 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1497 if (info
->count
< 4) {
1498 /* Degenerate case? */
1502 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1503 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1508 /* Now that we have a guaranteed terminating path, find the job.
1509 * Assignment commented out to prevent unused warning */
1511 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1513 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1515 ctx
->vertex_count
= info
->count
;
1517 /* For non-indexed draws, they're the same */
1518 unsigned invocation_count
= ctx
->vertex_count
;
1520 unsigned draw_flags
= 0;
1522 /* The draw flags interpret how primitive size is interpreted */
1524 if (panfrost_writes_point_size(ctx
))
1525 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1527 /* For higher amounts of vertices (greater than what fits in a 16-bit
1528 * short), the other value is needed, otherwise there will be bizarre
1529 * rendering artefacts. It's not clear what these values mean yet. */
1531 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1533 if (info
->index_size
) {
1534 /* Calculate the min/max index used so we can figure out how
1535 * many times to invoke the vertex shader */
1537 /* Fetch / calculate index bounds */
1538 unsigned min_index
= 0, max_index
= 0;
1540 if (info
->max_index
== ~0u) {
1541 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1543 min_index
= info
->min_index
;
1544 max_index
= info
->max_index
;
1547 /* Use the corresponding values */
1548 invocation_count
= max_index
- min_index
+ 1;
1549 ctx
->payload_vertex
.draw_start
= min_index
;
1550 ctx
->payload_tiler
.draw_start
= min_index
;
1552 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1553 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1555 //assert(!info->restart_index); /* TODO: Research */
1556 assert(!info
->index_bias
);
1558 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1559 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1561 /* Index count == vertex count, if no indexing is applied, as
1562 * if it is internally indexed in the expected order */
1564 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1565 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1567 /* Reverse index state */
1568 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1571 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1572 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1573 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1575 /* Fire off the draw itself */
1576 panfrost_queue_draw(ctx
);
1582 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1588 panfrost_create_rasterizer_state(
1589 struct pipe_context
*pctx
,
1590 const struct pipe_rasterizer_state
*cso
)
1592 struct panfrost_context
*ctx
= pan_context(pctx
);
1593 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1597 /* Bitmask, unknown meaning of the start value */
1598 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1600 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1601 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1603 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1604 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1606 if (cso
->cull_face
& PIPE_FACE_BACK
)
1607 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1613 panfrost_bind_rasterizer_state(
1614 struct pipe_context
*pctx
,
1617 struct panfrost_context
*ctx
= pan_context(pctx
);
1619 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1623 ctx
->rasterizer
= hwcso
;
1624 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1628 panfrost_create_vertex_elements_state(
1629 struct pipe_context
*pctx
,
1630 unsigned num_elements
,
1631 const struct pipe_vertex_element
*elements
)
1633 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1635 so
->num_elements
= num_elements
;
1636 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1638 /* XXX: What the cornball? This is totally, 100%, unapologetically
1639 * nonsense. And yet it somehow fixes a regression in -bshadow
1640 * (previously, we allocated the descriptor here... a newer commit
1641 * removed that allocation, and then memory corruption led to
1642 * shader_meta getting overwritten in bad ways and then the whole test
1643 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1645 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1647 for (int i
= 0; i
< num_elements
; ++i
) {
1648 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1650 enum pipe_format fmt
= elements
[i
].src_format
;
1651 const struct util_format_description
*desc
= util_format_description(fmt
);
1652 so
->hw
[i
].unknown1
= 0x2;
1653 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1655 so
->hw
[i
].format
= panfrost_find_format(desc
);
1657 /* The field itself should probably be shifted over */
1658 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1665 panfrost_bind_vertex_elements_state(
1666 struct pipe_context
*pctx
,
1669 struct panfrost_context
*ctx
= pan_context(pctx
);
1671 ctx
->vertex
= hwcso
;
1672 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1676 panfrost_create_shader_state(
1677 struct pipe_context
*pctx
,
1678 const struct pipe_shader_state
*cso
)
1680 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1683 /* Token deep copy to prevent memory corruption */
1685 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1686 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1692 panfrost_delete_shader_state(
1693 struct pipe_context
*pctx
,
1696 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1698 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1699 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1706 panfrost_create_sampler_state(
1707 struct pipe_context
*pctx
,
1708 const struct pipe_sampler_state
*cso
)
1710 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1713 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1715 struct mali_sampler_descriptor sampler_descriptor
= {
1716 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1717 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1718 | translate_mip_filter(cso
->min_mip_filter
)
1721 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1722 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1723 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1724 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1726 cso
->border_color
.f
[0],
1727 cso
->border_color
.f
[1],
1728 cso
->border_color
.f
[2],
1729 cso
->border_color
.f
[3]
1731 .min_lod
= FIXED_16(cso
->min_lod
),
1732 .max_lod
= FIXED_16(cso
->max_lod
),
1736 so
->hw
= sampler_descriptor
;
1742 panfrost_bind_sampler_states(
1743 struct pipe_context
*pctx
,
1744 enum pipe_shader_type shader
,
1745 unsigned start_slot
, unsigned num_sampler
,
1748 assert(start_slot
== 0);
1750 struct panfrost_context
*ctx
= pan_context(pctx
);
1752 /* XXX: Should upload, not just copy? */
1753 ctx
->sampler_count
[shader
] = num_sampler
;
1754 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1756 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1760 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1762 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1764 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1765 /* Make sure enable state is at least the same */
1766 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1770 /* Check that the contents of the test are the same */
1771 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1772 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1774 if (!(same_func
&& same_ref
)) {
1778 /* Otherwise, we're good to go */
1783 panfrost_bind_fs_state(
1784 struct pipe_context
*pctx
,
1787 struct panfrost_context
*ctx
= pan_context(pctx
);
1792 /* Match the appropriate variant */
1794 signed variant
= -1;
1796 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1798 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1799 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
1805 if (variant
== -1) {
1806 /* No variant matched, so create a new one */
1807 variant
= variants
->variant_count
++;
1808 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1810 variants
->variants
[variant
].base
= hwcso
;
1811 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1813 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
1814 struct panfrost_context
*ctx
= pan_context(pctx
);
1815 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1817 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1818 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1822 /* Select this variant */
1823 variants
->active_variant
= variant
;
1825 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1826 assert(panfrost_variant_matches(ctx
, shader_state
));
1828 /* Now we have a variant selected, so compile and go */
1830 if (!shader_state
->compiled
) {
1831 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
1832 shader_state
->compiled
= true;
1836 ctx
->dirty
|= PAN_DIRTY_FS
;
1840 panfrost_bind_vs_state(
1841 struct pipe_context
*pctx
,
1844 struct panfrost_context
*ctx
= pan_context(pctx
);
1849 if (!ctx
->vs
->variants
[0].compiled
) {
1850 ctx
->vs
->variants
[0].base
= hwcso
;
1852 /* TODO DRY from above */
1853 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1854 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1855 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
1857 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
1858 ctx
->vs
->variants
[0].compiled
= true;
1862 ctx
->dirty
|= PAN_DIRTY_VS
;
1866 panfrost_set_vertex_buffers(
1867 struct pipe_context
*pctx
,
1868 unsigned start_slot
,
1869 unsigned num_buffers
,
1870 const struct pipe_vertex_buffer
*buffers
)
1872 struct panfrost_context
*ctx
= pan_context(pctx
);
1874 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1878 panfrost_set_constant_buffer(
1879 struct pipe_context
*pctx
,
1880 enum pipe_shader_type shader
, uint index
,
1881 const struct pipe_constant_buffer
*buf
)
1883 struct panfrost_context
*ctx
= pan_context(pctx
);
1884 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1886 size_t sz
= buf
? buf
->buffer_size
: 0;
1888 /* Free previous buffer */
1895 pbuf
->buffer
= NULL
;
1898 /* If unbinding, we're done */
1903 /* Multiple constant buffers not yet supported */
1908 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1911 cpu
= rsrc
->bo
->cpu
;
1912 } else if (buf
->user_buffer
) {
1913 cpu
= buf
->user_buffer
;
1915 DBG("No constant buffer?\n");
1919 /* Copy the constant buffer into the driver context for later upload */
1921 pbuf
->buffer
= malloc(sz
);
1922 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1926 panfrost_set_stencil_ref(
1927 struct pipe_context
*pctx
,
1928 const struct pipe_stencil_ref
*ref
)
1930 struct panfrost_context
*ctx
= pan_context(pctx
);
1931 ctx
->stencil_ref
= *ref
;
1933 /* Shader core dirty */
1934 ctx
->dirty
|= PAN_DIRTY_FS
;
1937 static struct pipe_sampler_view
*
1938 panfrost_create_sampler_view(
1939 struct pipe_context
*pctx
,
1940 struct pipe_resource
*texture
,
1941 const struct pipe_sampler_view
*template)
1943 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1944 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1946 pipe_reference(NULL
, &texture
->reference
);
1948 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1951 so
->base
= *template;
1952 so
->base
.texture
= texture
;
1953 so
->base
.reference
.count
= 1;
1954 so
->base
.context
= pctx
;
1956 /* sampler_views correspond to texture descriptors, minus the texture
1957 * (data) itself. So, we serialise the descriptor here and cache it for
1960 /* Make sure it's something with which we're familiar */
1961 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1963 /* TODO: Detect from format better */
1964 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1966 unsigned char user_swizzle
[4] = {
1967 template->swizzle_r
,
1968 template->swizzle_g
,
1969 template->swizzle_b
,
1973 enum mali_format format
= panfrost_find_format(desc
);
1975 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
1977 unsigned usage2_layout
= 0x10;
1979 switch (prsrc
->bo
->layout
) {
1981 usage2_layout
|= 0x8 | 0x4;
1984 usage2_layout
|= 0x1;
1987 usage2_layout
|= is_depth
? 0x1 : 0x2;
1994 /* Check if we need to set a custom stride by computing the "expected"
1995 * stride and comparing it to what the BO actually wants. Only applies
1996 * to linear textures TODO: Mipmap? */
1998 unsigned actual_stride
= prsrc
->bo
->slices
[0].stride
;
2000 if (prsrc
->bo
->layout
== PAN_LINEAR
&&
2001 template->u
.tex
.last_level
== 0 &&
2002 template->u
.tex
.first_level
== 0 &&
2003 (texture
->width0
* bytes_per_pixel
) != actual_stride
) {
2004 usage2_layout
|= MALI_TEX_MANUAL_STRIDE
;
2007 struct mali_texture_descriptor texture_descriptor
= {
2008 .width
= MALI_POSITIVE(texture
->width0
),
2009 .height
= MALI_POSITIVE(texture
->height0
),
2010 .depth
= MALI_POSITIVE(texture
->depth0
),
2014 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2018 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
2020 .usage2
= usage2_layout
2023 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2026 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2027 assert (template->u
.tex
.first_level
== 0);
2029 /* Disable mipmapping for now to avoid regressions while automipmapping
2030 * is being implemented. TODO: Remove me once automipmaps work */
2032 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
2033 texture_descriptor
.nr_mipmap_levels
= 0;
2035 so
->hw
= texture_descriptor
;
2037 return (struct pipe_sampler_view
*) so
;
2041 panfrost_set_sampler_views(
2042 struct pipe_context
*pctx
,
2043 enum pipe_shader_type shader
,
2044 unsigned start_slot
, unsigned num_views
,
2045 struct pipe_sampler_view
**views
)
2047 struct panfrost_context
*ctx
= pan_context(pctx
);
2049 assert(start_slot
== 0);
2051 ctx
->sampler_view_count
[shader
] = num_views
;
2052 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2054 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2058 panfrost_sampler_view_destroy(
2059 struct pipe_context
*pctx
,
2060 struct pipe_sampler_view
*view
)
2062 pipe_resource_reference(&view
->texture
, NULL
);
2067 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2068 const struct pipe_framebuffer_state
*fb
)
2070 struct panfrost_context
*ctx
= pan_context(pctx
);
2072 /* Flush when switching away from an FBO */
2074 if (!panfrost_is_scanout(ctx
)) {
2075 panfrost_flush(pctx
, NULL
, 0);
2078 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2079 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2080 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2081 ctx
->pipe_framebuffer
.width
= fb
->width
;
2082 ctx
->pipe_framebuffer
.height
= fb
->height
;
2084 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2085 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2087 /* check if changing cbuf */
2088 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2090 if (cb
&& (i
!= 0)) {
2091 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2096 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2101 if (ctx
->require_sfbd
)
2102 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2104 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2106 panfrost_attach_vt_framebuffer(ctx
);
2108 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2109 enum pipe_format format
= ctx
->pipe_framebuffer
.cbufs
[i
]->format
;
2110 bool is_scanout
= panfrost_is_scanout(ctx
);
2112 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
&& panfrost_can_afbc(format
)) {
2113 /* The blob is aggressive about enabling AFBC. As such,
2114 * it's pretty much necessary to use it here, since we
2115 * have no traces of non-compressed FBO. */
2117 panfrost_enable_afbc(ctx
, tex
, false);
2120 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2121 /* Enable transaction elimination if we can */
2122 panfrost_enable_checksum(ctx
, tex
);
2127 struct pipe_surface
*zb
= fb
->zsbuf
;
2129 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2130 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2135 if (ctx
->require_sfbd
)
2136 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2138 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2140 panfrost_attach_vt_framebuffer(ctx
);
2142 /* Keep the depth FBO linear */
2149 panfrost_create_blend_state(struct pipe_context
*pipe
,
2150 const struct pipe_blend_state
*blend
)
2152 struct panfrost_context
*ctx
= pan_context(pipe
);
2153 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2156 /* TODO: The following features are not yet implemented */
2157 assert(!blend
->logicop_enable
);
2158 assert(!blend
->alpha_to_coverage
);
2159 assert(!blend
->alpha_to_one
);
2161 /* Compile the blend state, first as fixed-function if we can */
2163 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], so
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2166 /* If we can't, compile a blend shader instead */
2168 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2174 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2177 struct panfrost_context
*ctx
= pan_context(pipe
);
2178 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2179 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2180 ctx
->blend
= pblend
;
2185 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2187 /* TODO: Attach color */
2189 /* Shader itself is not dirty, but the shader core is */
2190 ctx
->dirty
|= PAN_DIRTY_FS
;
2194 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2197 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2199 if (so
->has_blend_shader
) {
2200 DBG("Deleting blend state leak blend shaders bytecode\n");
2207 panfrost_set_blend_color(struct pipe_context
*pipe
,
2208 const struct pipe_blend_color
*blend_color
)
2210 struct panfrost_context
*ctx
= pan_context(pipe
);
2212 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2215 ctx
->blend_color
= *blend_color
;
2217 /* The blend mode depends on the blend constant color, due to the
2218 * fixed/programmable split. So, we're forced to regenerate the blend
2221 /* TODO: Attach color */
2226 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2227 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2229 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2233 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2236 struct panfrost_context
*ctx
= pan_context(pipe
);
2237 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2238 ctx
->depth_stencil
= depth_stencil
;
2243 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2244 * emulated in the fragment shader */
2246 if (depth_stencil
->alpha
.enabled
) {
2247 /* We need to trigger a new shader (maybe) */
2248 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2252 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2254 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2255 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2257 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2258 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2260 /* Depth state (TODO: Refactor) */
2261 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2263 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2265 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2266 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2268 /* Bounds test not implemented */
2269 assert(!depth_stencil
->depth
.bounds_test
);
2271 ctx
->dirty
|= PAN_DIRTY_FS
;
2275 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2281 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2282 unsigned sample_mask
)
2287 panfrost_set_clip_state(struct pipe_context
*pipe
,
2288 const struct pipe_clip_state
*clip
)
2290 //struct panfrost_context *panfrost = pan_context(pipe);
2294 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2295 unsigned start_slot
,
2296 unsigned num_viewports
,
2297 const struct pipe_viewport_state
*viewports
)
2299 struct panfrost_context
*ctx
= pan_context(pipe
);
2301 assert(start_slot
== 0);
2302 assert(num_viewports
== 1);
2304 ctx
->pipe_viewport
= *viewports
;
2307 /* TODO: What if not centered? */
2308 float w
= abs(viewports
->scale
[0]) * 2.0;
2309 float h
= abs(viewports
->scale
[1]) * 2.0;
2311 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2312 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2317 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2318 unsigned start_slot
,
2319 unsigned num_scissors
,
2320 const struct pipe_scissor_state
*scissors
)
2322 struct panfrost_context
*ctx
= pan_context(pipe
);
2324 assert(start_slot
== 0);
2325 assert(num_scissors
== 1);
2327 ctx
->scissor
= *scissors
;
2331 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2332 const struct pipe_poly_stipple
*stipple
)
2334 //struct panfrost_context *panfrost = pan_context(pipe);
2338 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2341 //struct panfrost_context *panfrost = pan_context(pipe);
2345 panfrost_destroy(struct pipe_context
*pipe
)
2347 struct panfrost_context
*panfrost
= pan_context(pipe
);
2348 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2350 if (panfrost
->blitter
)
2351 util_blitter_destroy(panfrost
->blitter
);
2353 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2354 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2355 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2356 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2357 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2360 static struct pipe_query
*
2361 panfrost_create_query(struct pipe_context
*pipe
,
2365 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2370 return (struct pipe_query
*) q
;
2374 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2380 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2382 struct panfrost_context
*ctx
= pan_context(pipe
);
2383 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2385 switch (query
->type
) {
2386 case PIPE_QUERY_OCCLUSION_COUNTER
:
2387 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2388 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2390 /* Allocate a word for the query results to be stored */
2391 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2393 ctx
->occlusion_query
= query
;
2399 DBG("Skipping query %d\n", query
->type
);
2407 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2409 struct panfrost_context
*ctx
= pan_context(pipe
);
2410 ctx
->occlusion_query
= NULL
;
2415 panfrost_get_query_result(struct pipe_context
*pipe
,
2416 struct pipe_query
*q
,
2418 union pipe_query_result
*vresult
)
2421 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2423 /* We need to flush out the jobs to actually run the counter, TODO
2424 * check wait, TODO wallpaper after if needed */
2426 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2428 switch (query
->type
) {
2429 case PIPE_QUERY_OCCLUSION_COUNTER
:
2430 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2431 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2432 /* Read back the query results */
2433 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2434 unsigned passed
= *result
;
2436 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2437 vresult
->u64
= passed
;
2439 vresult
->b
= !!passed
;
2445 DBG("Skipped query get %d\n", query
->type
);
2452 static struct pipe_stream_output_target
*
2453 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2454 struct pipe_resource
*prsc
,
2455 unsigned buffer_offset
,
2456 unsigned buffer_size
)
2458 struct pipe_stream_output_target
*target
;
2460 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2465 pipe_reference_init(&target
->reference
, 1);
2466 pipe_resource_reference(&target
->buffer
, prsc
);
2468 target
->context
= pctx
;
2469 target
->buffer_offset
= buffer_offset
;
2470 target
->buffer_size
= buffer_size
;
2476 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2477 struct pipe_stream_output_target
*target
)
2479 pipe_resource_reference(&target
->buffer
, NULL
);
2484 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2485 unsigned num_targets
,
2486 struct pipe_stream_output_target
**targets
,
2487 const unsigned *offsets
)
2493 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2495 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2496 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2498 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2499 /* Allocate the beginning of the transient pool */
2500 int entry_size
= (1 << 22); /* 4MB */
2502 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2503 ctx
->transient_pools
[i
].entry_count
= 1;
2505 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2508 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2509 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2510 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2511 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2512 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2516 /* New context creation, which also does hardware initialisation since I don't
2517 * know the better way to structure this :smirk: */
2519 struct pipe_context
*
2520 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2522 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2523 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2524 memset(ctx
, 0, sizeof(*ctx
));
2525 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2528 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2530 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2531 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2533 gallium
->screen
= screen
;
2535 gallium
->destroy
= panfrost_destroy
;
2537 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2539 gallium
->flush
= panfrost_flush
;
2540 gallium
->clear
= panfrost_clear
;
2541 gallium
->draw_vbo
= panfrost_draw_vbo
;
2543 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2544 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2546 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2548 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2549 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2550 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2552 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2553 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2554 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2556 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2557 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2558 gallium
->delete_vertex_elements_state
= panfrost_generic_cso_delete
;
2560 gallium
->create_fs_state
= panfrost_create_shader_state
;
2561 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2562 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2564 gallium
->create_vs_state
= panfrost_create_shader_state
;
2565 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2566 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2568 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2569 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2570 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2572 gallium
->create_blend_state
= panfrost_create_blend_state
;
2573 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2574 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2576 gallium
->set_blend_color
= panfrost_set_blend_color
;
2578 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2579 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2580 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2582 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2584 gallium
->set_clip_state
= panfrost_set_clip_state
;
2585 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2586 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2587 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2588 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2590 gallium
->create_query
= panfrost_create_query
;
2591 gallium
->destroy_query
= panfrost_destroy_query
;
2592 gallium
->begin_query
= panfrost_begin_query
;
2593 gallium
->end_query
= panfrost_end_query
;
2594 gallium
->get_query_result
= panfrost_get_query_result
;
2596 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2597 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2598 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2600 panfrost_resource_context_init(gallium
);
2602 pscreen
->driver
->init_context(ctx
);
2604 panfrost_setup_hardware(ctx
);
2607 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2608 gallium
->const_uploader
= gallium
->stream_uploader
;
2609 assert(gallium
->stream_uploader
);
2611 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2612 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2614 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2616 ctx
->blitter
= util_blitter_create(gallium
);
2617 assert(ctx
->blitter
);
2619 /* Prepare for render! */
2621 panfrost_job_init(ctx
);
2622 panfrost_emit_vertex_payload(ctx
);
2623 panfrost_emit_tiler_payload(ctx
);
2624 panfrost_invalidate_frame(ctx
);
2625 panfrost_default_shader_backend(ctx
);
2626 panfrost_generate_space_filler_indices();