2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/u_vbuf.h"
38 #include "util/half_float.h"
39 #include "util/u_helpers.h"
40 #include "util/u_format.h"
41 #include "indices/u_primconvert.h"
42 #include "tgsi/tgsi_parse.h"
44 #include "pan_screen.h"
45 #include "pan_blending.h"
46 #include "pan_blend_shaders.h"
48 #include "pan_wallpaper.h"
50 static int performance_counter_number
= 0;
51 extern const char *pan_counters_base
;
53 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
56 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
57 * indepdent between color buffers and depth/stencil). To enable, we allocate
58 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
59 * edit the fragment job here. This routine should be called ONCE per
60 * AFBC-compressed buffer, rather than on every frame. */
63 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
65 if (ctx
->require_sfbd
) {
66 DBG("AFBC not supported yet on SFBD\n");
70 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
71 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
72 /* AFBC metadata is 16 bytes per tile */
73 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
74 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
75 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
76 int stride
= bytes_per_pixel
* ALIGN(rsrc
->base
.width0
, 16);
78 stride
*= 2; /* TODO: Should this be carried over? */
79 int main_size
= stride
* rsrc
->base
.height0
;
80 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
82 /* Allocate the AFBC slab itself, large enough to hold the above */
83 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
84 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
87 rsrc
->bo
->layout
= PAN_AFBC
;
89 /* Compressed textured reads use a tagged pointer to the metadata */
91 rsrc
->bo
->gpu
= rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
92 rsrc
->bo
->cpu
= rsrc
->bo
->afbc_slab
.cpu
;
93 rsrc
->bo
->gem_handle
= rsrc
->bo
->afbc_slab
.gem_handle
;
97 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
99 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
100 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
101 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
102 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
104 /* 8 byte checksum per tile */
105 rsrc
->bo
->checksum_stride
= tile_w
* 8;
106 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
107 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
109 rsrc
->bo
->has_checksum
= true;
112 /* Framebuffer descriptor */
115 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
117 fb
->width
= MALI_POSITIVE(w
);
118 fb
->height
= MALI_POSITIVE(h
);
120 /* No idea why this is needed, but it's how resolution_check is
121 * calculated. It's not clear to us yet why the hardware wants this.
122 * The formula itself was discovered mostly by manual bruteforce and
123 * aggressive algebraic simplification. */
125 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
128 struct mali_single_framebuffer
129 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
131 struct mali_single_framebuffer framebuffer
= {
133 .format
= 0x30000000,
134 .clear_flags
= 0x1000,
135 .unknown_address_0
= ctx
->scratchpad
.gpu
,
136 .unknown_address_1
= ctx
->misc_0
.gpu
,
137 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
139 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
140 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
143 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
148 struct bifrost_framebuffer
149 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
151 struct bifrost_framebuffer framebuffer
= {
152 /* It is not yet clear what tiler_meta means or how it's
153 * calculated, but we can tell the lower 32-bits are a
154 * (monotonically increasing?) function of tile count and
155 * geometry complexity; I suspect it defines a memory size of
156 * some kind? for the tiler. It's really unclear at the
157 * moment... but to add to the confusion, the hardware is happy
158 * enough to accept a zero in this field, so we don't even have
159 * to worry about it right now.
161 * The byte (just after the 32-bit mark) is much more
162 * interesting. The higher nibble I've only ever seen as 0xF,
163 * but the lower one I've seen as 0x0 or 0xF, and it's not
164 * obvious what the difference is. But what -is- obvious is
165 * that when the lower nibble is zero, performance is severely
166 * degraded compared to when the lower nibble is set.
167 * Evidently, that nibble enables some sort of fast path,
168 * perhaps relating to caching or tile flush? Regardless, at
169 * this point there's no clear reason not to set it, aside from
170 * substantially increased memory requirements (of the misc_0
173 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
175 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
176 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
177 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
178 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
183 .rt_count_1
= MALI_POSITIVE(1),
188 /* Corresponds to unknown_address_X of SFBD */
189 .scratchpad
= ctx
->scratchpad
.gpu
,
190 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
192 /* The constant added here is, like the lower word of
193 * tiler_meta, (loosely) another product of framebuffer size
194 * and geometry complexity. It must be sufficiently large for
195 * the tiler_meta fast path to work; if it's too small, there
196 * will be DATA_INVALID_FAULTs. Conversely, it must be less
197 * than the total size of misc_0, or else there's no room. It's
198 * possible this constant configures a partition between two
199 * parts of misc_0? We haven't investigated the functionality,
200 * as these buffers are internally used by the hardware
201 * (presumably by the tiler) but not seemingly touched by the driver
204 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
206 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
207 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
213 /* Are we currently rendering to the screen (rather than an FBO)? */
216 panfrost_is_scanout(struct panfrost_context
*ctx
)
218 /* If there is no color buffer, it's an FBO */
219 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
222 /* If we're too early that no framebuffer was sent, it's scanout */
223 if (!ctx
->pipe_framebuffer
.cbufs
[0])
226 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
227 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
228 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
231 /* Maps float 0.0-1.0 to int 0x00-0xFF */
233 normalised_float_to_u8(float f
)
235 return (uint8_t) (int) (f
* 255.0f
);
240 struct pipe_context
*pipe
,
242 const union pipe_color_union
*color
,
243 double depth
, unsigned stencil
)
245 struct panfrost_context
*ctx
= pan_context(pipe
);
246 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
248 if (buffers
& PIPE_CLEAR_COLOR
) {
249 /* Alpha clear only meaningful without alpha channel, TODO less ad hoc */
250 bool has_alpha
= util_format_has_alpha(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
251 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
253 uint32_t packed_color
=
254 (normalised_float_to_u8(clear_alpha
) << 24) |
255 (normalised_float_to_u8(color
->f
[2]) << 16) |
256 (normalised_float_to_u8(color
->f
[1]) << 8) |
257 (normalised_float_to_u8(color
->f
[0]) << 0);
259 job
->clear_color
= packed_color
;
263 if (buffers
& PIPE_CLEAR_DEPTH
) {
264 job
->clear_depth
= depth
;
267 if (buffers
& PIPE_CLEAR_STENCIL
) {
268 job
->clear_stencil
= stencil
;
271 job
->clear
|= buffers
;
275 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
277 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
278 struct bifrost_render_target rts_list
[] = {
283 .framebuffer
= ctx
->misc_0
.gpu
,
288 /* Allocate memory for the three components */
289 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
290 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
292 /* Opaque 1024-block */
293 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
295 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
296 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
298 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
302 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
304 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
308 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
310 mali_ptr framebuffer
= ctx
->require_sfbd
?
311 panfrost_attach_vt_sfbd(ctx
) :
312 panfrost_attach_vt_mfbd(ctx
);
314 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
315 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
318 /* Reset per-frame context, called on context initialisation as well as after
319 * flushing a frame */
322 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
324 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
325 DBG("Uploaded transient %d bytes\n", transient_count
);
327 /* Rotate cmdstream */
328 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
329 ctx
->cmdstream_i
= 0;
331 if (ctx
->require_sfbd
)
332 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
334 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
336 /* Reset varyings allocated */
337 ctx
->varying_height
= 0;
339 /* The transient cmdstream is dirty every frame; the only bits worth preserving
340 * (textures, shaders, etc) are in other buffers anyways */
342 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
343 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
345 /* Regenerate payloads */
346 panfrost_attach_vt_framebuffer(ctx
);
349 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
352 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
355 /* In practice, every field of these payloads should be configurable
356 * arbitrarily, which means these functions are basically catch-all's for
357 * as-of-yet unwavering unknowns */
360 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
362 struct midgard_payload_vertex_tiler payload
= {
364 .workgroups_z_shift
= 32,
365 .workgroups_x_shift_2
= 0x2,
366 .workgroups_x_shift_3
= 0x5,
368 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
371 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
375 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
377 struct midgard_payload_vertex_tiler payload
= {
379 .workgroups_z_shift
= 32,
380 .workgroups_x_shift_2
= 0x2,
381 .workgroups_x_shift_3
= 0x6,
383 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
387 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
391 translate_tex_wrap(enum pipe_tex_wrap w
)
394 case PIPE_TEX_WRAP_REPEAT
:
395 return MALI_WRAP_REPEAT
;
397 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
398 return MALI_WRAP_CLAMP_TO_EDGE
;
400 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
401 return MALI_WRAP_CLAMP_TO_BORDER
;
403 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
404 return MALI_WRAP_MIRRORED_REPEAT
;
413 translate_tex_filter(enum pipe_tex_filter f
)
416 case PIPE_TEX_FILTER_NEAREST
:
419 case PIPE_TEX_FILTER_LINEAR
:
429 translate_mip_filter(enum pipe_tex_mipfilter f
)
431 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
435 panfrost_translate_compare_func(enum pipe_compare_func in
)
438 case PIPE_FUNC_NEVER
:
439 return MALI_FUNC_NEVER
;
442 return MALI_FUNC_LESS
;
444 case PIPE_FUNC_EQUAL
:
445 return MALI_FUNC_EQUAL
;
447 case PIPE_FUNC_LEQUAL
:
448 return MALI_FUNC_LEQUAL
;
450 case PIPE_FUNC_GREATER
:
451 return MALI_FUNC_GREATER
;
453 case PIPE_FUNC_NOTEQUAL
:
454 return MALI_FUNC_NOTEQUAL
;
456 case PIPE_FUNC_GEQUAL
:
457 return MALI_FUNC_GEQUAL
;
459 case PIPE_FUNC_ALWAYS
:
460 return MALI_FUNC_ALWAYS
;
464 return 0; /* Unreachable */
468 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
471 case PIPE_FUNC_NEVER
:
472 return MALI_ALT_FUNC_NEVER
;
475 return MALI_ALT_FUNC_LESS
;
477 case PIPE_FUNC_EQUAL
:
478 return MALI_ALT_FUNC_EQUAL
;
480 case PIPE_FUNC_LEQUAL
:
481 return MALI_ALT_FUNC_LEQUAL
;
483 case PIPE_FUNC_GREATER
:
484 return MALI_ALT_FUNC_GREATER
;
486 case PIPE_FUNC_NOTEQUAL
:
487 return MALI_ALT_FUNC_NOTEQUAL
;
489 case PIPE_FUNC_GEQUAL
:
490 return MALI_ALT_FUNC_GEQUAL
;
492 case PIPE_FUNC_ALWAYS
:
493 return MALI_ALT_FUNC_ALWAYS
;
497 return 0; /* Unreachable */
501 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
504 case PIPE_STENCIL_OP_KEEP
:
505 return MALI_STENCIL_KEEP
;
507 case PIPE_STENCIL_OP_ZERO
:
508 return MALI_STENCIL_ZERO
;
510 case PIPE_STENCIL_OP_REPLACE
:
511 return MALI_STENCIL_REPLACE
;
513 case PIPE_STENCIL_OP_INCR
:
514 return MALI_STENCIL_INCR
;
516 case PIPE_STENCIL_OP_DECR
:
517 return MALI_STENCIL_DECR
;
519 case PIPE_STENCIL_OP_INCR_WRAP
:
520 return MALI_STENCIL_INCR_WRAP
;
522 case PIPE_STENCIL_OP_DECR_WRAP
:
523 return MALI_STENCIL_DECR_WRAP
;
525 case PIPE_STENCIL_OP_INVERT
:
526 return MALI_STENCIL_INVERT
;
530 return 0; /* Unreachable */
534 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
536 out
->ref
= 0; /* Gallium gets it from elsewhere */
538 out
->mask
= in
->valuemask
;
539 out
->func
= panfrost_translate_compare_func(in
->func
);
540 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
541 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
542 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
546 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
548 struct mali_shader_meta shader
= {
549 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
551 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
552 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
556 shader
.unknown2_4
|= 0x10;
559 struct pipe_stencil_state default_stencil
= {
561 .func
= PIPE_FUNC_ALWAYS
,
562 .fail_op
= MALI_STENCIL_KEEP
,
563 .zfail_op
= MALI_STENCIL_KEEP
,
564 .zpass_op
= MALI_STENCIL_KEEP
,
569 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
570 shader
.stencil_mask_front
= default_stencil
.writemask
;
572 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
573 shader
.stencil_mask_back
= default_stencil
.writemask
;
575 if (default_stencil
.enabled
)
576 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
578 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
581 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
582 * graphics command stream. It should be called once per draw, accordding to
583 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
584 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
587 struct panfrost_transfer
588 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
590 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
591 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
593 struct mali_job_descriptor_header job
= {
594 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
595 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
597 .job_descriptor_size
= 1,
601 /* Only non-elided tiler jobs have dependencies which are known at this point */
603 if (is_tiler
&& !is_elided_tiler
) {
604 /* Tiler jobs depend on vertex jobs */
606 job
.job_dependency_index_1
= draw_job_index
;
608 /* Tiler jobs also depend on the previous tiler job */
611 job
.job_dependency_index_2
= draw_job_index
- 1;
614 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
616 /* There's some padding hacks on 32-bit */
623 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
624 memcpy(transfer
.cpu
, &job
, sizeof(job
));
625 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
629 /* Generates a set value job. It's unclear what exactly this does, why it's
630 * necessary, and when to call it. */
633 panfrost_set_value_job(struct panfrost_context
*ctx
)
635 struct mali_job_descriptor_header job
= {
636 .job_type
= JOB_TYPE_SET_VALUE
,
637 .job_descriptor_size
= 1,
638 .job_index
= 1 + (2 * ctx
->draw_count
),
641 struct mali_payload_set_value payload
= {
642 .out
= ctx
->misc_0
.gpu
,
646 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
647 memcpy(transfer
.cpu
, &job
, sizeof(job
));
648 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
650 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
651 ctx
->set_value_job
= transfer
.gpu
;
655 panfrost_emit_varyings(
656 struct panfrost_context
*ctx
,
657 union mali_attr
*slot
,
661 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
663 /* Fill out the descriptor */
664 slot
->elements
= varying_address
| MALI_ATTR_LINEAR
;
665 slot
->stride
= stride
;
666 slot
->size
= stride
* count
;
668 ctx
->varying_height
+= ALIGN(slot
->size
, 64);
669 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
671 return varying_address
;
675 panfrost_emit_point_coord(union mali_attr
*slot
)
677 slot
->elements
= MALI_VARYING_POINT_COORD
| MALI_ATTR_LINEAR
;
678 slot
->stride
= slot
->size
= 0;
682 panfrost_emit_varying_descriptor(
683 struct panfrost_context
*ctx
,
684 unsigned invocation_count
)
686 /* Load the shaders */
688 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
689 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
691 /* Allocate the varying descriptor */
693 size_t vs_size
= sizeof(struct mali_attr_meta
) * vs
->tripipe
->varying_count
;
694 size_t fs_size
= sizeof(struct mali_attr_meta
) * fs
->tripipe
->varying_count
;
696 struct panfrost_transfer trans
= panfrost_allocate_transient(ctx
,
699 memcpy(trans
.cpu
, vs
->varyings
, vs_size
);
700 memcpy(trans
.cpu
+ vs_size
, fs
->varyings
, fs_size
);
702 ctx
->payload_vertex
.postfix
.varying_meta
= trans
.gpu
;
703 ctx
->payload_tiler
.postfix
.varying_meta
= trans
.gpu
+ vs_size
;
705 /* Buffer indices must be in this order per our convention */
706 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
709 /* General varyings -- use the VS's, since those are more likely to be
710 * accurate on desktop */
712 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
713 vs
->general_varying_stride
, invocation_count
);
715 /* fp32 vec4 gl_Position */
716 ctx
->payload_tiler
.postfix
.position_varying
=
717 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
718 sizeof(float) * 4, invocation_count
);
721 if (vs
->writes_point_size
|| fs
->reads_point_coord
) {
722 /* fp16 vec1 gl_PointSize */
723 ctx
->payload_tiler
.primitive_size
.pointer
=
724 panfrost_emit_varyings(ctx
, &varyings
[idx
++],
725 2, invocation_count
);
728 if (fs
->reads_point_coord
) {
729 /* Special descriptor */
730 panfrost_emit_point_coord(&varyings
[idx
++]);
733 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, idx
* sizeof(union mali_attr
));
734 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
735 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
739 panfrost_vertex_buffer_address(struct panfrost_context
*ctx
, unsigned i
)
741 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
742 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
744 return rsrc
->bo
->gpu
+ buf
->buffer_offset
;
747 /* Emits attributes and varying descriptors, which should be called every draw,
748 * excepting some obscure circumstances */
751 panfrost_emit_vertex_data(struct panfrost_context
*ctx
, struct panfrost_job
*job
)
753 /* Staged mali_attr, and index into them. i =/= k, depending on the
754 * vertex buffer mask */
755 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
758 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
760 for (int i
= 0; i
< ARRAY_SIZE(ctx
->vertex_buffers
); ++i
) {
761 if (!(ctx
->vb_mask
& (1 << i
))) continue;
763 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
764 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
768 /* Align to 64 bytes by masking off the lower bits. This
769 * will be adjusted back when we fixup the src_offset in
772 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, i
) & ~63;
774 /* Offset vertex count by draw_start to make sure we upload enough */
775 attrs
[k
].stride
= buf
->stride
;
776 attrs
[k
].size
= rsrc
->base
.width0
;
778 panfrost_job_add_bo(job
, rsrc
->bo
);
779 attrs
[k
].elements
= addr
| MALI_ATTR_LINEAR
;
784 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, k
* sizeof(union mali_attr
));
786 panfrost_emit_varying_descriptor(ctx
, invocation_count
);
790 panfrost_writes_point_size(struct panfrost_context
*ctx
)
793 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
795 return vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
798 /* Stage the attribute descriptors so we can adjust src_offset
799 * to let BOs align nicely */
802 panfrost_stage_attributes(struct panfrost_context
*ctx
)
804 struct panfrost_vertex_state
*so
= ctx
->vertex
;
806 size_t sz
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
807 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sz
);
808 struct mali_attr_meta
*target
= (struct mali_attr_meta
*) transfer
.cpu
;
810 /* Copy as-is for the first pass */
811 memcpy(target
, so
->hw
, sz
);
813 /* Fixup offsets for the second pass. Recall that the hardware
814 * calculates attribute addresses as:
816 * addr = base + (stride * vtx) + src_offset;
818 * However, on Mali, base must be aligned to 64-bytes, so we
821 * base' = base & ~63 = base - (base & 63)
823 * To compensate when using base' (see emit_vertex_data), we have
824 * to adjust src_offset by the masked off piece:
826 * addr' = base' + (stride * vtx) + (src_offset + (base & 63))
827 * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63)
828 * = base + (stride * vtx) + src_offset
834 for (unsigned i
= 0; i
< so
->num_elements
; ++i
) {
835 unsigned vbi
= so
->pipe
[i
].vertex_buffer_index
;
836 mali_ptr addr
= panfrost_vertex_buffer_address(ctx
, vbi
);
838 /* Adjust by the masked off bits of the offset */
839 target
[i
].src_offset
+= (addr
& 63);
842 ctx
->payload_vertex
.postfix
.attribute_meta
= transfer
.gpu
;
845 /* Go through dirty flags and actualise them in the cmdstream. */
848 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
850 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
852 if (with_vertex_data
) {
853 panfrost_emit_vertex_data(ctx
, job
);
856 bool msaa
= ctx
->rasterizer
->base
.multisample
;
858 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
859 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
861 /* TODO: Sample size */
862 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, msaa
);
863 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !msaa
);
866 /* Enable job requirements at draw-time */
869 job
->requirements
|= PAN_REQ_MSAA
;
871 if (ctx
->depth_stencil
->depth
.writemask
)
872 job
->requirements
|= PAN_REQ_DEPTH_WRITE
;
874 if (ctx
->occlusion_query
) {
875 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
876 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
879 if (ctx
->dirty
& PAN_DIRTY_VS
) {
882 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
884 /* Late shader descriptor assignments */
886 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
887 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
890 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
892 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
895 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
896 /* Check if we need to link the gl_PointSize varying */
897 if (!panfrost_writes_point_size(ctx
)) {
898 /* If the size is constant, write it out. Otherwise,
899 * don't touch primitive_size (since we would clobber
900 * the pointer there) */
902 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
906 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
908 ctx
->dirty
|= PAN_DIRTY_FS
;
910 if (ctx
->dirty
& PAN_DIRTY_FS
) {
912 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
914 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
917 COPY(attribute_count
);
919 COPY(midgard1
.uniform_count
);
920 COPY(midgard1
.work_count
);
921 COPY(midgard1
.unknown2
);
924 /* If there is a blend shader, work registers are shared */
926 if (ctx
->blend
->has_blend_shader
)
927 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
929 /* Set late due to depending on render state */
930 /* The one at the end seems to mean "1 UBO" */
931 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
933 /* Assign texture/sample count right before upload */
934 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
935 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
937 /* Assign the stencil refs late */
938 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
939 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
941 /* CAN_DISCARD should be set if the fragment shader possibly
942 * contains a 'discard' instruction. It is likely this is
943 * related to optimizations related to forward-pixel kill, as
944 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
945 * thing?" by Peter Harris
948 if (variant
->can_discard
) {
949 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
950 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
951 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
952 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
955 /* Check if we're using the default blend descriptor (fast path) */
958 !ctx
->blend
->has_blend_shader
&&
959 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
960 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
961 (ctx
->blend
->equation
.color_mask
== 0xf);
963 /* Even on MFBD, the shader descriptor gets blend shaders. It's
964 * *also* copied to the blend_meta appended (by convention),
965 * but this is the field actually read by the hardware. (Or
966 * maybe both are read...?) */
968 if (ctx
->blend
->has_blend_shader
) {
969 ctx
->fragment_shader_core
.blend_shader
= ctx
->blend
->blend_shader
;
972 if (ctx
->require_sfbd
) {
973 /* When only a single render target platform is used, the blend
974 * information is inside the shader meta itself. We
975 * additionally need to signal CAN_DISCARD for nontrivial blend
976 * modes (so we're able to read back the destination buffer) */
978 if (!ctx
->blend
->has_blend_shader
) {
979 memcpy(&ctx
->fragment_shader_core
.blend_equation
, &ctx
->blend
->equation
, sizeof(ctx
->blend
->equation
));
983 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
987 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct mali_blend_meta
);
988 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
989 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
991 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
993 if (!ctx
->require_sfbd
) {
994 /* Additional blend descriptor tacked on for jobs using MFBD */
996 unsigned blend_count
= 0;
998 if (ctx
->blend
->has_blend_shader
) {
999 /* For a blend shader, the bottom nibble corresponds to
1000 * the number of work registers used, which signals the
1001 * -existence- of a blend shader */
1003 assert(ctx
->blend
->blend_work_count
>= 2);
1004 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1006 /* Otherwise, the bottom bit simply specifies if
1007 * blending (anything other than REPLACE) is enabled */
1014 /* Second blend equation is always a simple replace */
1016 uint64_t replace_magic
= 0xf0122122;
1017 struct mali_blend_equation replace_mode
;
1018 memcpy(&replace_mode
, &replace_magic
, sizeof(replace_mode
));
1020 struct mali_blend_meta blend_meta
[] = {
1022 .unk1
= 0x200 | blend_count
,
1023 .blend_equation_1
= ctx
->blend
->equation
,
1024 .blend_equation_2
= replace_mode
1028 if (ctx
->blend
->has_blend_shader
) {
1029 blend_meta
[0].blend_shader
= ctx
->blend
->blend_shader
;
1032 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), blend_meta
, sizeof(blend_meta
));
1036 /* We stage to transient, so always dirty.. */
1037 panfrost_stage_attributes(ctx
);
1039 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
1040 /* Upload samplers back to back, no padding */
1042 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1043 if (!ctx
->sampler_count
[t
]) continue;
1045 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
1046 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
1048 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
1049 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
1052 if (t
== PIPE_SHADER_FRAGMENT
)
1053 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
1054 else if (t
== PIPE_SHADER_VERTEX
)
1055 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1061 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1062 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1064 if (!ctx
->sampler_view_count
[t
]) continue;
1066 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1068 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1069 if (!ctx
->sampler_views
[t
][i
])
1072 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1073 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1075 /* Inject the addresses in, interleaving cube
1076 * faces and mip levels appropriately. */
1078 for (int l
= 0; l
<= tex_rsrc
->last_level
; ++l
) {
1079 for (int f
= 0; f
< tex_rsrc
->array_size
; ++f
) {
1080 unsigned idx
= (l
* tex_rsrc
->array_size
) + f
;
1082 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[idx
] =
1084 rsrc
->bo
->slices
[l
].offset
+
1085 f
* rsrc
->bo
->cubemap_stride
;
1089 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1092 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1094 if (t
== PIPE_SHADER_FRAGMENT
)
1095 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1096 else if (t
== PIPE_SHADER_VERTEX
)
1097 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1103 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1105 /* For flipped-Y buffers (signaled by negative scale), the translate is
1106 * flipped as well */
1108 bool invert_y
= vp
->scale
[1] < 0.0;
1109 float translate_y
= vp
->translate
[1];
1112 translate_y
= ctx
->pipe_framebuffer
.height
- translate_y
;
1114 for (int i
= 0; i
<= PIPE_SHADER_FRAGMENT
; ++i
) {
1115 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1117 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1118 struct panfrost_shader_state
*fs
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1119 struct panfrost_shader_state
*ss
= (i
== PIPE_SHADER_FRAGMENT
) ? fs
: vs
;
1121 /* Allocate room for the sysval and the uniforms */
1122 size_t sys_size
= sizeof(float) * 4 * ss
->sysval_count
;
1123 size_t size
= sys_size
+ buf
->size
;
1124 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1126 /* Upload sysvals requested by the shader */
1127 float *uniforms
= (float *) transfer
.cpu
;
1128 for (unsigned i
= 0; i
< ss
->sysval_count
; ++i
) {
1129 int sysval
= ss
->sysval
[i
];
1131 if (sysval
== PAN_SYSVAL_VIEWPORT_SCALE
) {
1132 uniforms
[4*i
+ 0] = vp
->scale
[0];
1133 uniforms
[4*i
+ 1] = fabsf(vp
->scale
[1]);
1134 uniforms
[4*i
+ 2] = vp
->scale
[2];
1135 } else if (sysval
== PAN_SYSVAL_VIEWPORT_OFFSET
) {
1136 uniforms
[4*i
+ 0] = vp
->translate
[0];
1137 uniforms
[4*i
+ 1] = translate_y
;
1138 uniforms
[4*i
+ 2] = vp
->translate
[2];
1144 /* Upload uniforms */
1145 memcpy(transfer
.cpu
+ sys_size
, buf
->buffer
, buf
->size
);
1147 int uniform_count
= 0;
1149 struct mali_vertex_tiler_postfix
*postfix
;
1152 case PIPE_SHADER_VERTEX
:
1153 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1154 postfix
= &ctx
->payload_vertex
.postfix
;
1157 case PIPE_SHADER_FRAGMENT
:
1158 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1159 postfix
= &ctx
->payload_tiler
.postfix
;
1163 DBG("Unknown shader stage %d in uniform upload\n", i
);
1167 /* Also attach the same buffer as a UBO for extended access */
1169 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1171 .size
= MALI_POSITIVE((2 + uniform_count
)),
1172 .ptr
= transfer
.gpu
>> 2,
1176 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1177 postfix
->uniforms
= transfer
.gpu
;
1178 postfix
->uniform_buffers
= ubufs
;
1183 /* TODO: Upload the viewport somewhere more appropriate */
1185 /* Clip bounds are encoded as floats. The viewport itself is encoded as
1186 * (somewhat) asymmetric ints. */
1187 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1189 struct mali_viewport view
= {
1190 /* By default, do no viewport clipping, i.e. clip to (-inf,
1191 * inf) in each direction. Clipping to the viewport in theory
1192 * should work, but in practice causes issues when we're not
1193 * explicitly trying to scissor */
1204 /* Always scissor to the viewport by default. */
1205 view
.viewport0
[0] = (int) (vp
->translate
[0] - vp
->scale
[0]);
1206 view
.viewport1
[0] = MALI_POSITIVE((int) (vp
->translate
[0] + vp
->scale
[0]));
1208 view
.viewport0
[1] = (int) (translate_y
- fabs(vp
->scale
[1]));
1209 view
.viewport1
[1] = MALI_POSITIVE((int) (translate_y
+ fabs(vp
->scale
[1])));
1211 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
) {
1212 /* Invert scissor if needed */
1213 unsigned miny
= invert_y
?
1214 ctx
->pipe_framebuffer
.height
- ss
->maxy
: ss
->miny
;
1216 unsigned maxy
= invert_y
?
1217 ctx
->pipe_framebuffer
.height
- ss
->miny
: ss
->maxy
;
1219 /* Set the actual scissor */
1220 view
.viewport0
[0] = ss
->minx
;
1221 view
.viewport0
[1] = miny
;
1222 view
.viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1223 view
.viewport1
[1] = MALI_POSITIVE(maxy
);
1226 ctx
->payload_tiler
.postfix
.viewport
=
1227 panfrost_upload_transient(ctx
,
1229 sizeof(struct mali_viewport
));
1234 /* Corresponds to exactly one draw, but does not submit anything */
1237 panfrost_queue_draw(struct panfrost_context
*ctx
)
1239 /* TODO: Expand the array? */
1240 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1241 DBG("Job buffer overflow, ignoring draw\n");
1245 /* Handle dirty flags now */
1246 panfrost_emit_for_draw(ctx
, true);
1248 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1249 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1251 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1252 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1254 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1255 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1260 /* At the end of the frame, the vertex and tiler jobs are linked together and
1261 * then the fragment job is plonked at the end. Set value job is first for
1262 * unknown reasons. */
1265 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1267 if (first
->job_descriptor_size
)
1268 first
->next_job_64
= (u64
) (uintptr_t) next
;
1270 first
->next_job_32
= (u32
) (uintptr_t) next
;
1274 panfrost_link_jobs(struct panfrost_context
*ctx
)
1276 if (ctx
->draw_count
) {
1277 /* Generate the set_value_job */
1278 panfrost_set_value_job(ctx
);
1280 /* Have the first vertex job depend on the set value job */
1281 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1284 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1287 /* V -> V/T ; T -> T/null */
1288 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1289 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1291 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1295 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1296 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1297 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1301 /* The entire frame is in memory -- send it off to the kernel! */
1304 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1305 struct pipe_fence_handle
**fence
,
1306 struct panfrost_job
*job
)
1308 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1309 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1311 /* Edge case if screen is cleared and nothing else */
1312 bool has_draws
= ctx
->draw_count
> 0;
1314 /* Workaround a bizarre lockup (a hardware errata?) */
1316 flush_immediate
= true;
1318 /* A number of jobs are batched -- this must be linked and cleared */
1319 panfrost_link_jobs(ctx
);
1321 ctx
->draw_count
= 0;
1322 ctx
->vertex_job_count
= 0;
1323 ctx
->tiler_job_count
= 0;
1327 bool is_scanout
= panfrost_is_scanout(ctx
);
1328 screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1330 /* If visual, we can stall a frame */
1332 if (!flush_immediate
)
1333 screen
->driver
->force_flush_fragment(ctx
, fence
);
1335 screen
->last_fragment_flushed
= false;
1336 screen
->last_job
= job
;
1338 /* If readback, flush now (hurts the pipelined performance) */
1339 if (flush_immediate
)
1340 screen
->driver
->force_flush_fragment(ctx
, fence
);
1342 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1343 screen
->driver
->dump_counters(screen
);
1346 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1347 FILE *fp
= fopen(filename
, "wb");
1348 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1357 struct pipe_context
*pipe
,
1358 struct pipe_fence_handle
**fence
,
1361 struct panfrost_context
*ctx
= pan_context(pipe
);
1362 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1364 /* Nothing to do! */
1365 if (!ctx
->draw_count
&& !job
->clear
) return;
1367 /* Whether to stall the pipeline for immediately correct results */
1368 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1370 /* Submit the frame itself */
1371 panfrost_submit_frame(ctx
, flush_immediate
, fence
, job
);
1373 /* Prepare for the next frame */
1374 panfrost_invalidate_frame(ctx
);
1377 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1380 g2m_draw_mode(enum pipe_prim_type mode
)
1383 DEFINE_CASE(POINTS
);
1385 DEFINE_CASE(LINE_LOOP
);
1386 DEFINE_CASE(LINE_STRIP
);
1387 DEFINE_CASE(TRIANGLES
);
1388 DEFINE_CASE(TRIANGLE_STRIP
);
1389 DEFINE_CASE(TRIANGLE_FAN
);
1391 DEFINE_CASE(QUAD_STRIP
);
1392 DEFINE_CASE(POLYGON
);
1395 DBG("Illegal draw mode %d\n", mode
);
1397 return MALI_LINE_LOOP
;
1404 panfrost_translate_index_size(unsigned size
)
1408 return MALI_DRAW_INDEXED_UINT8
;
1411 return MALI_DRAW_INDEXED_UINT16
;
1414 return MALI_DRAW_INDEXED_UINT32
;
1417 DBG("Unknown index size %d\n", size
);
1423 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1424 * good for the duration of the draw (transient), could last longer */
1427 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1429 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1431 off_t offset
= info
->start
* info
->index_size
;
1433 if (!info
->has_user_indices
) {
1434 /* Only resources can be directly mapped */
1435 return rsrc
->bo
->gpu
+ offset
;
1437 /* Otherwise, we need to upload to transient memory */
1438 const uint8_t *ibuf8
= (const uint8_t *) info
->index
.user
;
1439 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1445 struct pipe_context
*pipe
,
1446 const struct pipe_draw_info
*info
)
1448 struct panfrost_context
*ctx
= pan_context(pipe
);
1450 ctx
->payload_vertex
.draw_start
= info
->start
;
1451 ctx
->payload_tiler
.draw_start
= info
->start
;
1453 int mode
= info
->mode
;
1455 /* Fallback for unsupported modes */
1457 if (!(ctx
->draw_modes
& (1 << mode
))) {
1458 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1459 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1461 if (info
->count
< 4) {
1462 /* Degenerate case? */
1466 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1467 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1472 /* Now that we have a guaranteed terminating path, find the job.
1473 * Assignment commented out to prevent unused warning */
1475 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1477 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1479 ctx
->vertex_count
= info
->count
;
1481 /* For non-indexed draws, they're the same */
1482 unsigned invocation_count
= ctx
->vertex_count
;
1484 unsigned draw_flags
= 0;
1486 /* The draw flags interpret how primitive size is interpreted */
1488 if (panfrost_writes_point_size(ctx
))
1489 draw_flags
|= MALI_DRAW_VARYING_SIZE
;
1491 /* For higher amounts of vertices (greater than what fits in a 16-bit
1492 * short), the other value is needed, otherwise there will be bizarre
1493 * rendering artefacts. It's not clear what these values mean yet. */
1495 draw_flags
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1497 if (info
->index_size
) {
1498 /* Calculate the min/max index used so we can figure out how
1499 * many times to invoke the vertex shader */
1501 /* Fetch / calculate index bounds */
1502 unsigned min_index
= 0, max_index
= 0;
1504 if (info
->max_index
== ~0u) {
1505 u_vbuf_get_minmax_index(pipe
, info
, &min_index
, &max_index
);
1507 min_index
= info
->min_index
;
1508 max_index
= info
->max_index
;
1511 /* Use the corresponding values */
1512 invocation_count
= max_index
- min_index
+ 1;
1513 ctx
->payload_vertex
.draw_start
= min_index
;
1514 ctx
->payload_tiler
.draw_start
= min_index
;
1516 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1517 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1519 //assert(!info->restart_index); /* TODO: Research */
1520 assert(!info
->index_bias
);
1522 draw_flags
|= panfrost_translate_index_size(info
->index_size
);
1523 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1525 /* Index count == vertex count, if no indexing is applied, as
1526 * if it is internally indexed in the expected order */
1528 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1529 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1531 /* Reverse index state */
1532 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1535 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1536 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1537 ctx
->payload_tiler
.prefix
.unknown_draw
= draw_flags
;
1539 /* Fire off the draw itself */
1540 panfrost_queue_draw(ctx
);
1546 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1552 panfrost_create_rasterizer_state(
1553 struct pipe_context
*pctx
,
1554 const struct pipe_rasterizer_state
*cso
)
1556 struct panfrost_context
*ctx
= pan_context(pctx
);
1557 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1561 /* Bitmask, unknown meaning of the start value */
1562 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1564 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1565 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1567 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1568 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1570 if (cso
->cull_face
& PIPE_FACE_BACK
)
1571 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1577 panfrost_bind_rasterizer_state(
1578 struct pipe_context
*pctx
,
1581 struct panfrost_context
*ctx
= pan_context(pctx
);
1583 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1587 ctx
->rasterizer
= hwcso
;
1588 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1592 panfrost_create_vertex_elements_state(
1593 struct pipe_context
*pctx
,
1594 unsigned num_elements
,
1595 const struct pipe_vertex_element
*elements
)
1597 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1599 so
->num_elements
= num_elements
;
1600 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1602 /* XXX: What the cornball? This is totally, 100%, unapologetically
1603 * nonsense. And yet it somehow fixes a regression in -bshadow
1604 * (previously, we allocated the descriptor here... a newer commit
1605 * removed that allocation, and then memory corruption led to
1606 * shader_meta getting overwritten in bad ways and then the whole test
1607 * case falling apart . TODO: LOOK INTO PLEASE XXX XXX BAD XXX XXX XXX
1609 panfrost_allocate_chunk(pan_context(pctx
), 0, HEAP_DESCRIPTOR
);
1611 for (int i
= 0; i
< num_elements
; ++i
) {
1612 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1614 enum pipe_format fmt
= elements
[i
].src_format
;
1615 const struct util_format_description
*desc
= util_format_description(fmt
);
1616 so
->hw
[i
].unknown1
= 0x2;
1617 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1619 so
->hw
[i
].format
= panfrost_find_format(desc
);
1621 /* The field itself should probably be shifted over */
1622 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1629 panfrost_bind_vertex_elements_state(
1630 struct pipe_context
*pctx
,
1633 struct panfrost_context
*ctx
= pan_context(pctx
);
1635 ctx
->vertex
= hwcso
;
1636 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1640 panfrost_delete_vertex_elements_state(struct pipe_context
*pctx
, void *hwcso
)
1642 struct panfrost_vertex_state
*so
= (struct panfrost_vertex_state
*) hwcso
;
1643 unsigned bytes
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
1644 DBG("Vertex elements delete leaks descriptor (%d bytes)\n", bytes
);
1649 panfrost_create_shader_state(
1650 struct pipe_context
*pctx
,
1651 const struct pipe_shader_state
*cso
)
1653 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1656 /* Token deep copy to prevent memory corruption */
1658 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1659 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1665 panfrost_delete_shader_state(
1666 struct pipe_context
*pctx
,
1669 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1671 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1672 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1675 unsigned leak
= cso
->variant_count
* sizeof(struct mali_shader_meta
);
1676 DBG("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak
);
1682 panfrost_create_sampler_state(
1683 struct pipe_context
*pctx
,
1684 const struct pipe_sampler_state
*cso
)
1686 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1689 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1691 struct mali_sampler_descriptor sampler_descriptor
= {
1692 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
1693 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
1694 | translate_mip_filter(cso
->min_mip_filter
)
1697 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
1698 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
1699 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
1700 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
1702 cso
->border_color
.f
[0],
1703 cso
->border_color
.f
[1],
1704 cso
->border_color
.f
[2],
1705 cso
->border_color
.f
[3]
1707 .min_lod
= FIXED_16(cso
->min_lod
),
1708 .max_lod
= FIXED_16(cso
->max_lod
),
1712 so
->hw
= sampler_descriptor
;
1718 panfrost_bind_sampler_states(
1719 struct pipe_context
*pctx
,
1720 enum pipe_shader_type shader
,
1721 unsigned start_slot
, unsigned num_sampler
,
1724 assert(start_slot
== 0);
1726 struct panfrost_context
*ctx
= pan_context(pctx
);
1728 /* XXX: Should upload, not just copy? */
1729 ctx
->sampler_count
[shader
] = num_sampler
;
1730 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
1732 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
1736 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
1738 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
1740 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
1741 /* Make sure enable state is at least the same */
1742 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
1746 /* Check that the contents of the test are the same */
1747 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
1748 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
1750 if (!(same_func
&& same_ref
)) {
1754 /* Otherwise, we're good to go */
1759 panfrost_bind_fs_state(
1760 struct pipe_context
*pctx
,
1763 struct panfrost_context
*ctx
= pan_context(pctx
);
1768 /* Match the appropriate variant */
1770 signed variant
= -1;
1772 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
1774 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
1775 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
1781 if (variant
== -1) {
1782 /* No variant matched, so create a new one */
1783 variant
= variants
->variant_count
++;
1784 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
1786 variants
->variants
[variant
].base
= hwcso
;
1787 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
1789 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
1790 struct panfrost_context
*ctx
= pan_context(pctx
);
1791 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1793 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1794 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
1798 /* Select this variant */
1799 variants
->active_variant
= variant
;
1801 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
1802 assert(panfrost_variant_matches(ctx
, shader_state
));
1804 /* Now we have a variant selected, so compile and go */
1806 if (!shader_state
->compiled
) {
1807 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
1808 shader_state
->compiled
= true;
1812 ctx
->dirty
|= PAN_DIRTY_FS
;
1816 panfrost_bind_vs_state(
1817 struct pipe_context
*pctx
,
1820 struct panfrost_context
*ctx
= pan_context(pctx
);
1825 if (!ctx
->vs
->variants
[0].compiled
) {
1826 ctx
->vs
->variants
[0].base
= hwcso
;
1828 /* TODO DRY from above */
1829 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
1830 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
1831 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
1833 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
1834 ctx
->vs
->variants
[0].compiled
= true;
1838 ctx
->dirty
|= PAN_DIRTY_VS
;
1842 panfrost_set_vertex_buffers(
1843 struct pipe_context
*pctx
,
1844 unsigned start_slot
,
1845 unsigned num_buffers
,
1846 const struct pipe_vertex_buffer
*buffers
)
1848 struct panfrost_context
*ctx
= pan_context(pctx
);
1850 util_set_vertex_buffers_mask(ctx
->vertex_buffers
, &ctx
->vb_mask
, buffers
, start_slot
, num_buffers
);
1854 panfrost_set_constant_buffer(
1855 struct pipe_context
*pctx
,
1856 enum pipe_shader_type shader
, uint index
,
1857 const struct pipe_constant_buffer
*buf
)
1859 struct panfrost_context
*ctx
= pan_context(pctx
);
1860 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
1862 size_t sz
= buf
? buf
->buffer_size
: 0;
1864 /* Free previous buffer */
1871 pbuf
->buffer
= NULL
;
1874 /* If unbinding, we're done */
1879 /* Multiple constant buffers not yet supported */
1884 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
1887 cpu
= rsrc
->bo
->cpu
;
1888 } else if (buf
->user_buffer
) {
1889 cpu
= buf
->user_buffer
;
1891 DBG("No constant buffer?\n");
1895 /* Copy the constant buffer into the driver context for later upload */
1897 pbuf
->buffer
= malloc(sz
);
1898 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
1902 panfrost_set_stencil_ref(
1903 struct pipe_context
*pctx
,
1904 const struct pipe_stencil_ref
*ref
)
1906 struct panfrost_context
*ctx
= pan_context(pctx
);
1907 ctx
->stencil_ref
= *ref
;
1909 /* Shader core dirty */
1910 ctx
->dirty
|= PAN_DIRTY_FS
;
1913 static struct pipe_sampler_view
*
1914 panfrost_create_sampler_view(
1915 struct pipe_context
*pctx
,
1916 struct pipe_resource
*texture
,
1917 const struct pipe_sampler_view
*template)
1919 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
1920 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
1922 pipe_reference(NULL
, &texture
->reference
);
1924 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
1926 so
->base
= *template;
1927 so
->base
.texture
= texture
;
1928 so
->base
.reference
.count
= 1;
1929 so
->base
.context
= pctx
;
1931 /* sampler_views correspond to texture descriptors, minus the texture
1932 * (data) itself. So, we serialise the descriptor here and cache it for
1935 /* Make sure it's something with which we're familiar */
1936 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
1938 /* TODO: Detect from format better */
1939 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
1941 unsigned char user_swizzle
[4] = {
1942 template->swizzle_r
,
1943 template->swizzle_g
,
1944 template->swizzle_b
,
1948 enum mali_format format
= panfrost_find_format(desc
);
1950 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
1952 unsigned usage2_layout
= 0x10;
1954 switch (prsrc
->bo
->layout
) {
1956 usage2_layout
|= 0x8 | 0x4;
1959 usage2_layout
|= 0x1;
1962 usage2_layout
|= is_depth
? 0x1 : 0x2;
1969 struct mali_texture_descriptor texture_descriptor
= {
1970 .width
= MALI_POSITIVE(texture
->width0
),
1971 .height
= MALI_POSITIVE(texture
->height0
),
1972 .depth
= MALI_POSITIVE(texture
->depth0
),
1976 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
1980 .is_not_cubemap
= texture
->target
!= PIPE_TEXTURE_CUBE
,
1982 .usage2
= usage2_layout
1985 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
1988 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
1989 assert (template->u
.tex
.first_level
== 0);
1991 /* Disable mipmapping for now to avoid regressions while automipmapping
1992 * is being implemented. TODO: Remove me once automipmaps work */
1994 //texture_descriptor.nr_mipmap_levels = template->u.tex.last_level - template->u.tex.first_level;
1995 texture_descriptor
.nr_mipmap_levels
= 0;
1997 so
->hw
= texture_descriptor
;
1999 return (struct pipe_sampler_view
*) so
;
2003 panfrost_set_sampler_views(
2004 struct pipe_context
*pctx
,
2005 enum pipe_shader_type shader
,
2006 unsigned start_slot
, unsigned num_views
,
2007 struct pipe_sampler_view
**views
)
2009 struct panfrost_context
*ctx
= pan_context(pctx
);
2011 assert(start_slot
== 0);
2013 ctx
->sampler_view_count
[shader
] = num_views
;
2014 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2016 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2020 panfrost_sampler_view_destroy(
2021 struct pipe_context
*pctx
,
2022 struct pipe_sampler_view
*views
)
2024 //struct panfrost_context *ctx = pan_context(pctx);
2032 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2033 const struct pipe_framebuffer_state
*fb
)
2035 struct panfrost_context
*ctx
= pan_context(pctx
);
2037 /* Flush when switching away from an FBO */
2039 if (!panfrost_is_scanout(ctx
)) {
2040 panfrost_flush(pctx
, NULL
, 0);
2043 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2044 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2045 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2046 ctx
->pipe_framebuffer
.width
= fb
->width
;
2047 ctx
->pipe_framebuffer
.height
= fb
->height
;
2049 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2050 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2052 /* check if changing cbuf */
2053 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2055 if (cb
&& (i
!= 0)) {
2056 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2061 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2066 if (ctx
->require_sfbd
)
2067 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2069 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2071 panfrost_attach_vt_framebuffer(ctx
);
2073 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2074 bool is_scanout
= panfrost_is_scanout(ctx
);
2076 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
) {
2077 /* The blob is aggressive about enabling AFBC. As such,
2078 * it's pretty much necessary to use it here, since we
2079 * have no traces of non-compressed FBO. */
2081 panfrost_enable_afbc(ctx
, tex
, false);
2084 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2085 /* Enable transaction elimination if we can */
2086 panfrost_enable_checksum(ctx
, tex
);
2091 struct pipe_surface
*zb
= fb
->zsbuf
;
2093 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2094 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2099 if (ctx
->require_sfbd
)
2100 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2102 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2104 panfrost_attach_vt_framebuffer(ctx
);
2106 /* Keep the depth FBO linear */
2113 panfrost_create_blend_state(struct pipe_context
*pipe
,
2114 const struct pipe_blend_state
*blend
)
2116 struct panfrost_context
*ctx
= pan_context(pipe
);
2117 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2120 /* TODO: The following features are not yet implemented */
2121 assert(!blend
->logicop_enable
);
2122 assert(!blend
->alpha_to_coverage
);
2123 assert(!blend
->alpha_to_one
);
2125 /* Compile the blend state, first as fixed-function if we can */
2127 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], &so
->equation
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2130 /* If we can't, compile a blend shader instead */
2132 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2138 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2141 struct panfrost_context
*ctx
= pan_context(pipe
);
2142 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2143 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2144 ctx
->blend
= pblend
;
2149 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2151 /* TODO: Attach color */
2153 /* Shader itself is not dirty, but the shader core is */
2154 ctx
->dirty
|= PAN_DIRTY_FS
;
2158 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2161 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2163 if (so
->has_blend_shader
) {
2164 DBG("Deleting blend state leak blend shaders bytecode\n");
2171 panfrost_set_blend_color(struct pipe_context
*pipe
,
2172 const struct pipe_blend_color
*blend_color
)
2174 struct panfrost_context
*ctx
= pan_context(pipe
);
2176 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2179 ctx
->blend_color
= *blend_color
;
2181 /* The blend mode depends on the blend constant color, due to the
2182 * fixed/programmable split. So, we're forced to regenerate the blend
2185 /* TODO: Attach color */
2190 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2191 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2193 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2197 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2200 struct panfrost_context
*ctx
= pan_context(pipe
);
2201 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2202 ctx
->depth_stencil
= depth_stencil
;
2207 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2208 * emulated in the fragment shader */
2210 if (depth_stencil
->alpha
.enabled
) {
2211 /* We need to trigger a new shader (maybe) */
2212 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2216 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2218 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2219 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2221 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2222 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2224 /* Depth state (TODO: Refactor) */
2225 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2227 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2229 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2230 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2232 /* Bounds test not implemented */
2233 assert(!depth_stencil
->depth
.bounds_test
);
2235 ctx
->dirty
|= PAN_DIRTY_FS
;
2239 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2245 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2246 unsigned sample_mask
)
2251 panfrost_set_clip_state(struct pipe_context
*pipe
,
2252 const struct pipe_clip_state
*clip
)
2254 //struct panfrost_context *panfrost = pan_context(pipe);
2258 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2259 unsigned start_slot
,
2260 unsigned num_viewports
,
2261 const struct pipe_viewport_state
*viewports
)
2263 struct panfrost_context
*ctx
= pan_context(pipe
);
2265 assert(start_slot
== 0);
2266 assert(num_viewports
== 1);
2268 ctx
->pipe_viewport
= *viewports
;
2271 /* TODO: What if not centered? */
2272 float w
= abs(viewports
->scale
[0]) * 2.0;
2273 float h
= abs(viewports
->scale
[1]) * 2.0;
2275 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2276 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2281 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2282 unsigned start_slot
,
2283 unsigned num_scissors
,
2284 const struct pipe_scissor_state
*scissors
)
2286 struct panfrost_context
*ctx
= pan_context(pipe
);
2288 assert(start_slot
== 0);
2289 assert(num_scissors
== 1);
2291 ctx
->scissor
= *scissors
;
2295 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2296 const struct pipe_poly_stipple
*stipple
)
2298 //struct panfrost_context *panfrost = pan_context(pipe);
2302 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2305 //struct panfrost_context *panfrost = pan_context(pipe);
2309 panfrost_destroy(struct pipe_context
*pipe
)
2311 struct panfrost_context
*panfrost
= pan_context(pipe
);
2312 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2314 if (panfrost
->blitter
)
2315 util_blitter_destroy(panfrost
->blitter
);
2317 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2318 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2319 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2320 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2321 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2324 static struct pipe_query
*
2325 panfrost_create_query(struct pipe_context
*pipe
,
2329 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2334 return (struct pipe_query
*) q
;
2338 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2344 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2346 struct panfrost_context
*ctx
= pan_context(pipe
);
2347 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2349 switch (query
->type
) {
2350 case PIPE_QUERY_OCCLUSION_COUNTER
:
2351 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2352 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2354 /* Allocate a word for the query results to be stored */
2355 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2357 ctx
->occlusion_query
= query
;
2363 DBG("Skipping query %d\n", query
->type
);
2371 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2373 struct panfrost_context
*ctx
= pan_context(pipe
);
2374 ctx
->occlusion_query
= NULL
;
2379 panfrost_get_query_result(struct pipe_context
*pipe
,
2380 struct pipe_query
*q
,
2382 union pipe_query_result
*vresult
)
2385 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2387 /* We need to flush out the jobs to actually run the counter, TODO
2388 * check wait, TODO wallpaper after if needed */
2390 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2392 switch (query
->type
) {
2393 case PIPE_QUERY_OCCLUSION_COUNTER
:
2394 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2395 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2396 /* Read back the query results */
2397 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2398 unsigned passed
= *result
;
2400 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2401 vresult
->u64
= passed
;
2403 vresult
->b
= !!passed
;
2409 DBG("Skipped query get %d\n", query
->type
);
2416 static struct pipe_stream_output_target
*
2417 panfrost_create_stream_output_target(struct pipe_context
*pctx
,
2418 struct pipe_resource
*prsc
,
2419 unsigned buffer_offset
,
2420 unsigned buffer_size
)
2422 struct pipe_stream_output_target
*target
;
2424 target
= CALLOC_STRUCT(pipe_stream_output_target
);
2429 pipe_reference_init(&target
->reference
, 1);
2430 pipe_resource_reference(&target
->buffer
, prsc
);
2432 target
->context
= pctx
;
2433 target
->buffer_offset
= buffer_offset
;
2434 target
->buffer_size
= buffer_size
;
2440 panfrost_stream_output_target_destroy(struct pipe_context
*pctx
,
2441 struct pipe_stream_output_target
*target
)
2443 pipe_resource_reference(&target
->buffer
, NULL
);
2448 panfrost_set_stream_output_targets(struct pipe_context
*pctx
,
2449 unsigned num_targets
,
2450 struct pipe_stream_output_target
**targets
,
2451 const unsigned *offsets
)
2457 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2459 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2460 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2462 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2463 /* Allocate the beginning of the transient pool */
2464 int entry_size
= (1 << 22); /* 4MB */
2466 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2467 ctx
->transient_pools
[i
].entry_count
= 1;
2469 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2472 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2473 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2474 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2475 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2476 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2480 /* New context creation, which also does hardware initialisation since I don't
2481 * know the better way to structure this :smirk: */
2483 struct pipe_context
*
2484 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2486 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2487 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2488 memset(ctx
, 0, sizeof(*ctx
));
2489 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2492 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2494 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means T760 or less */
2495 ctx
->require_sfbd
= gpu_id
< 0x0750; /* T760 is the first to support MFBD */
2497 gallium
->screen
= screen
;
2499 gallium
->destroy
= panfrost_destroy
;
2501 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2503 gallium
->flush
= panfrost_flush
;
2504 gallium
->clear
= panfrost_clear
;
2505 gallium
->draw_vbo
= panfrost_draw_vbo
;
2507 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2508 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2510 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2512 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2513 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2514 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2516 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2517 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2518 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2520 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2521 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2522 gallium
->delete_vertex_elements_state
= panfrost_delete_vertex_elements_state
;
2524 gallium
->create_fs_state
= panfrost_create_shader_state
;
2525 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2526 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2528 gallium
->create_vs_state
= panfrost_create_shader_state
;
2529 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2530 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2532 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2533 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2534 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2536 gallium
->create_blend_state
= panfrost_create_blend_state
;
2537 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2538 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2540 gallium
->set_blend_color
= panfrost_set_blend_color
;
2542 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2543 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2544 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2546 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2548 gallium
->set_clip_state
= panfrost_set_clip_state
;
2549 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2550 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2551 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2552 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2554 gallium
->create_query
= panfrost_create_query
;
2555 gallium
->destroy_query
= panfrost_destroy_query
;
2556 gallium
->begin_query
= panfrost_begin_query
;
2557 gallium
->end_query
= panfrost_end_query
;
2558 gallium
->get_query_result
= panfrost_get_query_result
;
2560 gallium
->create_stream_output_target
= panfrost_create_stream_output_target
;
2561 gallium
->stream_output_target_destroy
= panfrost_stream_output_target_destroy
;
2562 gallium
->set_stream_output_targets
= panfrost_set_stream_output_targets
;
2564 panfrost_resource_context_init(gallium
);
2566 pscreen
->driver
->init_context(ctx
);
2568 panfrost_setup_hardware(ctx
);
2571 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2572 gallium
->const_uploader
= gallium
->stream_uploader
;
2573 assert(gallium
->stream_uploader
);
2575 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2576 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2578 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2580 ctx
->blitter
= util_blitter_create(gallium
);
2581 assert(ctx
->blitter
);
2583 /* Prepare for render! */
2585 panfrost_job_init(ctx
);
2586 panfrost_emit_vertex_payload(ctx
);
2587 panfrost_emit_tiler_payload(ctx
);
2588 panfrost_invalidate_frame(ctx
);
2589 panfrost_default_shader_backend(ctx
);
2590 panfrost_generate_space_filler_indices();