2 * © Copyright 2018 Alyssa Rosenzweig
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "pan_context.h"
29 #include "pan_swizzle.h"
30 #include "pan_format.h"
32 #include "util/macros.h"
33 #include "util/u_format.h"
34 #include "util/u_inlines.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/u_memory.h"
37 #include "util/half_float.h"
38 #include "indices/u_primconvert.h"
39 #include "tgsi/tgsi_parse.h"
41 #include "pan_screen.h"
42 #include "pan_blending.h"
43 #include "pan_blend_shaders.h"
45 #include "pan_wallpaper.h"
47 static int performance_counter_number
= 0;
48 extern const char *pan_counters_base
;
50 /* Do not actually send anything to the GPU; merely generate the cmdstream as fast as possible. Disables framebuffer writes */
53 #define SET_BIT(lval, bit, cond) \
59 /* TODO: Sample size, etc */
62 panfrost_set_framebuffer_msaa(struct panfrost_context
*ctx
, bool enabled
)
64 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_HAS_MSAA
, enabled
);
65 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_MSAA
, !enabled
);
67 if (ctx
->require_sfbd
) {
68 SET_BIT(ctx
->fragment_sfbd
.format
, MALI_FRAMEBUFFER_MSAA_A
| MALI_FRAMEBUFFER_MSAA_B
, enabled
);
70 SET_BIT(ctx
->fragment_rts
[0].format
.flags
, MALI_MFBD_FORMAT_MSAA
, enabled
);
72 SET_BIT(ctx
->fragment_mfbd
.unk1
, (1 << 4) | (1 << 1), enabled
);
75 ctx
->fragment_mfbd
.rt_count_2
= enabled
? 4 : 1;
79 /* AFBC is enabled on a per-resource basis (AFBC enabling is theoretically
80 * indepdent between color buffers and depth/stencil). To enable, we allocate
81 * the AFBC metadata buffer and mark that it is enabled. We do -not- actually
82 * edit the fragment job here. This routine should be called ONCE per
83 * AFBC-compressed buffer, rather than on every frame. */
86 panfrost_enable_afbc(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
, bool ds
)
88 if (ctx
->require_sfbd
) {
89 DBG("AFBC not supported yet on SFBD\n");
93 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
94 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
95 /* AFBC metadata is 16 bytes per tile */
96 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
97 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
98 int bytes_per_pixel
= util_format_get_blocksize(rsrc
->base
.format
);
99 int stride
= bytes_per_pixel
* rsrc
->base
.width0
; /* TODO: Alignment? */
101 stride
*= 2; /* TODO: Should this be carried over? */
102 int main_size
= stride
* rsrc
->base
.height0
;
103 rsrc
->bo
->afbc_metadata_size
= tile_w
* tile_h
* 16;
105 /* Allocate the AFBC slab itself, large enough to hold the above */
106 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->afbc_slab
,
107 (rsrc
->bo
->afbc_metadata_size
+ main_size
+ 4095) / 4096,
110 rsrc
->bo
->layout
= PAN_AFBC
;
112 /* Compressed textured reads use a tagged pointer to the metadata */
114 rsrc
->bo
->gpu
[0] = rsrc
->bo
->afbc_slab
.gpu
| (ds
? 0 : 1);
115 rsrc
->bo
->cpu
[0] = rsrc
->bo
->afbc_slab
.cpu
;
119 panfrost_enable_checksum(struct panfrost_context
*ctx
, struct panfrost_resource
*rsrc
)
121 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
122 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
123 int tile_w
= (rsrc
->base
.width0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
124 int tile_h
= (rsrc
->base
.height0
+ (MALI_TILE_LENGTH
- 1)) >> MALI_TILE_SHIFT
;
126 /* 8 byte checksum per tile */
127 rsrc
->bo
->checksum_stride
= tile_w
* 8;
128 int pages
= (((rsrc
->bo
->checksum_stride
* tile_h
) + 4095) / 4096);
129 screen
->driver
->allocate_slab(screen
, &rsrc
->bo
->checksum_slab
, pages
, false, 0, 0, 0);
131 rsrc
->bo
->has_checksum
= true;
135 panfrost_sfbd_format_for_surface(struct pipe_surface
*surf
)
138 return 0xb84e0281; /* RGB32, no MSAA */
141 static struct mali_rt_format
142 panfrost_mfbd_format_for_surface(struct pipe_surface
*surf
)
144 /* Explode details on the format */
146 const struct util_format_description
*desc
=
147 util_format_description(surf
->texture
->format
);
149 /* Fill in accordingly */
151 struct mali_rt_format fmt
= {
154 .nr_channels
= MALI_POSITIVE(desc
->nr_channels
),
156 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
163 static bool panfrost_is_scanout(struct panfrost_context
*ctx
);
165 /* These routines link a fragment job with the bound surface, accounting for the
166 * BO layout. This routine runs per-frame */
169 panfrost_set_fragment_target_cbuf(
170 struct panfrost_context
*ctx
,
171 struct pipe_surface
*surf
,
174 struct panfrost_resource
*rsrc
= pan_resource(surf
->texture
);
177 util_format_get_stride(surf
->format
, surf
->texture
->width0
);
179 /* First, we set the format bits */
181 if (ctx
->require_sfbd
) {
182 ctx
->fragment_sfbd
.format
=
183 panfrost_sfbd_format_for_surface(surf
);
185 ctx
->fragment_rts
[cb
].format
=
186 panfrost_mfbd_format_for_surface(surf
);
189 /* Now, we set the layout specific pieces */
191 if (rsrc
->bo
->layout
== PAN_LINEAR
) {
192 mali_ptr framebuffer
= rsrc
->bo
->gpu
[0];
194 /* The default is upside down from OpenGL's perspective. */
195 if (panfrost_is_scanout(ctx
)) {
196 framebuffer
+= stride
* (surf
->texture
->height0
- 1);
200 if (ctx
->require_sfbd
) {
201 ctx
->fragment_sfbd
.framebuffer
= framebuffer
;
202 ctx
->fragment_sfbd
.stride
= stride
;
204 /* MFBD specifies stride in tiles */
205 ctx
->fragment_rts
[cb
].framebuffer
= framebuffer
;
206 ctx
->fragment_rts
[cb
].framebuffer_stride
= stride
/ 16;
208 } else if (rsrc
->bo
->layout
== PAN_AFBC
) {
209 /* TODO: AFBC on SFBD */
210 assert(!ctx
->require_sfbd
);
212 /* Enable AFBC for the render target */
213 ctx
->fragment_rts
[cb
].afbc
.metadata
= rsrc
->bo
->afbc_slab
.gpu
;
214 ctx
->fragment_rts
[cb
].afbc
.stride
= 0;
215 ctx
->fragment_rts
[cb
].afbc
.unk
= 0x30009;
217 ctx
->fragment_rts
[cb
].format
.flags
|= MALI_MFBD_FORMAT_AFBC
;
219 mali_ptr afbc_main
= rsrc
->bo
->afbc_slab
.gpu
+ rsrc
->bo
->afbc_metadata_size
;
220 ctx
->fragment_rts
[cb
].framebuffer
= afbc_main
;
222 /* TODO: Investigate shift */
223 ctx
->fragment_rts
[cb
].framebuffer_stride
= stride
<< 1;
225 fprintf(stderr
, "Invalid render layout (cbuf %d)", cb
);
231 panfrost_set_fragment_target(struct panfrost_context
*ctx
)
233 for (int cb
= 0; cb
< ctx
->pipe_framebuffer
.nr_cbufs
; ++cb
) {
234 struct pipe_surface
*surf
= ctx
->pipe_framebuffer
.cbufs
[cb
];
235 panfrost_set_fragment_target_cbuf(ctx
, surf
, cb
);
238 /* Enable depth/stencil AFBC for the framebuffer (not the render target) */
239 if (ctx
->pipe_framebuffer
.zsbuf
) {
240 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
;
242 if (rsrc
->bo
->layout
== PAN_AFBC
) {
243 if (ctx
->require_sfbd
) {
244 DBG("Depth AFBC not supported on SFBD\n");
248 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
250 ctx
->fragment_extra
.flags
=
257 ctx
->fragment_extra
.ds_afbc
.depth_stencil_afbc_metadata
= rsrc
->bo
->afbc_slab
.gpu
;
258 ctx
->fragment_extra
.ds_afbc
.depth_stencil_afbc_stride
= 0;
260 ctx
->fragment_extra
.ds_afbc
.depth_stencil
= rsrc
->bo
->afbc_slab
.gpu
+ rsrc
->bo
->afbc_metadata_size
;
262 ctx
->fragment_extra
.ds_afbc
.zero1
= 0x10009;
263 ctx
->fragment_extra
.ds_afbc
.padding
= 0x1000;
265 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_DEPTH_WRITE
;
269 /* For the special case of a depth-only FBO, we need to attach a dummy render target */
271 if (ctx
->pipe_framebuffer
.nr_cbufs
== 0) {
272 if (ctx
->require_sfbd
) {
273 DBG("Depth-only FBO not supported on SFBD\n");
277 struct mali_rt_format null_rt
= {
282 ctx
->fragment_rts
[0].format
= null_rt
;
283 ctx
->fragment_rts
[0].framebuffer
= 0;
284 ctx
->fragment_rts
[0].framebuffer_stride
= 0;
288 /* Framebuffer descriptor */
291 panfrost_set_framebuffer_resolution(struct mali_single_framebuffer
*fb
, int w
, int h
)
293 fb
->width
= MALI_POSITIVE(w
);
294 fb
->height
= MALI_POSITIVE(h
);
296 /* No idea why this is needed, but it's how resolution_check is
297 * calculated. It's not clear to us yet why the hardware wants this.
298 * The formula itself was discovered mostly by manual bruteforce and
299 * aggressive algebraic simplification. */
301 fb
->resolution_check
= ((w
+ h
) / 3) << 4;
304 static struct mali_single_framebuffer
305 panfrost_emit_sfbd(struct panfrost_context
*ctx
)
307 struct mali_single_framebuffer framebuffer
= {
309 .format
= 0x30000000,
310 .clear_flags
= 0x1000,
311 .unknown_address_0
= ctx
->scratchpad
.gpu
,
312 .unknown_address_1
= ctx
->misc_0
.gpu
,
313 .unknown_address_2
= ctx
->misc_0
.gpu
+ 40960,
315 .tiler_heap_free
= ctx
->tiler_heap
.gpu
,
316 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
319 panfrost_set_framebuffer_resolution(&framebuffer
, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
324 static struct bifrost_framebuffer
325 panfrost_emit_mfbd(struct panfrost_context
*ctx
)
327 struct bifrost_framebuffer framebuffer
= {
328 /* It is not yet clear what tiler_meta means or how it's
329 * calculated, but we can tell the lower 32-bits are a
330 * (monotonically increasing?) function of tile count and
331 * geometry complexity; I suspect it defines a memory size of
332 * some kind? for the tiler. It's really unclear at the
333 * moment... but to add to the confusion, the hardware is happy
334 * enough to accept a zero in this field, so we don't even have
335 * to worry about it right now.
337 * The byte (just after the 32-bit mark) is much more
338 * interesting. The higher nibble I've only ever seen as 0xF,
339 * but the lower one I've seen as 0x0 or 0xF, and it's not
340 * obvious what the difference is. But what -is- obvious is
341 * that when the lower nibble is zero, performance is severely
342 * degraded compared to when the lower nibble is set.
343 * Evidently, that nibble enables some sort of fast path,
344 * perhaps relating to caching or tile flush? Regardless, at
345 * this point there's no clear reason not to set it, aside from
346 * substantially increased memory requirements (of the misc_0
349 .tiler_meta
= ((uint64_t) 0xff << 32) | 0x0,
351 .width1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
352 .height1
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
353 .width2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.width
),
354 .height2
= MALI_POSITIVE(ctx
->pipe_framebuffer
.height
),
359 .rt_count_1
= MALI_POSITIVE(1),
364 /* Corresponds to unknown_address_X of SFBD */
365 .scratchpad
= ctx
->scratchpad
.gpu
,
366 .tiler_scratch_start
= ctx
->misc_0
.gpu
,
368 /* The constant added here is, like the lower word of
369 * tiler_meta, (loosely) another product of framebuffer size
370 * and geometry complexity. It must be sufficiently large for
371 * the tiler_meta fast path to work; if it's too small, there
372 * will be DATA_INVALID_FAULTs. Conversely, it must be less
373 * than the total size of misc_0, or else there's no room. It's
374 * possible this constant configures a partition between two
375 * parts of misc_0? We haven't investigated the functionality,
376 * as these buffers are internally used by the hardware
377 * (presumably by the tiler) but not seemingly touched by the driver
380 .tiler_scratch_middle
= ctx
->misc_0
.gpu
+ 0xf0000,
382 .tiler_heap_start
= ctx
->tiler_heap
.gpu
,
383 .tiler_heap_end
= ctx
->tiler_heap
.gpu
+ ctx
->tiler_heap
.size
,
389 /* Are we currently rendering to the screen (rather than an FBO)? */
392 panfrost_is_scanout(struct panfrost_context
*ctx
)
394 /* If there is no color buffer, it's an FBO */
395 if (!ctx
->pipe_framebuffer
.nr_cbufs
)
398 /* If we're too early that no framebuffer was sent, it's scanout */
399 if (!ctx
->pipe_framebuffer
.cbufs
[0])
402 return ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_DISPLAY_TARGET
||
403 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SCANOUT
||
404 ctx
->pipe_framebuffer
.cbufs
[0]->texture
->bind
& PIPE_BIND_SHARED
;
407 /* The above function is for generalised fbd emission, used in both fragment as
408 * well as vertex/tiler payloads. This payload is specific to fragment
412 panfrost_new_frag_framebuffer(struct panfrost_context
*ctx
)
414 if (ctx
->require_sfbd
) {
415 struct mali_single_framebuffer fb
= panfrost_emit_sfbd(ctx
);
416 memcpy(&ctx
->fragment_sfbd
, &fb
, sizeof(fb
));
418 struct bifrost_framebuffer fb
= panfrost_emit_mfbd(ctx
);
424 struct bifrost_render_target rt
= {};
426 memcpy(&ctx
->fragment_rts
[0], &rt
, sizeof(rt
));
427 memset(&ctx
->fragment_extra
, 0, sizeof(ctx
->fragment_extra
));
428 memcpy(&ctx
->fragment_mfbd
, &fb
, sizeof(fb
));
432 /* Maps float 0.0-1.0 to int 0x00-0xFF */
434 normalised_float_to_u8(float f
)
436 return (uint8_t) (int) (f
* 255.0f
);
440 panfrost_clear_sfbd(struct panfrost_job
*job
)
442 struct panfrost_context
*ctx
= job
->ctx
;
443 struct mali_single_framebuffer
*sfbd
= &ctx
->fragment_sfbd
;
445 if (job
->clear
& PIPE_CLEAR_COLOR
) {
446 sfbd
->clear_color_1
= job
->clear_color
;
447 sfbd
->clear_color_2
= job
->clear_color
;
448 sfbd
->clear_color_3
= job
->clear_color
;
449 sfbd
->clear_color_4
= job
->clear_color
;
452 if (job
->clear
& PIPE_CLEAR_DEPTH
) {
453 sfbd
->clear_depth_1
= job
->clear_depth
;
454 sfbd
->clear_depth_2
= job
->clear_depth
;
455 sfbd
->clear_depth_3
= job
->clear_depth
;
456 sfbd
->clear_depth_4
= job
->clear_depth
;
458 sfbd
->depth_buffer
= ctx
->depth_stencil_buffer
.gpu
;
459 sfbd
->depth_buffer_enable
= MALI_DEPTH_STENCIL_ENABLE
;
462 if (job
->clear
& PIPE_CLEAR_STENCIL
) {
463 sfbd
->clear_stencil
= job
->clear_stencil
;
465 sfbd
->stencil_buffer
= ctx
->depth_stencil_buffer
.gpu
;
466 sfbd
->stencil_buffer_enable
= MALI_DEPTH_STENCIL_ENABLE
;
469 /* Set flags based on what has been cleared, for the SFBD case */
470 /* XXX: What do these flags mean? */
471 int clear_flags
= 0x101100;
473 if (!(job
->clear
& ~(PIPE_CLEAR_COLOR
| PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
))) {
474 /* On a tiler like this, it's fastest to clear all three buffers at once */
476 clear_flags
|= MALI_CLEAR_FAST
;
478 clear_flags
|= MALI_CLEAR_SLOW
;
480 if (job
->clear
& PIPE_CLEAR_STENCIL
)
481 clear_flags
|= MALI_CLEAR_SLOW_STENCIL
;
484 sfbd
->clear_flags
= clear_flags
;
488 panfrost_clear_mfbd(struct panfrost_job
*job
)
490 struct panfrost_context
*ctx
= job
->ctx
;
491 struct bifrost_render_target
*buffer_color
= &ctx
->fragment_rts
[0];
492 struct bifrost_framebuffer
*buffer_ds
= &ctx
->fragment_mfbd
;
494 if (job
->clear
& PIPE_CLEAR_COLOR
) {
495 buffer_color
->clear_color_1
= job
->clear_color
;
496 buffer_color
->clear_color_2
= job
->clear_color
;
497 buffer_color
->clear_color_3
= job
->clear_color
;
498 buffer_color
->clear_color_4
= job
->clear_color
;
501 if (job
->clear
& PIPE_CLEAR_DEPTH
) {
502 buffer_ds
->clear_depth
= job
->clear_depth
;
505 if (job
->clear
& PIPE_CLEAR_STENCIL
) {
506 buffer_ds
->clear_stencil
= job
->clear_stencil
;
509 if (job
->clear
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
510 /* Setup combined 24/8 depth/stencil */
511 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
512 ctx
->fragment_extra
.flags
= 0x405;
513 ctx
->fragment_extra
.ds_linear
.depth
= ctx
->depth_stencil_buffer
.gpu
;
514 ctx
->fragment_extra
.ds_linear
.depth_stride
= ctx
->pipe_framebuffer
.width
* 4;
520 struct pipe_context
*pipe
,
522 const union pipe_color_union
*color
,
523 double depth
, unsigned stencil
)
525 struct panfrost_context
*ctx
= pan_context(pipe
);
526 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
528 if (buffers
& PIPE_CLEAR_COLOR
) {
529 /* Alpha clear only meaningful without alpha channel, TODO less ad hoc */
530 bool has_alpha
= util_format_has_alpha(ctx
->pipe_framebuffer
.cbufs
[0]->format
);
531 float clear_alpha
= has_alpha
? color
->f
[3] : 1.0f
;
533 uint32_t packed_color
=
534 (normalised_float_to_u8(clear_alpha
) << 24) |
535 (normalised_float_to_u8(color
->f
[2]) << 16) |
536 (normalised_float_to_u8(color
->f
[1]) << 8) |
537 (normalised_float_to_u8(color
->f
[0]) << 0);
539 job
->clear_color
= packed_color
;
543 if (buffers
& PIPE_CLEAR_DEPTH
) {
544 job
->clear_depth
= depth
;
547 if (buffers
& PIPE_CLEAR_STENCIL
) {
548 job
->clear_stencil
= stencil
;
551 job
->clear
|= buffers
;
555 panfrost_attach_vt_mfbd(struct panfrost_context
*ctx
)
557 /* MFBD needs a sequential semi-render target upload, but what exactly this is, is beyond me for now */
558 struct bifrost_render_target rts_list
[] = {
563 .framebuffer
= ctx
->misc_0
.gpu
,
568 /* Allocate memory for the three components */
569 int size
= 1024 + sizeof(ctx
->vt_framebuffer_mfbd
) + sizeof(rts_list
);
570 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
572 /* Opaque 1024-block */
573 rts_list
[0].chunknown
.pointer
= transfer
.gpu
;
575 memcpy(transfer
.cpu
+ 1024, &ctx
->vt_framebuffer_mfbd
, sizeof(ctx
->vt_framebuffer_mfbd
));
576 memcpy(transfer
.cpu
+ 1024 + sizeof(ctx
->vt_framebuffer_mfbd
), rts_list
, sizeof(rts_list
));
578 return (transfer
.gpu
+ 1024) | MALI_MFBD
;
582 panfrost_attach_vt_sfbd(struct panfrost_context
*ctx
)
584 return panfrost_upload_transient(ctx
, &ctx
->vt_framebuffer_sfbd
, sizeof(ctx
->vt_framebuffer_sfbd
)) | MALI_SFBD
;
588 panfrost_attach_vt_framebuffer(struct panfrost_context
*ctx
)
590 mali_ptr framebuffer
= ctx
->require_sfbd
?
591 panfrost_attach_vt_sfbd(ctx
) :
592 panfrost_attach_vt_mfbd(ctx
);
594 ctx
->payload_vertex
.postfix
.framebuffer
= framebuffer
;
595 ctx
->payload_tiler
.postfix
.framebuffer
= framebuffer
;
599 panfrost_viewport(struct panfrost_context
*ctx
,
600 float depth_clip_near
,
601 float depth_clip_far
,
602 int viewport_x0
, int viewport_y0
,
603 int viewport_x1
, int viewport_y1
)
605 /* Clip bounds are encoded as floats. The viewport itself is encoded as
606 * (somewhat) asymmetric ints. */
608 struct mali_viewport ret
= {
609 /* By default, do no viewport clipping, i.e. clip to (-inf,
610 * inf) in each direction. Clipping to the viewport in theory
611 * should work, but in practice causes issues when we're not
612 * explicitly trying to scissor */
619 /* We always perform depth clipping (TODO: Can this be disabled?) */
621 .clip_minz
= depth_clip_near
,
622 .clip_maxz
= depth_clip_far
,
624 .viewport0
= { viewport_x0
, viewport_y0
},
625 .viewport1
= { MALI_POSITIVE(viewport_x1
), MALI_POSITIVE(viewport_y1
) },
628 memcpy(ctx
->viewport
, &ret
, sizeof(ret
));
631 /* Reset per-frame context, called on context initialisation as well as after
632 * flushing a frame */
635 panfrost_invalidate_frame(struct panfrost_context
*ctx
)
637 unsigned transient_count
= ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
*ctx
->transient_pools
[0].entry_size
+ ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
;
638 DBG("Uploaded transient %d bytes\n", transient_count
);
640 /* Rotate cmdstream */
641 if ((++ctx
->cmdstream_i
) == (sizeof(ctx
->transient_pools
) / sizeof(ctx
->transient_pools
[0])))
642 ctx
->cmdstream_i
= 0;
644 if (ctx
->require_sfbd
)
645 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
647 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
649 panfrost_new_frag_framebuffer(ctx
);
651 /* Reset varyings allocated */
652 ctx
->varying_height
= 0;
654 /* The transient cmdstream is dirty every frame; the only bits worth preserving
655 * (textures, shaders, etc) are in other buffers anyways */
657 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_index
= 0;
658 ctx
->transient_pools
[ctx
->cmdstream_i
].entry_offset
= 0;
660 /* Regenerate payloads */
661 panfrost_attach_vt_framebuffer(ctx
);
664 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
667 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
| PAN_DIRTY_TEXTURES
;
670 /* In practice, every field of these payloads should be configurable
671 * arbitrarily, which means these functions are basically catch-all's for
672 * as-of-yet unwavering unknowns */
675 panfrost_emit_vertex_payload(struct panfrost_context
*ctx
)
677 struct midgard_payload_vertex_tiler payload
= {
679 .workgroups_z_shift
= 32,
680 .workgroups_x_shift_2
= 0x2,
681 .workgroups_x_shift_3
= 0x5,
683 .gl_enables
= 0x4 | (ctx
->is_t6xx
? 0 : 0x2),
686 memcpy(&ctx
->payload_vertex
, &payload
, sizeof(payload
));
690 panfrost_emit_tiler_payload(struct panfrost_context
*ctx
)
692 struct midgard_payload_vertex_tiler payload
= {
694 .workgroups_z_shift
= 32,
695 .workgroups_x_shift_2
= 0x2,
696 .workgroups_x_shift_3
= 0x6,
698 .zero1
= 0xffff, /* Why is this only seen on test-quad-textured? */
702 /* Reserve the viewport */
703 struct panfrost_transfer t
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_viewport
), HEAP_DESCRIPTOR
);
704 ctx
->viewport
= (struct mali_viewport
*) t
.cpu
;
705 payload
.postfix
.viewport
= t
.gpu
;
707 memcpy(&ctx
->payload_tiler
, &payload
, sizeof(payload
));
711 translate_tex_wrap(enum pipe_tex_wrap w
)
714 case PIPE_TEX_WRAP_REPEAT
:
715 return MALI_WRAP_REPEAT
;
717 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
718 return MALI_WRAP_CLAMP_TO_EDGE
;
720 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
721 return MALI_WRAP_CLAMP_TO_BORDER
;
723 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
724 return MALI_WRAP_MIRRORED_REPEAT
;
733 translate_tex_filter(enum pipe_tex_filter f
)
736 case PIPE_TEX_FILTER_NEAREST
:
739 case PIPE_TEX_FILTER_LINEAR
:
749 translate_mip_filter(enum pipe_tex_mipfilter f
)
751 return (f
== PIPE_TEX_MIPFILTER_LINEAR
) ? MALI_MIP_LINEAR
: 0;
755 panfrost_translate_compare_func(enum pipe_compare_func in
)
758 case PIPE_FUNC_NEVER
:
759 return MALI_FUNC_NEVER
;
762 return MALI_FUNC_LESS
;
764 case PIPE_FUNC_EQUAL
:
765 return MALI_FUNC_EQUAL
;
767 case PIPE_FUNC_LEQUAL
:
768 return MALI_FUNC_LEQUAL
;
770 case PIPE_FUNC_GREATER
:
771 return MALI_FUNC_GREATER
;
773 case PIPE_FUNC_NOTEQUAL
:
774 return MALI_FUNC_NOTEQUAL
;
776 case PIPE_FUNC_GEQUAL
:
777 return MALI_FUNC_GEQUAL
;
779 case PIPE_FUNC_ALWAYS
:
780 return MALI_FUNC_ALWAYS
;
784 return 0; /* Unreachable */
788 panfrost_translate_alt_compare_func(enum pipe_compare_func in
)
791 case PIPE_FUNC_NEVER
:
792 return MALI_ALT_FUNC_NEVER
;
795 return MALI_ALT_FUNC_LESS
;
797 case PIPE_FUNC_EQUAL
:
798 return MALI_ALT_FUNC_EQUAL
;
800 case PIPE_FUNC_LEQUAL
:
801 return MALI_ALT_FUNC_LEQUAL
;
803 case PIPE_FUNC_GREATER
:
804 return MALI_ALT_FUNC_GREATER
;
806 case PIPE_FUNC_NOTEQUAL
:
807 return MALI_ALT_FUNC_NOTEQUAL
;
809 case PIPE_FUNC_GEQUAL
:
810 return MALI_ALT_FUNC_GEQUAL
;
812 case PIPE_FUNC_ALWAYS
:
813 return MALI_ALT_FUNC_ALWAYS
;
817 return 0; /* Unreachable */
821 panfrost_translate_stencil_op(enum pipe_stencil_op in
)
824 case PIPE_STENCIL_OP_KEEP
:
825 return MALI_STENCIL_KEEP
;
827 case PIPE_STENCIL_OP_ZERO
:
828 return MALI_STENCIL_ZERO
;
830 case PIPE_STENCIL_OP_REPLACE
:
831 return MALI_STENCIL_REPLACE
;
833 case PIPE_STENCIL_OP_INCR
:
834 return MALI_STENCIL_INCR
;
836 case PIPE_STENCIL_OP_DECR
:
837 return MALI_STENCIL_DECR
;
839 case PIPE_STENCIL_OP_INCR_WRAP
:
840 return MALI_STENCIL_INCR_WRAP
;
842 case PIPE_STENCIL_OP_DECR_WRAP
:
843 return MALI_STENCIL_DECR_WRAP
;
845 case PIPE_STENCIL_OP_INVERT
:
846 return MALI_STENCIL_INVERT
;
850 return 0; /* Unreachable */
854 panfrost_make_stencil_state(const struct pipe_stencil_state
*in
, struct mali_stencil_test
*out
)
856 out
->ref
= 0; /* Gallium gets it from elsewhere */
858 out
->mask
= in
->valuemask
;
859 out
->func
= panfrost_translate_compare_func(in
->func
);
860 out
->sfail
= panfrost_translate_stencil_op(in
->fail_op
);
861 out
->dpfail
= panfrost_translate_stencil_op(in
->zfail_op
);
862 out
->dppass
= panfrost_translate_stencil_op(in
->zpass_op
);
866 panfrost_default_shader_backend(struct panfrost_context
*ctx
)
868 struct mali_shader_meta shader
= {
869 .alpha_coverage
= ~MALI_ALPHA_COVERAGE(0.000000),
871 .unknown2_3
= MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS
) | 0x3010,
872 .unknown2_4
= MALI_NO_MSAA
| 0x4e0,
876 shader
.unknown2_4
|= 0x10;
879 struct pipe_stencil_state default_stencil
= {
881 .func
= PIPE_FUNC_ALWAYS
,
882 .fail_op
= MALI_STENCIL_KEEP
,
883 .zfail_op
= MALI_STENCIL_KEEP
,
884 .zpass_op
= MALI_STENCIL_KEEP
,
889 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_front
);
890 shader
.stencil_mask_front
= default_stencil
.writemask
;
892 panfrost_make_stencil_state(&default_stencil
, &shader
.stencil_back
);
893 shader
.stencil_mask_back
= default_stencil
.writemask
;
895 if (default_stencil
.enabled
)
896 shader
.unknown2_4
|= MALI_STENCIL_TEST
;
898 memcpy(&ctx
->fragment_shader_core
, &shader
, sizeof(shader
));
901 /* Generates a vertex/tiler job. This is, in some sense, the heart of the
902 * graphics command stream. It should be called once per draw, accordding to
903 * presentations. Set is_tiler for "tiler" jobs (fragment shader jobs, but in
904 * Mali parlance, "fragment" refers to framebuffer writeout). Clear it for
907 struct panfrost_transfer
908 panfrost_vertex_tiler_job(struct panfrost_context
*ctx
, bool is_tiler
, bool is_elided_tiler
)
910 /* Each draw call corresponds to two jobs, and we want to offset to leave room for the set-value job */
911 int draw_job_index
= 1 + (2 * ctx
->draw_count
);
913 struct mali_job_descriptor_header job
= {
914 .job_type
= is_tiler
? JOB_TYPE_TILER
: JOB_TYPE_VERTEX
,
915 .job_index
= draw_job_index
+ (is_tiler
? 1 : 0),
917 .job_descriptor_size
= 1,
921 /* Only non-elided tiler jobs have dependencies which are known at this point */
923 if (is_tiler
&& !is_elided_tiler
) {
924 /* Tiler jobs depend on vertex jobs */
926 job
.job_dependency_index_1
= draw_job_index
;
928 /* Tiler jobs also depend on the previous tiler job */
931 job
.job_dependency_index_2
= draw_job_index
- 1;
934 struct midgard_payload_vertex_tiler
*payload
= is_tiler
? &ctx
->payload_tiler
: &ctx
->payload_vertex
;
936 /* There's some padding hacks on 32-bit */
943 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(*payload
));
944 memcpy(transfer
.cpu
, &job
, sizeof(job
));
945 memcpy(transfer
.cpu
+ sizeof(job
) - offset
, payload
, sizeof(*payload
));
949 /* Generates a set value job. It's unclear what exactly this does, why it's
950 * necessary, and when to call it. */
953 panfrost_set_value_job(struct panfrost_context
*ctx
)
955 struct mali_job_descriptor_header job
= {
956 .job_type
= JOB_TYPE_SET_VALUE
,
957 .job_descriptor_size
= 1,
958 .job_index
= 1 + (2 * ctx
->draw_count
),
961 struct mali_payload_set_value payload
= {
962 .out
= ctx
->misc_0
.gpu
,
966 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(job
) + sizeof(payload
));
967 memcpy(transfer
.cpu
, &job
, sizeof(job
));
968 memcpy(transfer
.cpu
+ sizeof(job
), &payload
, sizeof(payload
));
970 ctx
->u_set_value_job
= (struct mali_job_descriptor_header
*) transfer
.cpu
;
971 ctx
->set_value_job
= transfer
.gpu
;
974 /* Generate a fragment job. This should be called once per frame. (According to
975 * presentations, this is supposed to correspond to eglSwapBuffers) */
978 panfrost_fragment_job(struct panfrost_context
*ctx
)
980 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
982 /* Actualize the clear late; TODO: Fix order dependency between clear
985 if (ctx
->require_sfbd
) {
986 panfrost_clear_sfbd(job
);
988 panfrost_clear_mfbd(job
);
991 panfrost_set_fragment_target(ctx
);
993 if (ctx
->pipe_framebuffer
.nr_cbufs
== 1) {
994 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[0]->texture
;
996 if (rsrc
->bo
->has_checksum
) {
997 if (ctx
->require_sfbd
) {
998 DBG("Checksumming not supported on SFBD\n");
1002 int stride
= util_format_get_stride(rsrc
->base
.format
, rsrc
->base
.width0
);
1004 ctx
->fragment_mfbd
.unk3
|= MALI_MFBD_EXTRA
;
1005 ctx
->fragment_extra
.flags
|= MALI_EXTRA_PRESENT
;
1006 ctx
->fragment_extra
.checksum_stride
= rsrc
->bo
->checksum_stride
;
1007 ctx
->fragment_extra
.checksum
= rsrc
->bo
->gpu
[0] + stride
* rsrc
->base
.height0
;
1011 /* The frame is complete and therefore the framebuffer descriptor is
1012 * ready for linkage and upload */
1014 size_t sz
= ctx
->require_sfbd
? sizeof(struct mali_single_framebuffer
) : (sizeof(struct bifrost_framebuffer
) + sizeof(struct bifrost_fb_extra
) + sizeof(struct bifrost_render_target
) * 1);
1015 struct panfrost_transfer fbd_t
= panfrost_allocate_transient(ctx
, sz
);
1018 if (ctx
->require_sfbd
) {
1019 /* Upload just the SFBD all at once */
1020 memcpy(fbd_t
.cpu
, &ctx
->fragment_sfbd
, sizeof(ctx
->fragment_sfbd
));
1021 offset
+= sizeof(ctx
->fragment_sfbd
);
1023 /* Upload the MFBD header */
1024 memcpy(fbd_t
.cpu
, &ctx
->fragment_mfbd
, sizeof(ctx
->fragment_mfbd
));
1025 offset
+= sizeof(ctx
->fragment_mfbd
);
1027 /* Upload extra framebuffer info if necessary */
1028 if (ctx
->fragment_mfbd
.unk3
& MALI_MFBD_EXTRA
) {
1029 memcpy(fbd_t
.cpu
+ offset
, &ctx
->fragment_extra
, sizeof(struct bifrost_fb_extra
));
1030 offset
+= sizeof(struct bifrost_fb_extra
);
1033 /* Upload (single) render target */
1034 memcpy(fbd_t
.cpu
+ offset
, &ctx
->fragment_rts
[0], sizeof(struct bifrost_render_target
) * 1);
1037 /* Generate the fragment (frame) job */
1039 struct mali_job_descriptor_header header
= {
1040 .job_type
= JOB_TYPE_FRAGMENT
,
1043 .job_descriptor_size
= 1
1047 struct mali_payload_fragment payload
= {
1048 .min_tile_coord
= MALI_COORDINATE_TO_TILE_MIN(0, 0),
1049 .max_tile_coord
= MALI_COORDINATE_TO_TILE_MAX(ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
),
1050 .framebuffer
= fbd_t
.gpu
| (ctx
->require_sfbd
? MALI_SFBD
: MALI_MFBD
),
1053 if (!ctx
->require_sfbd
&& ctx
->fragment_mfbd
.unk3
& MALI_MFBD_EXTRA
) {
1054 /* Signal that there is an extra portion of the framebuffer
1057 payload
.framebuffer
|= 2;
1060 /* Normally, there should be no padding. However, fragment jobs are
1061 * shared with 64-bit Bifrost systems, and accordingly there is 4-bytes
1062 * of zero padding in between. */
1064 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(header
) + sizeof(payload
));
1065 memcpy(transfer
.cpu
, &header
, sizeof(header
));
1066 memcpy(transfer
.cpu
+ sizeof(header
), &payload
, sizeof(payload
));
1067 return transfer
.gpu
;
1070 /* Emits attributes and varying descriptors, which should be called every draw,
1071 * excepting some obscure circumstances */
1074 panfrost_emit_vertex_data(struct panfrost_context
*ctx
)
1076 /* TODO: Only update the dirtied buffers */
1077 union mali_attr attrs
[PIPE_MAX_ATTRIBS
];
1078 union mali_attr varyings
[PIPE_MAX_ATTRIBS
];
1080 unsigned invocation_count
= MALI_NEGATIVE(ctx
->payload_tiler
.prefix
.invocation_count
);
1082 for (int i
= 0; i
< ctx
->vertex_buffer_count
; ++i
) {
1083 struct pipe_vertex_buffer
*buf
= &ctx
->vertex_buffers
[i
];
1084 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
.resource
);
1086 /* Let's figure out the layout of the attributes in memory so
1087 * we can be smart about size computation. The idea is to
1088 * figure out the maximum src_offset, which tells us the latest
1089 * spot a vertex could start. Meanwhile, we figure out the size
1090 * of the attribute memory (assuming interleaved
1091 * representation) and tack on the max src_offset for a
1092 * reasonably good upper bound on the size.
1094 * Proving correctness is left as an exercise to the reader.
1097 unsigned max_src_offset
= 0;
1099 for (unsigned j
= 0; j
< ctx
->vertex
->num_elements
; ++j
) {
1100 if (ctx
->vertex
->pipe
[j
].vertex_buffer_index
!= i
) continue;
1101 max_src_offset
= MAX2(max_src_offset
, ctx
->vertex
->pipe
[j
].src_offset
);
1104 /* Offset vertex count by draw_start to make sure we upload enough */
1105 attrs
[i
].stride
= buf
->stride
;
1106 attrs
[i
].size
= buf
->stride
* (ctx
->payload_vertex
.draw_start
+ invocation_count
) + max_src_offset
;
1108 /* Vertex elements are -already- GPU-visible, at
1109 * rsrc->gpu. However, attribute buffers must be 64 aligned. If
1110 * it is not, for now we have to duplicate the buffer. */
1112 mali_ptr effective_address
= (rsrc
->bo
->gpu
[0] + buf
->buffer_offset
);
1114 if (effective_address
& 0x3F) {
1115 attrs
[i
].elements
= panfrost_upload_transient(ctx
, rsrc
->bo
->cpu
[0] + buf
->buffer_offset
, attrs
[i
].size
) | 1;
1117 attrs
[i
].elements
= effective_address
| 1;
1121 struct panfrost_varyings
*vars
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
1123 for (int i
= 0; i
< vars
->varying_buffer_count
; ++i
) {
1124 mali_ptr varying_address
= ctx
->varying_mem
.gpu
+ ctx
->varying_height
;
1126 varyings
[i
].elements
= varying_address
| 1;
1127 varyings
[i
].stride
= vars
->varyings_stride
[i
];
1128 varyings
[i
].size
= vars
->varyings_stride
[i
] * invocation_count
;
1130 /* If this varying has to be linked somewhere, do it now. See
1131 * pan_assemble.c for the indices. TODO: Use a more generic
1132 * linking interface */
1136 ctx
->payload_tiler
.postfix
.position_varying
= varying_address
;
1137 } else if (i
== 2) {
1139 ctx
->payload_tiler
.primitive_size
.pointer
= varying_address
;
1142 /* Varyings appear to need 64-byte alignment */
1143 ctx
->varying_height
+= ALIGN(varyings
[i
].size
, 64);
1145 /* Ensure that we fit */
1146 assert(ctx
->varying_height
< ctx
->varying_mem
.size
);
1149 ctx
->payload_vertex
.postfix
.attributes
= panfrost_upload_transient(ctx
, attrs
, ctx
->vertex_buffer_count
* sizeof(union mali_attr
));
1151 mali_ptr varyings_p
= panfrost_upload_transient(ctx
, &varyings
, vars
->varying_buffer_count
* sizeof(union mali_attr
));
1152 ctx
->payload_vertex
.postfix
.varyings
= varyings_p
;
1153 ctx
->payload_tiler
.postfix
.varyings
= varyings_p
;
1156 /* Go through dirty flags and actualise them in the cmdstream. */
1159 panfrost_emit_for_draw(struct panfrost_context
*ctx
, bool with_vertex_data
)
1161 if (with_vertex_data
) {
1162 panfrost_emit_vertex_data(ctx
);
1165 if (ctx
->dirty
& PAN_DIRTY_RASTERIZER
) {
1166 ctx
->payload_tiler
.gl_enables
= ctx
->rasterizer
->tiler_gl_enables
;
1167 panfrost_set_framebuffer_msaa(ctx
, ctx
->rasterizer
->base
.multisample
);
1170 if (ctx
->occlusion_query
) {
1171 ctx
->payload_tiler
.gl_enables
|= MALI_OCCLUSION_QUERY
| MALI_OCCLUSION_PRECISE
;
1172 ctx
->payload_tiler
.postfix
.occlusion_counter
= ctx
->occlusion_query
->transfer
.gpu
;
1175 if (ctx
->dirty
& PAN_DIRTY_VS
) {
1178 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1180 /* Late shader descriptor assignments */
1181 vs
->tripipe
->texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_VERTEX
];
1182 vs
->tripipe
->sampler_count
= ctx
->sampler_count
[PIPE_SHADER_VERTEX
];
1185 vs
->tripipe
->midgard1
.unknown1
= 0x2201;
1187 ctx
->payload_vertex
.postfix
._shader_upper
= vs
->tripipe_gpu
>> 4;
1189 /* Varying descriptor is tied to the vertex shader. Also the
1190 * fragment shader, I suppose, but it's generated with the
1191 * vertex shader so */
1193 struct panfrost_varyings
*varyings
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
].varyings
;
1195 ctx
->payload_vertex
.postfix
.varying_meta
= varyings
->varyings_descriptor
;
1196 ctx
->payload_tiler
.postfix
.varying_meta
= varyings
->varyings_descriptor_fragment
;
1199 if (ctx
->dirty
& (PAN_DIRTY_RASTERIZER
| PAN_DIRTY_VS
)) {
1200 /* Check if we need to link the gl_PointSize varying */
1202 struct panfrost_shader_state
*vs
= &ctx
->vs
->variants
[ctx
->vs
->active_variant
];
1204 bool needs_gl_point_size
= vs
->writes_point_size
&& ctx
->payload_tiler
.prefix
.draw_mode
== MALI_POINTS
;
1206 if (!needs_gl_point_size
) {
1207 /* If the size is constant, write it out. Otherwise,
1208 * don't touch primitive_size (since we would clobber
1209 * the pointer there) */
1211 ctx
->payload_tiler
.primitive_size
.constant
= ctx
->rasterizer
->base
.line_width
;
1214 /* Set the flag for varying (pointer) point size if the shader needs that */
1215 SET_BIT(ctx
->payload_tiler
.prefix
.unknown_draw
, MALI_DRAW_VARYING_SIZE
, needs_gl_point_size
);
1218 /* TODO: Maybe dirty track FS, maybe not. For now, it's transient. */
1220 ctx
->dirty
|= PAN_DIRTY_FS
;
1222 if (ctx
->dirty
& PAN_DIRTY_FS
) {
1224 struct panfrost_shader_state
*variant
= &ctx
->fs
->variants
[ctx
->fs
->active_variant
];
1226 #define COPY(name) ctx->fragment_shader_core.name = variant->tripipe->name
1229 COPY(attribute_count
);
1230 COPY(varying_count
);
1231 COPY(midgard1
.uniform_count
);
1232 COPY(midgard1
.work_count
);
1233 COPY(midgard1
.unknown2
);
1236 /* If there is a blend shader, work registers are shared */
1238 if (ctx
->blend
->has_blend_shader
)
1239 ctx
->fragment_shader_core
.midgard1
.work_count
= /*MAX2(ctx->fragment_shader_core.midgard1.work_count, ctx->blend->blend_work_count)*/16;
1241 /* Set late due to depending on render state */
1242 /* The one at the end seems to mean "1 UBO" */
1243 ctx
->fragment_shader_core
.midgard1
.unknown1
= MALI_NO_ALPHA_TO_COVERAGE
| 0x200 | 0x2201;
1245 /* Assign texture/sample count right before upload */
1246 ctx
->fragment_shader_core
.texture_count
= ctx
->sampler_view_count
[PIPE_SHADER_FRAGMENT
];
1247 ctx
->fragment_shader_core
.sampler_count
= ctx
->sampler_count
[PIPE_SHADER_FRAGMENT
];
1249 /* Assign the stencil refs late */
1250 ctx
->fragment_shader_core
.stencil_front
.ref
= ctx
->stencil_ref
.ref_value
[0];
1251 ctx
->fragment_shader_core
.stencil_back
.ref
= ctx
->stencil_ref
.ref_value
[1];
1253 /* CAN_DISCARD should be set if the fragment shader possibly
1254 * contains a 'discard' instruction. It is likely this is
1255 * related to optimizations related to forward-pixel kill, as
1256 * per "Mali Performance 3: Is EGL_BUFFER_PRESERVED a good
1257 * thing?" by Peter Harris
1260 if (variant
->can_discard
) {
1261 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1262 ctx
->fragment_shader_core
.midgard1
.unknown1
&= ~MALI_NO_ALPHA_TO_COVERAGE
;
1263 ctx
->fragment_shader_core
.midgard1
.unknown1
|= 0x4000;
1264 ctx
->fragment_shader_core
.midgard1
.unknown1
= 0x4200;
1267 /* Check if we're using the default blend descriptor (fast path) */
1270 !ctx
->blend
->has_blend_shader
&&
1271 (ctx
->blend
->equation
.rgb_mode
== 0x122) &&
1272 (ctx
->blend
->equation
.alpha_mode
== 0x122) &&
1273 (ctx
->blend
->equation
.color_mask
== 0xf);
1275 if (ctx
->require_sfbd
) {
1276 /* When only a single render target platform is used, the blend
1277 * information is inside the shader meta itself. We
1278 * additionally need to signal CAN_DISCARD for nontrivial blend
1279 * modes (so we're able to read back the destination buffer) */
1281 if (ctx
->blend
->has_blend_shader
) {
1282 ctx
->fragment_shader_core
.blend_shader
= ctx
->blend
->blend_shader
;
1284 memcpy(&ctx
->fragment_shader_core
.blend_equation
, &ctx
->blend
->equation
, sizeof(ctx
->blend
->equation
));
1288 ctx
->fragment_shader_core
.unknown2_3
|= MALI_CAN_DISCARD
;
1292 size_t size
= sizeof(struct mali_shader_meta
) + sizeof(struct mali_blend_meta
);
1293 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1294 memcpy(transfer
.cpu
, &ctx
->fragment_shader_core
, sizeof(struct mali_shader_meta
));
1296 ctx
->payload_tiler
.postfix
._shader_upper
= (transfer
.gpu
) >> 4;
1298 if (!ctx
->require_sfbd
) {
1299 /* Additional blend descriptor tacked on for jobs using MFBD */
1301 unsigned blend_count
= 0;
1303 if (ctx
->blend
->has_blend_shader
) {
1304 /* For a blend shader, the bottom nibble corresponds to
1305 * the number of work registers used, which signals the
1306 * -existence- of a blend shader */
1308 assert(ctx
->blend
->blend_work_count
>= 2);
1309 blend_count
|= MIN2(ctx
->blend
->blend_work_count
, 3);
1311 /* Otherwise, the bottom bit simply specifies if
1312 * blending (anything other than REPLACE) is enabled */
1319 /* Second blend equation is always a simple replace */
1321 uint64_t replace_magic
= 0xf0122122;
1322 struct mali_blend_equation replace_mode
;
1323 memcpy(&replace_mode
, &replace_magic
, sizeof(replace_mode
));
1325 struct mali_blend_meta blend_meta
[] = {
1327 .unk1
= 0x200 | blend_count
,
1328 .blend_equation_1
= ctx
->blend
->equation
,
1329 .blend_equation_2
= replace_mode
1333 if (ctx
->blend
->has_blend_shader
)
1334 memcpy(&blend_meta
[0].blend_equation_1
, &ctx
->blend
->blend_shader
, sizeof(ctx
->blend
->blend_shader
));
1336 memcpy(transfer
.cpu
+ sizeof(struct mali_shader_meta
), blend_meta
, sizeof(blend_meta
));
1340 if (ctx
->dirty
& PAN_DIRTY_VERTEX
) {
1341 ctx
->payload_vertex
.postfix
.attribute_meta
= ctx
->vertex
->descriptor_ptr
;
1344 if (ctx
->dirty
& PAN_DIRTY_SAMPLERS
) {
1345 /* Upload samplers back to back, no padding */
1347 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1348 if (!ctx
->sampler_count
[t
]) continue;
1350 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, sizeof(struct mali_sampler_descriptor
) * ctx
->sampler_count
[t
]);
1351 struct mali_sampler_descriptor
*desc
= (struct mali_sampler_descriptor
*) transfer
.cpu
;
1353 for (int i
= 0; i
< ctx
->sampler_count
[t
]; ++i
) {
1354 desc
[i
] = ctx
->samplers
[t
][i
]->hw
;
1357 if (t
== PIPE_SHADER_FRAGMENT
)
1358 ctx
->payload_tiler
.postfix
.sampler_descriptor
= transfer
.gpu
;
1359 else if (t
== PIPE_SHADER_VERTEX
)
1360 ctx
->payload_vertex
.postfix
.sampler_descriptor
= transfer
.gpu
;
1366 if (ctx
->dirty
& PAN_DIRTY_TEXTURES
) {
1367 for (int t
= 0; t
<= PIPE_SHADER_FRAGMENT
; ++t
) {
1369 if (!ctx
->sampler_view_count
[t
]) continue;
1371 uint64_t trampolines
[PIPE_MAX_SHADER_SAMPLER_VIEWS
];
1373 for (int i
= 0; i
< ctx
->sampler_view_count
[t
]; ++i
) {
1374 if (!ctx
->sampler_views
[t
][i
])
1377 struct pipe_resource
*tex_rsrc
= ctx
->sampler_views
[t
][i
]->base
.texture
;
1378 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) tex_rsrc
;
1380 /* Inject the address in. */
1381 for (int l
= 0; l
< (tex_rsrc
->last_level
+ 1); ++l
)
1382 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[l
] = rsrc
->bo
->gpu
[l
];
1384 /* Workaround maybe-errata (?) with non-mipmaps */
1385 int s
= ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
;
1387 if (!rsrc
->bo
->is_mipmap
) {
1389 /* HW ERRATA, not needed after t6XX */
1390 ctx
->sampler_views
[t
][i
]->hw
.swizzled_bitmaps
[1] = rsrc
->bo
->gpu
[0];
1392 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 1;
1395 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= 0;
1398 trampolines
[i
] = panfrost_upload_transient(ctx
, &ctx
->sampler_views
[t
][i
]->hw
, sizeof(struct mali_texture_descriptor
));
1401 ctx
->sampler_views
[t
][i
]->hw
.nr_mipmap_levels
= s
;
1404 ctx
->sampler_views
[t
][i
]->hw
.unknown3A
= 0;
1408 mali_ptr trampoline
= panfrost_upload_transient(ctx
, trampolines
, sizeof(uint64_t) * ctx
->sampler_view_count
[t
]);
1410 if (t
== PIPE_SHADER_FRAGMENT
)
1411 ctx
->payload_tiler
.postfix
.texture_trampoline
= trampoline
;
1412 else if (t
== PIPE_SHADER_VERTEX
)
1413 ctx
->payload_vertex
.postfix
.texture_trampoline
= trampoline
;
1419 /* Generate the viewport vector of the form: <width/2, height/2, centerx, centery> */
1420 const struct pipe_viewport_state
*vp
= &ctx
->pipe_viewport
;
1422 float viewport_vec4
[] = {
1424 fabsf(vp
->scale
[1]),
1427 /* -1.0 * vp->translate[1] */ fabs(1.0 * vp
->scale
[1]) /* XXX */
1430 for (int i
= 0; i
< PIPE_SHADER_TYPES
; ++i
) {
1431 struct panfrost_constant_buffer
*buf
= &ctx
->constant_buffer
[i
];
1433 if (i
== PIPE_SHADER_VERTEX
|| i
== PIPE_SHADER_FRAGMENT
) {
1434 /* It doesn't matter if we don't use all the memory;
1435 * we'd need a dummy UBO anyway. Compute the max */
1437 size_t size
= sizeof(viewport_vec4
) + buf
->size
;
1438 struct panfrost_transfer transfer
= panfrost_allocate_transient(ctx
, size
);
1440 /* Keep track how much we've uploaded */
1443 if (i
== PIPE_SHADER_VERTEX
) {
1444 /* Upload viewport */
1445 memcpy(transfer
.cpu
+ offset
, viewport_vec4
, sizeof(viewport_vec4
));
1446 offset
+= sizeof(viewport_vec4
);
1449 /* Upload uniforms */
1450 memcpy(transfer
.cpu
+ offset
, buf
->buffer
, buf
->size
);
1452 int uniform_count
= 0;
1454 struct mali_vertex_tiler_postfix
*postfix
;
1457 case PIPE_SHADER_VERTEX
:
1458 uniform_count
= ctx
->vs
->variants
[ctx
->vs
->active_variant
].uniform_count
;
1459 postfix
= &ctx
->payload_vertex
.postfix
;
1462 case PIPE_SHADER_FRAGMENT
:
1463 uniform_count
= ctx
->fs
->variants
[ctx
->fs
->active_variant
].uniform_count
;
1464 postfix
= &ctx
->payload_tiler
.postfix
;
1468 DBG("Unknown shader stage %d in uniform upload\n", i
);
1472 /* Also attach the same buffer as a UBO for extended access */
1474 struct mali_uniform_buffer_meta uniform_buffers
[] = {
1476 .size
= MALI_POSITIVE((2 + uniform_count
)),
1477 .ptr
= transfer
.gpu
>> 2,
1481 mali_ptr ubufs
= panfrost_upload_transient(ctx
, uniform_buffers
, sizeof(uniform_buffers
));
1482 postfix
->uniforms
= transfer
.gpu
;
1483 postfix
->uniform_buffers
= ubufs
;
1492 /* Corresponds to exactly one draw, but does not submit anything */
1495 panfrost_queue_draw(struct panfrost_context
*ctx
)
1497 /* TODO: Expand the array? */
1498 if (ctx
->draw_count
>= MAX_DRAW_CALLS
) {
1499 DBG("Job buffer overflow, ignoring draw\n");
1503 /* Handle dirty flags now */
1504 panfrost_emit_for_draw(ctx
, true);
1506 struct panfrost_transfer vertex
= panfrost_vertex_tiler_job(ctx
, false, false);
1507 struct panfrost_transfer tiler
= panfrost_vertex_tiler_job(ctx
, true, false);
1509 ctx
->u_vertex_jobs
[ctx
->vertex_job_count
] = (struct mali_job_descriptor_header
*) vertex
.cpu
;
1510 ctx
->vertex_jobs
[ctx
->vertex_job_count
++] = vertex
.gpu
;
1512 ctx
->u_tiler_jobs
[ctx
->tiler_job_count
] = (struct mali_job_descriptor_header
*) tiler
.cpu
;
1513 ctx
->tiler_jobs
[ctx
->tiler_job_count
++] = tiler
.gpu
;
1518 /* At the end of the frame, the vertex and tiler jobs are linked together and
1519 * then the fragment job is plonked at the end. Set value job is first for
1520 * unknown reasons. */
1523 panfrost_link_job_pair(struct mali_job_descriptor_header
*first
, mali_ptr next
)
1525 if (first
->job_descriptor_size
)
1526 first
->next_job_64
= (u64
) (uintptr_t) next
;
1528 first
->next_job_32
= (u32
) (uintptr_t) next
;
1532 panfrost_link_jobs(struct panfrost_context
*ctx
)
1534 if (ctx
->draw_count
) {
1535 /* Generate the set_value_job */
1536 panfrost_set_value_job(ctx
);
1538 /* Have the first vertex job depend on the set value job */
1539 ctx
->u_vertex_jobs
[0]->job_dependency_index_1
= ctx
->u_set_value_job
->job_index
;
1542 panfrost_link_job_pair(ctx
->u_set_value_job
, ctx
->vertex_jobs
[0]);
1545 /* V -> V/T ; T -> T/null */
1546 for (int i
= 0; i
< ctx
->vertex_job_count
; ++i
) {
1547 bool isLast
= (i
+ 1) == ctx
->vertex_job_count
;
1549 panfrost_link_job_pair(ctx
->u_vertex_jobs
[i
], isLast
? ctx
->tiler_jobs
[0] : ctx
->vertex_jobs
[i
+ 1]);
1553 for (int i
= 0; i
< ctx
->tiler_job_count
; ++i
) {
1554 bool isLast
= (i
+ 1) == ctx
->tiler_job_count
;
1555 panfrost_link_job_pair(ctx
->u_tiler_jobs
[i
], isLast
? 0 : ctx
->tiler_jobs
[i
+ 1]);
1559 /* The entire frame is in memory -- send it off to the kernel! */
1562 panfrost_submit_frame(struct panfrost_context
*ctx
, bool flush_immediate
,
1563 struct pipe_fence_handle
**fence
)
1565 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
1566 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
1568 /* Edge case if screen is cleared and nothing else */
1569 bool has_draws
= ctx
->draw_count
> 0;
1571 /* Workaround a bizarre lockup (a hardware errata?) */
1573 flush_immediate
= true;
1575 /* A number of jobs are batched -- this must be linked and cleared */
1576 panfrost_link_jobs(ctx
);
1578 ctx
->draw_count
= 0;
1579 ctx
->vertex_job_count
= 0;
1580 ctx
->tiler_job_count
= 0;
1584 bool is_scanout
= panfrost_is_scanout(ctx
);
1585 int fragment_id
= screen
->driver
->submit_vs_fs_job(ctx
, has_draws
, is_scanout
);
1587 /* If visual, we can stall a frame */
1589 if (!flush_immediate
)
1590 screen
->driver
->force_flush_fragment(ctx
, fence
);
1592 screen
->last_fragment_id
= fragment_id
;
1593 screen
->last_fragment_flushed
= false;
1595 /* If readback, flush now (hurts the pipelined performance) */
1596 if (flush_immediate
)
1597 screen
->driver
->force_flush_fragment(ctx
, fence
);
1599 if (screen
->driver
->dump_counters
&& pan_counters_base
) {
1600 screen
->driver
->dump_counters(screen
);
1603 snprintf(filename
, sizeof(filename
), "%s/frame%d.mdgprf", pan_counters_base
, ++performance_counter_number
);
1604 FILE *fp
= fopen(filename
, "wb");
1605 fwrite(screen
->perf_counters
.cpu
, 4096, sizeof(uint32_t), fp
);
1614 struct pipe_context
*pipe
,
1615 struct pipe_fence_handle
**fence
,
1618 struct panfrost_context
*ctx
= pan_context(pipe
);
1619 struct panfrost_job
*job
= panfrost_get_job_for_fbo(ctx
);
1621 /* Nothing to do! */
1622 if (!ctx
->draw_count
&& !job
->clear
) return;
1624 /* Whether to stall the pipeline for immediately correct results */
1625 bool flush_immediate
= flags
& PIPE_FLUSH_END_OF_FRAME
;
1627 /* Submit the frame itself */
1628 panfrost_submit_frame(ctx
, flush_immediate
, fence
);
1630 /* Prepare for the next frame */
1631 panfrost_invalidate_frame(ctx
);
1634 #define DEFINE_CASE(c) case PIPE_PRIM_##c: return MALI_##c;
1637 g2m_draw_mode(enum pipe_prim_type mode
)
1640 DEFINE_CASE(POINTS
);
1642 DEFINE_CASE(LINE_LOOP
);
1643 DEFINE_CASE(LINE_STRIP
);
1644 DEFINE_CASE(TRIANGLES
);
1645 DEFINE_CASE(TRIANGLE_STRIP
);
1646 DEFINE_CASE(TRIANGLE_FAN
);
1648 DEFINE_CASE(QUAD_STRIP
);
1649 DEFINE_CASE(POLYGON
);
1652 DBG("Illegal draw mode %d\n", mode
);
1654 return MALI_LINE_LOOP
;
1661 panfrost_translate_index_size(unsigned size
)
1665 return MALI_DRAW_INDEXED_UINT8
;
1668 return MALI_DRAW_INDEXED_UINT16
;
1671 return MALI_DRAW_INDEXED_UINT32
;
1674 DBG("Unknown index size %d\n", size
);
1680 static const uint8_t *
1681 panfrost_get_index_buffer_raw(const struct pipe_draw_info
*info
)
1683 if (info
->has_user_indices
) {
1684 return (const uint8_t *) info
->index
.user
;
1686 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1687 return (const uint8_t *) rsrc
->bo
->cpu
[0];
1691 /* Gets a GPU address for the associated index buffer. Only gauranteed to be
1692 * good for the duration of the draw (transient), could last longer */
1695 panfrost_get_index_buffer_mapped(struct panfrost_context
*ctx
, const struct pipe_draw_info
*info
)
1697 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (info
->index
.resource
);
1699 off_t offset
= info
->start
* info
->index_size
;
1701 if (!info
->has_user_indices
) {
1702 /* Only resources can be directly mapped */
1703 return rsrc
->bo
->gpu
[0] + offset
;
1705 /* Otherwise, we need to upload to transient memory */
1706 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1707 return panfrost_upload_transient(ctx
, ibuf8
+ offset
, info
->count
* info
->index_size
);
1711 #define CALCULATE_MIN_MAX_INDEX(T, buffer, start, count) \
1712 for (unsigned _idx = (start); _idx < (start + count); ++_idx) { \
1713 T idx = buffer[_idx]; \
1714 if (idx > max_index) max_index = idx; \
1715 if (idx < min_index) min_index = idx; \
1720 struct pipe_context
*pipe
,
1721 const struct pipe_draw_info
*info
)
1723 struct panfrost_context
*ctx
= pan_context(pipe
);
1725 ctx
->payload_vertex
.draw_start
= info
->start
;
1726 ctx
->payload_tiler
.draw_start
= info
->start
;
1728 int mode
= info
->mode
;
1730 /* Fallback for unsupported modes */
1732 if (!(ctx
->draw_modes
& mode
)) {
1733 if (mode
== PIPE_PRIM_QUADS
&& info
->count
== 4 && ctx
->rasterizer
&& !ctx
->rasterizer
->base
.flatshade
) {
1734 mode
= PIPE_PRIM_TRIANGLE_FAN
;
1736 if (info
->count
< 4) {
1737 /* Degenerate case? */
1741 util_primconvert_save_rasterizer_state(ctx
->primconvert
, &ctx
->rasterizer
->base
);
1742 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
1747 /* Now that we have a guaranteed terminating path, find the job.
1748 * Assignment commented out to prevent unused warning */
1750 /* struct panfrost_job *job = */ panfrost_get_job_for_fbo(ctx
);
1752 ctx
->payload_tiler
.prefix
.draw_mode
= g2m_draw_mode(mode
);
1754 ctx
->vertex_count
= info
->count
;
1756 /* For non-indexed draws, they're the same */
1757 unsigned invocation_count
= ctx
->vertex_count
;
1759 /* For higher amounts of vertices (greater than what fits in a 16-bit
1760 * short), the other value is needed, otherwise there will be bizarre
1761 * rendering artefacts. It's not clear what these values mean yet. */
1763 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~(0x3000 | 0x18000);
1764 ctx
->payload_tiler
.prefix
.unknown_draw
|= (mode
== PIPE_PRIM_POINTS
|| ctx
->vertex_count
> 65535) ? 0x3000 : 0x18000;
1766 if (info
->index_size
) {
1767 /* Calculate the min/max index used so we can figure out how
1768 * many times to invoke the vertex shader */
1770 const uint8_t *ibuf8
= panfrost_get_index_buffer_raw(info
);
1772 int min_index
= INT_MAX
;
1775 if (info
->index_size
== 1) {
1776 CALCULATE_MIN_MAX_INDEX(uint8_t, ibuf8
, info
->start
, info
->count
);
1777 } else if (info
->index_size
== 2) {
1778 const uint16_t *ibuf16
= (const uint16_t *) ibuf8
;
1779 CALCULATE_MIN_MAX_INDEX(uint16_t, ibuf16
, info
->start
, info
->count
);
1780 } else if (info
->index_size
== 4) {
1781 const uint32_t *ibuf32
= (const uint32_t *) ibuf8
;
1782 CALCULATE_MIN_MAX_INDEX(uint32_t, ibuf32
, info
->start
, info
->count
);
1787 /* Make sure we didn't go crazy */
1788 assert(min_index
< INT_MAX
);
1789 assert(max_index
> 0);
1790 assert(max_index
> min_index
);
1792 /* Use the corresponding values */
1793 invocation_count
= max_index
- min_index
+ 1;
1794 ctx
->payload_vertex
.draw_start
= min_index
;
1795 ctx
->payload_tiler
.draw_start
= min_index
;
1797 ctx
->payload_tiler
.prefix
.negative_start
= -min_index
;
1798 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(info
->count
);
1800 //assert(!info->restart_index); /* TODO: Research */
1801 assert(!info
->index_bias
);
1802 //assert(!info->min_index); /* TODO: Use value */
1804 ctx
->payload_tiler
.prefix
.unknown_draw
|= panfrost_translate_index_size(info
->index_size
);
1805 ctx
->payload_tiler
.prefix
.indices
= panfrost_get_index_buffer_mapped(ctx
, info
);
1807 /* Index count == vertex count, if no indexing is applied, as
1808 * if it is internally indexed in the expected order */
1810 ctx
->payload_tiler
.prefix
.negative_start
= 0;
1811 ctx
->payload_tiler
.prefix
.index_count
= MALI_POSITIVE(ctx
->vertex_count
);
1813 /* Reverse index state */
1814 ctx
->payload_tiler
.prefix
.unknown_draw
&= ~MALI_DRAW_INDEXED_UINT32
;
1815 ctx
->payload_tiler
.prefix
.indices
= (uintptr_t) NULL
;
1818 ctx
->payload_vertex
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1819 ctx
->payload_tiler
.prefix
.invocation_count
= MALI_POSITIVE(invocation_count
);
1821 /* Fire off the draw itself */
1822 panfrost_queue_draw(ctx
);
1828 panfrost_generic_cso_delete(struct pipe_context
*pctx
, void *hwcso
)
1834 panfrost_set_scissor(struct panfrost_context
*ctx
)
1836 const struct pipe_scissor_state
*ss
= &ctx
->scissor
;
1838 if (ss
&& ctx
->rasterizer
&& ctx
->rasterizer
->base
.scissor
&& 0) {
1839 ctx
->viewport
->viewport0
[0] = ss
->minx
;
1840 ctx
->viewport
->viewport0
[1] = ss
->miny
;
1841 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ss
->maxx
);
1842 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ss
->maxy
);
1844 ctx
->viewport
->viewport0
[0] = 0;
1845 ctx
->viewport
->viewport0
[1] = 0;
1846 ctx
->viewport
->viewport1
[0] = MALI_POSITIVE(ctx
->pipe_framebuffer
.width
);
1847 ctx
->viewport
->viewport1
[1] = MALI_POSITIVE(ctx
->pipe_framebuffer
.height
);
1852 panfrost_create_rasterizer_state(
1853 struct pipe_context
*pctx
,
1854 const struct pipe_rasterizer_state
*cso
)
1856 struct panfrost_context
*ctx
= pan_context(pctx
);
1857 struct panfrost_rasterizer
*so
= CALLOC_STRUCT(panfrost_rasterizer
);
1861 /* Bitmask, unknown meaning of the start value */
1862 so
->tiler_gl_enables
= ctx
->is_t6xx
? 0x105 : 0x7;
1864 so
->tiler_gl_enables
|= MALI_FRONT_FACE(
1865 cso
->front_ccw
? MALI_CCW
: MALI_CW
);
1867 if (cso
->cull_face
& PIPE_FACE_FRONT
)
1868 so
->tiler_gl_enables
|= MALI_CULL_FACE_FRONT
;
1870 if (cso
->cull_face
& PIPE_FACE_BACK
)
1871 so
->tiler_gl_enables
|= MALI_CULL_FACE_BACK
;
1877 panfrost_bind_rasterizer_state(
1878 struct pipe_context
*pctx
,
1881 struct panfrost_context
*ctx
= pan_context(pctx
);
1882 struct pipe_rasterizer_state
*cso
= hwcso
;
1884 /* TODO: Why can't rasterizer be NULL ever? Other drivers are fine.. */
1888 /* If scissor test has changed, we'll need to update that now */
1889 bool update_scissor
= !ctx
->rasterizer
|| ctx
->rasterizer
->base
.scissor
!= cso
->scissor
;
1891 ctx
->rasterizer
= hwcso
;
1893 /* Actualise late changes */
1895 panfrost_set_scissor(ctx
);
1897 ctx
->dirty
|= PAN_DIRTY_RASTERIZER
;
1901 panfrost_create_vertex_elements_state(
1902 struct pipe_context
*pctx
,
1903 unsigned num_elements
,
1904 const struct pipe_vertex_element
*elements
)
1906 struct panfrost_context
*ctx
= pan_context(pctx
);
1907 struct panfrost_vertex_state
*so
= CALLOC_STRUCT(panfrost_vertex_state
);
1909 so
->num_elements
= num_elements
;
1910 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
1912 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_attr_meta
) * num_elements
, HEAP_DESCRIPTOR
);
1913 so
->hw
= (struct mali_attr_meta
*) transfer
.cpu
;
1914 so
->descriptor_ptr
= transfer
.gpu
;
1916 /* Allocate memory for the descriptor state */
1918 for (int i
= 0; i
< num_elements
; ++i
) {
1919 so
->hw
[i
].index
= elements
[i
].vertex_buffer_index
;
1921 enum pipe_format fmt
= elements
[i
].src_format
;
1922 const struct util_format_description
*desc
= util_format_description(fmt
);
1923 so
->hw
[i
].unknown1
= 0x2;
1924 so
->hw
[i
].swizzle
= panfrost_get_default_swizzle(desc
->nr_channels
);
1926 so
->hw
[i
].format
= panfrost_find_format(desc
);
1928 /* The field itself should probably be shifted over */
1929 so
->hw
[i
].src_offset
= elements
[i
].src_offset
;
1936 panfrost_bind_vertex_elements_state(
1937 struct pipe_context
*pctx
,
1940 struct panfrost_context
*ctx
= pan_context(pctx
);
1942 ctx
->vertex
= hwcso
;
1943 ctx
->dirty
|= PAN_DIRTY_VERTEX
;
1947 panfrost_delete_vertex_elements_state(struct pipe_context
*pctx
, void *hwcso
)
1949 struct panfrost_vertex_state
*so
= (struct panfrost_vertex_state
*) hwcso
;
1950 unsigned bytes
= sizeof(struct mali_attr_meta
) * so
->num_elements
;
1951 DBG("Vertex elements delete leaks descriptor (%d bytes)\n", bytes
);
1956 panfrost_create_shader_state(
1957 struct pipe_context
*pctx
,
1958 const struct pipe_shader_state
*cso
)
1960 struct panfrost_shader_variants
*so
= CALLOC_STRUCT(panfrost_shader_variants
);
1963 /* Token deep copy to prevent memory corruption */
1965 if (cso
->type
== PIPE_SHADER_IR_TGSI
)
1966 so
->base
.tokens
= tgsi_dup_tokens(so
->base
.tokens
);
1972 panfrost_delete_shader_state(
1973 struct pipe_context
*pctx
,
1976 struct panfrost_shader_variants
*cso
= (struct panfrost_shader_variants
*) so
;
1978 if (cso
->base
.type
== PIPE_SHADER_IR_TGSI
) {
1979 DBG("Deleting TGSI shader leaks duplicated tokens\n");
1982 unsigned leak
= cso
->variant_count
* sizeof(struct mali_shader_meta
);
1983 DBG("Deleting shader state leaks descriptors (%d bytes), and shader bytecode\n", leak
);
1989 panfrost_create_sampler_state(
1990 struct pipe_context
*pctx
,
1991 const struct pipe_sampler_state
*cso
)
1993 struct panfrost_sampler_state
*so
= CALLOC_STRUCT(panfrost_sampler_state
);
1996 /* sampler_state corresponds to mali_sampler_descriptor, which we can generate entirely here */
1998 struct mali_sampler_descriptor sampler_descriptor
= {
1999 .filter_mode
= MALI_TEX_MIN(translate_tex_filter(cso
->min_img_filter
))
2000 | MALI_TEX_MAG(translate_tex_filter(cso
->mag_img_filter
))
2001 | translate_mip_filter(cso
->min_mip_filter
)
2004 .wrap_s
= translate_tex_wrap(cso
->wrap_s
),
2005 .wrap_t
= translate_tex_wrap(cso
->wrap_t
),
2006 .wrap_r
= translate_tex_wrap(cso
->wrap_r
),
2007 .compare_func
= panfrost_translate_alt_compare_func(cso
->compare_func
),
2009 cso
->border_color
.f
[0],
2010 cso
->border_color
.f
[1],
2011 cso
->border_color
.f
[2],
2012 cso
->border_color
.f
[3]
2014 .min_lod
= FIXED_16(0.0),
2015 .max_lod
= FIXED_16(31.0),
2019 so
->hw
= sampler_descriptor
;
2025 panfrost_bind_sampler_states(
2026 struct pipe_context
*pctx
,
2027 enum pipe_shader_type shader
,
2028 unsigned start_slot
, unsigned num_sampler
,
2031 assert(start_slot
== 0);
2033 struct panfrost_context
*ctx
= pan_context(pctx
);
2035 /* XXX: Should upload, not just copy? */
2036 ctx
->sampler_count
[shader
] = num_sampler
;
2037 memcpy(ctx
->samplers
[shader
], sampler
, num_sampler
* sizeof (void *));
2039 ctx
->dirty
|= PAN_DIRTY_SAMPLERS
;
2043 panfrost_variant_matches(struct panfrost_context
*ctx
, struct panfrost_shader_state
*variant
)
2045 struct pipe_alpha_state
*alpha
= &ctx
->depth_stencil
->alpha
;
2047 if (alpha
->enabled
|| variant
->alpha_state
.enabled
) {
2048 /* Make sure enable state is at least the same */
2049 if (alpha
->enabled
!= variant
->alpha_state
.enabled
) {
2053 /* Check that the contents of the test are the same */
2054 bool same_func
= alpha
->func
== variant
->alpha_state
.func
;
2055 bool same_ref
= alpha
->ref_value
== variant
->alpha_state
.ref_value
;
2057 if (!(same_func
&& same_ref
)) {
2061 /* Otherwise, we're good to go */
2066 panfrost_bind_fs_state(
2067 struct pipe_context
*pctx
,
2070 struct panfrost_context
*ctx
= pan_context(pctx
);
2075 /* Match the appropriate variant */
2077 signed variant
= -1;
2079 struct panfrost_shader_variants
*variants
= (struct panfrost_shader_variants
*) hwcso
;
2081 for (unsigned i
= 0; i
< variants
->variant_count
; ++i
) {
2082 if (panfrost_variant_matches(ctx
, &variants
->variants
[i
])) {
2088 if (variant
== -1) {
2089 /* No variant matched, so create a new one */
2090 variant
= variants
->variant_count
++;
2091 assert(variants
->variant_count
< MAX_SHADER_VARIANTS
);
2093 variants
->variants
[variant
].base
= hwcso
;
2094 variants
->variants
[variant
].alpha_state
= ctx
->depth_stencil
->alpha
;
2096 /* Allocate the mapped descriptor ahead-of-time. TODO: Use for FS as well as VS */
2097 struct panfrost_context
*ctx
= pan_context(pctx
);
2098 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2100 variants
->variants
[variant
].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2101 variants
->variants
[variant
].tripipe_gpu
= transfer
.gpu
;
2105 /* Select this variant */
2106 variants
->active_variant
= variant
;
2108 struct panfrost_shader_state
*shader_state
= &variants
->variants
[variant
];
2109 assert(panfrost_variant_matches(ctx
, shader_state
));
2111 /* Now we have a variant selected, so compile and go */
2113 if (!shader_state
->compiled
) {
2114 panfrost_shader_compile(ctx
, shader_state
->tripipe
, NULL
, JOB_TYPE_TILER
, shader_state
);
2115 shader_state
->compiled
= true;
2119 ctx
->dirty
|= PAN_DIRTY_FS
;
2123 panfrost_bind_vs_state(
2124 struct pipe_context
*pctx
,
2127 struct panfrost_context
*ctx
= pan_context(pctx
);
2132 if (!ctx
->vs
->variants
[0].compiled
) {
2133 ctx
->vs
->variants
[0].base
= hwcso
;
2135 /* TODO DRY from above */
2136 struct panfrost_transfer transfer
= panfrost_allocate_chunk(ctx
, sizeof(struct mali_shader_meta
), HEAP_DESCRIPTOR
);
2137 ctx
->vs
->variants
[0].tripipe
= (struct mali_shader_meta
*) transfer
.cpu
;
2138 ctx
->vs
->variants
[0].tripipe_gpu
= transfer
.gpu
;
2140 panfrost_shader_compile(ctx
, ctx
->vs
->variants
[0].tripipe
, NULL
, JOB_TYPE_VERTEX
, &ctx
->vs
->variants
[0]);
2141 ctx
->vs
->variants
[0].compiled
= true;
2145 ctx
->dirty
|= PAN_DIRTY_VS
;
2149 panfrost_set_vertex_buffers(
2150 struct pipe_context
*pctx
,
2151 unsigned start_slot
,
2152 unsigned num_buffers
,
2153 const struct pipe_vertex_buffer
*buffers
)
2155 struct panfrost_context
*ctx
= pan_context(pctx
);
2156 assert(num_buffers
<= PIPE_MAX_ATTRIBS
);
2158 /* XXX: Dirty tracking? etc */
2160 size_t sz
= sizeof(buffers
[0]) * num_buffers
;
2161 ctx
->vertex_buffers
= malloc(sz
);
2162 ctx
->vertex_buffer_count
= num_buffers
;
2163 memcpy(ctx
->vertex_buffers
, buffers
, sz
);
2165 if (ctx
->vertex_buffers
) {
2166 free(ctx
->vertex_buffers
);
2167 ctx
->vertex_buffers
= NULL
;
2170 ctx
->vertex_buffer_count
= 0;
2175 panfrost_set_constant_buffer(
2176 struct pipe_context
*pctx
,
2177 enum pipe_shader_type shader
, uint index
,
2178 const struct pipe_constant_buffer
*buf
)
2180 struct panfrost_context
*ctx
= pan_context(pctx
);
2181 struct panfrost_constant_buffer
*pbuf
= &ctx
->constant_buffer
[shader
];
2183 size_t sz
= buf
? buf
->buffer_size
: 0;
2185 /* Free previous buffer */
2192 pbuf
->buffer
= NULL
;
2195 /* If unbinding, we're done */
2200 /* Multiple constant buffers not yet supported */
2205 struct panfrost_resource
*rsrc
= (struct panfrost_resource
*) (buf
->buffer
);
2208 cpu
= rsrc
->bo
->cpu
[0];
2209 } else if (buf
->user_buffer
) {
2210 cpu
= buf
->user_buffer
;
2212 DBG("No constant buffer?\n");
2216 /* Copy the constant buffer into the driver context for later upload */
2218 pbuf
->buffer
= malloc(sz
);
2219 memcpy(pbuf
->buffer
, cpu
+ buf
->buffer_offset
, sz
);
2223 panfrost_set_stencil_ref(
2224 struct pipe_context
*pctx
,
2225 const struct pipe_stencil_ref
*ref
)
2227 struct panfrost_context
*ctx
= pan_context(pctx
);
2228 ctx
->stencil_ref
= *ref
;
2230 /* Shader core dirty */
2231 ctx
->dirty
|= PAN_DIRTY_FS
;
2234 static struct pipe_sampler_view
*
2235 panfrost_create_sampler_view(
2236 struct pipe_context
*pctx
,
2237 struct pipe_resource
*texture
,
2238 const struct pipe_sampler_view
*template)
2240 struct panfrost_sampler_view
*so
= CALLOC_STRUCT(panfrost_sampler_view
);
2241 int bytes_per_pixel
= util_format_get_blocksize(texture
->format
);
2243 pipe_reference(NULL
, &texture
->reference
);
2245 struct panfrost_resource
*prsrc
= (struct panfrost_resource
*) texture
;
2247 so
->base
= *template;
2248 so
->base
.texture
= texture
;
2249 so
->base
.reference
.count
= 1;
2250 so
->base
.context
= pctx
;
2252 /* sampler_views correspond to texture descriptors, minus the texture
2253 * (data) itself. So, we serialise the descriptor here and cache it for
2256 /* TODO: Other types of textures */
2257 assert(template->target
== PIPE_TEXTURE_2D
);
2259 /* Make sure it's something with which we're familiar */
2260 assert(bytes_per_pixel
>= 1 && bytes_per_pixel
<= 4);
2262 /* TODO: Detect from format better */
2263 const struct util_format_description
*desc
= util_format_description(prsrc
->base
.format
);
2265 unsigned char user_swizzle
[4] = {
2266 template->swizzle_r
,
2267 template->swizzle_g
,
2268 template->swizzle_b
,
2272 enum mali_format format
= panfrost_find_format(desc
);
2274 bool is_depth
= desc
->format
== PIPE_FORMAT_Z32_UNORM
;
2276 unsigned usage2_layout
= 0x10;
2278 switch (prsrc
->bo
->layout
) {
2280 usage2_layout
|= 0x8 | 0x4;
2283 usage2_layout
|= 0x1;
2286 usage2_layout
|= is_depth
? 0x1 : 0x2;
2293 struct mali_texture_descriptor texture_descriptor
= {
2294 .width
= MALI_POSITIVE(texture
->width0
),
2295 .height
= MALI_POSITIVE(texture
->height0
),
2296 .depth
= MALI_POSITIVE(texture
->depth0
),
2300 .swizzle
= panfrost_translate_swizzle_4(desc
->swizzle
),
2304 .is_not_cubemap
= 1,
2306 .usage2
= usage2_layout
2309 .swizzle
= panfrost_translate_swizzle_4(user_swizzle
)
2312 /* TODO: Other base levels require adjusting dimensions / level numbers / etc */
2313 assert (template->u
.tex
.first_level
== 0);
2315 texture_descriptor
.nr_mipmap_levels
= template->u
.tex
.last_level
- template->u
.tex
.first_level
;
2317 so
->hw
= texture_descriptor
;
2319 return (struct pipe_sampler_view
*) so
;
2323 panfrost_set_sampler_views(
2324 struct pipe_context
*pctx
,
2325 enum pipe_shader_type shader
,
2326 unsigned start_slot
, unsigned num_views
,
2327 struct pipe_sampler_view
**views
)
2329 struct panfrost_context
*ctx
= pan_context(pctx
);
2331 assert(start_slot
== 0);
2333 ctx
->sampler_view_count
[shader
] = num_views
;
2334 memcpy(ctx
->sampler_views
[shader
], views
, num_views
* sizeof (void *));
2336 ctx
->dirty
|= PAN_DIRTY_TEXTURES
;
2340 panfrost_sampler_view_destroy(
2341 struct pipe_context
*pctx
,
2342 struct pipe_sampler_view
*views
)
2344 //struct panfrost_context *ctx = pan_context(pctx);
2352 panfrost_set_framebuffer_state(struct pipe_context
*pctx
,
2353 const struct pipe_framebuffer_state
*fb
)
2355 struct panfrost_context
*ctx
= pan_context(pctx
);
2357 /* Flush when switching away from an FBO */
2359 if (!panfrost_is_scanout(ctx
)) {
2360 panfrost_flush(pctx
, NULL
, 0);
2363 ctx
->pipe_framebuffer
.nr_cbufs
= fb
->nr_cbufs
;
2364 ctx
->pipe_framebuffer
.samples
= fb
->samples
;
2365 ctx
->pipe_framebuffer
.layers
= fb
->layers
;
2366 ctx
->pipe_framebuffer
.width
= fb
->width
;
2367 ctx
->pipe_framebuffer
.height
= fb
->height
;
2369 for (int i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2370 struct pipe_surface
*cb
= i
< fb
->nr_cbufs
? fb
->cbufs
[i
] : NULL
;
2372 /* check if changing cbuf */
2373 if (ctx
->pipe_framebuffer
.cbufs
[i
] == cb
) continue;
2375 if (cb
&& (i
!= 0)) {
2376 DBG("XXX: Multiple render targets not supported before t7xx!\n");
2381 pipe_surface_reference(&ctx
->pipe_framebuffer
.cbufs
[i
], cb
);
2386 if (ctx
->require_sfbd
)
2387 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2389 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2391 panfrost_attach_vt_framebuffer(ctx
);
2392 panfrost_new_frag_framebuffer(ctx
);
2393 panfrost_set_scissor(ctx
);
2395 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.cbufs
[i
]->texture
);
2396 bool is_scanout
= panfrost_is_scanout(ctx
);
2398 if (!is_scanout
&& tex
->bo
->layout
!= PAN_AFBC
) {
2399 /* The blob is aggressive about enabling AFBC. As such,
2400 * it's pretty much necessary to use it here, since we
2401 * have no traces of non-compressed FBO. */
2403 panfrost_enable_afbc(ctx
, tex
, false);
2406 if (!is_scanout
&& !tex
->bo
->has_checksum
) {
2407 /* Enable transaction elimination if we can */
2408 panfrost_enable_checksum(ctx
, tex
);
2413 struct pipe_surface
*zb
= fb
->zsbuf
;
2415 if (ctx
->pipe_framebuffer
.zsbuf
!= zb
) {
2416 pipe_surface_reference(&ctx
->pipe_framebuffer
.zsbuf
, zb
);
2421 if (ctx
->require_sfbd
)
2422 ctx
->vt_framebuffer_sfbd
= panfrost_emit_sfbd(ctx
);
2424 ctx
->vt_framebuffer_mfbd
= panfrost_emit_mfbd(ctx
);
2426 panfrost_attach_vt_framebuffer(ctx
);
2427 panfrost_new_frag_framebuffer(ctx
);
2428 panfrost_set_scissor(ctx
);
2430 struct panfrost_resource
*tex
= ((struct panfrost_resource
*) ctx
->pipe_framebuffer
.zsbuf
->texture
);
2432 if (tex
->bo
->layout
!= PAN_AFBC
&& !panfrost_is_scanout(ctx
))
2433 panfrost_enable_afbc(ctx
, tex
, true);
2440 panfrost_create_blend_state(struct pipe_context
*pipe
,
2441 const struct pipe_blend_state
*blend
)
2443 struct panfrost_context
*ctx
= pan_context(pipe
);
2444 struct panfrost_blend_state
*so
= CALLOC_STRUCT(panfrost_blend_state
);
2447 /* TODO: The following features are not yet implemented */
2448 assert(!blend
->logicop_enable
);
2449 assert(!blend
->alpha_to_coverage
);
2450 assert(!blend
->alpha_to_one
);
2452 /* Compile the blend state, first as fixed-function if we can */
2454 if (panfrost_make_fixed_blend_mode(&blend
->rt
[0], &so
->equation
, blend
->rt
[0].colormask
, &ctx
->blend_color
))
2457 /* If we can't, compile a blend shader instead */
2459 panfrost_make_blend_shader(ctx
, so
, &ctx
->blend_color
);
2465 panfrost_bind_blend_state(struct pipe_context
*pipe
,
2468 struct panfrost_context
*ctx
= pan_context(pipe
);
2469 struct pipe_blend_state
*blend
= (struct pipe_blend_state
*) cso
;
2470 struct panfrost_blend_state
*pblend
= (struct panfrost_blend_state
*) cso
;
2471 ctx
->blend
= pblend
;
2476 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_NO_DITHER
, !blend
->dither
);
2478 /* TODO: Attach color */
2480 /* Shader itself is not dirty, but the shader core is */
2481 ctx
->dirty
|= PAN_DIRTY_FS
;
2485 panfrost_delete_blend_state(struct pipe_context
*pipe
,
2488 struct panfrost_blend_state
*so
= (struct panfrost_blend_state
*) blend
;
2490 if (so
->has_blend_shader
) {
2491 DBG("Deleting blend state leak blend shaders bytecode\n");
2498 panfrost_set_blend_color(struct pipe_context
*pipe
,
2499 const struct pipe_blend_color
*blend_color
)
2501 struct panfrost_context
*ctx
= pan_context(pipe
);
2503 /* If blend_color is we're unbinding, so ctx->blend_color is now undefined -> nothing to do */
2506 ctx
->blend_color
= *blend_color
;
2508 /* The blend mode depends on the blend constant color, due to the
2509 * fixed/programmable split. So, we're forced to regenerate the blend
2512 /* TODO: Attach color */
2517 panfrost_create_depth_stencil_state(struct pipe_context
*pipe
,
2518 const struct pipe_depth_stencil_alpha_state
*depth_stencil
)
2520 return mem_dup(depth_stencil
, sizeof(*depth_stencil
));
2524 panfrost_bind_depth_stencil_state(struct pipe_context
*pipe
,
2527 struct panfrost_context
*ctx
= pan_context(pipe
);
2528 struct pipe_depth_stencil_alpha_state
*depth_stencil
= cso
;
2529 ctx
->depth_stencil
= depth_stencil
;
2534 /* Alpha does not exist in the hardware (it's not in ES3), so it's
2535 * emulated in the fragment shader */
2537 if (depth_stencil
->alpha
.enabled
) {
2538 /* We need to trigger a new shader (maybe) */
2539 ctx
->base
.bind_fs_state(&ctx
->base
, ctx
->fs
);
2543 SET_BIT(ctx
->fragment_shader_core
.unknown2_4
, MALI_STENCIL_TEST
, depth_stencil
->stencil
[0].enabled
); /* XXX: which one? */
2545 panfrost_make_stencil_state(&depth_stencil
->stencil
[0], &ctx
->fragment_shader_core
.stencil_front
);
2546 ctx
->fragment_shader_core
.stencil_mask_front
= depth_stencil
->stencil
[0].writemask
;
2548 panfrost_make_stencil_state(&depth_stencil
->stencil
[1], &ctx
->fragment_shader_core
.stencil_back
);
2549 ctx
->fragment_shader_core
.stencil_mask_back
= depth_stencil
->stencil
[1].writemask
;
2551 /* Depth state (TODO: Refactor) */
2552 SET_BIT(ctx
->fragment_shader_core
.unknown2_3
, MALI_DEPTH_TEST
, depth_stencil
->depth
.enabled
);
2554 int func
= depth_stencil
->depth
.enabled
? depth_stencil
->depth
.func
: PIPE_FUNC_ALWAYS
;
2556 ctx
->fragment_shader_core
.unknown2_3
&= ~MALI_DEPTH_FUNC_MASK
;
2557 ctx
->fragment_shader_core
.unknown2_3
|= MALI_DEPTH_FUNC(panfrost_translate_compare_func(func
));
2559 /* Bounds test not implemented */
2560 assert(!depth_stencil
->depth
.bounds_test
);
2562 ctx
->dirty
|= PAN_DIRTY_FS
;
2566 panfrost_delete_depth_stencil_state(struct pipe_context
*pipe
, void *depth
)
2572 panfrost_set_sample_mask(struct pipe_context
*pipe
,
2573 unsigned sample_mask
)
2578 panfrost_set_clip_state(struct pipe_context
*pipe
,
2579 const struct pipe_clip_state
*clip
)
2581 //struct panfrost_context *panfrost = pan_context(pipe);
2585 panfrost_set_viewport_states(struct pipe_context
*pipe
,
2586 unsigned start_slot
,
2587 unsigned num_viewports
,
2588 const struct pipe_viewport_state
*viewports
)
2590 struct panfrost_context
*ctx
= pan_context(pipe
);
2592 assert(start_slot
== 0);
2593 assert(num_viewports
== 1);
2595 ctx
->pipe_viewport
= *viewports
;
2598 /* TODO: What if not centered? */
2599 float w
= abs(viewports
->scale
[0]) * 2.0;
2600 float h
= abs(viewports
->scale
[1]) * 2.0;
2602 ctx
->viewport
.viewport1
[0] = MALI_POSITIVE((int) w
);
2603 ctx
->viewport
.viewport1
[1] = MALI_POSITIVE((int) h
);
2608 panfrost_set_scissor_states(struct pipe_context
*pipe
,
2609 unsigned start_slot
,
2610 unsigned num_scissors
,
2611 const struct pipe_scissor_state
*scissors
)
2613 struct panfrost_context
*ctx
= pan_context(pipe
);
2615 assert(start_slot
== 0);
2616 assert(num_scissors
== 1);
2618 ctx
->scissor
= *scissors
;
2620 panfrost_set_scissor(ctx
);
2624 panfrost_set_polygon_stipple(struct pipe_context
*pipe
,
2625 const struct pipe_poly_stipple
*stipple
)
2627 //struct panfrost_context *panfrost = pan_context(pipe);
2631 panfrost_set_active_query_state(struct pipe_context
*pipe
,
2634 //struct panfrost_context *panfrost = pan_context(pipe);
2638 panfrost_destroy(struct pipe_context
*pipe
)
2640 struct panfrost_context
*panfrost
= pan_context(pipe
);
2641 struct panfrost_screen
*screen
= pan_screen(pipe
->screen
);
2643 if (panfrost
->blitter
)
2644 util_blitter_destroy(panfrost
->blitter
);
2646 screen
->driver
->free_slab(screen
, &panfrost
->scratchpad
);
2647 screen
->driver
->free_slab(screen
, &panfrost
->varying_mem
);
2648 screen
->driver
->free_slab(screen
, &panfrost
->shaders
);
2649 screen
->driver
->free_slab(screen
, &panfrost
->tiler_heap
);
2650 screen
->driver
->free_slab(screen
, &panfrost
->misc_0
);
2653 static struct pipe_query
*
2654 panfrost_create_query(struct pipe_context
*pipe
,
2658 struct panfrost_query
*q
= CALLOC_STRUCT(panfrost_query
);
2663 return (struct pipe_query
*) q
;
2667 panfrost_destroy_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2673 panfrost_begin_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2675 struct panfrost_context
*ctx
= pan_context(pipe
);
2676 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2678 switch (query
->type
) {
2679 case PIPE_QUERY_OCCLUSION_COUNTER
:
2680 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2681 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
:
2683 /* Allocate a word for the query results to be stored */
2684 query
->transfer
= panfrost_allocate_chunk(ctx
, sizeof(unsigned), HEAP_DESCRIPTOR
);
2686 ctx
->occlusion_query
= query
;
2692 DBG("Skipping query %d\n", query
->type
);
2700 panfrost_end_query(struct pipe_context
*pipe
, struct pipe_query
*q
)
2702 struct panfrost_context
*ctx
= pan_context(pipe
);
2703 ctx
->occlusion_query
= NULL
;
2708 panfrost_get_query_result(struct pipe_context
*pipe
,
2709 struct pipe_query
*q
,
2711 union pipe_query_result
*vresult
)
2714 struct panfrost_query
*query
= (struct panfrost_query
*) q
;
2716 /* We need to flush out the jobs to actually run the counter, TODO
2717 * check wait, TODO wallpaper after if needed */
2719 panfrost_flush(pipe
, NULL
, PIPE_FLUSH_END_OF_FRAME
);
2721 switch (query
->type
) {
2722 case PIPE_QUERY_OCCLUSION_COUNTER
:
2723 case PIPE_QUERY_OCCLUSION_PREDICATE
:
2724 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE
: {
2725 /* Read back the query results */
2726 unsigned *result
= (unsigned *) query
->transfer
.cpu
;
2727 unsigned passed
= *result
;
2729 if (query
->type
== PIPE_QUERY_OCCLUSION_COUNTER
) {
2730 vresult
->u64
= passed
;
2732 vresult
->b
= !!passed
;
2738 DBG("Skipped query get %d\n", query
->type
);
2746 panfrost_setup_hardware(struct panfrost_context
*ctx
)
2748 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2749 struct panfrost_screen
*screen
= pan_screen(gallium
->screen
);
2751 for (int i
= 0; i
< ARRAY_SIZE(ctx
->transient_pools
); ++i
) {
2752 /* Allocate the beginning of the transient pool */
2753 int entry_size
= (1 << 22); /* 4MB */
2755 ctx
->transient_pools
[i
].entry_size
= entry_size
;
2756 ctx
->transient_pools
[i
].entry_count
= 1;
2758 ctx
->transient_pools
[i
].entries
[0] = (struct panfrost_memory_entry
*) pb_slab_alloc(&screen
->slabs
, entry_size
, HEAP_TRANSIENT
);
2761 screen
->driver
->allocate_slab(screen
, &ctx
->scratchpad
, 64, false, 0, 0, 0);
2762 screen
->driver
->allocate_slab(screen
, &ctx
->varying_mem
, 16384, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_COHERENT_LOCAL
, 0, 0);
2763 screen
->driver
->allocate_slab(screen
, &ctx
->shaders
, 4096, true, PAN_ALLOCATE_EXECUTE
, 0, 0);
2764 screen
->driver
->allocate_slab(screen
, &ctx
->tiler_heap
, 32768, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2765 screen
->driver
->allocate_slab(screen
, &ctx
->misc_0
, 128*128, false, PAN_ALLOCATE_INVISIBLE
| PAN_ALLOCATE_GROWABLE
, 1, 128);
2769 /* New context creation, which also does hardware initialisation since I don't
2770 * know the better way to structure this :smirk: */
2772 struct pipe_context
*
2773 panfrost_create_context(struct pipe_screen
*screen
, void *priv
, unsigned flags
)
2775 struct panfrost_context
*ctx
= CALLOC_STRUCT(panfrost_context
);
2776 struct panfrost_screen
*pscreen
= pan_screen(screen
);
2777 memset(ctx
, 0, sizeof(*ctx
));
2778 struct pipe_context
*gallium
= (struct pipe_context
*) ctx
;
2781 gpu_id
= pscreen
->driver
->query_gpu_version(pscreen
);
2782 ctx
->is_t6xx
= gpu_id
<= 0x0750; /* For now, this flag means t76x or less */
2783 ctx
->require_sfbd
= gpu_id
< 0x0750; /* t76x is the first to support MFD */
2785 gallium
->screen
= screen
;
2787 gallium
->destroy
= panfrost_destroy
;
2789 gallium
->set_framebuffer_state
= panfrost_set_framebuffer_state
;
2791 gallium
->flush
= panfrost_flush
;
2792 gallium
->clear
= panfrost_clear
;
2793 gallium
->draw_vbo
= panfrost_draw_vbo
;
2795 gallium
->set_vertex_buffers
= panfrost_set_vertex_buffers
;
2796 gallium
->set_constant_buffer
= panfrost_set_constant_buffer
;
2798 gallium
->set_stencil_ref
= panfrost_set_stencil_ref
;
2800 gallium
->create_sampler_view
= panfrost_create_sampler_view
;
2801 gallium
->set_sampler_views
= panfrost_set_sampler_views
;
2802 gallium
->sampler_view_destroy
= panfrost_sampler_view_destroy
;
2804 gallium
->create_rasterizer_state
= panfrost_create_rasterizer_state
;
2805 gallium
->bind_rasterizer_state
= panfrost_bind_rasterizer_state
;
2806 gallium
->delete_rasterizer_state
= panfrost_generic_cso_delete
;
2808 gallium
->create_vertex_elements_state
= panfrost_create_vertex_elements_state
;
2809 gallium
->bind_vertex_elements_state
= panfrost_bind_vertex_elements_state
;
2810 gallium
->delete_vertex_elements_state
= panfrost_delete_vertex_elements_state
;
2812 gallium
->create_fs_state
= panfrost_create_shader_state
;
2813 gallium
->delete_fs_state
= panfrost_delete_shader_state
;
2814 gallium
->bind_fs_state
= panfrost_bind_fs_state
;
2816 gallium
->create_vs_state
= panfrost_create_shader_state
;
2817 gallium
->delete_vs_state
= panfrost_delete_shader_state
;
2818 gallium
->bind_vs_state
= panfrost_bind_vs_state
;
2820 gallium
->create_sampler_state
= panfrost_create_sampler_state
;
2821 gallium
->delete_sampler_state
= panfrost_generic_cso_delete
;
2822 gallium
->bind_sampler_states
= panfrost_bind_sampler_states
;
2824 gallium
->create_blend_state
= panfrost_create_blend_state
;
2825 gallium
->bind_blend_state
= panfrost_bind_blend_state
;
2826 gallium
->delete_blend_state
= panfrost_delete_blend_state
;
2828 gallium
->set_blend_color
= panfrost_set_blend_color
;
2830 gallium
->create_depth_stencil_alpha_state
= panfrost_create_depth_stencil_state
;
2831 gallium
->bind_depth_stencil_alpha_state
= panfrost_bind_depth_stencil_state
;
2832 gallium
->delete_depth_stencil_alpha_state
= panfrost_delete_depth_stencil_state
;
2834 gallium
->set_sample_mask
= panfrost_set_sample_mask
;
2836 gallium
->set_clip_state
= panfrost_set_clip_state
;
2837 gallium
->set_viewport_states
= panfrost_set_viewport_states
;
2838 gallium
->set_scissor_states
= panfrost_set_scissor_states
;
2839 gallium
->set_polygon_stipple
= panfrost_set_polygon_stipple
;
2840 gallium
->set_active_query_state
= panfrost_set_active_query_state
;
2842 gallium
->create_query
= panfrost_create_query
;
2843 gallium
->destroy_query
= panfrost_destroy_query
;
2844 gallium
->begin_query
= panfrost_begin_query
;
2845 gallium
->end_query
= panfrost_end_query
;
2846 gallium
->get_query_result
= panfrost_get_query_result
;
2848 panfrost_resource_context_init(gallium
);
2850 pscreen
->driver
->init_context(ctx
);
2852 panfrost_setup_hardware(ctx
);
2855 gallium
->stream_uploader
= u_upload_create_default(gallium
);
2856 gallium
->const_uploader
= gallium
->stream_uploader
;
2857 assert(gallium
->stream_uploader
);
2859 /* Midgard supports ES modes, plus QUADS/QUAD_STRIPS/POLYGON */
2860 ctx
->draw_modes
= (1 << (PIPE_PRIM_POLYGON
+ 1)) - 1;
2862 ctx
->primconvert
= util_primconvert_create(gallium
, ctx
->draw_modes
);
2864 ctx
->blitter
= util_blitter_create(gallium
);
2865 assert(ctx
->blitter
);
2867 /* Prepare for render! */
2869 panfrost_job_init(ctx
);
2870 panfrost_emit_vertex_payload(ctx
);
2871 panfrost_emit_tiler_payload(ctx
);
2872 panfrost_invalidate_frame(ctx
);
2873 panfrost_viewport(ctx
, 0.0, 1.0, 0, 0, ctx
->pipe_framebuffer
.width
, ctx
->pipe_framebuffer
.height
);
2874 panfrost_default_shader_backend(ctx
);
2875 panfrost_generate_space_filler_indices();